Reducing Soft-error Vulnerability of Caches using Data Compression

Conference · Fri Jan 01 00:00:00 EST 2016

DOI:https://doi.org/10.1145/2902961.2902977· OSTI ID:1326489

Mittal, Sparsh ^[1]; Vetter, Jeffrey S ^[1]

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1. ORNL

With ongoing chip miniaturization and voltage scaling, particle strike-induced soft errors present increasingly severe threat to the reliability of on-chip caches. In this paper, we present a technique to reduce the vulnerability of caches to soft-errors. Our technique uses data compression to reduce the number of vulnerable data bits in the cache and performs selective duplication of more critical data-bits to provide extra protection to them. Microarchitectural simulations have shown that our technique is effective in reducing architectural vulnerability factor (AVF) of the cache and outperforms another technique. For single and dual-core system configuration, the average reduction in AVF is 5.59X and 8.44X, respectively. Also, the implementation and performance overheads of our technique are minimal and it is useful for a broad range of workloads.

• Research Organization: Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States)
• Sponsoring Organization: USDOE Office of Science (SC)
• DOE Contract Number: AC05-00OR22725
• OSTI ID: 1326489
• Resource Relation: Conference: ACM Great Lakes Symposium on VLSI (GLSVLSI), Boston, MA, USA, 20160518, 20160518
• Country of Publication: United States
• Language: English