OpenSoC Fabric
Recent advancements in technology scaling have shown a trend towards greater integration with large-scale chips containing thousands of processors connected to memories and other I/O devices using non-trivial network topologies. Software simulation proves insufficient to study the tradeoffs in such complex systems due to slow execution time, whereas hardware RTL development is too time-consuming. We present OpenSoC Fabric, an on-chip network generation infrastructure which aims to provide a parameterizable and powerful on-chip network generator for evaluating future high performance computing architectures based on SoC technology. OpenSoC Fabric leverages a new hardware DSL, Chisel, which contains powerful abstractions provided by its base language, Scala, and generates both software (C++) and hardware (Verilog) models from a single code base. The OpenSoC Fabric2 infrastructure is modeled after existing state-of-the-art simulators, offers large and powerful collections of configuration options, and follows object-oriented design and functional programming to make functionality extension as easy as possible.
- Short Name / Acronym:
- OPENSOCFABRIC; 003074MLTPL00
- Project Type:
- Copyrighted
- Site Accession Number:
- 2014-154
- Version:
- 00
- Programming Language(s):
- Medium: X; OS: NA; Compatibility: Multiplatform
- Research Organization:
- Lawrence Berkeley National Laboratory (LBNL), Berkeley, CA (United States)
- Sponsoring Organization:
- USDOE
- Contributing Organization:
- Farzad Fatollahi-Fard, David Donofrio, Georgios Michelgiannakis, John Bachan
- DOE Contract Number:
- AC02-05CH11231
- OSTI ID:
- 1323923
- Country of Origin:
- United States
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