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This content will become publicly available on December 28, 2016

Title: A Survey of Architectural Techniques for Near-Threshold Computing

Energy efficiency has now become the primary obstacle in scaling the performance of all classes of computing systems. In low-voltage computing and specifically, near-threshold voltage computing (NTC), which involves operating the transistor very close to and yet above its threshold voltage, holds the promise of providing many-fold improvement in energy efficiency. However, use of NTC also presents several challenges such as increased parametric variation, failure rate and performance loss etc. Our paper surveys several re- cent techniques which aim to offset these challenges for fully leveraging the potential of NTC. By classifying these techniques along several dimensions, we also highlight their similarities and differences. Ultimately, we hope that this paper will provide insights into state-of-art NTC techniques to researchers and system-designers and inspire further research in this field.
  1. Oak Ridge National Laboratory (ORNL), Oak Ridge, TN (United States)
Publication Date:
OSTI Identifier:
Grant/Contract Number:
Accepted Manuscript
Journal Name:
ACM Journal on Emerging Technologies in Computing Systems
Additional Journal Information:
Journal Volume: 12; Journal Issue: 4; Journal ID: ISSN 1550-4832
Association for Computing Machinery
Research Org:
Oak Ridge National Laboratory (ORNL), Oak Ridge, TN (United States)
Sponsoring Org:
USDOE Office of Science (SC), Advanced Scientific Computing Research (ASCR) (SC-21)
Country of Publication:
United States
97 MATHEMATICS AND COMPUTING review; classification; near-threshold voltage computing (NT) (NTV) (NTC); low-voltage; voltage scaling; cache; memory; reliability; hard-error