Scalable Energy Efficiency with Resilience for High Performance Computing Systems: A Quantitative Methodology
Energy efficiency and resilience are two crucial challenges for HPC systems to reach exascale. While energy efficiency and resilience issues have been extensively studied individually, little has been done to understand the interplay between energy efficiency and resilience for HPC systems. Decreasing the supply voltage associated with a given operating frequency for processors and other CMOS-based components can significantly reduce power consumption. However, this often raises system failure rates and consequently increases application execution time. In this work, we present an energy saving undervolting approach that leverages the mainstream resilience techniques to tolerate the increased failures caused by undervolting.
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- Conference: 11th International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC 2016), January 18-20, 2016, Prague, Czech Republic
- ACM , New York, NY, United States(US).
- Research Org:
- Pacific Northwest National Laboratory (PNNL), Richland, WA (US)
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- Country of Publication:
- United States
- energy, resilience; failures; iso-energy-efficiency model, HPC