Design and testing of the first 2D Prototype Vertically Integrated Pattern Recognition Associative Memory
Abstract
An associative memory-based track finding approach has been proposed for a Level 1 tracking trigger to cope with increasing luminosities at the LHC. The associative memory uses a massively parallel architecture to tackle the intrinsically complex combinatorics of track finding algorithms, thus avoiding the typical power law dependence of execution time on occupancy and solving the pattern recognition in times roughly proportional to the number of hits. This is of crucial importance given the large occupancies typical of hadronic collisions. The design of an associative memory system capable of dealing with the complexity of HL-LHC collisions and with the short latency required by Level 1 triggering poses significant, as yet unsolved, technical challenges. For this reason, an aggressive R&D program has been launched at Fermilab to advance state of-the-art associative memory technology, the so called VIPRAM (Vertically Integrated Pattern Recognition Associative Memory) project. The VIPRAM leverages emerging 3D vertical integration technology to build faster and denser Associative Memory devices. The first step is to implement in conventional VLSI the associative memory building blocks that can be used in 3D stacking, in other words, the building blocks are laid out as if it is a 3D design. In this paper, wemore »
- Authors:
- Publication Date:
- Research Org.:
- Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States)
- Sponsoring Org.:
- USDOE Office of Science (SC), High Energy Physics (HEP)
- OSTI Identifier:
- 1252997
- Report Number(s):
- FERMILAB-PUB-14-478-E-PPD
Journal ID: ISSN 1748-0221; 1345306
- DOE Contract Number:
- AC02-07CH11359
- Resource Type:
- Journal Article
- Journal Name:
- Journal of Instrumentation
- Additional Journal Information:
- Journal Volume: 10; Journal Issue: 02; Journal ID: ISSN 1748-0221
- Publisher:
- Institute of Physics (IOP)
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND TECHNOLOGY
Citation Formats
Liu, T., Deptuch, G., Hoff, J., Jindariani, S., Joshi, S., Olsen, J., Tran, N., and Trimpl, M. Design and testing of the first 2D Prototype Vertically Integrated Pattern Recognition Associative Memory. United States: N. p., 2015.
Web. doi:10.1088/1748-0221/10/02/C02029.
Liu, T., Deptuch, G., Hoff, J., Jindariani, S., Joshi, S., Olsen, J., Tran, N., & Trimpl, M. Design and testing of the first 2D Prototype Vertically Integrated Pattern Recognition Associative Memory. United States. https://doi.org/10.1088/1748-0221/10/02/C02029
Liu, T., Deptuch, G., Hoff, J., Jindariani, S., Joshi, S., Olsen, J., Tran, N., and Trimpl, M. 2015.
"Design and testing of the first 2D Prototype Vertically Integrated Pattern Recognition Associative Memory". United States. https://doi.org/10.1088/1748-0221/10/02/C02029. https://www.osti.gov/servlets/purl/1252997.
@article{osti_1252997,
title = {Design and testing of the first 2D Prototype Vertically Integrated Pattern Recognition Associative Memory},
author = {Liu, T. and Deptuch, G. and Hoff, J. and Jindariani, S. and Joshi, S. and Olsen, J. and Tran, N. and Trimpl, M.},
abstractNote = {An associative memory-based track finding approach has been proposed for a Level 1 tracking trigger to cope with increasing luminosities at the LHC. The associative memory uses a massively parallel architecture to tackle the intrinsically complex combinatorics of track finding algorithms, thus avoiding the typical power law dependence of execution time on occupancy and solving the pattern recognition in times roughly proportional to the number of hits. This is of crucial importance given the large occupancies typical of hadronic collisions. The design of an associative memory system capable of dealing with the complexity of HL-LHC collisions and with the short latency required by Level 1 triggering poses significant, as yet unsolved, technical challenges. For this reason, an aggressive R&D program has been launched at Fermilab to advance state of-the-art associative memory technology, the so called VIPRAM (Vertically Integrated Pattern Recognition Associative Memory) project. The VIPRAM leverages emerging 3D vertical integration technology to build faster and denser Associative Memory devices. The first step is to implement in conventional VLSI the associative memory building blocks that can be used in 3D stacking, in other words, the building blocks are laid out as if it is a 3D design. In this paper, we report on the first successful implementation of a 2D VIPRAM demonstrator chip (protoVIPRAM00). The results show that these building blocks are ready for 3D stacking.},
doi = {10.1088/1748-0221/10/02/C02029},
url = {https://www.osti.gov/biblio/1252997},
journal = {Journal of Instrumentation},
issn = {1748-0221},
number = 02,
volume = 10,
place = {United States},
year = {Sun Feb 01 00:00:00 EST 2015},
month = {Sun Feb 01 00:00:00 EST 2015}
}