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Title: Architecture for on-die interconnect

Patent ·
OSTI ID:1243036
; ; ;

In an embodiment, an apparatus includes: a plurality of islands configured on a semiconductor die, each of the plurality of islands having a plurality of cores; and a plurality of network switches configured on the semiconductor die and each associated with one of the plurality of islands, where each network switch includes a plurality of output ports, a first set of the output ports are each to couple to the associated network switch of an island via a point-to-point interconnect and a second set of the output ports are each to couple to the associated network switches of a plurality of islands via a point-to-multipoint interconnect. Other embodiments are described and claimed.

Research Organization:
Intel Corporation, Santa Clara, CA (United States)
Sponsoring Organization:
USDOE
DOE Contract Number:
B600738
Assignee:
Intel Corporation (Santa Clara, CA)
Patent Number(s):
9,287,208
Application Number:
14/524,622
OSTI ID:
1243036
Resource Relation:
Patent File Date: 2014 Oct 27
Country of Publication:
United States
Language:
English

References (5)

Express Cube Topologies for on-Chip Interconnects conference February 2009
Cost-Efficient Dragonfly Topology for Large-Scale Systems journal January 2009
Methods and semiconductor devices with wiring layer fill structures to improve planarization uniformity patent February 2004
Semiconductor device patent April 2014
Multi-chip package and interposer with signal line compression patent October 2015

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