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Title: Exploiting data representation for fault tolerance

Incorrect computer hardware behavior may corrupt intermediate computations in numerical algorithms, possibly resulting in incorrect answers. Prior work models misbehaving hardware by randomly flipping bits in memory. We start by accepting this premise, and present an analytic model for the error introduced by a bit flip in an IEEE 754 floating-point number. We then relate this finding to the linear algebra concepts of normalization and matrix equilibration. In particular, we present a case study illustrating that normalizing both vector inputs of a dot product minimizes the probability of a single bit flip causing a large error in the dot product's result. Moreover, the absolute error is either less than one or very large, which allows detection of large errors. Then, we apply this to the GMRES iterative solver. We count all possible errors that can be introduced through faults in arithmetic in the computationally intensive orthogonalization phase of GMRES, and show that when the matrix is equilibrated, the absolute error is bounded above by one.
 [1] ;  [2] ;  [3] ;  [2]
  1. Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
  2. North Carolina State Univ., Raleigh, NC (United States)
  3. (SNL-NM), Albuquerque, NM (United States)
Publication Date:
OSTI Identifier:
Report Number(s):
Journal ID: ISSN 1877-7503; 619163
Grant/Contract Number:
Accepted Manuscript
Journal Name:
Journal of Computational Science
Additional Journal Information:
Journal Name: Journal of Computational Science; Journal ID: ISSN 1877-7503
Research Org:
Sandia National Laboratories (SNL-NM), Albuquerque, NM (United States)
Sponsoring Org:
USDOE National Nuclear Security Administration (NNSA)
Country of Publication:
United States
97 MATHEMATICS AND COMPUTING algorithm-based fault tolerance; resilient algorithms; numerical methods