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This content will become publicly available on December 7, 2016

Title: Vertical GaN power diodes with a bilayer edge termination

Vertical GaN power diodes with a bilayer edge termination (ET) are demonstrated. The GaN p-n junction is formed on a low threading dislocation defect density (104 - 105 cm-2) GaN substrate, and has a 15-μm-thick n-type drift layer with a free carrier concentration of 5 × 1015 cm-3. The ET structure is formed by N implantation into the p+-GaN epilayer just outside the p-type contact to create compensating defects. The implant defect profile may be approximated by a bilayer structure consisting of a fully compensated layer near the surface, followed by a 90% compensated (p) layer near the n-type drift region. These devices exhibit avalanche breakdown as high as 2.6 kV at room temperature. In addition simulations show that the ET created by implantation is an effective way to laterally distribute the electric field over a large area. This increases the voltage at which impact ionization occurs and leads to the observed higher breakdown voltages.
 [1] ;  [1] ;  [2] ;  [1] ;  [1] ;  [1] ;  [1] ;  [1] ;  [2] ;  [2] ;  [3]
  1. Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
  2. Avogy Inc., San Jose, CA (United States)
  3. Lehigh Univ., Bethlehem, PA (United States)
Publication Date:
OSTI Identifier:
Report Number(s):
Journal ID: ISSN 0018-9383; 603200
Grant/Contract Number:
Accepted Manuscript
Journal Name:
IEEE Transactions on Electron Devices
Additional Journal Information:
Journal Volume: 63; Journal Issue: 1; Journal ID: ISSN 0018-9383
Research Org:
Sandia National Laboratories (SNL-NM), Albuquerque, NM (United States)
Sponsoring Org:
USDOE National Nuclear Security Administration (NNSA)
Country of Publication:
United States
42 ENGINEERING powder semiconductor devices; p-n junctions; gallium nitride; avalanche breakdown