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Title: Three-dimensional stacked structured ASIC devices and methods of fabrication thereof

Patent ·
OSTI ID:1226234
; ; ; ;

A 3D stacked sASIC is provided that includes a plurality of 2D reconfigurable structured structured ASIC (sASIC) levels interconnected through hard-wired arrays of 3D vias. The 2D sASIC levels may contain logic, memory, analog functions, and device input/output pad circuitry. During fabrication, these 2D sASIC levels are stacked on top of each other and fused together with 3D metal vias. Such 3D vias may be fabricated as through-silicon vias (TSVs). They may connect to the back-side of the 2D sASIC level, or they may be connected to top metal pads on the front-side of the 2D sASIC level.

Research Organization:
Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
Sponsoring Organization:
USDOE
DOE Contract Number:
AC04-94AL85000
Assignee:
Sandia Corporation
Patent Number(s):
9,190,392
Application Number:
14/283,101
OSTI ID:
1226234
Resource Relation:
Patent File Date: 2014 May 20
Country of Publication:
United States
Language:
English

References (11)

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  • Kim, Dae Hyun; Athikulwongse, Krit; Healy, Michael
  • 2012 IEEE International Solid- State Circuits Conference - (ISSCC), 2012 IEEE International Solid-State Circuits Conference https://doi.org/10.1109/ISSCC.2012.6176969
conference February 2012
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Cost effectiveness of 3D integration options conference November 2010
Structured ASIC, evolution or revolution? conference January 2004
A customized design of DRAM controller for on-chip 3D DRAM stacking conference September 2010

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36 MATERIALS SCIENCE
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