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Title: Approximate circuits for increased reliability

Patent ·
OSTI ID:1210221

Embodiments of the invention describe a Boolean circuit having a voter circuit and a plurality of approximate circuits each based, at least in part, on a reference circuit. The approximate circuits are each to generate one or more output signals based on values of received input signals. The voter circuit is to receive the one or more output signals generated by each of the approximate circuits, and is to output one or more signals corresponding to a majority value of the received signals. At least some of the approximate circuits are to generate an output value different than the reference circuit for one or more input signal values; however, for each possible input signal value, the majority values of the one or more output signals generated by the approximate circuits and received by the voter circuit correspond to output signal result values of the reference circuit.

Research Organization:
Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
Sponsoring Organization:
USDOE
DOE Contract Number:
AC04-94AL85000
Assignee:
Sandia Corporation (Albuquerque, NM)
Patent Number(s):
9,112,490
Application Number:
14/052,896
OSTI ID:
1210221
Resource Relation:
Patent File Date: 2013 Oct 14
Country of Publication:
United States
Language:
English

References (6)

Reducing susceptibility of circuit designs to single event upsets patent November 2011
Design as you see FIT: System-level soft error analysis of sequential circuits conference April 2009
Seamless Integration of SER in Rewiring-Based Design Space Exploration conference October 2006
Soft Error Mitigation Through Selective Addition of Functionally Redundant Wires journal March 2008
Partial error masking to reduce soft error failure rate in logic circuits conference January 2003
Signature-Based SER Analysis and Design of Logic Circuits journal January 2009

Cited By (1)


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