Adaptive prefetching on POWER7: Improving performance and power consumption

Journal Article · Fri Oct 03 00:00:00 EDT 2014 · ACM Transactions on Parallel Computing

DOI:https://doi.org/10.1145/2588889· OSTI ID:1208786

Jimenez, Victor ^[1]; Cazorla, Francisco ^[1]; Gioiosa, Roberto ^[2]; Buyuktosunoglu, Alper ^[3]; Bose, Pradip ^[3]; O'Connel, Francis P. ^[3]; Mealey, Bruce G. ^[3]

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1. Barcelona Supercomputing Center and Univ. Politecnica de Catalunya, Barcelona (Spain)
2. Pacific Northwest National Lab. (PNNL), Richland, WA (United States)
3. IBM T. J. Watson Research Center, Yorktown Heights, NY (United States)

Hardware data prefetch engines are integral parts of many general purpose server-class microprocessors in the field today. Some prefetch engines allow users to change some of their parameters. But, the prefetcher is usually enabled in a default configuration during system bring-up, and dynamic reconfiguration of the prefetch engine is not an autonomic feature of current machines. Conceptually, however, it is easy to infer that commonly used prefetch algorithms—when applied in a fixed mode—will not help performance in many cases. In fact, they may actually degrade performance due to useless bus bandwidth consumption and cache pollution, which in turn, will also waste power. We present an adaptive prefetch scheme that dynamically modifies the prefetch settings in order to adapt to workloads

• Research Organization: Pacific Northwest National Lab. (PNNL), Richland, WA (United States)
• Sponsoring Organization: USDOE
• DOE Contract Number: AC05-76RL01830
• OSTI ID: 1208786
• Report Number(s): PNNL-SA-101761
• Journal Information: ACM Transactions on Parallel Computing, Vol. 1, Issue 1; ISSN 2329-4949
• Country of Publication: United States
• Language: English

Related Subjects

adaptive system
prefetching
performance
power consumption