Testing and operating a multiprocessor chip with processor redundancy
A system and method for improving the yield rate of a multiprocessor semiconductor chip that includes primary processor cores and one or more redundant processor cores. A first tester conducts a first test on one or more processor cores, and encodes results of the first test in an on-chip non-volatile memory. A second tester conducts a second test on the processor cores, and encodes results of the second test in an external non-volatile storage device. An override bit of a multiplexer is set if a processor core fails the second test. In response to the override bit, the multiplexer selects a physical-to-logical mapping of processor IDs according to one of: the encoded results in the memory device or the encoded results in the external storage device. On-chip logic configures the processor cores according to the selected physical-to-logical mapping.
- Research Organization:
- International Business Machines Corp., Armonk, NY (United States)
- Sponsoring Organization:
- USDOE
- DOE Contract Number:
- B554331
- Assignee:
- International Business Machines Corporation (Armonk, NY)
- Patent Number(s):
- 8,868,975
- Application Number:
- 13/196,459
- OSTI ID:
- 1160333
- Resource Relation:
- Patent File Date: 2011 Aug 02
- Country of Publication:
- United States
- Language:
- English
Similar Records
Technology development and circuit design for a parallel laser programmable floating-point application specific processor. Master's thesis
System and method for programmable bank selection for banked memory subsystems