The ultimate downscaling limit of FETs.
We created a highly efficient, universal 3D quant um transport simulator. We demonstrated that the simulator scales linearly - both with the problem size (N) and number of CPUs, which presents an important break-through in the field of computational nanoelectronics. It allowed us, for the first time, to accurately simulate and optim ize a large number of realistic nanodevices in a much shorter time, when compared to other methods/codes such as RGF[%7EN 2.333 ]/KNIT, KWANT, and QTBM[%7EN 3 ]/NEMO5. In order to determine the best-in-class for different beyond-CMOS paradigms, we performed rigorous device optimization for high-performance logic devices at 6-, 5- and 4-nm gate lengths. We have discovered that there exists a fundamental down-scaling limit for CMOS technology and other Field-Effect Transistors (FETs). We have found that, at room temperatures, all FETs, irre spective of their channel material, will start experiencing unacceptable level of thermally induced errors around 5-nm gate lengths.
- Publication Date:
- OSTI Identifier:
- Report Number(s):
- DOE Contract Number:
- Resource Type:
- Technical Report
- Research Org:
- Sandia National Laboratories (SNL-NM), Albuquerque, NM (United States)
- Sponsoring Org:
- USDOE National Nuclear Security Administration (NNSA)
- Country of Publication:
- United States
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