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Title: A Pixel Readout Chip in 40 nm CMOS Process for High Count Rate Imaging Systems with Minimization of Charge Sharing Effects

We present a prototype chip in 40 nm CMOS technology for readout of hybrid pixel detector. The prototype chip has a matrix of 18x24 pixels with a pixel pitch of 100 m. It can operate both in single photon counting (SPC) mode and in C8P1 mode. In SPC the measured ENC is 84 e rms (for the peaking time of 48 ns), while the effective offset spread is below 2 mV rms. In the C8P1 mode the chip reconstructs full charge deposited in the detector, even in the case of charge sharing, and it identifies a pixel with the largest charge deposition. The chip architecture and preliminary measurements are reported.
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Journal Name: NSS/MIC 2013 Proceedings; Journal Volume: C13-10-26; Conference: IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC), 2013 IEEE, Seoul, Korea, October 27, 2013 - November 2, 2013
Research Org:
Fermi National Accelerator Laboratory (FNAL), Batavia, IL
Sponsoring Org:
USDOE Office of Science (SC), High Energy Physics (HEP) (SC-25)
Contributing Orgs:
Pixels Collaboration
Country of Publication:
United States
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