SEGR in SiO$${}_2$$ –Si$$_3$$ N$$_4$$ Stacks
Journal Article
·
· IEEE Transactions on Nuclear Science
- Univ. of Jyvaskyla (Finland). Dept. of Phys.
- European Space Agency (ESTEC), Noordwijk (Netherlands)
- STMicroelectronics Srl, Catania (Italy)
- Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
This work presents experimental SEGR data for MOS-devices, where the gate dielectrics are are made of stacked SiO2–Si3N4 structures. Also a semi-empirical model for predicting the critical gate voltage in these structures under heavy-ion exposure is proposed. Then statistical interrelationship between SEGR cross-section data and simulated energy deposition probabilities in thin dielectric layers is discussed.
- Research Organization:
- Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
- Sponsoring Organization:
- USDOE National Nuclear Security Administration (NNSA)
- Grant/Contract Number:
- AC04-94AL85000
- OSTI ID:
- 1143834
- Report Number(s):
- SAND2013-8530J; 476604
- Journal Information:
- IEEE Transactions on Nuclear Science, Vol. 61, Issue 4; ISSN 0018-9499
- Publisher:
- Institute of Electrical and Electronics Engineers (IEEE)Copyright Statement
- Country of Publication:
- United States
- Language:
- English
Cited by: 5 works
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