Increasing throughput of multiplexed electrical bus in pipe-lined architecture
Techniques are disclosed for increasing the throughput of a multiplexed electrical bus by exploiting available pipeline stages of a computer or other system. For example, a method for increasing a throughput of an electrical bus that connects at least two devices in a system comprises introducing at least one signal hold stage in a signal-receiving one of the two devices, such that a maximum frequency at which the two devices are operated is not limited by a number of cycles of an operating frequency of the electrical bus needed for a signal to propagate from a signal-transmitting one of the two devices to the signal-receiving one of the two devices. Preferably, the signal hold stage introduced in the signal-receiving one of the two devices is a pipeline stage re-allocated from the signal-transmitting one of the two devices.
- Research Organization:
- International Business Machines Corp., Armonk, NY (United States)
- Sponsoring Organization:
- USDOE
- DOE Contract Number:
- B554331
- Assignee:
- International Business Machines Corporation (Armonk, NY)
- Patent Number(s):
- 8,737,233
- Application Number:
- 13/236,109
- OSTI ID:
- 1132572
- Resource Relation:
- Patent File Date: 2011 Sep 19
- Country of Publication:
- United States
- Language:
- English
Multi-FPGA prototyping of an ASIC circuit
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patent | July 2016 |
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