Exploring Manycore Multinode Systems for Irregular Applications with FPGA Prototyping
We present a prototype of a multi-core architecture implemented on FPGA, designed to enable efficient execution of irregular applications on distributed shared memory machines, while maintaining high performance on regular workloads. The architecture is composed of off-the-shelf soft-core cores, local interconnection and memory interface, integrated with custom components that optimize it for irregular applications. It relies on three key elements: a global address space, multithreading, and fine-grained synchronization. Global addresses are scrambled to reduce the formation of network hot-spots, while the latency of the transactions is covered by integrating an hardware scheduler within the custom load/store buffers to take advantage from the availability of multiple executions threads, increasing the efficiency in a transparent way to the application. We evaluated a dual node system irregular kernels showing scalability in the number of cores and threads.
- Research Organization:
- Pacific Northwest National Lab. (PNNL), Richland, WA (United States)
- Sponsoring Organization:
- USDOE
- DOE Contract Number:
- AC05-76RL01830
- OSTI ID:
- 1126350
- Report Number(s):
- PNNL-SA-90226; 400470000
- Resource Relation:
- Conference: IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM 2013), April 28-30, 2013, Seattle, Washington, 238
- Country of Publication:
- United States
- Language:
- English
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