Development of Production PVD-AIN Buffer Layer System and Processes to Reduce Epitaxy Costs and Increase LED Efficiency
The DOE has set aggressive goals for solid state lighting (SSL) adoption, which require manufacturing and quality improvements for virtually all process steps leading to an LED luminaire product. The goals pertinent to this proposed project are to reduce the cost and improve the quality of the epitaxial growth processes used to build LED structures. The objectives outlined in this proposal focus on achieving cost reduction and performance improvements over state-of-the-art, using technologies that are low in cost and amenable to high efficiency manufacturing. The objectives of the outlined proposal focus on cost reductions in epitaxial growth by reducing epitaxy layer thickness and hetero-epitaxial strain, and by enabling the use of larger, less expensive silicon substrates and would be accomplished through the introduction of a high productivity reactive sputtering system and an effective sputtered aluminum-nitride (AlN) buffer/nucleation layer process. Success of the proposed project could enable efficient adoption of GaN on-silicon (GaN/Si) epitaxial technology on 150mm silicon substrates. The reduction in epitaxy cost per cm{sup 2} using 150mm GaN-on-Si technology derives from (1) a reduction in cost of ownership and increase in throughput for the buffer deposition process via the elimination of MOCVD buffer layers and other throughput and CoO enhancements, (2) improvement in brightness through reductions in defect density, (3) reduction in substrate cost through the replacement of sapphire with silicon, and (4) reduction in non-ESD yield loss through reductions in wafer bow and temperature variation. The adoption of 150mm GaN/Si processing will also facilitate significant cost reductions in subsequent wafer fabrication manufacturing costs. There were three phases to this project. These three phases overlap in order to aggressively facilitate a commercially available production GaN/Si capability. In Phase I of the project, the repeatability of the performance was analyzed and improvements implemented to the Veeco PVD-AlN prototype system to establish a specification and baseline PVD-AlN films on sapphire and in parallel the evaluation of PVD AlN on silicon substrates began. In Phase II of the project a Beta tool based on a scaled-up process module capable of depositing uniform films on batches of 4”or 6” diameter substrates in a production worthy operation was developed and qualified. In Phase III, the means to increase the throughput of the PVD-AlN system was evaluated and focused primarily on minimizing the impact of the substrate heating and cooling times that dominated the overall cycle time.
- Research Organization:
- Veeco Process Equipment, Incorporated
- Sponsoring Organization:
- USDOE
- DOE Contract Number:
- EE0005064
- OSTI ID:
- 1111425
- Country of Publication:
- United States
- Language:
- English
Similar Records
Low-Cost Illumination-Grade LEDs
Effects of high-temperature AIN buffer on the microstructure of AlGaN/GaN HEMTs