Efficient wiring of reconfigurable parallel processors
Conference
·
OSTI ID:10143368
The advent of chips which include one or more CPUS, some local memory, and rudimentary communications and routing hardware has opened a new area in computer architecture design. What is the best way to connect these chips to solve particular problems? This paper defines the efficiency of a wiring scheme for a set of communication patterns. It then gives upper and lower bounds on the best efficiency achievable. It also presents simple wiring schemes for some stencil patterns used in mesh-based discrete simulations.
- Research Organization:
- Sandia National Labs., Albuquerque, NM (United States)
- Sponsoring Organization:
- USDOE, Washington, DC (United States)
- DOE Contract Number:
- AC04-76DP00789
- OSTI ID:
- 10143368
- Report Number(s):
- SAND-92-2011C; CONF-930194-2; ON: DE93009847
- Resource Relation:
- Conference: 4. annual ACM-SIAM conference on discrete algorithms,Austin, TX (United States),25-27 Jan 1993; Other Information: PBD: 28 Aug 1992
- Country of Publication:
- United States
- Language:
- English
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