Practical Loop Transformations for Tensor Contraction Expressions on Multi-Level Memory Hierarchies
Modern architectures are characterized by deeper levels of memory hierarchy, often explicitly addressable. Optimizing applications for such architectures requires careful management of the data movement across all these levels. In this paper, we focus on the problem of mapping tensor contractions to memory hierarchies with more than two levels, specifically addressing placement of memory allocation and data movement statements, choice of loop fusions, and tile size selection. Existing algorithms to find an integrated solution to this problem even for two-level memory hierarchies has been shown to be expensive. We improve upon this work by focusing on the first-order cost components, simplifying the analysis required and reducing the number of candidates to be evaluated. We have evaluated our framework on a cluster of GPUs. Using five tensor contraction expressions, we show that fusion at multiple levels improves performance, and our framework is effective in determining protable transformations.
- Research Organization:
- Pacific Northwest National Lab. (PNNL), Richland, WA (United States)
- Sponsoring Organization:
- USDOE
- DOE Contract Number:
- AC05-76RL01830
- OSTI ID:
- 1013930
- Report Number(s):
- PNNL-SA-77072; KJ0402000; TRN: US201110%%831
- Resource Relation:
- Conference: Compiler Construction: 20th International Conference, CC 2011, Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2011, March 26 - April 3, 2011, Saarbrucken, Germany. Lecture Notes in Computer Science, 6601:266-285
- Country of Publication:
- United States
- Language:
- English
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