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Title: An evaluation of MPI message rate on hybrid-core processors

Abstract

Power and energy concerns are motivating chip manufacturers to consider future hybrid-core processor designs that may combine a small number of traditional cores optimized for single-thread performance with a large number of simpler cores optimized for throughput performance. This trend is likely to impact the way in which compute resources for network protocol processing functions are allocated and managed. In particular, the performance of MPI match processing is critical to achieving high message throughput. In this paper, we analyze the ability of simple and more complex cores to perform MPI matching operations for various scenarios in order to gain insight into how MPI implementations for future hybrid-core processors should be designed.

Authors:
 [1];  [1];  [1];  [2];  [2]
  1. Sandia National Lab. (SNL-NM), Albuquerque, NM (United States). Scalable System Software
  2. Sandia National Lab. (SNL-NM), Albuquerque, NM (United States). Scalable Computer Architecture
Publication Date:
Research Org.:
Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
Sponsoring Org.:
USDOE National Nuclear Security Administration (NNSA)
OSTI Identifier:
1185011
Report Number(s):
SAND-2014-20472J
Journal ID: ISSN 1094-3420; 547795
Grant/Contract Number:  
AC04-94AL85000
Resource Type:
Accepted Manuscript
Journal Name:
International Journal of High Performance Computing Applications
Additional Journal Information:
Journal Volume: 28; Journal Issue: 4; Journal ID: ISSN 1094-3420
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Citation Formats

Barrett, Brian W., Brightwell, Ron, Grant, Ryan, Hammond, Simon D., and Hemmert, K. Scott. An evaluation of MPI message rate on hybrid-core processors. United States: N. p., 2014. Web. doi:10.1177/1094342014552085.
Barrett, Brian W., Brightwell, Ron, Grant, Ryan, Hammond, Simon D., & Hemmert, K. Scott. An evaluation of MPI message rate on hybrid-core processors. United States. https://doi.org/10.1177/1094342014552085
Barrett, Brian W., Brightwell, Ron, Grant, Ryan, Hammond, Simon D., and Hemmert, K. Scott. Sat . "An evaluation of MPI message rate on hybrid-core processors". United States. https://doi.org/10.1177/1094342014552085. https://www.osti.gov/servlets/purl/1185011.
@article{osti_1185011,
title = {An evaluation of MPI message rate on hybrid-core processors},
author = {Barrett, Brian W. and Brightwell, Ron and Grant, Ryan and Hammond, Simon D. and Hemmert, K. Scott},
abstractNote = {Power and energy concerns are motivating chip manufacturers to consider future hybrid-core processor designs that may combine a small number of traditional cores optimized for single-thread performance with a large number of simpler cores optimized for throughput performance. This trend is likely to impact the way in which compute resources for network protocol processing functions are allocated and managed. In particular, the performance of MPI match processing is critical to achieving high message throughput. In this paper, we analyze the ability of simple and more complex cores to perform MPI matching operations for various scenarios in order to gain insight into how MPI implementations for future hybrid-core processors should be designed.},
doi = {10.1177/1094342014552085},
journal = {International Journal of High Performance Computing Applications},
number = 4,
volume = 28,
place = {United States},
year = {Sat Nov 01 00:00:00 EDT 2014},
month = {Sat Nov 01 00:00:00 EDT 2014}
}

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Cited by: 17 works
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Works referenced in this record:

The impact of hybrid-core processors on MPI message rate
conference, January 2013

  • Barrett, Brian W.; Hammond, Simon D.; Brightwell, Ron
  • Proceedings of the 20th European MPI Users' Group Meeting on - EuroMPI '13
  • DOI: 10.1145/2488551.2488560

An application based MPI message throughput benchmark
conference, August 2009

  • Barrett, Brian W.; Hemmert, K. Scott
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Implementation and evaluation of shared-memory communication and synchronization operations in MPICH2 using the Nemesis communication subsystem
journal, September 2007


A high-performance, portable implementation of the MPI message passing interface standard
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The impact of MPI queue usage on message latency
conference, January 2004

  • Underwood, K. D.; Brightwell, R.
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  • DOI: 10.1109/ICPP.2004.1327915

Works referencing / citing this record:

Communication‐aware message matching in MPI
journal, September 2018

  • Ghazimirsaeed, S. Mahdieh; Mirsadeghi, Seyed H.; Afsahi, Ahmad
  • Concurrency and Computation: Practice and Experience, Vol. 32, Issue 3
  • DOI: 10.1002/cpe.4862

Hardware MPI message matching: Insights into MPI matching behavior to inform design
journal, February 2019

  • Ferreira, Kurt; Grant, Ryan E.; Levenhagen, Michael J.
  • Concurrency and Computation: Practice and Experience, Vol. 32, Issue 3
  • DOI: 10.1002/cpe.5150

Tail queues: A multi‐threaded matching architecture
journal, February 2019

  • Dosanjh, Matthew G. F.; Grant, Ryan E.; Schonbein, Whit
  • Concurrency and Computation: Practice and Experience, Vol. 32, Issue 3
  • DOI: 10.1002/cpe.5158

The survey on ARM processors for HPC
journal, June 2019

  • Yokoyama, Daniel; Schulze, Bruno; Borges, Fábio
  • The Journal of Supercomputing, Vol. 75, Issue 10
  • DOI: 10.1007/s11227-019-02911-9