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Title: SEGR in SiO$${}_2$$ –Si$_3$ N$_4$ Stacks

This work presents experimental SEGR data for MOS-devices, where the gate dielectrics are are made of stacked SiO2–Si3N4 structures. Also a semi-empirical model for predicting the critical gate voltage in these structures under heavy-ion exposure is proposed. Then statistical interrelationship between SEGR cross-section data and simulated energy deposition probabilities in thin dielectric layers is discussed.
Authors:
 [1] ;  [2] ;  [1] ;  [1] ;  [1] ;  [2] ;  [3] ;  [1] ;  [4] ;  [4] ;  [1]
  1. Univ. of Jyvaskyla (Finland). Dept. of Phys.
  2. European Space Agency (ESTEC), Noordwijk (Netherlands)
  3. STMicroelectronics Srl, Catania (Italy)
  4. Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
Publication Date:
OSTI Identifier:
1143834
Report Number(s):
SAND2013--8530J
Journal ID: ISSN 0018-9499; 476604
Grant/Contract Number:
AC04-94AL85000
Type:
Accepted Manuscript
Journal Name:
IEEE Transactions on Nuclear Science
Additional Journal Information:
Journal Volume: 61; Journal Issue: 4; Journal ID: ISSN 0018-9499
Publisher:
Institute of Electrical and Electronics Engineers (IEEE)
Research Org:
Sandia National Laboratories (SNL-NM), Albuquerque, NM (United States)
Sponsoring Org:
USDOE National Nuclear Security Administration (NNSA)
Country of Publication:
United States
Language:
English
Subject:
75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND SUPERFLUIDITY semi-empirical; Single Event Gate Rupture (SEGR); Modeling; MOS; hboxSiO₂