Sample records for transistor gate oxide

  1. Looking at Transistor Gate Oxide Formation in Real Time

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    that conducts current and permits control of the electron flow between the source and drain electrodes of the transistor. This layer is traditionally made of silicon dioxide but...

  2. Diminished Short Channel Effects in Nanoscale Double-Gate Silicon-on-Insulator MetalOxideSemiconductor Field-Effect-Transistors

    E-Print Network [OSTI]

    Kumar, M. Jagadesh

    ) and the back-gate oxide (tb) thickness is 2 nm. The doping in the p-type body and n+ source/drain regions­Oxide­Semiconductor Field-Effect-Transistors due to Induced Back-Gate Step Potential M. Jagadesh KUMAR Ã and G. Venkateshwar surface potential profile at the back gate of an asymmetrical double gate (DG) silicon-on-insulator (SOI

  3. Top-gate zinc tin oxide thin-film transistors with high bias and environmental stress stability

    SciTech Connect (OSTI)

    Fakhri, M.; Theisen, M.; Behrendt, A.; Görrn, P.; Riedl, T. [Institute of Electronic Devices, University of Wuppertal, Wuppertal 42119 (Germany)

    2014-06-23T23:59:59.000Z

    Top gated metal-oxide thin-film transistors (TFTs) provide two benefits compared to their conventional bottom-gate counterparts: (i) The gate dielectric may concomitantly serve as encapsulation layer for the TFT channel. (ii) Damage of the dielectric due to high-energetic particles during channel deposition can be avoided. In our work, the top-gate dielectric is prepared by ozone based atomic layer deposition at low temperatures. For ultra-low gas permeation rates, we introduce nano-laminates of Al{sub 2}O{sub 3}/ZrO{sub 2} as dielectrics. The resulting TFTs show a superior environmental stability even at elevated temperatures. Their outstanding stability vs. bias stress is benchmarked against bottom-gate devices with encapsulation.

  4. Study of gate oxide traps in HfO[subscript 2]/AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors by use of ac transconductance method

    E-Print Network [OSTI]

    Sun, X.

    We introduce an ac-transconductance method to profile the gate oxide traps in a HfO[subscript 2] gated AlGaN/GaN Metal-Oxide-Semiconductor High-Electron-Mobility Transistors (MOS-HEMTs) that can exchange carriers with metal ...

  5. Advanced insulated gate bipolar transistor gate drive

    DOE Patents [OSTI]

    Short, James Evans (Monongahela, PA); West, Shawn Michael (West Mifflin, PA); Fabean, Robert J. (Donora, PA)

    2009-08-04T23:59:59.000Z

    A gate drive for an insulated gate bipolar transistor (IGBT) includes a control and protection module coupled to a collector terminal of the IGBT, an optical communications module coupled to the control and protection module, a power supply module coupled to the control and protection module and an output power stage module with inputs coupled to the power supply module and the control and protection module, and outputs coupled to a gate terminal and an emitter terminal of the IGBT. The optical communications module is configured to send control signals to the control and protection module. The power supply module is configured to distribute inputted power to the control and protection module. The control and protection module outputs on/off, soft turn-off and/or soft turn-on signals to the output power stage module, which, in turn, supplies a current based on the signal(s) from the control and protection module for charging or discharging an input capacitance of the IGBT.

  6. Electroluminescence in ion gel gated organic polymer semiconductor transistors

    E-Print Network [OSTI]

    Bhat, Shrivalli

    2011-07-12T23:59:59.000Z

    This thesis reports the light emission in ion gel gated, thin film organic semiconductor transistors and investigates the light emission mechanism behind these devices. We report that ion gel gated organic polymer semiconductor transistors emit...

  7. Retention and switching kinetics of protonated gate field effect transistors

    SciTech Connect (OSTI)

    DEVINE,R.A.B.; HERRERA,GILBERT V.

    2000-05-23T23:59:59.000Z

    The switching and memory retention time has been measured in 50 {micro}m gatelength pseudo-non-volatile memory MOSFETS containing, protonated 40 nm gate oxides. Times of the order of 3.3 seconds are observed for fields of 3 MV cm{sup {minus}1}. The retention time with protons placed either at the gate oxide/substrate or gate oxide/gate electrode interfaces is found to better than 96{percent} after 5,000 seconds. Measurement of the time dependence of the source-drain current during switching provides clear evidence for the presence of dispersive proton transport through the gate oxide.

  8. Retention and Switching Kinetics of Protonated Gate Field Effect Transistors

    SciTech Connect (OSTI)

    DEVINE,R.A.B.; HERRERA,GILBERT V.

    2000-06-27T23:59:59.000Z

    The switching and memory retention time has been measured in 50 {micro}m gatelength pseudo-non-volatile memory MOSFETs containing, protonated 40 nm gate oxides. Times of the order of 3.3 seconds are observed for fields of 3 MV cm{sup {minus}1}. The retention time with protons placed either at the gate oxide/substrate or gate oxide/gate electrode interfaces is found to better than 96% after 5,000 seconds. Measurement of the time dependence of the source-drain current during switching provides clear evidence for the presence of dispersive proton transport through the gate oxide.

  9. Improved Stability Of Amorphous Zinc Tin Oxide Thin Film Transistors...

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Stability Of Amorphous Zinc Tin Oxide Thin Film Transistors Using Molecular Passivation. Improved Stability Of Amorphous Zinc Tin Oxide Thin Film Transistors Using Molecular...

  10. Design, Simulation and Modeling of Insulated Gate Bipolar Transistor

    E-Print Network [OSTI]

    Gupta, Kaustubh

    2013-07-09T23:59:59.000Z

    The market for Insulated Gate Bipolar Transistor (IGBT) is growing and there is a need for techniques to improve the design, modeling and simulation of IGBT. In this thesis, we first developed a new method to optimize the layout and dimensions...

  11. Hafnium-doped tantalum oxide high-k gate dielectric films for future CMOS technology 

    E-Print Network [OSTI]

    Lu, Jiang

    2007-04-25T23:59:59.000Z

    A novel high-k gate dielectric material, i.e., hafnium-doped tantalum oxide (Hf-doped TaOx), has been studied for the application of the future generation metal-oxidesemiconductor field effect transistor (MOSFET). The ...

  12. Double Gated Single Molecular Transistor for Charge Detection

    E-Print Network [OSTI]

    S. J. Ray; R. Chowdhury

    2014-11-09T23:59:59.000Z

    The electrostatic behaviour of an 1,3-Cyclobutadiene (C$_{4}$H$_{4}$) based Single Molecular Transistor (SMT) has been investigated using the first principle calculation based on Density functional Theory and non-equilibrium Green's function approach. While the molecule is placed on top of a dielectric layer (backed by a metallic gate) and weakly coupled between the Source/Drain electrodes, the charge stability diagram revealed the presence of individual charge states in the Coulomb Blockade regime. This gets affected significantly on addition of an another gate electrode placed on the top of the molecule. This modified double-gated geometry allows additional control of the total energy of the system that is sensitive to the individual charge states of the molecule which can be used as a charge sensing technique operational at room temperature.

  13. Electrically-gated near-field radiative thermal transistor

    E-Print Network [OSTI]

    Yang, Yue

    2015-01-01T23:59:59.000Z

    In this work, we propose a near-field radiative thermal transistor made of two graphene-covered silicon carbide (SiC) plates separated by a nanometer vacuum gap. Thick SiC plates serve as the thermal "source" and "drain", while graphene sheets function as the "gate" to modulate the near-field photon tunneling by tuning chemical potential with applied voltage biases symmetrically or asymmetrically. The radiative heat flux calculated from fluctuational electrodynamics significantly varies with graphene chemical potentials, which can tune the coupling between graphene plasmon across the vacuum gap. Thermal modulation, switching, and amplification, which are the key features required for a thermal transistor, are theoretically realized and analyzed. This work will pave the way to active thermal management, thermal circuits, and thermal computing.

  14. High Performance Polycrystalline SiGe Thin Film Transistors Using Al2O3 Gate Insulator

    E-Print Network [OSTI]

    1 High Performance Polycrystalline SiGe Thin Film Transistors Using Al2O3 Gate Insulator Zhonghe as the gate insulator for low temperature (SiGe thin film transistors (TFTs) has been between the Al2O3 and the SiGe channel layer is sufficiently passivated to make Al2O3 a better alternative

  15. Touch sensors based on planar liquid crystal-gated-organic field-effect transistors

    SciTech Connect (OSTI)

    Seo, Jooyeok; Lee, Chulyeon; Han, Hyemi; Lee, Sooyong; Nam, Sungho; Kim, Youngkyoo, E-mail: ykimm@knu.ac.kr [Organic Nanoelectronics Laboratory, Department of Chemical Engineering and Graduate School of Applied Chemical Engineering, Kyungpook National University, Daegu, 702-701 (Korea, Republic of); Kim, Hwajeong [Organic Nanoelectronics Laboratory, Department of Chemical Engineering and Graduate School of Applied Chemical Engineering, Kyungpook National University, Daegu, 702-701 (Korea, Republic of); Priority Research Center, Research Institute of Advanced Energy Technology, Kyungpook National University, Daegu, 702-701 (Korea, Republic of); Lee, Joon-Hyung [School of Materials Science and Engineering, Kyungpook National University, Daegu, 702-701 (Korea, Republic of); Park, Soo-Young; Kang, Inn-Kyu [Department of Polymer Science and Engineering and Graduate School of Applied Chemical Engineering, Kyungpook National University, Daegu, 702-701 (Korea, Republic of)

    2014-09-15T23:59:59.000Z

    We report a tactile touch sensor based on a planar liquid crystal-gated-organic field-effect transistor (LC-g-OFET) structure. The LC-g-OFET touch sensors were fabricated by forming the 10 ?m thick LC layer (4-cyano-4{sup ?}-pentylbiphenyl - 5CB) on top of the 50 nm thick channel layer (poly(3-hexylthiophene) - P3HT) that is coated on the in-plane aligned drain/source/gate electrodes (indium-tin oxide - ITO). As an external physical stimulation to examine the tactile touch performance, a weak nitrogen flow (83.3 ?l/s) was employed to stimulate the LC layer of the touch device. The LC-g-OFET device exhibited p-type transistor characteristics with a hole mobility of 1.5 cm{sup 2}/Vs, but no sensing current by the nitrogen flow touch was measured at sufficiently high drain (V{sub D}) and gate (V{sub G}) voltages. However, a clear sensing current signal was detected at lower voltages, which was quite sensitive to the combination of V{sub D} and V{sub G}. The best voltage combination was V{sub D} = ?0.2 V and V{sub G} = ?1 V for the highest ratio of signal currents to base currents (i.e., signal-to-noise ratio). The change in the LC alignment upon the nitrogen flow touch was assigned as the mechanism for the present LC-g-OFET touch sensors.

  16. Molecular doping for control of gate bias stress in organic thin film transistors

    SciTech Connect (OSTI)

    Hein, Moritz P., E-mail: hein@iapp.de; Lüssem, Björn; Jankowski, Jens; Tietze, Max L.; Riede, Moritz K. [Institut für Angewandte Photophysik, Technische Universität Dresden, George-Bähr-Straße 1, 01069 Dresden (Germany)] [Institut für Angewandte Photophysik, Technische Universität Dresden, George-Bähr-Straße 1, 01069 Dresden (Germany); Zakhidov, Alexander A. [Fraunhofer COMEDD, Maria-Reiche-Str. 2, 01109 Dresden (Germany)] [Fraunhofer COMEDD, Maria-Reiche-Str. 2, 01109 Dresden (Germany); Leo, Karl [Institut für Angewandte Photophysik, Technische Universität Dresden, George-Bähr-Straße 1, 01069 Dresden (Germany) [Institut für Angewandte Photophysik, Technische Universität Dresden, George-Bähr-Straße 1, 01069 Dresden (Germany); Fraunhofer COMEDD, Maria-Reiche-Str. 2, 01109 Dresden (Germany)

    2014-01-06T23:59:59.000Z

    The key active devices of future organic electronic circuits are organic thin film transistors (OTFTs). Reliability of OTFTs remains one of the most challenging obstacles to be overcome for broad commercial applications. In particular, bias stress was identified as the key instability under operation for numerous OTFT devices and interfaces. Despite a multitude of experimental observations, a comprehensive mechanism describing this behavior is still missing. Furthermore, controlled methods to overcome these instabilities are so far lacking. Here, we present the approach to control and significantly alleviate the bias stress effect by using molecular doping at low concentrations. For pentacene and silicon oxide as gate oxide, we are able to reduce the time constant of degradation by three orders of magnitude. The effect of molecular doping on the bias stress behavior is explained in terms of the shift of Fermi Level and, thus, exponentially reduced proton generation at the pentacene/oxide interface.

  17. TIME DEPENDENT BREAKDOWN OF GATE OXIDE AND PREDICTION OF OXIDE GATE LIFETIME

    E-Print Network [OSTI]

    Mahmoodi, Hamid

    TIME DEPENDENT BREAKDOWN OF GATE OXIDE AND PREDICTION OF OXIDE GATE LIFETIME A thesis submitted Masters of Science In Engineering: Embedded System by Bin Wu San Francisco, California May, 2012 #12;CERTIFICATION OF APPROVAL I certify that I have read Time dependent Breakdown of Gate Oxide and Prediction

  18. Electrolyte-gated graphene field-effect transistors : modeling and applications

    E-Print Network [OSTI]

    Mackin, Charles Edward

    2015-01-01T23:59:59.000Z

    This work presents a model for electrolyte-gated graphene field-effect transistors (EGFETs) that incorporates the effects of the double layer capacitance and the quantum capacitance of graphene. The model is validated ...

  19. pH sensing properties of graphene solution-gated field-effect transistors

    E-Print Network [OSTI]

    Mailly-Giacchetti, Benjamin

    2013-01-01T23:59:59.000Z

    The use of graphene grown by chemical vapor deposition to fabricate solution-gated field-effect transistors (SGFET) on different substrates is reported. SGFETs were fabricated using graphene transferred on poly(ethylene ...

  20. All-Optical Switch and Transistor Gated by One Stored Photon

    E-Print Network [OSTI]

    Chen, Wenlan

    The realization of an all-optical transistor, in which one “gate” photon controls a “source” light beam, is a long-standing goal in optics. By stopping a light pulse in an atomic ensemble contained inside an optical ...

  1. Surface mobility near threshold and other parameters of insulated gate field effect transistors

    E-Print Network [OSTI]

    Gnadinger, Alfred P.

    1970-01-01T23:59:59.000Z

    SURFACE MOBILITY NEAR THRESHOLD AND OTHER PARAMETERS OF INSULATED GATE FIELD EFFECT TRANSISTORS BY Alfred P. Gnadinger Dipl. El. Ing. ETH Swiss Federal Institute of Technology, Zurich, 1965 M.S.E.E, University of Kansas, Lawrence, 1968... Committee: May, 1970 RD0107 4S0S0 TO MY WIFE AND OUR PARENTS i ABSTRACT The mobility of the mobile carriers in the inversion layer of an Insulated Gate Field Effect Transistor (IGFET) has been investigated with particular...

  2. Influence of Electrolyte Composition on Liquid-Gated Carbon Nanotube and Graphene Transistors

    E-Print Network [OSTI]

    Dekker, Cees

    Influence of Electrolyte Composition on Liquid-Gated Carbon Nanotube and Graphene Transistors Iddo-walled carbon nanotubes (SWNTs) and graphene can function as highly sensitive nanoscale (bio)sensors in solution. Here, we compare experimentally how SWNT and graphene transistors respond to changes in the composition

  3. AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors using barium strontium titanate

    E-Print Network [OSTI]

    York, Robert A.

    AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors using barium strontium; published 13 October 2004) Use of high-k gate dielectrics in AlGaN/GaN heterostructure field transconductance and pinchoff voltage. To achieve this, AlGaN/GaN metal-oxide-semiconductor heterostructure field

  4. Native point defects in yttria and relevance to its use as a high-dielectric-constant gate oxide material: First-principles study

    E-Print Network [OSTI]

    Ceder, Gerbrand

    a promising gate oxide material to replace silicon dioxide in metal-oxide- semiconductor devices. Using-earth-doped lasers. Recently, Y2O3 has re- ceived attention as a promising candidate for replacing sili- con dioxide SiO2 as a gate dielectric material in metal- oxide-semiconductor MOS transistors.1­10 The continual

  5. Graphene field-effect transistors based on boron nitride gate dielectrics Inanc Meric1

    E-Print Network [OSTI]

    Shepard, Kenneth

    Graphene field-effect transistors based on boron nitride gate dielectrics Inanc Meric1 , Cory Dean1, 10027 Tel: (212) 854-2529, Fax: (212) 932-9421, Email: shepard@ee.columbia.edu Abstract Graphene field of graphene, as the gate dielectric. The devices ex- hibit mobility values exceeding 10,000 cm2 /V

  6. Near room temperature lithographically processed metal-oxide transistors

    E-Print Network [OSTI]

    Tang, Hui, M. Eng. Massachusetts Institute of Technology

    2008-01-01T23:59:59.000Z

    A fully lithographic process at near-room-temperature was developed for the purpose of fabricating transistors based on metal-oxide channel materials. The combination of indium tin oxide (ITO) as the source/drain electrodes, ...

  7. Coherent molecular transistor: Control through variation of the gate wave function

    SciTech Connect (OSTI)

    Ernzerhof, Matthias, E-mail: Matthias.Ernzerhof@UMontreal.ca [Département de Chimie, Université de Montréal, C.P. 6128 Succursale A, Montréal, Quebec H3C 3J7 (Canada)] [Département de Chimie, Université de Montréal, C.P. 6128 Succursale A, Montréal, Quebec H3C 3J7 (Canada)

    2014-03-21T23:59:59.000Z

    In quantum interference transistors (QUITs), the current through the device is controlled by variation of the gate component of the wave function that interferes with the wave function component joining the source and the sink. Initially, mesoscopic QUITs have been studied and more recently, QUITs at the molecular scale have been proposed and implemented. Typically, in these devices the gate lead is subjected to externally adjustable physical parameters that permit interference control through modifications of the gate wave function. Here, we present an alternative model of a molecular QUIT in which the gate wave function is directly considered as a variable and the transistor operation is discussed in terms of this variable. This implies that we specify the gate current as well as the phase of the gate wave function component and calculate the resulting current through the source-sink channel. Thus, we extend on prior works that focus on the phase of the gate wave function component as a control parameter while having zero or certain discrete values of the current. We address a large class of systems, including finite graphene flakes, and obtain analytic solutions for how the gate wave function controls the transistor.

  8. Effect of Temperature on GaGdO/GaN Metal Oxide Semiconductor Field Effect Transistors

    SciTech Connect (OSTI)

    Abernathy, C.R.; Baca, A.; Chu, S.N.G.; Hong, M.; Lothian, J.R.; Marcus, M.A.; Pearton, S.J.; Ren, F.; Schurman, M.J.

    1998-10-14T23:59:59.000Z

    GaGdO was deposited on GaN for use as a gate dielectric in order to fabricate a depletion metal oxide semiconductor field effect transistor (MOSFET). This is the fmt demonstration of such a device in the III-Nitride system. Analysis of the effect of temperature on the device shows that gate leakage is significantly reduced at elevated temperature relative to a conventional metal semiconductor field effeet transistor (MESFET) fabricated on the same GaN layer. MOSFET device operation in fact improved upon heating to 400 C. Modeling of the effeet of temperature on contact resistance suggests that the improvement is due to a reduction in the parasitic resistances present in the device.

  9. Choosing a gate dielectric for graphene based transistors

    E-Print Network [OSTI]

    Hsu, Pei-Lan, M. Eng. Massachusetts Institute of Technology

    2008-01-01T23:59:59.000Z

    Much attention has recently been focused on graphene as an alternative semiconductor to silicon. Transistors with graphene conduction channels have only recently been fabricated and their performance remains to be optimized. ...

  10. High-performance carbon-nanotube-based complementary field-effect-transistors and integrated circuits with yttrium oxide

    SciTech Connect (OSTI)

    Liang, Shibo; Zhang, Zhiyong, E-mail: zyzhang@pku.edu.cn; Si, Jia; Zhong, Donglai; Peng, Lian-Mao, E-mail: lmpeng@pku.edu.cn [Key Laboratory for the Physics and Chemistry of Nanodevices, Department of Electronics, Peking University, Beijing 100871 (China)

    2014-08-11T23:59:59.000Z

    High-performance p-type carbon nanotube (CNT) transistors utilizing yttrium oxide as gate dielectric are presented by optimizing oxidization and annealing processes. Complementary metal-oxide-semiconductor (CMOS) field-effect-transistors (FETs) are then fabricated on CNTs, and the p- and n-type devices exhibit symmetrical high performances, especially with low threshold voltage near to zero. The corresponding CMOS CNT inverter is demonstrated to operate at an ultra-low supply voltage down to 0.2?V, while displaying sufficient voltage gain, high noise margin, and low power consumption. Yttrium oxide is proven to be a competitive gate dielectric for constructing high-performance CNT CMOS FETs and integrated circuits.

  11. Case Studies on Variation Tolerant and Low Power Design Using Planar Asymmetric Double Gate Transistor

    E-Print Network [OSTI]

    Singh, Amrinder

    2011-10-21T23:59:59.000Z

    . ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? Front gate Source Back gate Drain n+n+ p- Body Fig. I.1. Planar double gate NFET DGFETs can be broadly classified into two categories: ? Symmetric: In symmetrical DGFET, the front and the back gate are identical, having same oxide thickness... nanometer regime. In short channel devices, Vth decreases with reduction in channel length. This phenomenon is also known as Vth roll-off. It can lead to significant increase in leakage power. Drain induced barrier lowering (DIBL) is another phenomenon...

  12. Dirac point and transconductance of top-gated graphene field-effect transistors operating at elevated temperature

    SciTech Connect (OSTI)

    Hopf, T.; Vassilevski, K. V., E-mail: k.vasilevskiy@ncl.ac.uk; Escobedo-Cousin, E.; King, P. J.; Wright, N. G.; O'Neill, A. G.; Horsfall, A. B.; Goss, J. P. [School of Electrical and Electronic Engineering, Newcastle University, Newcastle upon Tyne NE1 7RU (United Kingdom); Wells, G. H.; Hunt, M. R. C. [Department of Physics, Durham University, Durham DH1 3LE (United Kingdom)

    2014-10-21T23:59:59.000Z

    Top-gated graphene field-effect transistors (GFETs) have been fabricated using bilayer epitaxial graphene grown on the Si-face of 4H-SiC substrates by thermal decomposition of silicon carbide in high vacuum. Graphene films were characterized by Raman spectroscopy, Atomic Force Microscopy, Scanning Tunnelling Microscopy, and Hall measurements to estimate graphene thickness, morphology, and charge transport properties. A 27?nm thick Al?O? gate dielectric was grown by atomic layer deposition with an e-beam evaporated Al seed layer. Electrical characterization of the GFETs has been performed at operating temperatures up to 100?°C limited by deterioration of the gate dielectric performance at higher temperatures. Devices displayed stable operation with the gate oxide dielectric strength exceeding 4.5 MV/cm at 100?°C. Significant shifting of the charge neutrality point and an increase of the peak transconductance were observed in the GFETs as the operating temperature was elevated from room temperature to 100?°C.

  13. Spin transistor operation driven by the Rashba spin-orbit coupling in the gated nanowire

    SciTech Connect (OSTI)

    Wójcik, P.; Adamowski, J., E-mail: adamowski@fis.agh.edu.pl; Spisak, B. J.; Wo?oszyn, M. [Faculty of Physics and Applied Computer Science, AGH University of Science and Technology, al. Mickiewicza 30, Kraków (Poland)

    2014-03-14T23:59:59.000Z

    A theoretical description has been proposed for the operation of the spin transistor in the gate-controlled InAs nanowire. The calculated current-voltage characteristics show that the electron current flowing from the source (spin injector) to the drain (spin detector) oscillates as a function of the gate voltage, which results from the precession of the electron spin caused by the Rashba spin-orbit interaction in the vicinity of the gate. We have studied the operation of the spin transistor under the following conditions: (A) the full spin polarization of electrons in the contacts, zero temperature, and the single conduction channel corresponding to the lowest-energy subband of the transverse motion and (B) the partial spin polarization of the electrons in the contacts, the room temperature, and the conduction via many transverse subbands taken into account. For case (A), the spin-polarized current can be switched on/off by the suitable tuning of the gate voltage, for case (B) the current also exhibits the pronounced oscillations but with no-zero minimal values. The computational results obtained for case (B) have been compared with the recent experimental data and a good agreement has been found.

  14. Self-heating simulation of GaN-based metal-oxide-semiconductor high-electron-mobility transistors including hot electron

    E-Print Network [OSTI]

    Ye, Peide "Peter"

    Self-heating simulation of GaN-based metal-oxide-semiconductor high-electron-mobility transistors the results of self-heating simulations of the GaN-based MOS-HEMTs, including hot electron and quantum effects of the gate and source/drain extension lengths on both the output performance and self-heating is discussed

  15. Naphthacene Based Organic Thin Film Transistor With Rare Earth Oxide

    SciTech Connect (OSTI)

    Konwar, K. [Department of Physics, Digboi College, Digboi-786171, Assam (India); Baishya, B. [Department of Physics, Dibrugarh University, Dibrugarh-786004, Assam (India)

    2010-12-01T23:59:59.000Z

    Naphthacene based organic thin film transistors (OTFTs) have been fabricated using La{sub 2}O{sub 3}, as the gate insulator. All the OTFTs have been fabricated by the process of thermal evaporation in vacuum on perfectly cleaned glass substrates with aluminium as source-drain and gate electrodes. The naphthacene film morphology on the glass substrate has been studied by XRD and found to be polycrystalline in nature. The field effect mobility, output resistance, amplification factor, transconductance and gain bandwidth product of the OTFTs have been calculated by using theoretical TFT model. The highest value of field effect mobility is found to be 0.07x10{sup -3} cm{sup 2}V{sup -1}s{sup -1} for the devices annealed in vacuum at 90 deg. C for 5 hours.

  16. Anomalous electron transport in back-gated field-effect transistors with TiTe2 semimetal thin-film channels

    E-Print Network [OSTI]

    Anomalous electron transport in back-gated field-effect transistors with TiTe2 semimetal thin. The exfoliated crystalline TiTe2 films were used as the channel layers in the back-gated field-effect transistors-voltage characteristics revealed strongly non-linear behavior with signatures of the source-drain threshold voltage

  17. P-type and N-type multi-gate polycrystalline silicon vertical thin film transistors based on low-temperature technology

    E-Print Network [OSTI]

    Boyer, Edmond

    is obtained. P-type and N-type vertical TFTs have shown symmetric electrical characteristics. DifferentP-type and N-type multi-gate polycrystalline silicon vertical thin film transistors based on low) ABSTRACT P-type and N-type multi-gate vertical thin film transistors (vertical TFTs) have been fabricated

  18. Characterization of the pentacene thin-film transistors with an epoxy resin-based polymeric gate insulator

    E-Print Network [OSTI]

    Boyer, Edmond

    Characterization of the pentacene thin-film transistors with an epoxy resin-based polymeric gate seeking desirable semi- conductor/insulator combinations [3]. In this study, we adopted an epoxy resin fabricated and characterized. SU-8, a reliable epoxy-based pho- toresist, is tested as a potential highly

  19. Contact resistance improvement using interfacial silver nanoparticles in amorphous indium-zinc-oxide thin film transistors

    SciTech Connect (OSTI)

    Xu, Rui; He, Jian [School of Engineering, Brown University, Providence, Rhode Island 02912 (United States); State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China (UESTC), Chengdu 610054 (China); Song, Yang [Department of Physics, Brown University, Providence, Rhode Island 02912 (United States); Li, Wei [State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China (UESTC), Chengdu 610054 (China); Zaslavsky, A. [School of Engineering, Brown University, Providence, Rhode Island 02912 (United States); Department of Physics, Brown University, Providence, Rhode Island 02912 (United States); Paine, D. C., E-mail: David-Paine@brown.edu [School of Engineering, Brown University, Providence, Rhode Island 02912 (United States)

    2014-09-01T23:59:59.000Z

    We describe an approach to reduce the contact resistance at compositional conducting/semiconducting indium-zinc-oxide (IZO) homojunctions used for contacts in thin film transistors (TFTs). By introducing silver nanoparticles (Ag NPs) at the homojunction interface between the conducting IZO electrodes and the amorphous IZO channel, we reduce the specific contact resistance, obtained by transmission line model measurements, down to ?10{sup ?2?}??cm{sup 2}, ?3 orders of magnitude lower than either NP-free homojunction contacts or solid Ag metal contacts. The resulting back-gated TFTs with Ag NP contacts exhibit good field effect mobility of ?27?cm{sup 2}/V?s and an on/off ratio >10{sup 7}. We attribute the improved contact resistance to electric field concentration by the Ag NPs.

  20. A Strained Organic Field-Effect-Transistor with a Gate-Tunable Superconducting Channel

    E-Print Network [OSTI]

    Hiroshi M. Yamamoto; Masaki Nakano; Masayuki Suda; Yoshihiro Iwasa; Masashi Kawasaki; Reizo Kato

    2013-09-02T23:59:59.000Z

    In state-of-the-art silicon devices, mobility of the carrier is enhanced by the lattice strain from the back substrate. Such an extra control of device performance is significant in realizing high performance computing and should be valid for electric-field-induced superconducting devices, too. However, so far, the carrier density is the sole parameter for field-induced superconducting interfaces. Here we show an active organic superconducting field-effect-transistor whose lattice is modulated by the strain from the substrate. The soft organic lattice allows tuning of the strain by a choice of the back substrate to make an induced superconducting state accessible at low temperature with a paraelectric solid gate. An active three terminal Josephson junction device thus realized is useful both in advanced computing and in elucidating a direct connection between filling-controlled and bandwidth-controlled superconducting phases in correlated materials.

  1. A Low Temperature Fully Lithographic Process For Metal–Oxide Field-Effect Transistors

    E-Print Network [OSTI]

    Sodini, Charles G.

    We report a low temperature ( ~ 100à °C) lithographic method for fabricating hybrid metal oxide/organic field-effect transistors (FETs) that combine a zinc-indium-oxide (ZIO) semiconductor channel and organic, parylene, ...

  2. Poly(methyl methacrylate) as a self-assembled gate dielectric for graphene field-effect transistors

    SciTech Connect (OSTI)

    Sanne, A.; Movva, H. C. P.; Kang, S.; McClellan, C.; Corbet, C. M.; Banerjee, S. K. [Microelectronics Research Center, University of Texas, Austin, Texas 78758 (United States)

    2014-02-24T23:59:59.000Z

    We investigate poly(methyl methacrylate) (PMMA) as a low thermal budget organic gate dielectric for graphene field effect-transistors (GFETs) based on a simple process flow. We show that high temperature baking steps above the glass transition temperature (?130?°C) can leave a self-assembled, thin PMMA film on graphene, where we get a gate dielectric almost for “free” without additional atomic layer deposition type steps. Electrical characterization of GFETs with PMMA as a gate dielectric yields a dielectric constant of k?=?3.0. GFETs with thinner PMMA dielectrics have a lower dielectric constant due to decreased polarization arising from neutralization of dipoles and charged carriers as baking temperatures increase. The leakage through PMMA gate dielectric increases with decreasing dielectric thickness and increasing electric field. Unlike conventional high-k gate dielectrics, such low-k organic gate dielectrics are potentially attractive for devices such as the proposed Bilayer pseudoSpin Field-Effect Transistor or flexible high speed graphene electronics.

  3. Single trap dynamics in electrolyte-gated Si-nanowire field effect transistors

    SciTech Connect (OSTI)

    Pud, S.; Li, J.; Offenhäusser, A.; Vitusevich, S. A., E-mail: s.vitusevich@fz-juelich.de [Peter Grünberg Institute (PGI-8), Forschungszentrum Jülich, 52425 Jülich (Germany); Gasparyan, F. [Peter Grünberg Institute (PGI-8), Forschungszentrum Jülich, 52425 Jülich (Germany); Department of Semiconductor Physics and Microelectronics, Yerevan State University, 1 Alex Manoogian St., 0025 Yerevan (Armenia); Petrychuk, M. [Radiophysics Faculty, T. Shevchenko National University of Kyiv, 60 Volodymyrska St., 01601 Kyiv (Ukraine)

    2014-06-21T23:59:59.000Z

    Liquid-gated silicon nanowire (NW) field effect transistors (FETs) are fabricated and their transport and dynamic properties are investigated experimentally and theoretically. Random telegraph signal (RTS) fluctuations were registered in the nanolength channel FETs and used for the experimental and theoretical analysis of transport properties. The drain current and the carrier interaction processes with a single trap are analyzed using a quantum-mechanical evaluation of carrier distribution in the channel and also a classical evaluation. Both approaches are applied to treat the experimental data and to define an appropriate solution for describing the drain current behavior influenced by single trap resulting in RTS fluctuations in the Si NW FETs. It is shown that quantization and tunneling effects explain the behavior of the electron capture time on the single trap. Based on the experimental data, parameters of the single trap were determined. The trap is located at a distance of about 2?nm from the interface Si/SiO{sub 2} and has a repulsive character. The theory of dynamic processes in liquid-gated Si NW FET put forward here is in good agreement with experimental observations of transport in the structures and highlights the importance of quantization in carrier distribution for analyzing dynamic processes in the nanostructures.

  4. Enhancing controllability and stability of bottom-gated graphene thin-film transistors by passivation with methylamine

    SciTech Connect (OSTI)

    Drapeko, Maksim, E-mail: maksim.drapeko.10@ucl.ac.uk, E-mail: md584@cam.ac.uk [London Centre for Nanotechnology, University College London, 17-19 Gordon Street, WC1H 0AH London, United Kingdom and Centre for Advanced Photonics and Electronics, Department of Engineering, Cambridge University, 9 J J Thomson Avenue, CB3 0HE Cambridge (United Kingdom)

    2014-06-02T23:59:59.000Z

    This paper is intended to aid to bridge the gap between chemistry and electronic engineering. In this work, the fabrication of chemical vapour deposited graphene field-effect transistors employing silicon-nitride (Si{sub 3}N{sub 4}) gate dielectric is presented, showing originally p-type channel conduction due to ambient impurities yielding uncontrollable behaviour. Vacuum annealing has been performed to balance off hole and electron conduction in the channel, leading to the observation of the Dirac point and therefore improving controllability. Non-covalent functionalisation by methylamine has been performed for passivation and stability reasons yielding electron mobility of 4800?cm{sup 2}/V?s and hole mobility of 3800?cm{sup 2}/V?s as well as stabilised controllable behaviour of a bottom-gated transistor. The introduction of interface charge following the non-covalent functionalisation as well as the charge balance have been discussed and analysed.

  5. Si and SiGe based double top gated accumulation mode single electron transistors for quantum bits.

    SciTech Connect (OSTI)

    Wendt, Joel Robert; Ten Eyck, Gregory A.; Childs, Kenton David; Celler, G. (SOITEC); Eng, Kevin; Eriksson, Mark A. (University of Wisconsin); Kluskiewicz, Dan (University of New Mexico); Stevens, Jeffrey; Carroll, Malcolm S.; Nordberg, Eric; Lilly, Michael Patrick; Lemp, Thomas; Sheng, Josephine Juin-Jye

    2008-10-01T23:59:59.000Z

    There is significant interest in forming quantum bits (qubits) out of single electron devices for quantum information processing (QIP). Information can be encoded using properties like charge or spin. Spin is appealing because it is less strongly coupled to the solid-state environment so it is believed that the quantum state can better be preserved over longer times (i.e., that is longer decoherence times may be achieved). Long spin decoherence times would allow more complex qubit operations to be completed with higher accuracy. Recently spin qubits were demonstrated by several groups using electrostatically gated modulation doped GaAs double quantum dots (DQD) [1], which represented a significant breakthrough in the solid-state field. Although no Si spin qubit has been demonstrated to date, work on Si and SiGe based spin qubits is motivated by the observation that spin decoherence times can be significantly longer than in GaAs. Spin decoherence times in GaAs are in part limited by the random spectral diffusion of the non-zero nuclear spins of the Ga and As that couple to the electron spin through the hyperfine interaction. This effect can be greatly suppressed by using a semiconductor matrix with a near zero nuclear spin background. Near zero nuclear spin backgrounds can be engineered using Si by growing {sup 28}Si enriched epitaxy. In this talk, we will present fabrication details and electrical transport results of an accumulation mode double top gated Si metal insulator semiconductor (MIS) nanostructure, Fig 1 (a) & (b). We will describe how this single electron device structure represent a path towards forming a Si based spin qubit similar in design as that demonstrated in GaAs. Potential advantages of this novel qubit structure relative to previous approaches include the combination of: no doping (i.e., not modulation doped); variable two-dimensional electron gas (2DEG) density; CMOS compatible processes; and relatively small vertical length scales to achieve smaller dots. A primary concern in this structure is defects at the insulator-silicon interface. The Sandia National Laboratories 0.35 {micro}m fab line was used for critical processing steps including formation of the gate oxide to examine the utility of a standard CMOS quality oxide silicon interface for the purpose of fabricating Si qubits. Large area metal oxide silicon (MOS) structures showed a peak mobility of 15,000 cm{sup 2}/V-s at electron densities of {approx}1 x 10{sup 12} cm{sup -2} for an oxide thickness of 10 nm. Defect density measured using standard C-V techniques was found to be greater with decreasing oxide thickness suggesting a device design trade-off between oxide thickness and quantum dot size. The quantum dot structure is completed using electron beam lithography and poly-silicon etch to form the depletion gates, Fig 1 (a). The accumulation gate is added by introducing a second insulating Al{sub 2}O{sub 3} layer, deposited by atomic layer deposition, followed by an Al top gate deposition, Fig. 1 (b). Initial single electron transistor devices using SiO{sub 2} show significant disorder in structures with relatively large critical dimensions of the order of 200-300 nm, Fig 2. This is not uncommon for large silicon structures and has been cited in the literature [2]. Although smaller structures will likely minimize the effect of disorder and well controlled small Si SETs have been demonstrated [3], the design constraints presented by disorder combined with long term concerns about effects of defects on spin decoherence time (e.g., paramagnetic centers) motivates pursuit of a 2nd generation structure that uses a compound semiconductor approach, an epitaxial SiGe barrier as shown in Fig. 2 (c). SiGe may be used as an electron barrier when combined with tensilely strained Si. The introduction of strained-Si into the double top gated device structure, however, represents additional fabrication challenges. Thermal budget is potentially constrained due to concerns related to strain relaxation. Fabrication details related to the introduction of st

  6. Looking at Transistor Gate Oxide Formation in Real Time

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    AFDC Printable Version Share this resource Send a link to EERE: Alternative Fuels Data Center Home Page to someone by E-mail Share EERE: Alternative Fuels Data Center Home Page on Facebook Tweet about EERE: Alternative Fuels Data Center Home Page on Twitter Bookmark EERE: Alternative1 First Use of Energy for All Purposes (Fuel and Nonfuel), 2002; Level: National5Sales for4,645U.S. DOE Office of Science (SC)Integrated Codes |Is Your HomeLatestCenterLogging in LoggingLong-TermJefferson

  7. Looking at Transistor Gate Oxide Formation in Real Time

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    AFDC Printable Version Share this resource Send a link to EERE: Alternative Fuels Data Center Home Page to someone by E-mail Share EERE: Alternative Fuels Data Center Home Page on Facebook Tweet about EERE: Alternative Fuels Data Center Home Page on Twitter Bookmark EERE: Alternative1 First Use of Energy for All Purposes (Fuel and Nonfuel), 2002; Level: National5Sales for4,645U.S. DOE Office of Science (SC)Integrated Codes |Is Your HomeLatestCenterLogging in LoggingLong-TermJeffersonLooking

  8. Looking at Transistor Gate Oxide Formation in Real Time

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    AFDC Printable Version Share this resource Send a link to EERE: Alternative Fuels Data Center Home Page to someone by E-mail Share EERE: Alternative Fuels Data Center Home Page on Facebook Tweet about EERE: Alternative Fuels Data Center Home Page on Twitter Bookmark EERE: Alternative1 First Use of Energy for All Purposes (Fuel and Nonfuel), 2002; Level: National5Sales for4,645U.S. DOE Office of Science (SC)Integrated Codes |Is Your HomeLatestCenterLogging in

  9. Looking at Transistor Gate Oxide Formation in Real Time

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    AFDC Printable Version Share this resource Send a link to EERE: Alternative Fuels Data Center Home Page to someone by E-mail Share EERE: Alternative Fuels Data Center Home Page on Facebook Tweet about EERE: Alternative Fuels Data Center Home Page on Twitter Bookmark EERE: Alternative1 First Use of Energy for All Purposes (Fuel and Nonfuel), 2002; Level: National5Sales for4,645U.S. DOEThe Bonneville PowerCherries 82981-1cnHigh SchoolIn12electron 9 5Let usNucleartearingLongTermSchool

  10. Looking at Transistor Gate Oxide Formation in Real Time

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    AFDC Printable Version Share this resource Send a link to EERE: Alternative Fuels Data Center Home Page to someone by E-mail Share EERE: Alternative Fuels Data Center Home Page on Facebook Tweet about EERE: Alternative Fuels Data Center Home Page on Twitter Bookmark EERE: Alternative1 First Use of Energy for All Purposes (Fuel and Nonfuel), 2002; Level: National5Sales for4,645U.S. DOEThe Bonneville PowerCherries 82981-1cnHigh SchoolIn12electron 9 5Let usNucleartearingLongTermSchoolLooking at

  11. Looking at Transistor Gate Oxide Formation in Real Time

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    AFDC Printable Version Share this resource Send a link to EERE: Alternative Fuels Data Center Home Page to someone by E-mail Share EERE: Alternative Fuels Data Center Home Page on Facebook Tweet about EERE: Alternative Fuels Data Center Home Page on Twitter Bookmark EERE: Alternative1 First Use of Energy for All Purposes (Fuel and Nonfuel), 2002; Level: National5Sales for4,645U.S. DOEThe Bonneville PowerCherries 82981-1cnHigh SchoolIn12electron 9 5Let usNucleartearingLongTermSchoolLooking

  12. Looking at Transistor Gate Oxide Formation in Real Time

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    AFDC Printable Version Share this resource Send a link to EERE: Alternative Fuels Data Center Home Page to someone by E-mail Share EERE: Alternative Fuels Data Center Home Page on Facebook Tweet about EERE: Alternative Fuels Data Center Home Page on Twitter Bookmark EERE: Alternative1 First Use of Energy for All Purposes (Fuel and Nonfuel), 2002; Level: National5Sales for4,645U.S. DOEThe Bonneville PowerCherries 82981-1cnHigh SchoolIn12electron 9 5Let usNucleartearingLongTermSchoolLookingLooking

  13. Looking at Transistor Gate Oxide Formation in Real Time

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    AFDC Printable Version Share this resource Send a link to EERE: Alternative Fuels Data Center Home Page to someone by E-mail Share EERE: Alternative Fuels Data Center Home Page on Facebook Tweet about EERE: Alternative Fuels Data Center Home Page on Twitter Bookmark EERE: Alternative1 First Use of Energy for All Purposes (Fuel and Nonfuel), 2002; Level: National5Sales for4,645U.S. DOEThe Bonneville PowerCherries 82981-1cnHigh SchoolIn12electron 9 5Let

  14. Electron Transport Behavior on Gate Length Scaling in Sub-50 nm GaAs Metal Semiconductor Field Effect Transistors

    SciTech Connect (OSTI)

    Han, Jaeheon [Department of Electronic Engineering, Kangnam University, 111 Gugal-dong, Giheung-gu, Yongin-city, Gyeonggi-do, Korea 446-702 (Korea, Republic of)

    2011-12-23T23:59:59.000Z

    Short channel GaAs Metal Semiconductor Field Effect Transistors (MESFETs) have been fabricated with gate length to 20 nm, in order to examine the characteristics of sub-50 nm MESFET scaling. Here the rise in the measured transconductance is mainly attributed to electron velocity overshoot. For gate lengths below 40 nm, however, the transconductance drops suddenly. The behavior of velocity overshoot and its degradation is investigated and simulated by using a transport model based on the retarded Langevin equation (RLE). This indicates the existence of a minimum acceleration length needed for the carriers to reach the overshoot velocity. The argument shows that the source resistance must be included as an internal element, or appropriate boundary condition, of relative importance in any model where the gate length is comparable to the inelastic mean free path of the carriers.

  15. Physics of gate leakage current in N-polar InAlN/GaN heterojunction field effect transistors

    SciTech Connect (OSTI)

    Goswami, Arunesh; Trew, Robert J.; Bilbro, Griff L. [ECE Department, Box 7911, North Carolina State University, Raleigh, North Carolina 27695-7911 (United States)

    2014-10-28T23:59:59.000Z

    A physics based model of the gate leakage current in N-polar InAlN/GaN heterojunction field effect transistors is demonstrated. The model is based on the space charge limited current flow dominated by the effects of deep traps in the InAlN surface layer. The model predicts accurately the gate-leakage measurement data of the N-polar InAlN/GaN device with InAlN cap layer. In the pinch-off state, the gate leakage current conduction through the surface of the device in the drain access region dominates the current flow through the two dimensional electron gas channel. One deep trap level and two levels of shallow traps are extracted by fitting the model results with measurement data.

  16. Tradeoffs between Gate Oxide Leakage and Delay for Dual ToxToxTox Circuits

    E-Print Network [OSTI]

    Sapatnekar, Sachin

    lead to gate oxide leakage current (Igate), are coming into play from the 90nm node onwards. AccordingTradeoffs between Gate Oxide Leakage and Delay for Dual ToxToxTox Circuits Anup Kumar Sultania Department of ECE University of Minnesota Minneapolis, MN 55455. sachin@ece.umn.edu ABSTRACT Gate oxide

  17. Reconciliation of Different Gate-Voltage Dependencies of 1/f Noise in n-MOS and p-MOS Transistors

    E-Print Network [OSTI]

    Scofield, John H.

    approaches the valence band edge. It is evidently these differences in Dt(E) that lead to differences noise of metal- oxide-semiconductor field-effect transistors (MOSFETs) suggests that their noise of the noise of many fluctuators leads to the ubiquitous inverse frequency dependence commonly observed

  18. Thin Film Transistors On Plastic Substrates

    DOE Patents [OSTI]

    Carey, Paul G. (Mountain View, CA); Smith, Patrick M. (San Ramon, CA); Sigmon, Thomas W. (Portola Valley, CA); Aceves, Randy C. (Livermore, CA)

    2004-01-20T23:59:59.000Z

    A process for formation of thin film transistors (TFTs) on plastic substrates replaces standard thin film transistor fabrication techniques, and uses sufficiently lower processing temperatures so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The silicon based thin film transistor produced by the process includes a low temperature substrate incapable of withstanding sustained processing temperatures greater than about 250.degree. C., an insulating layer on the substrate, a layer of silicon on the insulating layer having sections of doped silicon, undoped silicon, and poly-silicon, a gate dielectric layer on the layer of silicon, a layer of gate metal on the dielectric layer, a layer of oxide on sections of the layer of silicon and the layer of gate metal, and metal contacts on sections of the layer of silicon and layer of gate metal defining source, gate, and drain contacts, and interconnects.

  19. Part I:Part I: Degradation in 3.2 nm Gate Oxides:Degradation in 3.2 nm Gate Oxides: Effects on Inverter Performance and MOSFETEffects on Inverter Performance and MOSFET

    E-Print Network [OSTI]

    Anlage, Steven

    1 Part I:Part I: Degradation in 3.2 nm Gate Oxides:Degradation in 3.2 nm Gate Oxides: Effects--Thin GateThin Gate Oxide DegradationOxide Degradation #12;2 AcknowledgmentsAcknowledgments University), ECE Miles Wiscombe (UG), ECE #12;3 Part I:Part I: Degradation in 3.2 nm Gate Oxides:Degradation in 3

  20. Under-gate defect formation in Ni-gate AlGaN/GaN high electron mobility transistors

    E-Print Network [OSTI]

    Florida, University of

    energy loss spectroscopy [23]. In contrast, HEMTs utilizing a Pt liner layer did not show the same gate electrical contact to the 2DEG. However, when stressing occurs in O2 or air, the O2 present reacts

  1. Ballistic performance comparison of monolayer transition metal dichalcogenide MX{sub 2} (M = Mo, W; X = S, Se, Te) metal-oxide-semiconductor field effect transistors

    SciTech Connect (OSTI)

    Chang, Jiwon; Register, Leonard F.; Banerjee, Sanjay K. [Microelectronics Research Center, The University of Texas at Austin, Austin, Texas 78758 (United States)

    2014-02-28T23:59:59.000Z

    We study the transport properties of monolayer MX{sub 2} (M?=?Mo, W; X?=?S, Se, Te) n- and p-channel metal-oxide-semiconductor field effect transistors (MOSFETs) using full-band ballistic non-equilibrium Green's function simulations with an atomistic tight-binding Hamiltonian with hopping potentials obtained from density functional theory. We discuss the subthreshold slope, drain-induced barrier lowering (DIBL), as well as gate-induced drain leakage (GIDL) for different monolayer MX{sub 2} MOSFETs. We also report the possibility of negative differential resistance behavior in the output characteristics of nanoscale monolayer MX{sub 2} MOSFETs.

  2. 1282 IEEE ELECTRON DEVICE LETTERS, VOL. 33, NO. 9, SEPTEMBER 2012 Top-Gate GaN Thin-Film Transistors Based

    E-Print Network [OSTI]

    is to deposit high-quality GaN thin films using inexpensive substrate under low temper- ature. Recently1282 IEEE ELECTRON DEVICE LETTERS, VOL. 33, NO. 9, SEPTEMBER 2012 Top-Gate GaN Thin-Film Transistors Based on AlN/GaN Heterostructures Rongsheng Chen, Wei Zhou, Meng Zhang, and Hoi Sing Kwok Abstract

  3. Controlling the Performance of a Three-Terminal Molecular Transistor: Conformational versus Conventional Gating

    E-Print Network [OSTI]

    Pandey, Ravi

    University, Houghton, Michigan 49931, United States Shashi P. Karna* U.S. Army Research Laboratory, Weapons *S Supporting Information ABSTRACT: The effect of conformational changes in the gate arm of a three of the gate field. The current modulation is found to reach its maximum only under exclusive effect of voltage

  4. Hafnium-doped tantalum oxide high-k gate dielectric films for future CMOS technology

    E-Print Network [OSTI]

    Lu, Jiang

    2007-04-25T23:59:59.000Z

    of the doped films were explained by their compositions and bond structures. The Hf-doped TaOx film is a potential high-k gate dielectric for future MOS transistors. A 5 Ã?Â? tantalum nitride (TaNx) interface layer has been inserted between the Hf-doped Ta...

  5. Organic Nanodielectrics for Low Voltage Carbon Nanotube Thin Film Transistors and Complementary Logic Gates

    E-Print Network [OSTI]

    Rogers, John A.

    illustrates the device layout which includes patterned metal source and drain electrodes, a random SWNT serving as substrate and back gate. The SAS nanodielectric multilayer was deposited via solution methods- lithographic patterning of source and drain electrodes

  6. L{sub g}?=?100?nm In{sub 0.7}Ga{sub 0.3}As quantum well metal-oxide semiconductor field-effect transistors with atomic layer deposited beryllium oxide as interfacial layer

    SciTech Connect (OSTI)

    Koh, D., E-mail: dh.koh@utexas.edu, E-mail: Taewoo.Kim@sematech.org [Department of Electrical and Computer Engineering, Microelectronics Research Center, The University of Texas at Austin, Austin, Texas 78758 (United States); SEMATECH, Inc., Albany, New York 12203 (United States); Kwon, H. M. [Department of Electronics Engineering, Chungnam National University, Daejeon 305-764 (Korea, Republic of); Kim, T.-W., E-mail: dh.koh@utexas.edu, E-mail: Taewoo.Kim@sematech.org; Veksler, D.; Gilmer, D.; Kirsch, P. D. [SEMATECH, Inc., Albany, New York 12203 (United States); Kim, D.-H. [SEMATECH, Inc., Albany, New York 12203 (United States); GLOBALFOUNDRIES, Malta, New York 12020 (United States); Hudnall, Todd W. [Department of Chemistry and Biochemistry, Texas State University, San Marcos, Texas, 78666 (United States); Bielawski, Christopher W. [Department of Chemistry and Biochemistry, The University of Texas at Austin, Austin, Texas 78712 (United States); Maszara, W. [GLOBALFOUNDRIES, Santa Clara, California 95054 (United States); Banerjee, S. K. [Department of Electrical and Computer Engineering, Microelectronics Research Center, The University of Texas at Austin, Austin, Texas 78758 (United States)

    2014-04-21T23:59:59.000Z

    In this study, we have fabricated nanometer-scale channel length quantum-well (QW) metal-oxide-semiconductor field effect transistors (MOSFETs) incorporating beryllium oxide (BeO) as an interfacial layer. BeO has high thermal stability, excellent electrical insulating characteristics, and a large band-gap, which make it an attractive candidate for use as a gate dielectric in making MOSFETs. BeO can also act as a good diffusion barrier to oxygen owing to its small atomic bonding length. In this work, we have fabricated In{sub 0.53}Ga{sub 0.47}As MOS capacitors with BeO and Al{sub 2}O{sub 3} and compared their electrical characteristics. As interface passivation layer, BeO/HfO{sub 2} bilayer gate stack presented effective oxide thickness less 1 nm. Furthermore, we have demonstrated In{sub 0.7}Ga{sub 0.3}As QW MOSFETs with a BeO/HfO{sub 2} dielectric, showing a sub-threshold slope of 100?mV/dec, and a transconductance (g{sub m,max}) of 1.1 mS/?m, while displaying low values of gate leakage current. These results highlight the potential of atomic layer deposited BeO for use as a gate dielectric or interface passivation layer for III–V MOSFETs at the 7?nm technology node and/or beyond.

  7. Molybdenum as a contact material in zinc tin oxide thin film transistors

    SciTech Connect (OSTI)

    Hu, W.; Peterson, R. L., E-mail: blpeters@umich.edu [Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, Michigan 48109-2122 (United States)

    2014-05-12T23:59:59.000Z

    Amorphous oxide semiconductors are of increasing interest for a variety of thin film electronics applications. Here, the contact properties of different source/drain electrode materials to solution-processed amorphous zinc tin oxide (ZTO) thin-film transistors are studied using the transmission line method. The width-normalized contact resistance between ZTO and sputtered molybdenum is measured to be 8.7 ?-cm, which is 10, 20, and 600 times smaller than that of gold/titanium, indium tin oxide, and evaporated molybdenum electrodes, respectively. The superior contact formed using sputtered molybdenum is due to a favorable work function lineup, an insulator-free interface, bombardment of ZTO during molybdenum sputtering, and trap-assisted tunneling. The transfer length of the sputtered molybdenum/ZTO contact is 0.34??m, opening the door to future radio-frequency sub-micron molybdenum/ZTO thin film transistors.

  8. High performance organic field-effect transistors with ultra-thin HfO{sub 2} gate insulator deposited directly onto the organic semiconductor

    SciTech Connect (OSTI)

    Ono, S., E-mail: shimpei@criepi.denken.or.jp [Central Research Institute of Electric Power Industry, Komae, Tokyo 201-8511 (Japan); Häusermann, R. [Central Research Institute of Electric Power Industry, Komae, Tokyo 201-8511 (Japan) [Central Research Institute of Electric Power Industry, Komae, Tokyo 201-8511 (Japan); Laboratory for Solid State Physics, ETH Zurich, Zurich 8093 (Switzerland); Chiba, D. [Institute for Chemical Research, Kyoto University, Gokasho, Uji, Kyoto 611-0011 (Japan) [Institute for Chemical Research, Kyoto University, Gokasho, Uji, Kyoto 611-0011 (Japan); PRESTO, Japan Science and Technology Agency, 4-1-8 Honcho Kawaguchi, Saitama 322-0012 (Japan); Department of Applied Physics, University of Tokyo, Tokyo 113-8656 (Japan); Shimamura, K.; Ono, T. [Institute for Chemical Research, Kyoto University, Gokasho, Uji, Kyoto 611-0011 (Japan)] [Institute for Chemical Research, Kyoto University, Gokasho, Uji, Kyoto 611-0011 (Japan); Batlogg, B. [Laboratory for Solid State Physics, ETH Zurich, Zurich 8093 (Switzerland)] [Laboratory for Solid State Physics, ETH Zurich, Zurich 8093 (Switzerland)

    2014-01-06T23:59:59.000Z

    We have produced stable organic field-effect transistors (OFETs) with an ultra-thin HfO{sub 2} gate insulator deposited directly on top of rubrene single crystals by atomic layer deposition (ALD). We find that ALD is a gentle deposition process to grow thin films without damaging rubrene single crystals, as results these devices have a negligibly small threshold voltage and are very stable against gate-bias-stress, and the mobility exceeds 1 cm{sup 2}/V s. Moreover, the devices show very little degradation even when kept in air for more than 2 months. These results demonstrate thin HfO{sub 2} layers deposited by ALD to be well suited as high capacitance gate dielectrics in OFETs operating at small gate voltage. In addition, the dielectric layer acts as an effective passivation layer to protect the organic semiconductor.

  9. AlGaN/GaN High-Electron-Mobility Transistor Employing an Additional Gate for High-Voltage Switching Applications

    E-Print Network [OSTI]

    Seo, Kwang Seok

    AlGaN/GaN High-Electron-Mobility Transistor Employing an Additional Gate for High-Voltage Switching 16, 2004; accepted May 10, 2005; published September 8, 2005) We have proposed and fabricated an AlGaN/GaN: GaN, AlGaN, HEMT, switch 1. Introduction GaN has attracted attention for high-power and high

  10. Current collapse imaging of Schottky gate AlGaN/GaN high electron mobility transistors by electric field-induced optical second-harmonic generation measurement

    SciTech Connect (OSTI)

    Katsuno, Takashi, E-mail: e1417@mosk.tytlabs.co.jp; Ishikawa, Tsuyoshi; Ueda, Hiroyuki; Uesugi, Tsutomu [Toyota Central R and D Laboratories Inc., Nagakute, Aichi 480-1192 (Japan); Manaka, Takaaki; Iwamoto, Mitsumasa [Department of Physical Electronics, Tokyo Institute of Technology, Meguro, Tokyo 152-8552 (Japan)

    2014-06-23T23:59:59.000Z

    Two-dimensional current collapse imaging of a Schottky gate AlGaN/GaN high electron mobility transistor device was achieved by optical electric field-induced second-harmonic generation (EFISHG) measurements. EFISHG measurements can detect the electric field produced by carriers trapped in the on-state of the device, which leads to current collapse. Immediately after (e.g., 1, 100, or 800??s) the completion of drain-stress voltage (200?V) in the off-state, the second-harmonic (SH) signals appeared within 2??m from the gate edge on the drain electrode. The SH signal intensity became weak with time, which suggests that the trapped carriers are emitted from the trap sites. The SH signal location supports the well-known virtual gate model for current collapse.

  11. New insights into self-heating in double-gate transistors by solving Boltzmann transport equations

    SciTech Connect (OSTI)

    Thu Trang Nghiêm, T., E-mail: tthutrang.nghiem@gmail.com [Institute of Fundamental Electronics, UMR 8622, CNRS-University of Paris-Sud, Orsay (France); The Center for Thermal Sciences of Lyon, UMR 5008, CNRS–INSA–University of Lyon 1, Villeurbanne (France); Saint-Martin, J.; Dollfus, P. [Institute of Fundamental Electronics, UMR 8622, CNRS-University of Paris-Sud, Orsay (France)

    2014-08-21T23:59:59.000Z

    Electro-thermal effects become one of the most critical issues for continuing the downscaling of electron devices. To study this problem, a new efficient self-consistent electron-phonon transport model has been developed. Our model of phonon Boltzmann transport equation (pBTE) includes the decay of optical phonons into acoustic modes and a generation term given by electron-Monte Carlo simulation. The solution of pBTE uses an analytic phonon dispersion and the relaxation time approximation for acoustic and optical phonons. This coupled simulation is applied to investigate the self-heating effects in a 20?nm-long double gate MOSFET. The temperature profile per mode and the comparison between Fourier temperature and the effective temperature are discussed. Some significant differences occur mainly in the hot spot region. It is shown that under the influence of self-heating effects, the potential profile is modified and both the drain current and the electron ballisticity are reduced because of enhanced electron-phonon scattering rates.

  12. Alumina nanoparticle/polymer nanocomposite dielectric for flexible amorphous indium-gallium-zinc oxide thin film transistors on plastic substrate with superior stability

    SciTech Connect (OSTI)

    Lai, Hsin-Cheng [Department of Electrical Engineering, National Chung Hsing University, Taichung 40227, Taiwan (China); Pei, Zingway, E-mail: zingway@dragon.nchu.edu.tw [Department of Electrical Engineering, National Chung Hsing University, Taichung 40227, Taiwan (China); Graduate Institute of Optoelectronic Engineering, National Chung Hsing University, Taichung 40227, Taiwan (China); Center of Nanoscience and Nanotechnology, National Chung Hsing University, Taichung 40227, Taiwan (China); Jian, Jyun-Ruri; Tzeng, Bo-Jie [Graduate Institute of Optoelectronic Engineering, National Chung Hsing University, Taichung 40227, Taiwan (China)

    2014-07-21T23:59:59.000Z

    In this study, the Al{sub 2}O{sub 3} nanoparticles were incorporated into polymer as a nono-composite dielectric for used in a flexible amorphous Indium-Gallium-Zinc Oxide (a-IGZO) thin-film transistor (TFT) on a polyethylene naphthalate substrate by solution process. The process temperature was well below 100?°C. The a-IGZO TFT exhibit a mobility of 5.13?cm{sup 2}/V s on the flexible substrate. After bending at a radius of 4?mm (strain?=?1.56%) for more than 100 times, the performance of this a-IGZO TFT was nearly unchanged. In addition, the electrical characteristics are less altered after positive gate bias stress at 10?V for 1500?s. Thus, this technology is suitable for use in flexible displays.

  13. Abstract--Bias temperature instability, hot-carrier injection, and gate-oxide wearout will cause severe lifetime degradation in

    E-Print Network [OSTI]

    Lipasti, Mikko H.

    affect device performance and lead to timing violations; as well as gate-oxide wearout [3] which can probability of oxide breakdown, leading to a hard failure of a device that exceeds its intended (or targetedAbstract--Bias temperature instability, hot-carrier injection, and gate-oxide wearout will cause

  14. Radiation-hardened transistor and integrated circuit

    DOE Patents [OSTI]

    Ma, Kwok K. (Albuquerque, NM)

    2007-11-20T23:59:59.000Z

    A composite transistor is disclosed for use in radiation hardening a CMOS IC formed on an SOI or bulk semiconductor substrate. The composite transistor has a circuit transistor and a blocking transistor connected in series with a common gate connection. A body terminal of the blocking transistor is connected only to a source terminal thereof, and to no other connection point. The blocking transistor acts to prevent a single-event transient (SET) occurring in the circuit transistor from being coupled outside the composite transistor. Similarly, when a SET occurs in the blocking transistor, the circuit transistor prevents the SET from being coupled outside the composite transistor. N-type and P-type composite transistors can be used for each and every transistor in the CMOS IC to radiation harden the IC, and can be used to form inverters and transmission gates which are the building blocks of CMOS ICs.

  15. Characterization of device parameters in high-temperature metal-oxide-semiconductor field-effect transistors in. beta. -SiC thin films

    SciTech Connect (OSTI)

    Palmour, J.W.; Kong, H.S.; Davis, R.F.

    1988-08-15T23:59:59.000Z

    Both inversion- and depletion-mode n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) have been fabricated on ..beta..-SiC thin films grown by chemical-vapor deposition. The inversion-mode devices were made on in situ doped (Al) p-type ..beta..-SiC(100) thin films grown on Si(100) substrates. The depletion-mode MOSFETs were made on n-type ..beta..-SiC(111) thin films grown on the Si(0001) face of a 6H ..cap alpha..-SiC substrates. Stable saturation and low subthreshold currents were achieved at drain-source voltages exceeding 5 and 25 V for the inversion-mode and depletion-mode devices, respectively. The transconductance increased with temperature up to 673 K for the short-gate-length devices, of either mode, and then decreased with further increases in temperature. It is proposed that the transconductances and threshold voltages for the inversion-mode devices are greatly affected by minority-carrier injection from the source. Stable transistor action was observed for both types of devices at temperatures up to 823 K, with the depletion-mode devices operating very well up to 923 K.

  16. Thin film three-dimensional topological insulator metal-oxide-semiconductor field-effect-transistors: A candidate for sub-10?nm devices

    SciTech Connect (OSTI)

    Akhavan, N. D., E-mail: nima.dehdashti@uwa.edu.au; Jolley, G.; Umana-Membreno, G. A.; Antoszewski, J.; Faraone, L. [Department of Electrical, Electronic and Computer Engineering, University of Western Australia, Crawley, WA 6009 (Australia)

    2014-08-28T23:59:59.000Z

    Three-dimensional (3D) topological insulators (TI) are a new state of quantum matter in which surface states reside in the bulk insulating energy bandgap and are protected by time-reversal symmetry. It is possible to create an energy bandgap as a consequence of the interaction between the conduction band and valence band surface states from the opposite surfaces of a TI thin film, and the width of the bandgap can be controlled by the thin film thickness. The formation of an energy bandgap raises the possibility of thin-film TI-based metal-oxide-semiconductor field-effect-transistors (MOSFETs). In this paper, we explore the performance of MOSFETs based on thin film 3D-TI structures by employing quantum ballistic transport simulations using the effective continuous Hamiltonian with fitting parameters extracted from ab-initio calculations. We demonstrate that thin film transistors based on a 3D-TI structure provide similar electrical characteristics compared to a Si-MOSFET for gate lengths down to 10?nm. Thus, such a device can be a potential candidate to replace Si-based MOSFETs in the sub-10?nm regime.

  17. Double-dot charge transport in Si single-electronhole transistors L. P. Rokhinson,a)

    E-Print Network [OSTI]

    Rokhinson, Leonid

    ­oxide­ semiconductor field-effect transistors MOSFETs brought to light several issues related to the electrical beneath the dot transforming it into a free-standing bridge. Subsequently, 40 or 50 nm of oxide are thermally grown which further reduce the size of the dot. Polysilicon gate is deposited over the bridge

  18. AlGaN/GaN Metal Oxide Semiconductor Field Effect Transistors using Titanium Dioxide P. J. HANSEN

    E-Print Network [OSTI]

    York, Robert A.

    AlGaN/GaN Metal Oxide Semiconductor Field Effect Transistors using Titanium Dioxide P. J. HANSEN 1 epitaxially on AlGaN/GaN HFET structures by molecular beam epitaxy (MBE). Growth was first performed on GaN templates to establish epitaxial growth conditions. X-ray diffraction showed [001] TiO2 || [1010]GaN

  19. Significant electrical control of amorphous oxide thin film transistors by an ultrathin Ti surface polarity modifier

    SciTech Connect (OSTI)

    Cho, Byungsu [Division of Materials Science and Engineering, Hanyang University, Seoul 133-791 (Korea, Republic of); Samsung Display Co. Ltd., Tangjeong, Chungcheongnam-Do 336-741 (Korea, Republic of); Choi, Yonghyuk; Shin, Seokyoon [Division of Materials Science and Engineering, Hanyang University, Seoul 133-791 (Korea, Republic of); Jeon, Heeyoung [Department of Nano-scale Semiconductor Engineering, Hanyang University, Seoul 133-791 (Korea, Republic of); Seo, Hyungtak, E-mail: hseo@ajou.ac.kr [Department of Materials Science and Engineering and Energy Systems Research, Ajou University, Suwon 443-739 (Korea, Republic of); Jeon, Hyeongtag, E-mail: hjeon@hanyang.ac.kr [Division of Materials Science and Engineering, Hanyang University, Seoul 133-791 (Korea, Republic of); Department of Nano-scale Semiconductor Engineering, Hanyang University, Seoul 133-791 (Korea, Republic of)

    2014-01-27T23:59:59.000Z

    We demonstrate an enhanced electrical stability through a Ti oxide (TiO{sub x}) layer on the amorphous InGaZnO (a-IGZO) back-channel; this layer acts as a surface polarity modifier. Ultrathin Ti deposited on the a-IGZO existed as a TiO{sub x} thin film, resulting in oxygen cross-binding with a-IGZO surface. The electrical properties of a-IGZO thin film transistors (TFTs) with TiO{sub x} depend on the surface polarity change and electronic band structure evolution. This result indicates that TiO{sub x} on the back-channel serves as not only a passivation layer protecting the channel from ambient molecules or process variables but also a control layer of TFT device parameters.

  20. Lanthanum silicate gate dielectric stacks with subnanometer equivalent oxide thickness utilizing an interfacial silica consumption reaction

    E-Print Network [OSTI]

    Garfunkel, Eric

    Lanthanum silicate gate dielectric stacks with subnanometer equivalent oxide thickness utilizing-8087 Received 13 April 2005; accepted 6 June 2005; published online 26 July 2005 A silicate reaction between process route to interface elimination, while producing a silicate dielectric with a higher temperature

  1. Reverse gate bias-induced degradation of AlGaN/GaN high electron mobility transistors

    E-Print Network [OSTI]

    Florida, University of

    , or temperature in- creases due to self-heating. For example, in the on-state stress condition, there may be strong self-heating of the HEMT and a high density of hot electrons in the channel, but accompanied and gate leakage, but should reduce contributions from hot electrons and self-heating.13

  2. Total dose induced latch in short channel NMOS/SOI transistors

    SciTech Connect (OSTI)

    Ferlet-Cavrois, V.; Quoizola, S.; Musseau, O.; Flament, O.; Leray, J.L. [CEA/DRIF, Bruyeres-le-Chatel (France)] [CEA/DRIF, Bruyeres-le-Chatel (France); Pelloie, J.L.; Raynaud, C.; Faynot, O. [CEA/DTA-LETI, Grenoble (France)] [CEA/DTA-LETI, Grenoble (France)

    1998-12-01T23:59:59.000Z

    A latch effect induced by total dose irradiation is observed in short channel SOI transistors. This effect appears on NMOS transistors with either a fully or a partially depleted structure. It is characterized by a hysteresis behavior of the Id-Vg characteristics at high drain bias for a given critical dose. Above this dose, the authors still observe a limited leakage current at low drain bias (0.1 V), but a high conduction current at high drain bias (2 V) as the transistor should be in the off-state. The critical dose above which the latch appears strongly depends on gate length, transistor structure (fully or partially depleted), buried oxide thickness and supply voltage. Two-dimensional (2D) numerical simulations indicate that the parasitic condition is due to the latch of the back gate transistor triggered by charge trapping in the buried oxide. To avoid the latch induced by the floating body effect, different techniques can be used: doping engineering, body contacts, etc. The study of the main parameters influencing the latch (gate length, supply voltage) shows that the scaling of technologies does not necessarily imply an increased latch sensitivity. Some technological parameters like the buried oxide hardness and thickness can be used to avoid latch, even at high cumulated dose, on highly integrated SOI technologies.

  3. Experimental study on vertical scaling of InAs-on-insulator metal-oxide-semiconductor field-effect transistors

    SciTech Connect (OSTI)

    Kim, SangHyeon, E-mail: dadembyora@mosfet.t.u-tokyo.ac.jp, E-mail: sh-kim@kist.re.kr; Yokoyama, Masafumi; Nakane, Ryosho; Takenaka, Mitsuru; Takagi, Shinichi [Department of Electrical Engineering and Information Systems, The University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656 (Japan); Ichikawa, Osamu; Osada, Takenori; Hata, Masahiko [Sumitomo Chemical Co., Ltd., 6 Kitahara, Tsukuba, Ibaraki 300-3294 (Japan)

    2014-06-30T23:59:59.000Z

    We have investigated effects of the vertical scaling on electrical properties in extremely thin-body InAs-on-insulator (-OI) metal-oxide-semiconductor field-effect transistors (MOSFETs). It is found that the body thickness (T{sub body}) scaling provides better short channel effect (SCE) control, whereas the T{sub body} scaling also causes the reduction of the mobility limited by channel thickness fluctuation (?T{sub body}) scattering (?{sub fluctuation}). Also, in order to achieve better SCEs control, the thickness of InAs channel layer (T{sub channel}) scaling is more favorable than the thickness of MOS interface buffer layer (T{sub buffer}) scaling from a viewpoint of a balance between SCEs control and ?{sub fluctuation} reduction. These results indicate necessity of quantum well channel structure in InAs-OI MOSFETs and these should be considered in future transistor design.

  4. BUSFET -- A radiation-hardened SOI transistor

    SciTech Connect (OSTI)

    Schwank, J.R.; Shaneyfelt, M.R.; Draper, B.L.; Dodd, P.E.

    1999-12-01T23:59:59.000Z

    The total-dose hardness of SOI technology is limited by radiation-induced charge trapping in gate, field, and SOI buried oxides. Charge trapping in the buried oxide can lead to back-channel leakage and makes hardening SOI transistors more challenging than hardening bulk-silicon transistors. Two avenues for hardening the back-channel are (1) to use specially prepared SOI buried oxides that reduce the net amount of trapped positive charge or (2) to design transistors that are less sensitive to the effects of trapped charge in the buried oxide. In this work, the authors propose a partially-depleted SOI transistor structure for mitigating the effects of trapped charge in the buried oxide on radiation hardness. They call this structure the BUSFET--Body Under Source FET. The BUSFET utilizes a shallow source and a deep drain. As a result, the silicon depletion region at the back channel caused by radiation-induced charge trapping in the buried oxide does not form a conducting path between source and drain. Thus, the BUSFET structure design can significantly reduce radiation-induced back-channel leakage without using specially prepared buried oxides. Total dose hardness is achieved without degrading the intrinsic SEU or dose rate hardness of SOI technology. The effectiveness of the BUSFET structure for reducing total-dose back-channel leakage depends on several variables, including the top silicon film thickness and doping concentration, and the depth of the source. 3-D simulations show that for a body doping concentration of 10{sup 18} cm{sup {minus}3}, a drain bias of 3 V, and a source depth of 90 nm, a silicon film thickness of 180 nm is sufficient to almost completely eliminate radiation-induced back-channel leakage. However, for a doping concentration of 3 x 10{sup 17} cm{sup {minus}3}, a thicker silicon film (300 nm) must be used.

  5. Charge Noise in Graphene Transistors Iddo Heller,,

    E-Print Network [OSTI]

    Dekker, Cees

    Charge Noise in Graphene Transistors Iddo Heller,,§ Sohail Chatoor, Jaan Ma¨nnik, Marcel A. G an experimental study of 1/f noise in liquid-gated graphene transistors. We show that the gate dependence to the graphene, while at high carrier density it is consistent with noise due to scattering in the channel

  6. Strained Ge channel p-type metal-oxide-semiconductor field-effect transistors grown on Siâ?â??xGex/Si virtual substrates

    E-Print Network [OSTI]

    Lee, Minjoo L.

    We have fabricated strained Ge channel p-type metal-oxide-semiconductor field-effect transistors (p-MOSFETs) on Siâ??.â??Geâ??.â?? virtual substrates. The poor interface between silicon dioxide (SiOâ??) and the Ge channel ...

  7. Ferroelectric-gated terahertz plasmonics on graphene

    E-Print Network [OSTI]

    Jin, Dafei

    Inspired by recent advancement of ferroelectric-gated memories and transistors, we propose a design of ferroelectric-gated nanoplasmonic devices based on graphene sheets clamped in ferroelectric crystals. We show that the ...

  8. Enhanced stability against bias-stress of metal-oxide thin film transistors deposited at elevated temperatures

    SciTech Connect (OSTI)

    Fakhri, M.; Goerrn, P.; Riedl, T. [Institute of Electronic Devices, University of Wuppertal, Rainer-Gruenter-St. 21, 42119 Wuppertal (Germany); Weimann, T.; Hinze, P. [Physikalisch-Technische Bundesanstalt Braunschweig, Bundesallee 100, 38116 Braunschweig (Germany)

    2011-09-19T23:59:59.000Z

    Transparent zinc-tin-oxide (ZTO) thin film transistors (TFTs) have been prepared by DC magnetron sputtering. Compared to reference devices with a channel deposited at room temperature and subsequently annealing at 400 deg. C, a substantially enhanced stability against bias stress is evidenced for devices with in-situ substrate heating during deposition (400 deg. C). A reduced density of sub-gap defect states in TFT channels prepared with in-situ substrate heating is found. Concomitantly, a reduced sensitivity to the adsorption of ambient gases is evidenced for the in-situ heated devices. This finding is of particular importance for an application as driver electronics for organic light emitting diode displays.

  9. BUSFET - A Novel Radiation-Hardened SOI Transistor

    SciTech Connect (OSTI)

    Schwank, J.R.; Shaneyfelt, M.R.; Draper, B.L.; Dodd, P.E.

    1999-07-20T23:59:59.000Z

    The total-dose hardness of SOI technology is limited by radiation-induced charge trapping in gate, field, and SOI buried oxides. Charge trapping in the buried oxide can lead to back-channel leakage and makes hardening SOI transistors more challenging than hardening bulk-silicon transistors. Two avenues for hardening the back-channel are (1) to use specially prepared SOI buried oxides that reduce the net amount of trapped positive charge or (2) to design transistors that are less sensitive to the effects of trapped charge in the buried oxide. In this work, we propose a new partially-depleted SOI transistor structure that we call the BUSFET--Body Under Source FET. The BUSFET utilizes a shallow source and a deep drain. As a result, the silicon depletion region at the back channel caused by radiation-induced charge trapping in the buried oxide does not form a conducting path between source and drain. Thus, the BUSFET structure design can significantly reduce radiation-induced back-channel leakage without using specially prepared buried oxides. Total dose hardness is achieved without degrading the intrinsic SEU and dose rate hardness of SOI technology. The effectiveness of the BUSFET structure for reducing total-dose back-channel leakage depends on several variables, including the top silicon film thickness and doping concentration and the depth of the source. 3-D simulations show that for a doping concentration of 10{sup 18} cm{sup {minus}3} and a source depth of 90 nm, a silicon film thickness of 180 nm is sufficient to almost completely eliminate radiation-induced back-channel leakage. However, for a doping concentration of 3x10{sup 17} cm{sup {minus}3}, a thicker silicon film (300 nm) must be used.

  10. Effects of rapid thermal annealing on the electrical properties of the AlGaN/AlN/GaN heterostructure field-effect transistors with Ti/Al/Ni/Au gate electrodes

    SciTech Connect (OSTI)

    Zhao, Jingtao; Lin, Zhaojun, E-mail: linzj@sdu.edu.cn; Luan, Chongbiao; Zhou, Yang; Yang, Ming [School of Physics, Shandong University, Jinan 250100 (China); Lv, Yuanjie; Feng, Zhihong [National Key Laboratory of Application Specific Integrated Circuit (ASIC), Hebei Semiconductor Research Institute, Shijiazhuang 050051 (China)

    2014-08-25T23:59:59.000Z

    In this study, we investigated the electrical properties of the AlGaN/AlN/GaN heterostructure field-effect transistors (HFETs) with Ti/Al/Ni/Au gate electrodes using the measured capacitance-voltage, current-voltage characteristics, and micro-Raman spectroscopy. We found that the uneven distribution of the strain caused by the Schottky metals was a major factor that generates the polarization Coulomb field scattering in AlGaN/AlN/GaN HFETs, and after appropriate rapid thermal annealing (RTA) processes, the polarization Coulomb field scattering was greatly weakened and the two-dimensional electron gas electron mobility was improved. We also found that the Schottky barrier height and the DC characteristics of the devices became better after appropriate RTA. Of course, the electrical performances mentioned above became deteriorated after excessive annealing.

  11. SiO2 Passivation Effects on the Leakage Current in Dual-Gate AlGaN/GaN High Electron Mobility Transistors

    E-Print Network [OSTI]

    Seo, Kwang Seok

    was grown on c-plane sapphire substrate by MOCVD. Undoped 30 nm-thick Al0.26Ga0.74N and Fe-doped 3 m GaN substrate 3 nm undoped GaN 0.26 0.74 Source DrainMain-GateSiO2 2DEG SiO2 SiO2 Additional Gate 5 m3 m3 m 3 mSiO2 Passivation Effects on the Leakage Current in Dual-Gate AlGaN/GaN High Electron Mobility

  12. Device Research Conference, June 2003 SiGe Single-Hole Transistor Fabricated by AFM Oxidation and Epitaxial Regrowth

    E-Print Network [OSTI]

    61st Device Research Conference, June 2003 129 SiGe Single-Hole Transistor Fabricated by AFM-energy patterning process based on AFM lithography (to avoid defects from e-beam and RIE) and Si/SiGe). Single-hole transistor, which is the first reported SiGe quantum device with heterojunction passivation

  13. Two-stage Model for Lifetime Prediction of Highly Stable Amorphous-Silicon Thin-Film Transistors under Low-Gate Field

    E-Print Network [OSTI]

    that (i) a "unified stretched exponential fit" models the drain current degradation from 60°C to 140 stable back-channel passivated (BCP) a-Si TFTs were fabricated with a standard bottom-gate non field of 2.0×105 V/cm) and a constant drain voltage of 7.5V. The positive threshold voltage shift of a

  14. Anomalous output characteristic shift for the n-type lateral diffused metal-oxide-semiconductor transistor with floating P-top layer

    SciTech Connect (OSTI)

    Liu, Siyang; Zhang, Chunwei; Sun, Weifeng, E-mail: swffrog@seu.edu.cn [National ASIC System Engineering Research Center, Southeast University, Nanjing 210096 (China); Su, Wei; Wang, Shaorong; Ma, Shulang; Huang, Yu [CSMC Technologies Corporation, Wuxi 214061 (China)

    2014-04-14T23:59:59.000Z

    Anomalous output characteristic shift of the n-type lateral diffused metal-oxide-semiconductor transistor with floating P-top layer is investigated. It shows that the linear drain current has obvious decrease when the output characteristic of fresh device is measured for two consecutive times. The charge pumping experiments demonstrate that the decrease is not from hot-carrier degradation. The reduction of cross section area for the current flowing, which results from the squeezing of the depletion region surrounding the P-top layer, is responsible for the shift. Consequently, the current capability of this special device should be evaluated by the second measured output characteristic.

  15. High-Performance Solution-Processed Amorphous-Oxide-Semiconductor TFTs with Organic Polymeric Gate Dielectrics

    E-Print Network [OSTI]

    Pecunia, Vincenzo; Banger, Kulbinder; Sirringhaus, Henning

    2015-01-13T23:59:59.000Z

    energy offsets (? 1 eV) between the conduction/valence bands of the semiconductor and the gate dielectric are needed to confine the charge carriers at the active interface and minimize undesirable charge injection from the semiconductor into the gate... in solution, all the other polymers came in the form of pellets or powder and were dissolved in suitable anhydrous organic solvents: P?MS was dissolved in xylene at a concentration of 60 mg mL-1; SAN in butyronitrile at 40 mg mL-1; PC in 1,2-dichlorobenzene...

  16. Gate potential control of nanofluidic devices

    E-Print Network [OSTI]

    Le Coguic, Arnaud

    2005-01-01T23:59:59.000Z

    The effect of an external gate potential control on the nanofluidic nanochannels was experimentally investigated in this work. Like in the field effect transistors (FET) in microelectronics, molecular transport in ...

  17. RF Characteristics of Room-Temperature-Deposited, Small Gate Dimension Indium Zinc Oxide TFTs

    E-Print Network [OSTI]

    Pearton, Stephen J.

    .16 These transparent conducting oxides may also be used as electrodes in solar cells and flat-panel

  18. Nanocrystals Embedded Zirconium-doped Hafnium Oxide High-k Gate Dielectric Films

    E-Print Network [OSTI]

    Lin, Chen-Han

    2012-10-19T23:59:59.000Z

    , can be expected. In this study, the ZrHfO high-k MOS capacitors that separately contain nanocrystalline ruthenium oxide (nc-RuO), indium tin oxide (nc-ITO), and zinc oxide (nc-ZnO) have been successfully fabricated by the sputtering deposition method...

  19. Nonvolatile memory disturbs due to gate and junction leakage currents

    E-Print Network [OSTI]

    Schroder, Dieter K.

    ) from traps within the gate oxides. Such low gate leakage currents can lead to sufficient charge; accepted 10 September 2002 Abstract We address disturbs due to gate oxide and junction leakage currents in floating gate nonvolatile memories (NVM). The junction leakage is important, because the gate oxide current

  20. Method of making self-aligned lightly-doped-drain structure for MOS transistors

    DOE Patents [OSTI]

    Weiner, Kurt H. (San Jose, CA); Carey, Paul G. (Mountain View, CA)

    2001-01-01T23:59:59.000Z

    A process for fabricating lightly-doped-drains (LDD) for short-channel metal oxide semiconductor (MOS) transistors. The process utilizes a pulsed laser process to incorporate the dopants, thus eliminating the prior oxide deposition and etching steps. During the process, the silicon in the source/drain region is melted by the laser energy. Impurities from the gas phase diffuse into the molten silicon to appropriately dope the source/drain regions. By controlling the energy of the laser, a lightly-doped-drain can be formed in one processing step. This is accomplished by first using a single high energy laser pulse to melt the silicon to a significant depth and thus the amount of dopants incorporated into the silicon is small. Furthermore, the dopants incorporated during this step diffuse to the edge of the MOS transistor gate structure. Next, many low energy laser pulses are used to heavily dope the source/drain silicon only in a very shallow region. Because of two-dimensional heat transfer at the MOS transistor gate edge, the low energy pulses are inset from the region initially doped by the high energy pulse. By computer control of the laser energy, the single high energy laser pulse and the subsequent low energy laser pulses are carried out in a single operational step to produce a self-aligned lightly-doped-drain-structure.

  1. Process sensing and metrology in gate oxide growth by rapid thermal chemical vapor deposition from SiH4 and N2O

    E-Print Network [OSTI]

    Rubloff, Gary W.

    Process sensing and metrology in gate oxide growth by rapid thermal chemical vapor deposition from for Advanced Electronic Materials Processing, North Carolina State University, Raleigh, North Carolina 27695-7920 Received 7 January 1999; accepted 21 May 1999 Active sampling mass spectrometry has been used for process

  2. Photoemission spectroscopy study of the lanthanum lutetium oxide/silicon interface

    SciTech Connect (OSTI)

    Nichau, A.; Schnee, M.; Schubert, J.; Bernardy, P.; Hollaender, B.; Buca, D.; Mantl, S. [Peter Gruenberg Institute 9 (PGI9-IT), Forschungszentrum Juelich, 52425 Juelich (Germany); JARA-Fundamentals of Future Information Technologies, 52425 Juelich (Germany); Besmehn, A.; Breuer, U. [Central Division for Chemical Analysis (ZCH), Forschungszentrum Juelich, 52425 Juelich (Germany); Rubio-Zuazo, J.; Castro, G. R. [Spanish CRG BM25 Beamline-SpLine, European Synchrotron Radiation Facility (ESRF), Rue Jules Horowitz BP 220, F-38043 Grenoble, Cedex 09 (France); Muecklich, A.; Borany, J. von [Institute of Ion Beam Physics and Materials Research, Helmholtz-Zentrum' Dresden-Rossendorf e.V., 01314 Dresden (Germany)

    2013-04-21T23:59:59.000Z

    Rare earth oxides are promising candidates for future integration into nano-electronics. A key property of these oxides is their ability to form silicates in order to replace the interfacial layer in Si-based complementary metal-oxide field effect transistors. In this work a detailed study of lanthanum lutetium oxide based gate stacks is presented. Special attention is given to the silicate formation at temperatures typical for CMOS processing. The experimental analysis is based on hard x-ray photoemission spectroscopy complemented by standard laboratory experiments as Rutherford backscattering spectrometry and high-resolution transmission electron microscopy. Homogenously distributed La silicate and Lu silicate at the Si interface are proven to form already during gate oxide deposition. During the thermal treatment Si atoms diffuse through the oxide layer towards the TiN metal gate. This mechanism is identified to be promoted via Lu-O bonds, whereby the diffusion of La was found to be less important.

  3. Triple-Mode Single-Transistor Graphene Amplifier and Its Applications

    E-Print Network [OSTI]

    blocks in analog circuits. There are three types of single-transistor amplifiers: common-source, common-drain. The common-source amplifier provides nega- tive gain, whereas the common-drain and common-gate amplifiers amplifier utilizing a three-terminal back-gated single-layer graphene transistor. The ambipolar nature

  4. New Insights into Fully-Depleted SOI Transistor Response During Total-Dose Irradiation

    SciTech Connect (OSTI)

    BURNS,J.A.; DODD,PAUL E.; KEAST,C.L.; SCHWANK,JAMES R.; SHANEYFELT,MARTY R.; WYATT,P.W.

    1999-09-14T23:59:59.000Z

    Previous work showed the possible existence of a total-dose latch effect in fully-depleted SOI transistors that could severely limit the radiation hardness of SOI devices. Other work showed that worst-case bias configuration during irradiation was the transmission gate bias configuration. In this work we further explore the effects of total-dose ionizing irradiation on fully-depleted SOI transistors. Closed-geometry and standard transistors fabricated in two fully-depleted processes were irradiated with 10-keV x rays. Our results show no evidence for a total-dose latch effect as proposed by others. Instead, in absence of parasitic trench sidewall leakage, our data suggests that the increase in radiation-induced leakage current is caused by positive charge trapping in the buried oxide inverting the back-channel interface. At moderate levels of trapped charge, the back-channel interface is slightly inverted causing a small leakage current to flow. This leakage current is amplified to considerably higher levels by impact ionization. Because the back-channel interface is in weak inversion, the top-gate bias can modulate the back-channel interface and turn the leakage current off at large, negative voltage levels. At high levels of trapped charge, the back-channel interface is fully inverted and the gate bias has little effect on leakage current. However, it is likely that this current also is amplified by impact ionization. For these transistors, the worst-case bias configuration was determined to be the ''ON'' bias configuration. These results have important implication on hardness assurance.

  5. Gate-all-around silicon nanowire MOSFETs : top-down fabrication and transport enhancement techniques

    E-Print Network [OSTI]

    Hashemi, Pouya

    2010-01-01T23:59:59.000Z

    Scaling MOSFETs beyond 15 nm gate lengths is extremely challenging using a planar device architecture due to the stringent criteria required for the transistor switching. The top-down fabricated, gate-all-around architecture ...

  6. Zirconium-doped tantalum oxide high-k gate dielectric films 

    E-Print Network [OSTI]

    Tewg, Jun-Yen

    2005-02-17T23:59:59.000Z

    A new high-k dielectric material, i.e., zirconium-doped tantalum oxide (Zr-doped TaOx), in the form of a sputter-deposited thin film with a thickness range of 5-100 nm, has been studied. Important applications of this new ...

  7. Zirconium-doped tantalum oxide high-k gate dielectric films

    E-Print Network [OSTI]

    Tewg, Jun-Yen

    2005-02-17T23:59:59.000Z

    A new high-k dielectric material, i.e., zirconium-doped tantalum oxide (Zr-doped TaOx), in the form of a sputter-deposited thin film with a thickness range of 5-100 nm, has been studied. Important applications of this new dielectric material include...

  8. COOPER PAIR TRANSISTOR IN A TUNABLE ENVIRONMENT

    E-Print Network [OSTI]

    Haviland, David

    COOPER PAIR TRANSISTOR IN A TUNABLE ENVIRONMENT S. Corlevi, W. Guichard, and D. B. Haviland* 1 measurements of the CPT, which are performed in a low impedance environment, the charging effects are observed as gate voltage modulation of the critical current. However, in a high impedance environment, a Coulomb

  9. Charge noise analysis of metal oxide semiconductor dual-gate Si/SiGe quantum point contacts

    SciTech Connect (OSTI)

    Kamioka, J.; Oda, S. [Quantum Nanoelectronics Research Center, Tokyo Institute of Technology, 2-12-1-S9-11, Ookayama, Meguro-ku, Tokyo, 152-8552 (Japan); Kodera, T., E-mail: kodera.t.ac@m.titech.ac.jp [Quantum Nanoelectronics Research Center, Tokyo Institute of Technology, 2-12-1-S9-11, Ookayama, Meguro-ku, Tokyo, 152-8552 (Japan); Department of Physical Electronics, Tokyo Institute of Technology, 2-12-1-NE-25, Ookayama, Meguro-ku, Tokyo, 152-8552 (Japan); PRESTO, Japan Science and Technology Agency (JST), 4-1-8 Honcho, Kawaguchi, Saitama 332-0012 (Japan); Takeda, K.; Obata, T. [Department of Applied Physics, School of Engineering, The University of Tokyo, 7-3-1, Hongo, Bunkyo-ku, Tokyo 113-8656 (Japan); Tarucha, S. [Department of Applied Physics, School of Engineering, The University of Tokyo, 7-3-1, Hongo, Bunkyo-ku, Tokyo 113-8656 (Japan); RIKEN, Center for Emergent Matter Science (CEMS), 2-1, Hirosawa, Wako, Saitama 351-0198 (Japan)

    2014-05-28T23:59:59.000Z

    The frequency dependence of conductance noise through a gate-defined quantum point contact fabricated on a Si/SiGe modulation doped wafer is characterized. The 1/f{sup 2} noise, which is characteristic of random telegraph noise, is reduced by application of a negative bias on the global top gate to reduce the local gate voltage. Direct leakage from the large global gate voltage also causes random telegraph noise, and therefore, there is a suitable point to operate quantum dot measurement.

  10. Back bias induced dynamic and steep subthreshold swing in junctionless transistors

    SciTech Connect (OSTI)

    Parihar, Mukta Singh; Kranti, Abhinav, E-mail: akranti@iiti.ac.in [Low Power Nanoelectronics Research Group, Electrical Engineering Discipline, Indian Institute of Technology Indore, Indore (India)

    2014-07-21T23:59:59.000Z

    In this work, we analyze back bias induced steep and dynamic subthreshold swing in junctionless double gate transistors operated in the asymmetric mode. This impact ionization induced dynamic subthreshold swing is explained in terms of the ratio between minimum hole concentration and peak electron concentration, and the dynamic change in the location of the conduction channel with applied front gate voltage. The reason for the occurrence of impact ionization at sub-bandgap drain voltages in silicon junctionless transistors is also accounted for. The optimum junctionless transistor operating at a back gate bias of ?0.9?V, achieves over 5 orders of change in drain current at a gate overdrive of 200?mV and drain bias of 1?V. These results for junctionless transistors are significantly better than those exhibited by silicon tunnel field effect transistors operating at the same drain bias.

  11. Chemical Bonding, Interfaces and Defects in Hafnium Oxide/Germanium Oxynitride Gate Stacks on Ge (100)

    SciTech Connect (OSTI)

    Oshima, Yasuhiro; /Stanford U., Materials Sci. Dept.; Sun, Yun; /SLAC, SSRL; Kuzum, Duygu; /Stanford U.; Sugawara, Takuya; Saraswat, Krishna C.; Pianetta, Piero; /SLAC, SSRL; McIntyre, Paul C.; /Stanford U., Materials Sci. Dept.

    2008-10-31T23:59:59.000Z

    Correlations among interface properties and chemical bonding characteristics in HfO{sub 2}/GeO{sub x}N{sub y}/Ge MIS stacks were investigated using in-situ remote nitridation of the Ge (100) surface prior to HfO{sub 2} atomic layer deposition (ALD). Ultra thin ({approx}1.1 nm), thermally stable and aqueous etch-resistant GeO{sub x}N{sub y} interfaces layers that exhibited Ge core level photoelectron spectra (PES) similar to stoichiometric Ge{sub 3}N{sub 4} were synthesized. To evaluate GeO{sub x}N{sub y}/Ge interface defects, the density of interface states (D{sub it}) was extracted by the conductance method across the band gap. Forming gas annealed (FGA) samples exhibited substantially lower D{sub it} ({approx} 1 x 10{sup 12} cm{sup -2} eV{sup -1}) than did high vacuum annealed (HVA) and inert gas anneal (IGA) samples ({approx} 1x 10{sup 13} cm{sup -2} eV{sup -1}). Germanium core level photoelectron spectra from similar FGA-treated samples detected out-diffusion of germanium oxide to the HfO{sub 2} film surface and apparent modification of chemical bonding at the GeO{sub x}N{sub y}/Ge interface, which is related to the reduced D{sub it}.

  12. Physical understanding of electron mobility in asymmetrically strained InGaAs-on-insulator metal-oxide-semiconductor field-effect transistors fabricated by lateral strain relaxation

    SciTech Connect (OSTI)

    Kim, SangHyeon, E-mail: dadembyora@mosfet.t.u-tokyo.ac.jp, E-mail: sh-kim@kist.re.kr; Yokoyama, Masafumi; Ikku, Yuki; Nakane, Ryosho; Takenaka, Mitsuru; Takagi, Shinichi [Department of Electrical Engineering and Information Systems, The University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656 (Japan); Ichikawa, Osamu; Osada, Takenori; Hata, Masahiko [Sumitomo Chemical Co. Ltd., 6 Kitahara, Tsukuba, Ibaraki 300-3294 (Japan)

    2014-03-17T23:59:59.000Z

    In this paper, we fabricated asymmetrically tensile-strained In{sub 0.53}Ga{sub 0.47}As-on-insulator (-OI) metal-oxide-semiconductor field-effect transistors (MOSFETs) using a lateral strain relaxation technique. A stripe-like line structure, fabricated in biaxially strained In{sub 0.53}Ga{sub 0.47}As-OI can lead to the lateral strain relaxation and asymmetric strain configuration in In{sub 0.53}Ga{sub 0.47}As-OI with the channel width of 100?nm. We have found that the effective mobility (?{sub eff}) enhancement in In{sub 0.53}Ga{sub 0.47}As-OI MOSFETs with uniaxial-like asymmetric strain becomes smaller than that in In{sub 0.53}Ga{sub 0.47}As-OI MOSFETs with biaxial strain. We have clarified from a systematic analysis between the strain values and the ?{sub eff} characteristics that this mobility behavior can be understood by the change of the energy level of the conduction band minimum due to the lateral strain relaxation.

  13. Submitted to Device Research Conference, June 2003 SiGe Single-Hole Transistor Fabricated by AFM Oxidation and Epitaxial Regrowth

    E-Print Network [OSTI]

    Rokhinson, Leonid

    Submitted to Device Research Conference, June 2003 SiGe Single-Hole Transistor Fabricated by AFM-energy patterning process based on AFM lithography (to avoid defects from e-beam and RIE) and Si/SiGe). A single-hole transistor, which is the first reported SiGe quantum device with heterojunction passivation

  14. C-H surface diamond field effect transistors for high temperature (400?°C) and high voltage (500?V) operation

    SciTech Connect (OSTI)

    Kawarada, H., E-mail: kawarada@waseda.jp [Faculty of Science and Engineering, Waseda University, Shinjuku, Tokyo 169-8555 (Japan); Institute of Nano-Science and Nano-Engineering, Waseda University, Shinjuku, Tokyo 169-8555 (Japan); Kagami Memorial Laboratory for Material Science and Technology, Waseda University, Shinjuku, Tokyo 169-0051 (Japan); Tsuboi, H.; Naruo, T.; Yamada, T.; Xu, D.; Daicho, A.; Saito, T. [Faculty of Science and Engineering, Waseda University, Shinjuku, Tokyo 169-8555 (Japan); Hiraiwa, A. [Institute of Nano-Science and Nano-Engineering, Waseda University, Shinjuku, Tokyo 169-8555 (Japan)

    2014-07-07T23:59:59.000Z

    By forming a highly stable Al{sub 2}O{sub 3} gate oxide on a C-H bonded channel of diamond, high-temperature, and high-voltage metal-oxide-semiconductor field-effect transistor (MOSFET) has been realized. From room temperature to 400?°C (673?K), the variation of maximum drain-current is within 30% at a given gate bias. The maximum breakdown voltage (V{sub B}) of the MOSFET without a field plate is 600?V at a gate-drain distance (L{sub GD}) of 7 ?m. We fabricated some MOSFETs for which V{sub B}/L{sub GD}?>?100?V/?m. These values are comparable to those of lateral SiC or GaN FETs. The Al{sub 2}O{sub 3} was deposited on the C-H surface by atomic layer deposition (ALD) at 450?°C using H{sub 2}O as an oxidant. The ALD at relatively high temperature results in stable p-type conduction and FET operation at 400?°C in vacuum. The drain current density and transconductance normalized by the gate width are almost constant from room temperature to 400?°C in vacuum and are about 10 times higher than those of boron-doped diamond FETs.

  15. Femtosecond all-optical parallel logic gates based on tunable saturable to reverse saturable absorption in graphene-oxide thin films

    SciTech Connect (OSTI)

    Roy, Sukhdev, E-mail: sukhdevroy@dei.ac.in; Yadav, Chandresh [Department of Physics and Computer Science, Dayalbagh Educational Institute, Dayalbagh, Agra 282 005 (India)] [Department of Physics and Computer Science, Dayalbagh Educational Institute, Dayalbagh, Agra 282 005 (India)

    2013-12-09T23:59:59.000Z

    A detailed theoretical analysis of ultrafast transition from saturable absorption (SA) to reverse saturable absorption (RSA) has been presented in graphene-oxide thin films with femtosecond laser pulses at 800?nm. Increase in pulse intensity leads to switching from SA to RSA with increased contrast due to two-photon absorption induced excited-state absorption. Theoretical results are in good agreement with reported experimental results. Interestingly, it is also shown that increase in concentration results in RSA to SA transition. The switching has been optimized to design parallel all-optical femtosecond NOT, AND, OR, XOR, and the universal NAND and NOR logic gates.

  16. Positive bias temperature instability in p-type metal-oxide-semiconductor devices with HfSiON/SiO{sub 2} gate dielectrics

    SciTech Connect (OSTI)

    Samanta, Piyas, E-mail: piyas@vcfw.org [Department of Physics, Vidyasagar College for Women, 39 Sankar Ghosh Lane, Kolkata 700 006 (India); Huang, Heng-Sheng; Chen, Shuang-Yuan [Institute of Mechatronic Engineering, National Taipei University of Technology, No. 1, Sec. 3, Chung-Hsiao E. Rd., Taipei 106, Taiwan (China); Liu, Chuan-Hsi [Department of Mechatronic Technology, National Taiwan Normal University, No. 162, Sec. 1, He-Ping E. Rd., Taipei 106, Taiwan (China); Cheng, Li-Wei [Central R and D Division, United Microelectronics Corporation, No. 3, Li-Hsin Rd. II, Hsinchu 300, Taiwan (China)

    2014-02-21T23:59:59.000Z

    We present a detailed investigation on positive-bias temperature stress (PBTS) induced degradation of nitrided hafnium silicate (HfSiON)/SiO{sub 2} gate stack in n{sup +}-poly crystalline silicon (polySi) gate p-type metal-oxide-semiconductor (pMOS) devices. The measurement results indicate that gate dielectric degradation is a composite effect of electron trapping in as-fabricated as well as newly generated neutral traps, resulting a significant amount of stress-induced leakage current and generation of surface states at the Si/SiO{sub 2} interface. Although, a significant amount of interface states are created during PBTS, the threshold voltage (V{sub T}) instability of the HfSiON based pMOS devices is primarily caused by electron trapping and detrapping. It is also shown that PBTS creates both acceptor- and donor-like interface traps via different depassivation mechanisms of the Si{sub 3}???SiH bonds at the Si/SiO{sub 2} interface in pMOS devices. However, the number of donor-like interface traps ?N{sub it}{sup D} is significantly greater than that of acceptor-like interface traps ?N{sup A}{sub it}, resulting the PBTS induced net interface traps as donor-like.

  17. Compact modeling of quantum effects in double gate MOSFETs

    E-Print Network [OSTI]

    Wang, Wei

    2007-01-01T23:59:59.000Z

    However, ultrathin gate oxide will lead to high gate leakagethe high enough oxide barrier confinement leads to zero waveoxide becomes significant. The random dopant fluctuation effects increase with shrinking device size and leads

  18. A methodology to identify and quantify mobility-reducing defects in 4H-silicon carbide power metal-oxide-semiconductor field-effect transistors

    SciTech Connect (OSTI)

    Ettisserry, D. P., E-mail: deva@umd.edu; Goldsman, N. [Department of Electrical and Computer Engineering, University of Maryland, College Park, Maryland 20742 (United States); Lelis, A. [U.S. Army Research Laboratory, 2800 Powder Mill Road, Adelphi, Maryland 20783 (United States)

    2014-03-14T23:59:59.000Z

    In this paper, we present a methodology for the identification and quantification of defects responsible for low channel mobility in 4H-Silicon Carbide (SiC) power metal-oxide-semiconductor field-effect transistors (MOSFETs). To achieve this, we use an algorithm based on 2D-device simulations of a power MOSFET, density functional simulations, and measurement data. Using physical modeling of carrier mobility and interface traps, we reproduce the experimental I-V characteristics of a 4H-SiC doubly implanted MOSFET through drift-diffusion simulation. We extract the position of Fermi level and the occupied trap density as a function of applied bias and temperature. Using these inputs, our algorithm estimates the number of possible trap types, their energy levels, and concentrations at 4H-SiC/SiO{sub 2} interface. Subsequently, we use density functional theory (DFT)-based ab initio simulations to identify the atomic make-up of defects causing these trap levels. We study silicon vacancy and carbon di-interstitial defects in the SiC side of the interface. Our algorithm indicates that the D{sub it} spectrum near the conduction band edge (3.25?eV) is composed of three trap types located at 2.8–2.85?eV, 3.05?eV, and 3.1–3.2?eV, and also calculates their densities. Based on DFT simulations, this work attributes the trap levels very close to the conduction band edge to the C di-interstitial defect.

  19. Sample size requirements for estimating effective dose from computed tomography using solid-state metal-oxide-semiconductor field-effect transistor dosimetry

    SciTech Connect (OSTI)

    Trattner, Sigal [Department of Medicine, Division of Cardiology, Columbia University Medical Center and New York-Presbyterian Hospital, New York, New York 10032 (United States)] [Department of Medicine, Division of Cardiology, Columbia University Medical Center and New York-Presbyterian Hospital, New York, New York 10032 (United States); Cheng, Bin [Department of Biostatistics, Columbia University Mailman School of Public Health, New York, New York 10032 (United States)] [Department of Biostatistics, Columbia University Mailman School of Public Health, New York, New York 10032 (United States); Pieniazek, Radoslaw L. [Center for Radiological Research, Columbia University Medical Center and New York-Presbyterian Hospital, New York, New York 10032 (United States)] [Center for Radiological Research, Columbia University Medical Center and New York-Presbyterian Hospital, New York, New York 10032 (United States); Hoffmann, Udo [Department of Radiology, Massachusetts General Hospital and Harvard Medical School, Boston, Massachusetts 02114 (United States)] [Department of Radiology, Massachusetts General Hospital and Harvard Medical School, Boston, Massachusetts 02114 (United States); Douglas, Pamela S. [Department of Medicine, Division of Cardiology, Duke University, Durham, North Carolina 27715 (United States)] [Department of Medicine, Division of Cardiology, Duke University, Durham, North Carolina 27715 (United States); Einstein, Andrew J., E-mail: andrew.einstein@columbia.edu [Department of Medicine, Division of Cardiology, Columbia University Medical Center and New York-Presbyterian Hospital, New York, New York and Department of Radiology, Columbia University Medical Center and New York-Presbyterian Hospital, New York, New York (United States)

    2014-04-15T23:59:59.000Z

    Purpose: Effective dose (ED) is a widely used metric for comparing ionizing radiation burden between different imaging modalities, scanners, and scan protocols. In computed tomography (CT), ED can be estimated by performing scans on an anthropomorphic phantom in which metal-oxide-semiconductor field-effect transistor (MOSFET) solid-state dosimeters have been placed to enable organ dose measurements. Here a statistical framework is established to determine the sample size (number of scans) needed for estimating ED to a desired precision and confidence, for a particular scanner and scan protocol, subject to practical limitations. Methods: The statistical scheme involves solving equations which minimize the sample size required for estimating ED to desired precision and confidence. It is subject to a constrained variation of the estimated ED and solved using the Lagrange multiplier method. The scheme incorporates measurement variation introduced both by MOSFET calibration, and by variation in MOSFET readings between repeated CT scans. Sample size requirements are illustrated on cardiac, chest, and abdomen–pelvis CT scans performed on a 320-row scanner and chest CT performed on a 16-row scanner. Results: Sample sizes for estimating ED vary considerably between scanners and protocols. Sample size increases as the required precision or confidence is higher and also as the anticipated ED is lower. For example, for a helical chest protocol, for 95% confidence and 5% precision for the ED, 30 measurements are required on the 320-row scanner and 11 on the 16-row scanner when the anticipated ED is 4 mSv; these sample sizes are 5 and 2, respectively, when the anticipated ED is 10 mSv. Conclusions: Applying the suggested scheme, it was found that even at modest sample sizes, it is feasible to estimate ED with high precision and a high degree of confidence. As CT technology develops enabling ED to be lowered, more MOSFET measurements are needed to estimate ED with the same precision and confidence.

  20. Integration of pentacene-based thin film transistors via photolithography for low and high voltage applications

    E-Print Network [OSTI]

    Smith, Melissa Alyson

    2012-01-01T23:59:59.000Z

    An organic thin film transistor (OTFT) technology platform has been developed for flexible integrated circuits applications. OTFT performance is tuned by engineering the dielectric constant of the gate insulator and the ...

  1. High-performance amorphous gallium indium zinc oxide thin-film transistors through N{sub 2}O plasma passivation

    SciTech Connect (OSTI)

    Park, Jaechul; Kim, Sangwook; Kim, Changjung; Kim, Sunil; Song, Ihun; Yin, Huaxiang; Kim, Kyoung-Kok; Lee, Sunghoon; Hong, Kiha; Park, Youngsoo [Semiconductor Device Laboratory, Samsung Advanced Institute of Technology, Yongin-Si, Gyeonggi-Do 449-712 (Korea, Republic of); Lee, Jaecheol; Jung, Jaekwan; Lee, Eunha [Analytical Engineering Center, Samsung Advanced Institute of Technology, Yongin-Si, Gyeonggi-Do 449-712 (Korea, Republic of); Kwon, Kee-Won [Department of Semiconductor Systems Engineering, Sungkyunkwan University, Suwon-Si, Gyeonggi-Do 440-746 (Korea, Republic of)

    2008-08-04T23:59:59.000Z

    Amorphous-gallium-indium-zinc-oxide (a-GIZO) thin filmtransistors (TFTs) are fabricated without annealing, using processes and equipment for conventional a-Si:H TFTs. It has been very difficult to obtain sound TFT characteristics, because the a-GIZO active layer becomes conductive after dry etching the Mo source/drain electrode and depositing the a-SiO{sub 2} passivation layer. To prevent such damages, N{sub 2}O plasma is applied to the back surface of the a-GIZO channel layer before a-SiO{sub 2} deposition. N{sub 2}O plasma-treated a-GIZO TFTs exhibit excellent electrical properties: a field effect mobility of 37 cm{sup 2}/V s, a threshold voltage of 0.1 V, a subthreshold swing of 0.25 V/decade, and an I{sub on/off} ratio of 7.

  2. All diamond self-aligned thin film transistor

    DOE Patents [OSTI]

    Gerbi, Jennifer (Champaign, IL)

    2008-07-01T23:59:59.000Z

    A substantially all diamond transistor with an electrically insulating substrate, an electrically conductive diamond layer on the substrate, and a source and a drain contact on the electrically conductive diamond layer. An electrically insulating diamond layer is in contact with the electrically conductive diamond layer, and a gate contact is on the electrically insulating diamond layer. The diamond layers may be homoepitaxial, polycrystalline, nanocrystalline or ultrananocrystalline in various combinations.A method of making a substantially all diamond self-aligned gate transistor is disclosed in which seeding and patterning can be avoided or minimized, if desired.

  3. Quantum Behavior of Graphene Transistors near the Scaling Limit Yanqing Wu,,

    E-Print Network [OSTI]

    Perebeinos, Vasili

    and drain metallic contacts alter the intrinsic graphene properties and produce an effective electron of the entire graphene device including the source and drain electrodes is of vital importance in technology of practical graphene transistors. Transport Mechanism of a Back-Gated Graphene Transistor. Arrays

  4. Electrical gating effects on the magnetic properties of (Ga,Mn)As diluted magnetic semiconductors

    E-Print Network [OSTI]

    Owen, Man Hon Samuel

    2010-11-16T23:59:59.000Z

    -effect transistor (FET) based on low-doped Ga0.975Mn0.025As was fabricated. It has an in-built n-GaAs back-gate, which, in addition to being a normal gate, enhances the gating effects, especially in the depletion of the epilayer, by decreasing the effective channel...

  5. Gate-First AlGaN/GaN HEMT Technology for High-Frequency Applications

    E-Print Network [OSTI]

    Piner, Edwin L.

    This letter describes a gate-first AlGaN/GaN high-electron mobility transistor (HEMT) with a W/high-k dielectric gate stack. In this new fabrication technology, the gate stack is deposited before the ohmic contacts, and ...

  6. Electrostatic Control of Ions and Molecules in Nanofluidic Transistors

    E-Print Network [OSTI]

    Yang, Peidong

    Electrostatic Control of Ions and Molecules in Nanofluidic Transistors Rohit Karnik,,| Rong Fan report a nanofluidic transistor based on a metal-oxide-solution (MOSol) system that is similar to a metal the ionic conductance. Our results illustrate the efficacy of field-effect control in nanofluidics, which

  7. A thermalization energy analysis of the threshold voltage shift in amorphous indium gallium zinc oxide thin film transistors under simultaneous negative gate bias and illumination

    E-Print Network [OSTI]

    Flewitt, Andrew J.; Powell, M.J.

    2014-01-01T23:59:59.000Z

    of the display industry as it moves from liquid crystal to organic light emitting diode technology and with requirements for larger areas and higher resolutions. A number of alternative material systems to a-Si:H have emerged, including organic semiconductors...

  8. ZrO2 gate dielectrics produced by ultraviolet ozone oxidation for GaN and AlGaN/GaN transistors

    E-Print Network [OSTI]

    2006-01-01T23:59:59.000Z

    MOSCAP process ?ow: n-GaN substrate; Ohmic metallization andtion for a AlGaN/ GaN HEMT on a substrate which has a poorsapphire substrate, a well-passivated AlGaN/ GaN HEMT grown

  9. Al{sub 2}O{sub 3}/GeO{sub x} gate stack on germanium substrate fabricated by in situ cycling ozone oxidation method

    SciTech Connect (OSTI)

    Yang, Xu; Zeng, Zhen-Hua [Advanced Photonics Center, School of Electronic Science and Engineering, Southeast University, Nanjing 210096 (China); Microwave Device and IC Department, Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029 (China); Wang, Sheng-Kai, E-mail: wangshengkai@ime.ac.cn, E-mail: xzhang62@aliyun.com, E-mail: liuhonggang@ime.ac.cn; Sun, Bing; Zhao, Wei; Chang, Hu-Dong; Liu, Honggang, E-mail: wangshengkai@ime.ac.cn, E-mail: xzhang62@aliyun.com, E-mail: liuhonggang@ime.ac.cn [Microwave Device and IC Department, Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029 (China); Zhang, Xiong, E-mail: wangshengkai@ime.ac.cn, E-mail: xzhang62@aliyun.com, E-mail: liuhonggang@ime.ac.cn [Advanced Photonics Center, School of Electronic Science and Engineering, Southeast University, Nanjing 210096 (China)

    2014-09-01T23:59:59.000Z

    Al{sub 2}O{sub 3}/GeO{sub x}/Ge gate stack fabricated by an in situ cycling ozone oxidation (COO) method in the atomic layer deposition (ALD) system at low temperature is systematically investigated. Excellent electrical characteristics such as minimum interface trap density as low as 1.9?×?10{sup 11?}cm{sup ?2?}eV{sup ?1} have been obtained by COO treatment. The impact of COO treatment against the band alignment of Al{sub 2}O{sub 3} with respect to Ge is studied by x-ray photoelectron spectroscopy (XPS) and spectroscopic ellipsometry (SE). Based on both XPS and SE studies, the origin of gate leakage in the ALD-Al{sub 2}O{sub 3} is attributed to the sub-gap states, which may be correlated to the OH-related groups in Al{sub 2}O{sub 3} network. It is demonstrated that the COO method is effective in repairing the OH-related defects in high-k dielectrics as well as forming superior high-k/Ge interface for high performance Ge MOS devices.

  10. Synthesis and charge-transport properties of polymers derived from the oxidation of 1-hydro-1'-(6-(pyrrol-1-yl)hexyl)-4,4'-bipyridium Bis(hexafluorophosphate) and demonstration of pH-sensitive microelectrochemical transistor derived from the redox properties of a conventional redox center

    SciTech Connect (OSTI)

    Shu, C.F.; Wrighton, M.S.

    1988-09-08T23:59:59.000Z

    This article describes the synthesis and electrochemical properties of redox polymers, having a polypyrrole backbone and viologen subunits, derived from oxidative electropolymerization of 1-methyl-1'-(6-(pyrrol-1-yl)hexyl)-4,4'-bipyridinium (P-V-Me/sup 2 +/) and 1-hydro-1'-(6-(pyrrol-1-yl)hexyl)-4,4'-bipyridinium (P-V-H/sup 2 +/). Closely spaced (approx. 1.5 ..mu..M) Au microelectrode arrays (approx. 2.5 ..mu..m wide /times/ 50 ..mu..m long /times/ 0.1 ..mu..m high) modified with the polymers can be used to study aspects of the charge-transport behavior of the viologen redox system. Poly(P-V-Me/sup 2 +/) have been used to investigate the characteristics of microelectrochemical transistors based on a viologen redox center and a similar redox center, protonated, monoquaternized bipyridinium, which is pH dependent. The interesting properties from poly(P-V-Me/sup 2 +/) and poly(P-V-H/sup 2 +/) stem from behavior of the pendant viologen redox centers. The device based on poly(P-V-Me/sup 2 +/) has a narrow region (approx. 200 mV) of gate voltage, V/sub G/, where the source-drain current, I/sub D/, is nonzero and has a sharp, pH-independent peak in the I/sub D/-V/sub G/ plot at approx. 0.53 V versus SCE associated with the reversible, one-electron reduction of viologen. This result is consistent with electron self-exchange between redox centers being the mechanism for charge transport. The device based on poly(P-V-H/sup 2 +/) shows a pH-dependent I/sub D/ at fixed V/sub G/, as expected from the electrochemical behavior from reversible protonation of the terminal N of the bipyridinium group of poly(P-V-H/sup 2 +/). The microelectrochemical transistor based on poly(P-V-H/sup 2 +/) illustrates the design of chemically sensitive, molecule-based devices using conventional redox materials.

  11. Hole mobility enhancements in strained SiSi1yGey p-type metal-oxide-semiconductor field-effect transistors grown on relaxed

    E-Print Network [OSTI]

    -effect transistors grown on relaxed Si1ÀxGex ,,xËy... virtual substrates C. W. Leitz,a) M. T. Currie, M. L. Lee, Z.-Y. Cheng, D. A. Antoniadis,b) and E. A. Fitzgerald Department of Materials Science and Engineering

  12. III International Conference on SiGe(C) Epitaxy and Heterostructures, NM, Mar. 2003 SiGe Single-Hole Transistor Fabricated by AFM Oxidation and Epitaxial Regrowth

    E-Print Network [OSTI]

    III International Conference on SiGe(C) Epitaxy and Heterostructures, NM, Mar. 2003 110 SiGe Single, West Lafayette, IN 47907, U.S.A. Nanodevices on Si/SiGe heterostructures are of growing interest [1 the performance of the devices. In this paper, we demonstrate a reproducible single-hole transistor SiGe device

  13. Single hole quantum dot transistors in silicon Effendi Leobandung, Lingjie Guo, and Stephen Y. Choua)

    E-Print Network [OSTI]

    of the gate voltage have been observed at temperatures over 81 K and drain biases over 66 mV. The oscillations to the drain. As the gate voltage was scanned, the drain current i.e., the hole current oscil- lated Fig. 3-dot transistors were fabricated in silicon-on-insulator. Strong oscillations in the drain current as a function

  14. X-ray lithographic alignment and overlay applied to double-gate MOSFET fabrication

    E-Print Network [OSTI]

    Meinhold, Mitchell W., 1972-

    2003-01-01T23:59:59.000Z

    Double-gate MOSFETs represent a significant solution to transistor scaling problems and promise a dramatic improvement in both performance and power consumption. In this work, a planar lithographic process is presented ...

  15. Atomistic full-band simulations of monolayer MoS{sub 2} transistors

    SciTech Connect (OSTI)

    Chang, Jiwon; Register, Leonard F.; Banerjee, Sanjay K. [Microelectronics Research Center, The University of Texas at Austin, Austin, Texas 78758 (United States)] [Microelectronics Research Center, The University of Texas at Austin, Austin, Texas 78758 (United States)

    2013-11-25T23:59:59.000Z

    We study the transport properties of deeply scaled monolayer MoS{sub 2} n-channel metal-oxide-semiconductor field effect transistors (MOSFETs), using full-band ballistic quantum transport simulations, with an atomistic tight-binding Hamiltonian obtained from density functional theory. Our simulations suggest that monolayer MoS{sub 2} MOSFETs can provide near-ideal subthreshold slope, suppression of drain-induced barrier lowering, and gate-induced drain leakage. However, these full-band simulations exhibit limited transconductance. These ballistic simulations also exhibit negative differential resistance (NDR) in the output characteristics associated with the narrow width in energy of the lowest conduction band, but this NDR may be substantially reduced or eliminated by scattering in MoS{sub 2}.

  16. Detection of terahertz radiation by tightly concatenated InGaAs field-effect transistors integrated on a single chip

    SciTech Connect (OSTI)

    Popov, V. V., E-mail: popov-slava@yahoo.co.uk [Kotelnikov Institute of Radio Engineering and Electronics (Saratov Branch), Russian Academy of Sciences, Saratov 410019 (Russian Federation); Yermolaev, D. M.; Shapoval, S. Yu. [Institute of Microelectronic Technology and High-Purity Materials, Russian Academy of Sciences, Chernogolovka, Moscow Region 142432 (Russian Federation); Maremyanin, K. V.; Gavrilenko, V. I. [Institute for Physics of Microstructures, Russian Academy of Sciences, Nizhny Novgorod 603950 (Russian Federation); Lobachevsky State University of Nizhni Novgorod, Nizhni Novgorod 603950 (Russian Federation); Zemlyakov, V. E.; Bespalov, V. A.; Yegorkin, V. I. [National Research University of Electronic Technology, Zelenograd, Moscow 124498 (Russian Federation); Maleev, N. A.; Ustinov, V. M. [Ioffe Physical Technical Institute, Russian Academy of Sciences, St. Petersburg 194021 (Russian Federation)

    2014-04-21T23:59:59.000Z

    A tightly concatenated chain of InGaAs field-effect transistors with an asymmetric T-gate in each transistor demonstrates strong terahertz photovoltaic response without using supplementary antenna elements. We obtain the responsivity above 1000?V/W and up to 2000?V/W for unbiased and drain-biased transistors in the chain, respectively, with the noise equivalent power below 10{sup ?11} W/Hz{sup 0.5} in the unbiased mode of the detector operation.

  17. Electrothermal simulation of the self-heating effects in GaN-based field-effect transistors

    E-Print Network [OSTI]

    Electrothermal simulation of the self-heating effects in GaN-based field-effect transistors of self-heating effects in GaN-based high-power field-effect transistors. The problem of heat transfer with multiple gate fingers. Particular attention has been paid to comparison of self-heating effects in Ga

  18. Vertical graphene base transistor

    E-Print Network [OSTI]

    2012-01-01T23:59:59.000Z

    M. Baus, and H. Kurz, “A graphene ?eld-effect device,” IEEERooks, and P. Avouris, “Graphene nano- ribbon electronics,”High-frequency, scaled graphene transistors on diamond- like

  19. Fabricating metal-oxide-semiconductor field-effect transistors on a polyethylene terephthalate substrate by applying low-temperature layer transfer of a single-crystalline silicon layer by meniscus force

    SciTech Connect (OSTI)

    Sakaike, Kohei; Akazawa, Muneki; Nakamura, Shogo [Department of Semiconductor Electronics and Integration Science, Graduate School of Advanced Sciences of Matter, Hiroshima University, Kagamiyama 1-3-1, Higashihiroshima, Hiroshima 739-8530 (Japan)] [Department of Semiconductor Electronics and Integration Science, Graduate School of Advanced Sciences of Matter, Hiroshima University, Kagamiyama 1-3-1, Higashihiroshima, Hiroshima 739-8530 (Japan); Higashi, Seiichiro [Department of Semiconductor Electronics and Integration Science, Graduate School of Advanced Sciences of Matter, Hiroshima University, Kagamiyama 1-3-1, Higashihiroshima, Hiroshima 739-8530 (Japan) [Department of Semiconductor Electronics and Integration Science, Graduate School of Advanced Sciences of Matter, Hiroshima University, Kagamiyama 1-3-1, Higashihiroshima, Hiroshima 739-8530 (Japan); Research Institute for Nanodevice and Bio Systems, Hiroshima University, Kagamiyama 1-4-2, Higashihiroshima, Hiroshima 739-8527 (Japan)

    2013-12-02T23:59:59.000Z

    A low-temperature local-layer technique for transferring a single-crystalline silicon (c-Si) film by using a meniscus force was proposed, and an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) was fabricated on polyethylene terephthalate (PET) substrate. It was demonstrated that it is possible to transfer and form c-Si films in the required shape at the required position on PET substrates at extremely low temperatures by utilizing a meniscus force. The proposed technique for layer transfer was applied for fabricating high-performance c-Si MOSFETs on a PET substrate. The fabricated MOSFET showed a high on/off ratio of more than 10{sup 8} and a high field-effect mobility of 609 cm{sup 2} V{sup ?1} s{sup ?1}.

  20. Controlled ambient and temperature treatment of InGaZnO thin film transistors for improved bias-illumination stress reliability

    SciTech Connect (OSTI)

    Vemuri, Rajitha N. P., E-mail: rvemuri@asu.edu [School for Engineering of Matter, Transport and Energy, Arizona State University, Tempe 85287 (United States); Hasin, Muhammad R. [School of Electrical, Computer and Energy Engineering, Arizona State University, Tempe 85287 (United States); Alford, T. L., E-mail: TA@asu.edu [School for Engineering of Matter, Transport and Energy, Arizona State University, Tempe 85287 and School of Electrical, Computer and Energy Engineering, Arizona State University, Tempe 85287 (United States)

    2014-03-15T23:59:59.000Z

    The failure mechanisms arising from the instability in operation of indium gallium zinc oxide based thin film transistors (TFTs) upon prolonged real application stresses (bias and illumination) have been extensively studied and reported. Positive and negative gate bias conditions, along with high photonic energy wavelengths within visible light spectrum are used as stress conditions. The increased carrier concentration due to photonic excitation of defects within bandgap and ionization of deep level vacancies is compensated by the reduction in off currents under illumination due to the trapping of carriers in the intermetal dielectric. Band lowering at the source-channel junction due to accumulation of negative carriers repelled due to negative gate bias stress further causes high carrier flow into the channel and drives the devices into failure. The defect identification during failure and degradation assisted in proposing suitable low temperature post processing in specific ambients. Reliability tests after specific anneals in oxygen, vacuum, and forming gas ambients confirm the correlation of the defect type with anneal ambient. Annealed TFTs demonstrate high stabilities under illumination stresses and do not fail when subjected to combined stresses that cause failure in as-fabricated TFTs. Oxygen and forming gas anneals are impactful on the reliability and opens an area of study on donor and vacancy behavior in amorphous mixed oxide based TFTs. The subthreshold swing, field-effect mobilities, and off currents provide knowledge on best anneal practices by understanding role of hydrogen and oxygen in vacancy annihilation and transistor switching properties.

  1. Improvement of bias-stability in amorphous-indium-gallium-zinc-oxide thin-film transistors by using solution-processed Y{sub 2}O{sub 3} passivation

    SciTech Connect (OSTI)

    An, Sungjin; Mativenga, Mallory; Kim, Youngoo; Jang, Jin, E-mail: jjang@khu.ac.kr [Advanced Display Research Center, Department of Information Display, Kyung Hee University, Dongdaemun-gu, Seoul 130-701 (Korea, Republic of)

    2014-08-04T23:59:59.000Z

    We demonstrate back channel improvement of back-channel-etch amorphous-indium-gallium-zinc-oxide (a-IGZO) thin-film transistors by using solution-processed yttrium oxide (Y{sub 2}O{sub 3}) passivation. Two different solvents, which are acetonitrile (35%)?+?ethylene glycol (65%), solvent A and deionized water, solvent B are investigated for the spin-on process of the Y{sub 2}O{sub 3} passivation—performed after patterning source/drain (S/D) Mo electrodes by a conventional HNO{sub 3}-based wet-etch process. Both solvents yield devices with good performance but those passivated by using solvent B exhibit better light and bias stability. Presence of yttrium at the a-IGZO back interface, where it occupies metal vacancy sites, is confirmed by X-ray photoelectron spectroscopy. The passivation effect of yttrium is more significant when solvent A is used because of the existence of more metal vacancies, given that the alcohol (65% ethylene glycol) in solvent A may dissolve the metal oxide (a-IGZO) through the formation of alkoxides and water.

  2. Design and characterization of a signal insulation coreless transformer integrated in a CMOS gate driver chip

    E-Print Network [OSTI]

    Paris-Sud XI, Université de

    Design and characterization of a signal insulation coreless transformer integrated in a CMOS gate the implementation of numerous distinct power transistor gate drivers, the control signal insulation is becoming more results will be shown in order to validate the functionality. I. INTRODUCTION An insulation system

  3. Printed inorganic transistors

    E-Print Network [OSTI]

    Ridley, Brent (Brent Alan), 1974-

    2003-01-01T23:59:59.000Z

    Forty years of exponential growth of semiconductor technology have been predicated on the miniaturization of the transistors that comprise integrated circuits. While complexity has greatly increased within a given area of ...

  4. Method for formation of thin film transistors on plastic substrates

    DOE Patents [OSTI]

    Carey, P.G.; Smith, P.M.; Sigmon, T.W.; Aceves, R.C.

    1998-10-06T23:59:59.000Z

    A process for formation of thin film transistors (TFTs) on plastic substrates replaces standard thin film transistor fabrication techniques, and uses sufficiently lower processing temperatures so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The process relies on techniques for depositing semiconductors, dielectrics, and metals at low temperatures; crystallizing and doping semiconductor layers in the TFT with a pulsed energy source; and creating top-gate self-aligned as well as back-gate TFT structures. The process enables the fabrication of amorphous and polycrystalline channel silicon TFTs at temperatures sufficiently low to prevent damage to plastic substrates. The process has use in large area low cost electronics, such as flat panel displays and portable electronics. 5 figs.

  5. Method for formation of thin film transistors on plastic substrates

    DOE Patents [OSTI]

    Carey, Paul G. (Mountain View, CA); Smith, Patrick M. (San Ramon, CA); Sigmon, Thomas W. (Portola Valley, CA); Aceves, Randy C. (Livermore, CA)

    1998-10-06T23:59:59.000Z

    A process for formation of thin film transistors (TFTs) on plastic substrates replaces standard thin film transistor fabrication techniques, and uses sufficiently lower processing temperatures so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The process relies on techniques for depositing semiconductors, dielectrics, and metals at low temperatures; crystallizing and doping semiconductor layers in the TFT with a pulsed energy source; and creating top-gate self-aligned as well as back-gate TFT structures. The process enables the fabrication of amorphous and polycrystalline channel silicon TFTs at temperatures sufficiently low to prevent damage to plastic substrates. The process has use in large area low cost electronics, such as flat panel displays and portable electronics.

  6. Total-dose response of silicon-on-insulator (soi) metal-oxide- semiconductor field-effect transistor's (mosfet's). Master's thesis

    SciTech Connect (OSTI)

    Biwer, M.C.

    1988-06-01T23:59:59.000Z

    Total-dose response of both NMOS and PMOS FET's fabricated on SIMOX and ZMR substrates was studied. Two types of back-channel leakage currents were identified for the SIMOX devices. A back channel leakage due to MOSFET action uses the substrate bias as the gate bias. The other component is due to soft reverse characteristics of the body-drain junction. The back-channel leakage due to MOSFET action varies with the substrate bias and thus varies with irradiation due to threshold-voltage shift. The soft reverse current is a function of drain-body voltage and hence varies with substrate bias and irradiation. The threshold-voltage, I-V characteristics, and subthreshold currents of both front and back channels as a function of total dose were obtained.

  7. SiGe virtual substrate HMOS transistor for analogue applications K. Michelakisa,*

    E-Print Network [OSTI]

    Papavassiliou, Christos

    SiGe virtual substrate HMOS transistor for analogue applications K. Michelakisa,* , S Abstract Silicon­germanium (SiGe) heterojunction metal-oxide-semiconductor field-effect transistors (SiGe design. The results suggest that the realisation of buried-channel SiGe n-HMOSFETs is feasible in MOS

  8. Feasibility of a vortex transistor

    SciTech Connect (OSTI)

    Nevirkovets, I.P.; Rudenko, E.M.

    1985-08-01T23:59:59.000Z

    An experimental test is reported of the feasibility of developing a vortex transistor using tunnel junctions made from tin. (AIP)

  9. IEEE ELECTRON DEVICE LETTERS, VOL. 21, NO. 12, DECEMBER 2000 549 Dual-Gate AlGaN/GaN Modulation-Doped

    E-Print Network [OSTI]

    Rodwell, Mark J. W.

    IEEE ELECTRON DEVICE LETTERS, VOL. 21, NO. 12, DECEMBER 2000 549 Dual-Gate AlGaN/GaN Modulation--We demonstrate dual-gate AlGaN/GaN modula- tion-doped field-effect transistors (MODFETs) with gate-lengths of 0 power amplifiers. Index Terms--AlGaN/GaN, broadband power amplifiers, dual-gate FETs. I. INTRODUCTION

  10. Gate Access

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    AFDC Printable Version Share this resource Send a link to EERE: Alternative Fuels Data Center Home Page to someone by E-mail Share EERE: Alternative Fuels Data Center Home Page on Facebook Tweet about EERE: Alternative Fuels Data Center Home Page on Twitter Bookmark EERE: Alternative1 First Use of Energy for All Purposes (Fuel and Nonfuel), 2002; Level: National5Sales for4,645 3,625 1,006 492 742EnergyOnItem NotEnergy,ARMFormsGasReleaseSpeechesHall ATours,Dioxide andNationalall petroleumGate

  11. Low interface defect density of atomic layer deposition BeO with self-cleaning reaction for InGaAs metal oxide semiconductor field effect transistors

    SciTech Connect (OSTI)

    Shin, H. S. [Department of Electronics Engineering, Chungnam National University, Daejeon (Korea, Republic of) [Department of Electronics Engineering, Chungnam National University, Daejeon (Korea, Republic of); SEMATECH, 2706 Montopolis Dr., Austin, Texas 78741 (United States); The University of Texas, Austin, Texas 78758 (United States); Yum, J. H. [SEMATECH, 2706 Montopolis Dr., Austin, Texas 78741 (United States) [SEMATECH, 2706 Montopolis Dr., Austin, Texas 78741 (United States); The University of Texas, Austin, Texas 78758 (United States); Johnson, D. W. [SEMATECH, 2706 Montopolis Dr., Austin, Texas 78741 (United States) [SEMATECH, 2706 Montopolis Dr., Austin, Texas 78741 (United States); Texas A and M University College Station, Texas 77843 (United States); Harris, H. R. [Texas A and M University College Station, Texas 77843 (United States)] [Texas A and M University College Station, Texas 77843 (United States); Hudnall, Todd W. [Texas State University, 601 University Drive, San Marcos, Texas 78666 (United States)] [Texas State University, 601 University Drive, San Marcos, Texas 78666 (United States); Oh, J. [Yonsei University, Incheon, 406-840 (Korea, Republic of)] [Yonsei University, Incheon, 406-840 (Korea, Republic of); Kirsch, P.; Wang, W.-E. [SEMATECH, 2706 Montopolis Dr., Austin, Texas 78741 (United States)] [SEMATECH, 2706 Montopolis Dr., Austin, Texas 78741 (United States); Bielawski, C. W.; Banerjee, S. K.; Lee, J. C. [The University of Texas, Austin, Texas 78758 (United States)] [The University of Texas, Austin, Texas 78758 (United States); Lee, H. D. [Department of Electronics Engineering, Chungnam National University, Daejeon (Korea, Republic of)] [Department of Electronics Engineering, Chungnam National University, Daejeon (Korea, Republic of)

    2013-11-25T23:59:59.000Z

    In this paper, we discuss atomic configuration of atomic layer deposition (ALD) beryllium oxide (BeO) using the quantum chemistry to understand the theoretical origin. BeO has shorter bond length, higher reaction enthalpy, and larger bandgap energy compared with those of ALD aluminum oxide. It is shown that the excellent material properties of ALD BeO can reduce interface defect density due to the self-cleaning reaction and this contributes to the improvement of device performance of InGaAs MOSFETs. The low interface defect density and low leakage current of InGaAs MOSFET were demonstrated using X-ray photoelectron spectroscopy and the corresponding electrical results.

  12. THERMAL DEPENDENCE OF LOW-FREQUENCY NOISE IN POLYSILICON THIN FILM TRANSISTORS

    E-Print Network [OSTI]

    Boyer, Edmond

    characteristic energy. 1. Introduction Polysilicon thin-film transistors (TFTs) are key elements for flat panel and is crystallized by a solid phase crystallization thermal annealing at 600°C. A 60 nm thick SiO2 gate insulatorV) from weak to strong inversion. A temperature controlled wafer system, operating in vacuum (10-6 - 10

  13. The benzene molecule as a molecular resonant-tunneling transistor M. Di Ventraa)

    E-Print Network [OSTI]

    Pantelides, Sokrates T.

    The benzene molecule as a molecular resonant-tunneling transistor M. Di Ventraa) and S. T of transport through a benzene-1, 4-dithiolate molecule with a third capacitive terminal gate . We find rectification was demonstrated in 1993.2 More recently, Reed et al. investigated the benzene-1, 4-dithiol rings

  14. Gating of Permanent Molds for ALuminum Casting

    SciTech Connect (OSTI)

    David Schwam; John F. Wallace; Tom Engle; Qingming Chang

    2004-03-30T23:59:59.000Z

    This report summarizes a two-year project, DE-FC07-01ID13983 that concerns the gating of aluminum castings in permanent molds. The main goal of the project is to improve the quality of aluminum castings produced in permanent molds. The approach taken was determine how the vertical type gating systems used for permanent mold castings can be designed to fill the mold cavity with a minimum of damage to the quality of the resulting casting. It is evident that somewhat different systems are preferred for different shapes and sizes of aluminum castings. The main problems caused by improper gating are entrained aluminum oxide films and entrapped gas. The project highlights the characteristic features of gating systems used in permanent mold aluminum foundries and recommends gating procedures designed to avoid common defects. The study also provides direct evidence on the filling pattern and heat flow behavior in permanent mold castings.

  15. Electrical behavior of atomic layer deposited high quality SiO{sub 2} gate dielectric

    SciTech Connect (OSTI)

    Pradhan, Sangram K.; Tanyi, Ekembu K.; Skuza, Jonathan R.; Xiao, Bo; Pradhan, Aswini K., E-mail: apradhan@nsu.edu [Center for Materials Research, Norfolk State University, 700 Park Ave., Norfolk, Virginia 23504 (United States)

    2015-01-01T23:59:59.000Z

    Comprehensive and systematic electrical studies were performed on fabrication of high quality SiO{sub 2} thin films MOS capacitor using the robust, novel, and simple atomic layer deposition (ALD) technique using highly reactive ozone and tris (dimethylamino) silane (TDMAS) precursors. Ideal capacitance–voltage curve exhibits a very small frequency dispersion and hysteresis behavior of the SiO{sub 2} MOS capacitor grown at 1?s TDMAS pulse, suggesting excellent interfacial quality and purity of the film as probed using x-ray photoelectron studies. The flat-band voltage of the device shifted from negative toward positive voltage axis with increase of TDMAS pulses from 0.2 to 2 s. Based on an equivalent oxide thickness point of view, all SiO{sub 2} films have gate leakage current density of (5.18?×?10{sup ?8} A/cm{sup 2}) as well as high dielectric break down fields of more than (?10 MV/cm), which is better and comparable to that of thermally grown SiO{sub 2} at temperatures above 800?°C. These appealing electrical properties of ALD grown SiO{sub 2} thin films enable its potential applications such as high-quality gate insulators for thin film MOS transistors, as well as insulators for sensor and nanostructures on nonsilicon substrates.

  16. Ripple gate drive circuit for fast operation of series connected IGBTs

    DOE Patents [OSTI]

    Rockot, Joseph H.; Murray, Thomas W.; Bass, Kevin C.

    2005-09-20T23:59:59.000Z

    A ripple gate drive circuit includes a plurality of transistors having their power terminals connected in series across an electrical potential. A plurality of control circuits, each associated with one of the transistors, is provided. Each control circuit is responsive to a control signal and an optical signal received from at least one other control circuit for controlling the conduction of electrical current through the power terminals of the associated transistor. The control circuits are responsive to a first state of the control circuit for causing each transistor in series to turn on sequentially and responsive to a second state of the control signal for causing each transistor in series to turn off sequentially.

  17. Electrical characterization of native-oxide InAlPGaAs metal-oxide-semiconductor heterostructures using

    E-Print Network [OSTI]

    Electrical characterization of native-oxide InAlPÕGaAs metal-oxide-semiconductor heterostructures 8 December 2003; accepted 20 January 2004 InAIP native oxide/GaAs metal-oxide-semiconductor MOS of Schottky gates can lead to excessive gate leakage current and also restrict the forward gate bias to only

  18. Strained Ge channel p-type metaloxidesemiconductor field-effect transistors grown on Si1xGex Si virtual substrates

    E-Print Network [OSTI]

    Strained Ge channel p-type metal­oxide­semiconductor field-effect transistors grown on Si1ÀxGex ÕSi 2001; accepted for publication 29 August 2001 We have fabricated strained Ge channel p-type metal­oxide­semiconductor field-effect transistors (p-MOSFETs) on Si0.3Ge0.7 virtual substrates. The poor interface between

  19. Reduced-dimension transistors: Reduced-dimension transistors

    E-Print Network [OSTI]

    Pulfrey, David L.

    1 Reduced-dimension transistors: the HEMT LECTURE 20 · Reduced-dimension transistors · HEMT · 2-D;8 For a finite well · Wavefunction not completely confined · Use undoped spacer #12;9 Employment of a spacer scattering (µ ). · Electrons and donors separated no I I scattering, i.e., µ · Undoped spacer also helps

  20. Single atom impurity in a single molecular transistor

    SciTech Connect (OSTI)

    Ray, S. J., E-mail: ray.sjr@gmail.com [Institute of Materials Science, Technical University of Darmstadt, Alarich-Weiss Str. 2, 64287 Darmstadt (Germany)

    2014-10-21T23:59:59.000Z

    The influence of an impurity atom on the electrostatic behaviour of a Single Molecular Transistor was investigated through Ab-initio calculations in a double-gated geometry. The charge stability diagram carries unique signature of the position of the impurity atom in such devices which together with the charging energy of the molecule could be utilised as an electronic fingerprint for the detection of such impurity states in a nano-electronic device. The two gated geometry allows additional control over the electrostatics as can be seen from the total energy surfaces (for a specific charge state), which is sensitive to the positions of the impurity. These devices which are operational at room temperature can provide significant advantages over the conventional silicon based single dopant devices functional at low temperature. The present approach could be a very powerful tool for the detection and control of individual impurity atoms in a single molecular device and for applications in future molecular electronics.

  1. On the interest of carbon-coated plasma reactor for advanced gate stack etching processes

    SciTech Connect (OSTI)

    Ramos, R.; Cunge, G.; Joubert, O. [Freescale Semiconductor Inc., 850 Rue Jean Monnet, 38921 Crolles Cedex (France) and Laboratoire des Technologies de la Microelectronique, CNRS, 17 Rue des Martyrs (c/o CEA-LETI), 38054 Grenoble Cedex 9 (France); Laboratoire des Technologies de la Microelectronique, CNRS, 17 Rue des Martyrs (c/o CEA-LETI), 38054 Grenoble Cedex 9 (France)

    2007-03-15T23:59:59.000Z

    In integrated circuit fabrication the most wide spread strategy to achieve acceptable wafer-to-wafer reproducibility of the gate stack etching process is to dry-clean the plasma reactor walls between each wafer processed. However, inherent exposure of the reactor walls to fluorine-based plasma leads to formation and accumulation of nonvolatile fluoride residues (such as AlF{sub x}) on reactor wall surfaces, which in turn leads to process drifts and metallic contamination of wafers. To prevent this while keeping an Al{sub 2}O{sub 3} reactor wall material, a coating strategy must be used, in which the reactor is coated by a protective layer between wafers. It was shown recently that deposition of carbon-rich coating on the reactor walls allows improvements of process reproducibility and reactor wall protection. The authors show that this strategy results in a higher ion-to-neutral flux ratio to the wafer when compared to other strategies (clean or SiOCl{sub x}-coated reactors) because the carbon walls load reactive radical densities while keeping the same ion current. As a result, the etching rates are generally smaller in a carbon-coated reactor, but a highly anisotropic etching profile can be achieved in silicon and metal gates, whose etching is strongly ion assisted. Furthermore, thanks to the low density of Cl atoms in the carbon-coated reactor, silicon etching can be achieved almost without sidewall passivation layers, allowing fine critical dimension control to be achieved. In addition, it is shown that although the O atom density is also smaller in the carbon-coated reactor, the selectivity toward ultrathin gate oxides is not reduced dramatically. Furthermore, during metal gate etching over high-k dielectric, the low level of parasitic oxygen in the carbon-coated reactor also allows one to minimize bulk silicon reoxidation through HfO{sub 2} high-k gate dielectric. It is then shown that the BCl{sub 3} etching process of the HfO{sub 2} high-k material is highly selective toward the substrate in the carbon-coated reactor, and the carbon-coating strategy thus allows minimizing the silicon recess of the active area of transistors. The authors eventually demonstrate that the carbon-coating strategy drastically reduces on-wafer metallic contamination. Finally, the consumption of carbon from the reactor during the etching process is discussed (and thus the amount of initial deposit that is required to protect the reactor walls) together with the best way of cleaning the reactor after a silicon etching process.

  2. Impacts of SiN passivation on the degradation modes of AlGaN/GaN high electron mobility transistors under reverse-bias stress

    SciTech Connect (OSTI)

    Chen, Wei-Wei; Ma, Xiao-Hua, E-mail: xhma@xidian.edu.cn, E-mail: yhao@xidian.edu.cn; Hou, Bin; Zhu, Jie-Jie [School of Advanced Materials and Nanotechnology, Xidian University, Xi'an 710071 (China); Key Laboratory of Wide Band-Gap Semiconductor Materials and Devices, School of Microelectronics, Xidian University, Xi'an 710071 (China); Chen, Yong-He; Zheng, Xue-Feng; Zhang, Jin-Cheng; Hao, Yue, E-mail: xhma@xidian.edu.cn, E-mail: yhao@xidian.edu.cn [Key Laboratory of Wide Band-Gap Semiconductor Materials and Devices, School of Microelectronics, Xidian University, Xi'an 710071 (China)

    2014-10-27T23:59:59.000Z

    Impacts of SiN passivation on the degradation modes of AlGaN/GaN high electron mobility transistors are investigated. The gate leakage current decreases significantly upon removing the SiN layer and no clear critical voltage for the sudden degradation of the gate leakage current can be observed in the reverse-bias step-stress experiments. Gate-lag measurements reveal the decrease of the fast-state surface traps and the increase of slow-state traps after the passivation layer removal. It is postulated that consistent surface charging relieves the electric field peak on the gate edge, thus the inverse piezoelectric effect is shielded.

  3. Gated strip proportional detector

    DOE Patents [OSTI]

    Morris, Christopher L. (Los Alamos, NM); Idzorek, George C. (Los Alamos, NM); Atencio, Leroy G. (Espanola, NM)

    1987-01-01T23:59:59.000Z

    A gated strip proportional detector includes a gas tight chamber which encloses a solid ground plane, a wire anode plane, a wire gating plane, and a multiconductor cathode plane. The anode plane amplifies the amount of charge deposited in the chamber by a factor of up to 10.sup.6. The gating plane allows only charge within a narrow strip to reach the cathode. The cathode plane collects the charge allowed to pass through the gating plane on a set of conductors perpendicular to the open-gated region. By scanning the open-gated region across the chamber and reading out the charge collected on the cathode conductors after a suitable integration time for each location of the gate, a two-dimensional image of the intensity of the ionizing radiation incident on the detector can be made.

  4. Gated strip proportional detector

    DOE Patents [OSTI]

    Morris, C.L.; Idzorek, G.C.; Atencio, L.G.

    1985-02-19T23:59:59.000Z

    A gated strip proportional detector includes a gas tight chamber which encloses a solid ground plane, a wire anode plane, a wire gating plane, and a multiconductor cathode plane. The anode plane amplifies the amount of charge deposited in the chamber by a factor of up to 10/sup 6/. The gating plane allows only charge within a narrow strip to reach the cathode. The cathode plane collects the charge allowed to pass through the gating plane on a set of conductors perpendicular to the open-gated region. By scanning the open-gated region across the chamber and reading out the charge collected on the cathode conductors after a suitable integration time for each location of the gate, a two-dimensional image of the intensity of the ionizing radiation incident on the detector can be made.

  5. Adiabatic Quantum Transistors

    DOE Public Access Gateway for Energy & Science Beta (PAGES Beta)

    Bacon, Dave; Flammia, Steven T.; Crosswhite, Gregory M.

    2013-06-01T23:59:59.000Z

    We describe a many-body quantum system that can be made to quantum compute by the adiabatic application of a large applied field to the system. Prior to the application of the field, quantum information is localized on one boundary of the device, and after the application of the field, this information propagates to the other side of the device, with a quantum circuit applied to the information. The applied circuit depends on the many-body Hamiltonian of the material, and the computation takes place in a degenerate ground space with symmetry-protected topological order. Such “adiabatic quantum transistors” are universal adiabatic quantum computing devices that have the added benefit of being modular. Here, we describe this model, provide arguments for why it is an efficient model of quantum computing, and examine these many-body systems in the presence of a noisy environment.

  6. Range gated imaging experiments using gated intensifiers

    SciTech Connect (OSTI)

    McDonald, T.E. Jr.; Yates, G.J.; Cverna, F.H.; Gallegos, R.A.; Jaramillo, S.A.; Numkena, D.M.; Payton, J.; Pena-Abeyta, C.R.

    1999-03-01T23:59:59.000Z

    A variety of range gated imaging experiments using high-speed gated/shuttered proximity focused microchannel plate image intensifiers (MCPII) are reported. Range gated imaging experiments were conducted in water for detection of submerged mines in controlled turbidity tank test and in sea water for the Naval Coastal Sea Command/US Marine Corps. Field experiments have been conducted consisting of kilometer range imaging of resolution targets and military vehicles in atmosphere at Eglin Air Force Base for the US Air Force, and similar imaging experiments, but in smoke environment, at Redstone Arsenal for the US Army Aviation and Missile Command (AMCOM). Wavelength of the illuminating laser was 532 nm with pulse width ranging from 6 to 12 ns and comparable gate widths. These tests have shown depth resolution in the tens of centimeters range from time phasing reflected LADAR images with MCPII shutter opening.

  7. Ultrafast gating of proximity-focused microchannel-plate intensifiers

    SciTech Connect (OSTI)

    Lundy, A.S.; Iverson, A.E.

    1982-01-01T23:59:59.000Z

    Proximity-focused, microchannel-plate (MCP) image intensifiers have been used at Los Alamos for many years to allow single frame film and video exposure times in the range of 2.5 to 10 ns. There is now a program to reduce gating times to < 1 ns. This paper reviews previous work and the problems in achieving good resolution with gating times of < 1 ns. The key problems involve applying fast electrical gating signals to the tube elements. We present computer modeling studies of the combined tube, tube connection, and pulser system and show that low photocathode surface resistivity must be obtained to permit fast gating between the photocathode and the MCP input. We discuss ways of making low-resistivity S20 photocathodes, using gallium arsenide photocathodes, and various means of gating the tubes. A variety of pulser designs are being experimentally evaluated including spark gaps, avalanche transistors, Krytron tubes with sharpening gaps, step recovery diodes, and photoconductive elements (PCEs). The results of these studies are presented. Because of the high capacitances involved in most gating schemes, the tube connection geometry must be of low-impedance design, and our solution is presented. Finally, ways of testing these high-speed camera systems are discussed.

  8. Silicon-on-insulator field effect transistor with improved body ties for rad-hard applications

    DOE Patents [OSTI]

    Schwank, James R. (Albuquerque, NM); Shaneyfelt, Marty R. (Albuquerque, NM); Draper, Bruce L. (Albuquerque, NM); Dodd, Paul E. (Tijeras, NM)

    2001-01-01T23:59:59.000Z

    A silicon-on-insulator (SOI) field-effect transistor (FET) and a method for making the same are disclosed. The SOI FET is characterized by a source which extends only partially (e.g. about half-way) through the active layer wherein the transistor is formed. Additionally, a minimal-area body tie contact is provided with a short-circuit electrical connection to the source for reducing floating body effects. The body tie contact improves the electrical characteristics of the transistor and also provides an improved single-event-upset (SEU) radiation hardness of the device for terrestrial and space applications. The SOI FET also provides an improvement in total-dose radiation hardness as compared to conventional SOI transistors fabricated without a specially prepared hardened buried oxide layer. Complementary n-channel and p-channel SOI FETs can be fabricated according to the present invention to form integrated circuits (ICs) for commercial and military applications.

  9. Behavior of the drain leakage current in metal-induced laterally crystallized thin lm transistors

    E-Print Network [OSTI]

    - sistors on the same glass panel for active matrix liquid crystal displays (AMLCDs). Although solid phase 0 3 2 8 - 7 #12;low temperature oxide (LTO) gate insulator and 200 nm thick a-Si gate electrode were and drain regions. About 2 nm of Ni was deposited in an ultra-high vacuum evaporation system. For those TFTs

  10. Optical Determination of Gate--Tunable Bandgap in Bilayer Graphene

    SciTech Connect (OSTI)

    Zhang, Yuanbo; Tang, Tsung-Ta; Girit, Caglar; Hao, Zhao; Martin, Michael C.; Zettl, Alex; Crommie, Michael F.; Shen, Y. Ron; Wang, Feng

    2009-08-11T23:59:59.000Z

    The electronic bandgap is an intrinsic property of semiconductors and insulators that largely determines their transport and optical properties. As such, it has a central role in modern device physics and technology and governs the operation of semiconductor devices such as p-n junctions, transistors, photodiodes and lasers. A tunable bandgap would be highly desirable because it would allow great flexibility in design and optimization of such devices, in particular if it could be tuned by applying a variable external electric field. However, in conventional materials, the bandgap is fixed by their crystalline structure, preventing such bandgap control. Here we demonstrate the realization of a widely tunable electronic bandgap in electrically gated bilayer graphene. Using a dual-gate bilayer graphene field-effect transistor (FET) and infrared microspectroscopy, we demonstrate a gate-controlled, continuously tunable bandgap of up to 250 meV. Our technique avoids uncontrolled chemical doping and provides direct evidence of a widely tunable bandgap -- spanning a spectral range from zero to mid-infrared -- that has eluded previous attempts. Combined with the remarkable electrical transport properties of such systems, this electrostatic bandgap control suggests novel nanoelectronic and nanophotonic device applications based on graphene.

  11. Adiabatically implementing quantum gates

    SciTech Connect (OSTI)

    Sun, Jie; Lu, Songfeng, E-mail: lusongfeng@hotmail.com; Liu, Fang [School of Computer Science and Technology, Huazhong University of Science and Technology, Wuhan 430074 (China)

    2014-06-14T23:59:59.000Z

    We show that, through the approach of quantum adiabatic evolution, all of the usual quantum gates can be implemented efficiently, yielding running time of order O(1). This may be considered as a useful alternative to the standard quantum computing approach, which involves quantum gates transforming quantum states during the computing process.

  12. A Planar Quantum Transistor Based on 2D-2D Tunneling in Double Quantum Well Heterostructures

    SciTech Connect (OSTI)

    Baca, W.E.; Blount, M.A.; Hafich, M.J.; Lyo, S.K.; Moon, J.S.; Reno, J.L.; Simmons, J.A.; Wendt, J.R.

    1998-12-14T23:59:59.000Z

    We report on our work on the double electron layer tunneling transistor (DELTT), based on the gate-control of two-dimensional -- two-dimensional (2D-2D) tunneling in a double quantum well heterostructure. While previous quantum transistors have typically required tiny laterally-defined features, by contrast the DELTT is entirely planar and can be reliably fabricated in large numbers. We use a novel epoxy-bond-and-stop-etch (EBASE) flip-chip process, whereby submicron gating on opposite sides of semiconductor epitaxial layers as thin as 0.24 microns can be achieved. Because both electron layers in the DELTT are 2D, the resonant tunneling features are unusually sharp, and can be easily modulated with one or more surface gates. We demonstrate DELTTs with peak-to-valley ratios in the source-drain I-V curve of order 20:1 below 1 K. Both the height and position of the resonant current peak can be controlled by gate voltage over a wide range. DELTTs with larger subband energy offsets ({approximately} 21 meV) exhibit characteristics that are nearly as good at 77 K, in good agreement with our theoretical calculations. Using these devices, we also demonstrate bistable memories operating at 77 K. Finally, we briefly discuss the prospects for room temperature operation, increases in gain, and high-speed.

  13. Optical XOR gate

    DOE Patents [OSTI]

    Vawter, G. Allen

    2013-11-12T23:59:59.000Z

    An optical XOR gate is formed as a photonic integrated circuit (PIC) from two sets of optical waveguide devices on a substrate, with each set of the optical waveguide devices including an electroabsorption modulator electrically connected in series with a waveguide photodetector. The optical XOR gate utilizes two digital optical inputs to generate an XOR function digital optical output. The optical XOR gate can be formed from III-V compound semiconductor layers which are epitaxially deposited on a III-V compound semiconductor substrate, and operates at a wavelength in the range of 0.8-2.0 .mu.m.

  14. Impact of barrier thickness on transistor performance in AlN/GaN high electron mobility transistors grown on free-standing GaN substrates

    SciTech Connect (OSTI)

    Deen, David A., E-mail: david.deen@alumni.nd.edu; Storm, David F.; Meyer, David J.; Bass, Robert; Binari, Steven C. [Electronics Science and Technology Division, Naval Research Laboratory, Washington, DC 20375-5347 (United States); Gougousi, Theodosia [Physics Department, University of Maryland Baltimore County, Baltimore, Maryland 21250 (United States); Evans, Keith R. [Kyma Technologies, Raleigh, North Carolina 27617 (United States)

    2014-09-01T23:59:59.000Z

    A series of six ultrathin AlN/GaN heterostructures with varied AlN thicknesses from 1.5–6?nm have been grown by molecular beam epitaxy on free-standing hydride vapor phase epitaxy GaN substrates. High electron mobility transistors (HEMTs) were fabricated from the set in order to assess the impact of barrier thickness and homo-epitaxial growth on transistor performance. Room temperature Hall characteristics revealed mobility of 1700?cm{sup 2}/V s and sheet resistance of 130 ?/? for a 3?nm thick barrier, ranking amongst the lowest room-temperature sheet resistance values reported for a polarization-doped single heterostructure in the III-Nitride family. DC and small signal HEMT electrical characteristics from submicron gate length HEMTs further elucidated the effect of the AlN barrier thickness on device performance.

  15. Reliability of AlGaN/GaN high electron mobility transistors on low dislocation density bulk GaN substrate: Implications of surface step edges

    SciTech Connect (OSTI)

    Killat, N., E-mail: Nicole.Killat@bristol.ac.uk, E-mail: Martin.Kuball@bristol.ac.uk; Montes Bajo, M.; Kuball, M., E-mail: Nicole.Killat@bristol.ac.uk, E-mail: Martin.Kuball@bristol.ac.uk [Center for Device Thermography and Reliability (CDTR), H.H. Wills Physics Laboratory, Tyndall Avenue, Bristol BS8 1TL (United Kingdom); Paskova, T. [Kyma Technologies, Inc., Raleigh, North Carolina 27617 (United States) [Kyma Technologies, Inc., Raleigh, North Carolina 27617 (United States); Materials Science and Engineering Department, North Carolina State University, Raleigh, North Carolina 27695 (United States); Evans, K. R. [Kyma Technologies, Inc., Raleigh, North Carolina 27617 (United States)] [Kyma Technologies, Inc., Raleigh, North Carolina 27617 (United States); Leach, J. [Kyma Technologies, Inc., Raleigh, North Carolina 27617 (United States) [Kyma Technologies, Inc., Raleigh, North Carolina 27617 (United States); Electrical and Computer Engineering Department, Virginia Commonwealth University, Richmond, Virginia 23284 (United States); Li, X.; Özgür, Ü.; Morkoç, H. [Electrical and Computer Engineering Department, Virginia Commonwealth University, Richmond, Virginia 23284 (United States)] [Electrical and Computer Engineering Department, Virginia Commonwealth University, Richmond, Virginia 23284 (United States); Chabak, K. D.; Crespo, A.; Gillespie, J. K.; Fitch, R.; Kossler, M.; Walker, D. E.; Trejo, M.; Via, G. D.; Blevins, J. D. [Air Force Research Laboratory, Wright-Patterson Air Force Base, Dayton, Ohio 45433 (United States)] [Air Force Research Laboratory, Wright-Patterson Air Force Base, Dayton, Ohio 45433 (United States)

    2013-11-04T23:59:59.000Z

    To enable gaining insight into degradation mechanisms of AlGaN/GaN high electron mobility transistors, devices grown on a low-dislocation-density bulk-GaN substrate were studied. Gate leakage current and electroluminescence (EL) monitoring revealed a progressive appearance of EL spots during off-state stress which signify the generation of gate current leakage paths. Atomic force microscopy evidenced the formation of semiconductor surface pits at the failure location, which corresponds to the interaction region of the gate contact edge and the edges of surface steps.

  16. Cellular Gate Technology

    E-Print Network [OSTI]

    Knight, Thomas F.

    1998-01-05T23:59:59.000Z

    We propose a biochemically plausible mechanism for constructing digital logic signals and gates of significant complexity within living cells. These mechanisms rely largely on co-opting existing biochemical machinery and ...

  17. Realizing high-voltage thin film lateral bipolar transistors on SOI with a collector-tub

    E-Print Network [OSTI]

    Kumar, M. Jagadesh

    Realizing high-voltage thin film lateral bipolar transistors on SOI with a collector-tub Sukhendu-dimensional device simulation to examine the effect of a collector tub on the collector breakdown of the SOI based BJTs. This method involves creating a collector tub by etching the buried oxide followed by an n

  18. Semianalytical quantum model for graphene field-effect transistors

    SciTech Connect (OSTI)

    Pugnaghi, Claudio; Grassi, Roberto, E-mail: roberto.grassi@unibo.it; Gnudi, Antonio; Di Lecce, Valerio; Gnani, Elena; Reggiani, Susanna; Baccarani, Giorgio [ARCES and DEI, University of Bologna, Viale Risorgimento 2, 40136 Bologna (Italy)

    2014-09-21T23:59:59.000Z

    We develop a semianalytical model for monolayer graphene field-effect transistors in the ballistic limit. Two types of devices are considered: in the first device, the source and drain regions are doped by charge transfer with Schottky contacts, while, in the second device, the source and drain regions are doped electrostatically by a back gate. The model captures two important effects that influence the operation of both devices: (i) the finite density of states in the source and drain regions, which limits the number of states available for transport and can be responsible for negative output differential resistance effects, and (ii) quantum tunneling across the potential steps at the source-channel and drain-channel interfaces. By comparison with a self-consistent non-equilibrium Green's function solver, we show that our model provides very accurate results for both types of devices, in the bias region of quasi-saturation as well as in that of negative differential resistance.

  19. Axial SiGe Heteronanowire Tunneling Field-Effect Transistors

    SciTech Connect (OSTI)

    Le, Son T.; Jannaty, P.; Luo, Xu; Zaslavsky, A.; Perea, Daniel E.; Dayeh, Shadi A.; Picraux, Samuel T.

    2012-10-31T23:59:59.000Z

    We present silicon-compatible tri-gated p-Ge/i-Si/n-Si axial heteronanowire tunneling field-effect transistors (TFETs), where on-state tunneling occurs in the Ge drain section, while off-state leakage is dominated by the Si junction in the source. Our TFETs have high ION ~ 2 µA/µm, fully suppressed ambipolarity, and a sub-threshold slope SS ~ 140 mV/decade over 4 decades of current with lowest SS ~ 50 mV/decade. Device operation in the tunneling mode is confirmed by three-dimensional TCAD simulation. Interestingly, in addition to the TFET mode, our devices work as standard nanowire FETs with good ION/IOFF ratio when the source-drain junction is forward-biased. The improved transport in both biasing modes confirms the benefits of utilizing bandgap engineered axial nanowires for enhancing device performance.

  20. Performance limits of tunnel transistors based on mono-layer transition-metal dichalcogenides

    SciTech Connect (OSTI)

    Jiang, Xiang-Wei, E-mail: xwjiang@semi.ac.cn; Li, Shu-Shen [State Key Laboratory of Superlattices and Microstructures, Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083 (China); Synergetic Innovation Center of Quantum Information and Quantum Physics, University of Science and Technology of China, Hefei, Anhui 230026 (China)

    2014-05-12T23:59:59.000Z

    Performance limits of tunnel field-effect transistors based on mono-layer transition metal dichalcogenides are investigated through numerical quantum mechanical simulations. The atomic mono-layer nature of the devices results in a much smaller natural length ?, leading to much larger electric field inside the tunneling diodes. As a result, the inter-band tunneling currents are found to be very high as long as ultra-thin high-k gate dielectric is possible. The highest on-state driving current is found to be close to 600??A/?m at V{sub g}?=?V{sub d}?=?0.5?V when 2?nm thin HfO{sub 2} layer is used for gate dielectric, outperforming most of the conventional semiconductor tunnel transistors. In the five simulated transition-metal dichalcogenides, mono-layer WSe{sub 2} based tunnel field-effect transistor shows the best potential. Deep analysis reveals that there is plenty room to further enhance the device performance by either geometry, alloy, or strain engineering on these mono-layer materials.

  1. Formation of low resistivity titanium silicide gates in semiconductor integrated circuits

    DOE Patents [OSTI]

    Ishida, Emi (Sunnyvale, CA)

    1999-08-10T23:59:59.000Z

    A method of forming a titanium silicide (69) includes the steps of forming a transistor having a source region (58), a drain region (60) and a gate structure (56) and forming a titanium layer (66) over the transistor. A first anneal is performed with a laser anneal at an energy level that causes the titanium layer (66) to react with the gate structure (56) to form a high resistivity titanium silicide phase (68) having substantially small grain sizes. The unreacted portions of the titanium layer (66) are removed and a second anneal is performed, thereby causing the high resistivity titanium silicide phase (68) to convert to a low resistivity titanium silicide phase (69). The small grain sizes obtained by the first anneal allow low resistivity titanium silicide phase (69) to be achieved at device geometries less than about 0.25 micron.

  2. Tetracene air-gap single-crystal field-effect transistors Yu Xia, Vivek Kalihari, and C. Daniel Frisbiea

    E-Print Network [OSTI]

    Rogers, John A.

    Tetracene air-gap single-crystal field-effect transistors Yu Xia, Vivek Kalihari, and C. Daniel FETs utilizing an air or vacuum gap as the gate dielectric. The linear mobility of the device can be as high as 1.6 cm2 /V s in air, with a subthreshold slope lower than 0.5 V nF/decade cm2 . By changing

  3. Sandia National Laboratories: organic field effect transistor

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    organic field effect transistor ECIS and Compass Metals: Platinum Nanostructures for Enhanced Catalysis On March 29, 2013, in Advanced Materials Laboratory, Capabilities, Energy,...

  4. Complementary junction heterostructure field-effect transistor

    DOE Patents [OSTI]

    Baca, Albert G. (Albuquerque, NM); Drummond, Timothy J. (Albuquerque, NM); Robertson, Perry J. (Albuquerque, NM); Zipperian, Thomas E. (Albuquerque, NM)

    1995-01-01T23:59:59.000Z

    A complimentary pair of compound semiconductor junction heterostructure field-effect transistors and a method for their manufacture are disclosed. The p-channel junction heterostructure field-effect transistor uses a strained layer to split the degeneracy of the valence band for a greatly improved hole mobility and speed. The n-channel device is formed by a compatible process after removing the strained layer. In this manner, both types of transistors may be independently optimized. Ion implantation is used to form the transistor active and isolation regions for both types of complimentary devices. The invention has uses for the development of low power, high-speed digital integrated circuits.

  5. Complementary junction heterostructure field-effect transistor

    DOE Patents [OSTI]

    Baca, A.G.; Drummond, T.J.; Robertson, P.J.; Zipperian, T.E.

    1995-12-26T23:59:59.000Z

    A complimentary pair of compound semiconductor junction heterostructure field-effect transistors and a method for their manufacture are disclosed. The p-channel junction heterostructure field-effect transistor uses a strained layer to split the degeneracy of the valence band for a greatly improved hole mobility and speed. The n-channel device is formed by a compatible process after removing the strained layer. In this manner, both types of transistors may be independently optimized. Ion implantation is used to form the transistor active and isolation regions for both types of complimentary devices. The invention has uses for the development of low power, high-speed digital integrated circuits. 10 figs.

  6. Cardiac gated ventilation

    SciTech Connect (OSTI)

    Hanson, C.W. III [Hospital of the Univ. of Pennsylvania, Philadelphia, PA (United States). Dept. Anesthesia; Hoffman, E.A. [Univ. of Iowa College of Medicine, Iowa City, IA (United States). Div. of Physiologic Imaging

    1995-12-31T23:59:59.000Z

    There are several theoretic advantages to synchronizing positive pressure breaths with the cardiac cycle, including the potential for improving distribution of pulmonary and myocardial blood flow and enhancing cardiac output. The authors evaluated the effects of synchronizing respiration to the cardiac cycle using a programmable ventilator and electron beam CT (EBCT) scanning. The hearts of anesthetized dogs were imaged during cardiac gated respiration with a 50 msec scan aperture. Multi slice, short axis, dynamic image data sets spanning the apex to base of the left ventricle were evaluated to determine the volume of the left ventricular chamber at end-diastole and end-systole during apnea, systolic and diastolic cardiac gating. The authors observed an increase in cardiac output of up to 30% with inspiration gated to the systolic phase of the cardiac cycle in a non-failing model of the heart.

  7. Gate-Recessed InAlN/GaN HEMTs on SiC Substrate With Al[subscript 2]O[subscript 3] Passivation

    E-Print Network [OSTI]

    Guo, Shiping

    We studied submicrometer (L[subscript G] = 0.15-0.25 à ¿m) gate-recessed InAlN/AlN/GaN high-electron mobility transistors (HEMTs) on SiC substrates with 25-nm Al[subscript 2]O[subscript 3] passivation. The combination of ...

  8. Heterostructure unipolar spin transistors M. E. Flatta

    E-Print Network [OSTI]

    Flatte, Michael E.

    carriers on one side of the device are spin-down spin-up electrons and on the other side of the device semiconductor electronics and spin-based unipolar electronics by considering unipolar spin transistors electrons to the collector limits the performance of "homojunction" unipolar spin transistors, in which

  9. Universal power transistor base drive control unit

    DOE Patents [OSTI]

    Gale, A.R.; Gritter, D.J.

    1988-06-07T23:59:59.000Z

    A saturation condition regulator system for a power transistor is disclosed which achieves the regulation objectives of a Baker clamp but without dumping excess base drive current into the transistor output circuit. The base drive current of the transistor is sensed and used through an active feedback circuit to produce an error signal which modulates the base drive current through a linearly operating FET. The collector base voltage of the power transistor is independently monitored to develop a second error signal which is also used to regulate base drive current. The current-sensitive circuit operates as a limiter. In addition, a fail-safe timing circuit is disclosed which automatically resets to a turn OFF condition in the event the transistor does not turn ON within a predetermined time after the input signal transition. 2 figs.

  10. Universal power transistor base drive control unit

    SciTech Connect (OSTI)

    Gale, Allan R. (Allen Park, MI); Gritter, David J. (Racine, WI)

    1988-01-01T23:59:59.000Z

    A saturation condition regulator system for a power transistor which achieves the regulation objectives of a Baker clamp but without dumping excess base drive current into the transistor output circuit. The base drive current of the transistor is sensed and used through an active feedback circuit to produce an error signal which modulates the base drive current through a linearly operating FET. The collector base voltage of the power transistor is independently monitored to develop a second error signal which is also used to regulate base drive current. The current-sensitive circuit operates as a limiter. In addition, a fail-safe timing circuit is disclosed which automatically resets to a turn OFF condition in the event the transistor does not turn ON within a predetermined time after the input signal transition.

  11. Impact ionization in N-polar AlGaN/GaN high electron mobility transistors

    SciTech Connect (OSTI)

    Killat, N., E-mail: Nicole.Killat@bristol.ac.uk, E-mail: Martin.Kuball@bristol.ac.uk; Uren, M. J.; Kuball, M., E-mail: Nicole.Killat@bristol.ac.uk, E-mail: Martin.Kuball@bristol.ac.uk [Center for Device Thermography and Reliability (CDTR), H. H. Wills Physics Laboratory, University of Bristol, Tyndall Avenue, Bristol BS8 1TL (United Kingdom); Keller, S.; Kolluri, S.; Mishra, U. K. [Department of Electrical and Computer Engineering, University of Santa Barbara California, Santa Barbara, California 93106 (United States)

    2014-08-11T23:59:59.000Z

    The existence of impact ionization as one of the open questions for GaN device reliability was studied in N-polar AlGaN/GaN high electron mobility transistors. Electroluminescence (EL) imaging and spectroscopy from underneath the device gate contact revealed the presence of hot electrons in excess of the GaN bandgap energy even at moderate on-state bias conditions, enabling impact ionization with hole currents up to several hundreds of pA/mm. The detection of high energy luminescence from hot electrons demonstrates that EL analysis is a highly sensitive tool to study degradation mechanisms in GaN devices.

  12. Giant amplification of tunnel magnetoresistance in a molecular junction: Molecular spin-valve transistor

    SciTech Connect (OSTI)

    Dhungana, Kamal B.; Pati, Ranjit, E-mail: patir@mtu.edu [Department of Physics, Michigan Technological University, Houghton, Michigan 49931 (United States)

    2014-04-21T23:59:59.000Z

    Amplification of tunnel magnetoresistance by gate field in a molecular junction is the most important requirement for the development of a molecular spin valve transistor. Herein, we predict a giant amplification of tunnel magnetoresistance in a single molecular spin valve junction, which consists of Ru-bis-terpyridine molecule as a spacer between two ferromagnetic nickel contacts. Based on the first-principles quantum transport approach, we show that a modest change in the gate field that is experimentally accessible can lead to a substantial amplification (320%) of tunnel magnetoresistance. The origin of such large amplification is attributed to the spin dependent modification of orbitals at the molecule-lead interface and the resultant Stark effect induced shift in channel position with respect to the Fermi energy.

  13. Conductance modulation in topological insulator Bi{sub 2}Se{sub 3} thin films with ionic liquid gating

    SciTech Connect (OSTI)

    Son, Jaesung; Banerjee, Karan; Yang, Hyunsoo, E-mail: eleyang@nus.edu.sg [Department of Electrical and Computer Engineering, National University of Singapore, 4 Engineering Drive 3, Singapore 117576 (Singapore)] [Department of Electrical and Computer Engineering, National University of Singapore, 4 Engineering Drive 3, Singapore 117576 (Singapore); Brahlek, Matthew; Koirala, Nikesh; Oh, Seongshik [Department of Physics and Astronomy, Rutgers, The State University of New Jersey, 136 Frelinghuysen Road, Piscataway, New Jersey 08854 (United States)] [Department of Physics and Astronomy, Rutgers, The State University of New Jersey, 136 Frelinghuysen Road, Piscataway, New Jersey 08854 (United States); Lee, Seoung-Ki [School of Advanced Materials Science and Engineering, Sungkyunkwan University, Suwon 440-746 (Korea, Republic of) [School of Advanced Materials Science and Engineering, Sungkyunkwan University, Suwon 440-746 (Korea, Republic of); School of Electrical and Electronic Engineering, Yonsei University, Seoul 120-749 (Korea, Republic of); Ahn, Jong-Hyun [School of Electrical and Electronic Engineering, Yonsei University, Seoul 120-749 (Korea, Republic of)] [School of Electrical and Electronic Engineering, Yonsei University, Seoul 120-749 (Korea, Republic of)

    2013-11-18T23:59:59.000Z

    A Bi{sub 2}Se{sub 3} topological insulator field effect transistor is investigated by using ionic liquid as an electric double layer gating material, leading to a conductance modulation of 365% at room temperature. We discuss the role of charged impurities on the transport properties. The conductance modulation with gate bias is due to a change in the carrier concentration, whereas the temperature dependent conductance change is originated from a change in mobility. Large conductance modulation at room temperature along with the transparent optical properties makes topological insulators as an interesting (opto)electronic material.

  14. Spin effects in single-electron transistors

    E-Print Network [OSTI]

    Granger, Ghislain

    2005-01-01T23:59:59.000Z

    Basic electron transport phenomena observed in single-electron transistors (SETs) are introduced, such as Coulomb-blockade diamonds, inelastic cotunneling thresholds, the spin-1/2 Kondo effect, and Fano interference. With ...

  15. Development of gallium nitride power transistors

    E-Print Network [OSTI]

    Piedra, Daniel, M. Eng. Massachusetts Institute of Technology

    2011-01-01T23:59:59.000Z

    GaN-based high-voltage transistors have outstanding properties for the development of ultra-high efficiency and compact power electronics. This thesis describes a new process technology for the fabrication of GaN power ...

  16. Method of fabrication of display pixels driven by silicon thin film transistors

    DOE Patents [OSTI]

    Carey, Paul G. (Mountain View, CA); Smith, Patrick M. (San Ramon, CA)

    1999-01-01T23:59:59.000Z

    Display pixels driven by silicon thin film transistors are fabricated on plastic substrates for use in active matrix displays, such as flat panel displays. The process for forming the pixels involves a prior method for forming individual silicon thin film transistors on low-temperature plastic substrates. Low-temperature substrates are generally considered as being incapable of withstanding sustained processing temperatures greater than about 200.degree. C. The pixel formation process results in a complete pixel and active matrix pixel array. A pixel (or picture element) in an active matrix display consists of a silicon thin film transistor (TFT) and a large electrode, which may control a liquid crystal light valve, an emissive material (such as a light emitting diode or LED), or some other light emitting or attenuating material. The pixels can be connected in arrays wherein rows of pixels contain common gate electrodes and columns of pixels contain common drain electrodes. The source electrode of each pixel TFT is connected to its pixel electrode, and is electrically isolated from every other circuit element in the pixel array.

  17. SnTe field effect transistors and the anomalous electrical response of structural phase transition

    SciTech Connect (OSTI)

    Li, Haitao, E-mail: haitao.li@nist.gov; Zhu, Hao; Yuan, Hui; Li, Qiliang, E-mail: qli6@gmu.edu [Department of Electrical and Computer Engineering, George Mason University, Fairfax, Virginia 22030 (United States); Semiconductor and Dimensional Metrology Division, National Institute of Standards and Technology, Gaithersburg, Maryland 20899 (United States); You, Lin; Kopanski, Joseph J. [Department of Electrical and Computer Engineering, George Mason University, Fairfax, Virginia 22030 (United States); Richter, Curt A. [Semiconductor and Dimensional Metrology Division, National Institute of Standards and Technology, Gaithersburg, Maryland 20899 (United States); Zhao, Erhai [School of Physics, Astronomy, and Computational Sciences, George Mason University, Fairfax, Virginia 22030 (United States)

    2014-07-07T23:59:59.000Z

    SnTe is a conventional thermoelectric material and has been newly found to be a topological crystalline insulator. In this work, back-gate SnTe field-effect transistors have been fabricated and fully characterized. The devices exhibit n-type transistor behaviors with excellent current-voltage characteristics and large on/off ratio (>10{sup 6}). The device threshold voltage, conductance, mobility, and subthreshold swing have been studied and compared at different temperatures. It is found that the subthreshold swings as a function of temperature have an apparent response to the SnTe phase transition between cubic and rhombohedral structures at 110?K. The abnormal and rapid increase in subthreshold swing around the phase transition temperature may be due to the soft phonon/structure change which causes the large increase in SnTe dielectric constant. Such an interesting and remarkable electrical response to phase transition at different temperatures makes the small SnTe transistor attractive for various electronic devices.

  18. Penn State DOE GATE Program

    SciTech Connect (OSTI)

    Anstrom, Joel

    2012-08-31T23:59:59.000Z

    The Graduate Automotive Technology Education (GATE) Program at The Pennsylvania State University (Penn State) was established in October 1998 pursuant to an award from the U.S. Department of Energy (U.S. DOE). The focus area of the Penn State GATE Program is advanced energy storage systems for electric and hybrid vehicles.

  19. A Sequence of Quantum Gates

    E-Print Network [OSTI]

    Yorick Hardy; Willi-Hans Steeb

    2012-02-10T23:59:59.000Z

    We study a sequence of quantum gates in finite-dimensional Hilbert spaces given by the normalized eigenvectors of the unitary operators. The corresponding sequence of the Hamilton operators is also given. From the Hamilton operators we construct another hierarchy of quantum gates via the Cayley transform.

  20. Low temperature thin film transistors with hollow cathode plasma-assisted atomic layer deposition based GaN channels

    SciTech Connect (OSTI)

    Bolat, S., E-mail: bolat@ee.bilkent.edu.tr, E-mail: aokyay@ee.bilkent.edu.tr; Tekcan, B. [Department of Electrical and Electronics Engineering, Bilkent University, Ankara 06800 (Turkey); UNAM, National Nanotechnology Research Center, Bilkent University, Ankara 06800 (Turkey); Ozgit-Akgun, C.; Biyikli, N. [UNAM, National Nanotechnology Research Center, Bilkent University, Ankara 06800 (Turkey); Institute of Materials Science and Nanotechnology, Bilkent University, Ankara 06800 (Turkey); Okyay, A. K., E-mail: bolat@ee.bilkent.edu.tr, E-mail: aokyay@ee.bilkent.edu.tr [Department of Electrical and Electronics Engineering, Bilkent University, Ankara 06800 (Turkey); UNAM, National Nanotechnology Research Center, Bilkent University, Ankara 06800 (Turkey); Institute of Materials Science and Nanotechnology, Bilkent University, Ankara 06800 (Turkey)

    2014-06-16T23:59:59.000Z

    We report GaN thin film transistors (TFT) with a thermal budget below 250?°C. GaN thin films are grown at 200?°C by hollow cathode plasma-assisted atomic layer deposition (HCPA-ALD). HCPA-ALD-based GaN thin films are found to have a polycrystalline wurtzite structure with an average crystallite size of 9.3?nm. TFTs with bottom gate configuration are fabricated with HCPA-ALD grown GaN channel layers. Fabricated TFTs exhibit n-type field effect characteristics. N-channel GaN TFTs demonstrated on-to-off ratios (I{sub ON}/I{sub OFF}) of 10{sup 3} and sub-threshold swing of 3.3?V/decade. The entire TFT device fabrication process temperature is below 250?°C, which is the lowest process temperature reported for GaN based transistors, so far.

  1. All-Metallic Vertical Transistors Based on Stacked Dirac Materials

    E-Print Network [OSTI]

    Wang, Yangyang

    It is an ongoing pursuit to use metal as a channel material in a field effect transistor. All metallic transistor can be fabricated from pristine semimetallic Dirac materials (such as graphene, silicene, and germanene), ...

  2. High Performance Lateral Schottky Collector Bipolar Transistors on SOI

    E-Print Network [OSTI]

    Kumar, M. Jagadesh

    C-emitter lateral NPM Schottky collector transistor. To study the novel characteristics of these lateral Schottky junction of the proposed lateral PNM (NPM) transistor consists of a Schottky junction between N-base (P

  3. Graphene nanopore field effect transistors

    SciTech Connect (OSTI)

    Qiu, Wanzhi; Skafidas, Efstratios, E-mail: sskaf@unimelb.edu.au [Centre for Neural Engineering, The University of Melbourne, 203 Bouverie Street, Carlton, Victoria 3053 (Australia); Department of Electrical and Electronic Engineering, The University of Melbourne, Parkville, Victoria 3010 (Australia)

    2014-07-14T23:59:59.000Z

    Graphene holds great promise for replacing conventional Si material in field effect transistors (FETs) due to its high carrier mobility. Previously proposed graphene FETs either suffer from low ON-state current resulting from constrained channel width or require complex fabrication processes for edge-defecting or doping. Here, we propose an alternative graphene FET structure created on intrinsic metallic armchair-edged graphene nanoribbons with uniform width, where the channel region is made semiconducting by drilling a pore in the interior, and the two ends of the nanoribbon act naturally as connecting electrodes. The proposed GNP-FETs have high ON-state currents due to seamless atomic interface between the channel and electrodes and are able to be created with arbitrarily wide ribbons. In addition, the performance of GNP-FETs can be tuned by varying pore size and ribbon width. As a result, their performance and fabrication process are more predictable and controllable in comparison to schemes based on edge-defects and doping. Using first-principle transport calculations, we show that GNP-FETs can achieve competitive leakage current of ?70?pA, subthreshold swing of ?60?mV/decade, and significantly improved On/Off current ratios on the order of 10{sup 5} as compared with other forms of graphene FETs.

  4. Avalanche spin-valve transistor K. J. Russell,a)

    E-Print Network [OSTI]

    Russell, Kasey

    Avalanche spin-valve transistor K. J. Russell,a) Ian Appelbaum,b) Wei Yi, D. J. Monsma, F. Capasso, California 93106 (Received 11 June 2004; accepted 10 September 2004) A spin-valve transistor with a Ga allow fabrication of spin-valve transistors with high gain in a variety of materials. © 2004 American

  5. Ultrafast, high precision gated integrator

    SciTech Connect (OSTI)

    Wang, X.

    1995-01-01T23:59:59.000Z

    An ultrafast, high precision gated integrator has been developed by introducing new design approaches that overcome the problems associated with earlier gated integrator circuits. The very high speed is evidenced by the output settling time of less than 50 ns and 20 MHz input pulse rate. The very high precision is demonstrated by the total output offset error of less than 0.2mV and the output droop rate of less than 10{mu}V/{mu}s. This paper describes the theory of this new gated integrator circuit operation. The completed circuit test results are presented.

  6. Strong Room-temperature Negative Transconductance In An Axial Si/Ge Hetero-nanowire Tunneling Field-effect Transistor

    SciTech Connect (OSTI)

    Zhang, Peng; Le, Son T.; Hou, Xiaoxiao; Zaslavsky, A.; Perea, Daniel E.; Dayeh, Shadi A.; Picraux, Samuel T.

    2014-08-11T23:59:59.000Z

    We report on room-temperature negative transconductance (NTC) in axial Si/Ge hetero-nanowire tunneling field-effect transistors (TFETs). The NTC produces a current peak-to-valley ratio > 45, a high value for a Si-based device. We characterize the NTC characteristics over a range of gate VG and drain VD voltages, finding that NTC persists down to VD = –50 mV. The physical mechanism responsible for the NTC is the VG-induced depletion in the p-Ge section that eventually reduces the maximum electric field that triggers the tunneling ID, as confirmed via three-dimensional TCAD simulations.

  7. Ultra-low noise high electron mobility transistors for high-impedance and low-frequency deep cryogenic readout electronics

    SciTech Connect (OSTI)

    Dong, Q.; Liang, Y. X.; Ferry, D.; Cavanna, A.; Gennser, U.; Couraud, L.; Jin, Y., E-mail: yong.jin@LPN.cnrs.fr [CNRS, Laboratoire de Photonique et de Nanostructures (LPN), Route de Nozay, 91460 Marcoussis (France)

    2014-07-07T23:59:59.000Z

    We report on the results obtained from specially designed high electron mobility transistors at 4.2?K: the gate leakage current can be limited lower than 1 aA, and the equivalent input noise-voltage and noise-current at 1?Hz can reach 6.3 nV/Hz{sup 1?2} and 20 aA/Hz{sup 1?2}, respectively. These results open the way to realize high performance low-frequency readout electronics under very low-temperature conditions.

  8. Characterization of AlGaN/GaN Heterostructure Field Effect Transistors (HFETs) with Variable Thickness Channel and Substrate Type

    SciTech Connect (OSTI)

    Hussein, A. SH.; Hassan, Z.; Hassan, H. Abu; Thahab, S. M. [Nano-Optoelectronics Research and Technology Laboratory, School of Physics, Universiti Sains Malaysia, 11800 Penang (Malaysia)

    2010-07-07T23:59:59.000Z

    In this study, AlGaN/GaN-based heterostructure field effect transistor (HFET) was simulated by using ISE TCAD software. The effects of varying thickness, substrate type and doping channel levels were investigated. The device output characteristics of drain current and voltage with various gate biases were presented. A maximum drain current and extrinsic transconductance were achieved with AlGaN HFET grown on AlN/SiC substrate. The device performance can be improved by optimizing the substrate type and heavily doped channel layer which will reduce the contact resistance and enhance the transconductance. All results are comparable with the experimental results obtained by other researchers.

  9. Air-gap gating of MgZnO/ZnO heterostructures

    SciTech Connect (OSTI)

    Tambo, T.; Falson, J., E-mail: falson@kwsk.t.u-tokyo.ac.jp; Kozuka, Y. [Department of Applied Physics and Quantum-Phase Electronics Center (QPEC), University of Tokyo, Tokyo 113-8656 (Japan); Maryenko, D. [RIKEN Center for Emergent Matter Science (CEMS), Wako 351-0198 (Japan); Tsukazaki, A. [Institute for Materials Research (IMR), Tohoku University, Sendai 980-8577 (Japan); PRESTO, Japan Science and Technology Agency (JST), Tokyo 102-0075 (Japan); Kawasaki, M. [Department of Applied Physics and Quantum-Phase Electronics Center (QPEC), University of Tokyo, Tokyo 113-8656 (Japan); RIKEN Center for Emergent Matter Science (CEMS), Wako 351-0198 (Japan)

    2014-08-28T23:59:59.000Z

    The adaptation of “air-gap” dielectric based field-effect transistor technology to controlling the MgZnO/ZnO heterointerface confined two-dimensional electron system (2DES) is reported. We find it possible to tune the charge density of the 2DES via a gate electrode spatially separated from the heterostructure surface by a distance of 5??m. Under static gating, the observation of the quantum Hall effect suggests that the charge carrier density remains homogeneous, with the 2DES in the 3?mm square sample the sole conductor. The availability of this technology enables the exploration of the charge carrier density degree of freedom in the pristine sample limit.

  10. Comparative investigation of InGaP/GaAs pseudomorphic field-effect transistors with triple doped-channel profiles

    SciTech Connect (OSTI)

    Tsai, Jung-Hui, E-mail: jhtsai@nknucc.nknu.edu.tw [National Kaohsiung Normal University, Department of Electronic Engineering, Taiwan (China); Guo, Der-Feng [Air Force Academy, Department of Electronic Engineering, Taiwan (China); Lour, Wen-Shiung [National Taiwan Ocean University, Department of Electrical Engineering, Taiwan (China)

    2011-09-15T23:59:59.000Z

    In this article, the comparison of DC performance on InGaP/GaAs pseudomorphic field-effect transistors with tripe doped-channel profiles is demonstrated. As compared to the uniform and high-medium-low doped-channel devices, the low-medium-high doped-channel device exhibits the broadest gate voltage swing and the best device linearity because more twodimensional electron gases are formed in the heaviest doped channel to enhance the magnitude of negative threshold voltage. Experimentally, the transconductance within 50% of its maximum value for gate voltage swing is 4.62 V in the low-medium-high doped-channel device, which is greater than 3.58 (3.30) V in the uniform (high-medium-low) doped-channel device.

  11. Investigation of trap states under Schottky contact in GaN/AlGaN/AlN/GaN high electron mobility transistors

    SciTech Connect (OSTI)

    Ma, Xiao-Hua, E-mail: xhma@xidian.edu.cn, E-mail: yhao@xidian.edu.cn; Chen, Wei-Wei; Hou, Bin; Zhu, Jie-Jie [School of Advanced Materials and Nanotechnology, Xidian University, Xi'an 710071 (China); Key Lab of Wide Band-Gap Semiconductor Materials and Devices, School of Microelectronics, Xidian University, Xi'an 710071 (China); Zhang, Kai; Zhang, Jin-Cheng; Zheng, Xue-Feng; Hao, Yue, E-mail: xhma@xidian.edu.cn, E-mail: yhao@xidian.edu.cn [Key Lab of Wide Band-Gap Semiconductor Materials and Devices, School of Microelectronics, Xidian University, Xi'an 710071 (China)

    2014-03-03T23:59:59.000Z

    Forward gate-bias stress experiments are performed to investigate the variation of trap states under Schottky contact in GaN-based high electron mobility transistors. Traps with activation energy E{sub T} ranging from 0.22?eV to 0.31?eV are detected at the gate-semiconductor interface by dynamic conductance technique. Trap density decreases prominently after stressing, particularly for traps with E{sub T}?>?0.24?eV. X-ray photoelectron spectroscopy measurements reveal a weaker Ga-O peak on the stressed semiconductor surface. It is postulated that oxygen is stripped by Ni to form NiO upon electrical stress, contributing to the decrease in O{sub N} donor sates under the gate contact.

  12. Non-Hermitian quantum gates are more common than Hermitian quantum gates

    E-Print Network [OSTI]

    Anirban Pathak

    2013-09-16T23:59:59.000Z

    Most of the frequently used quantum gates (e.g., NOT, Hadamard, CNOT, SWAP, Toffoli, Fredkin and Pauli gates) are self-inverse (Hermitian). However, with a simple minded argument it is established that most of the allowed quantum gates are non-Hermitian (non-self-inverse). It is also shown that the % of non-Hermitian gates increases with the dimension. For example, 58.33% of the 2-qubit gates, 98.10% of the 3-qubit gates and 99.99% of the 4-qubit gates are non-Hermitian. As classical reversible gates are essentially permutation gates so the above statistics is strictly valid for classical reversible gates. Further, since Hermiticity is not of much interest in context of the classical reversible gate, hence the result implies that most of the allowed classical reversible gates are non-self-inverse.

  13. Gallium nitride junction field-effect transistor

    DOE Patents [OSTI]

    Zolper, John C. (Albuquerque, NM); Shul, Randy J. (Albuquerque, NM)

    1999-01-01T23:59:59.000Z

    An all-ion implanted gallium-nitride (GaN) junction field-effect transistor (JFET) and method of making the same. Also disclosed are various ion implants, both n- and p-type, together with or without phosphorous co-implantation, in selected III-V semiconductor materials.

  14. A thin film transistor driven microchannel device 

    E-Print Network [OSTI]

    Lee, Hyun Ho

    2005-02-17T23:59:59.000Z

    perturbation, an amorphous silicon (a-Si:H) thin film transistor (TFT) was connected to the microchannel device. The self-aligned a-Si:H TFT was fabricated with a two-photomask process. The result shows that the attachment of the TFT successfully suppressed...

  15. Gallium nitride junction field-effect transistor

    DOE Patents [OSTI]

    Zolper, J.C.; Shul, R.J.

    1999-02-02T23:59:59.000Z

    An ion implanted gallium-nitride (GaN) junction field-effect transistor (JFET) and method of making the same are disclosed. Also disclosed are various ion implants, both n- and p-type, together with or without phosphorus co-implantation, in selected III-V semiconductor materials. 19 figs.

  16. Deformable Transparent All-Carbon-Nanotube Transistors

    E-Print Network [OSTI]

    Maruyama, Shigeo

    and organic materials16,17 are candidates for next-generation flexible and transparent electronic devices-carbon-nanotube field-effect transistors (CNT- FETs), making use of the flexible yet robust nature of single than those used in other flexible CNT-FETs allowed our devices to be highly deformable without

  17. GaSb molecular beam epitaxial growth on p-InP(001) and passivation with in situ deposited Al{sub 2}O{sub 3} gate oxide

    SciTech Connect (OSTI)

    Merckling, C.; Brammertz, G.; Hoffmann, T. Y.; Caymax, M.; Dekoster, J. [Interuniversity Microelectronics Center (IMEC vzw), Kapeldreef 75, 3001, Leuven (Belgium); Sun, X. [Katholieke Universiteit Leuven, Celestijnelaan 200D, 3001, Leuven (Belgium); Department of Electrical Engineering, Yale University, New Haven, Connecticut 06520-8284 (United States); Alian, A.; Heyns, M. [Interuniversity Microelectronics Center (IMEC vzw), Kapeldreef 75, 3001, Leuven (Belgium); Katholieke Universiteit Leuven, Celestijnelaan 200D, 3001, Leuven (Belgium); Afanas'ev, V. V. [Katholieke Universiteit Leuven, Celestijnelaan 200D, 3001, Leuven (Belgium)

    2011-04-01T23:59:59.000Z

    The integration of high carrier mobility materials into future CMOS generations is presently being studied in order to increase drive current capability and to decrease power consumption in future generation CMOS devices. If III-V materials are the candidates of choice for n-type channel devices, antimonide-based semiconductors present high hole mobility and could be used for p-type channel devices. In this work we first demonstrate the heteroepitaxy of fully relaxed GaSb epilayers on InP(001) substrates. In a second part, the properties of the Al{sub 2}O{sub 3}/GaSb interface have been studied by in situ deposition of an Al{sub 2}O{sub 3} high-{kappa} gate dielectric. The interface is abrupt without any substantial interfacial layer, and is characterized by high conduction and valence band offsets. Finally, MOS capacitors show well-behaved C-V with relatively low D{sub it} along the bandgap, these results point out an efficient electrical passivation of the Al{sub 2}O{sub 3}/GaSb interface.

  18. Field-effect transistor having a superlattice channel and high carrier velocities at high applied fields

    DOE Patents [OSTI]

    Chaffin, R.J.; Dawson, L.R.; Fritz, I.J.; Osbourn, G.C.; Zipperian, T.E.

    1987-06-08T23:59:59.000Z

    A field effect transistor comprises a semiconductor having a source, a drain, a channel and a gate in operational relationship. The semiconductor is a strained layer superlattice comprising alternating quantum well and barrier layers, the quantum well layers and barrier layers being selected from the group of layer pairs consisting of InGaAs/AlGaAs, InAs/InAlGaAs, and InAs/InAlAsP. The layer thicknesses of the quantum well and barrier layers are sufficiently thin that the alternating layers constitute a superlattice which has a superlattice conduction band energy level structure in k-vector space. The layer thicknesses of the quantum well layers are selected to provide a superlattice L/sub 2D/-valley which has a shape which is substantially more two-dimensional than that of said bulk L-valley. 2 figs.

  19. Examination of hot-carrier stress induced degradation on fin field-effect transistor

    SciTech Connect (OSTI)

    Yang, Yi-Lin, E-mail: t3550@nknu.edu.tw; Yen, Tzu-Sung; Ku, Chao-Chen; Wu, Tai-Hsuan; Wang, Tzuo-Li; Li, Chien-Yi; Wu, Bing-Tze [Department of Electronic Engineering, National Kaohsiung Normal University, No. 62, Shenjhong Rd., Yanchao Dist., Kaohsiung City 824, Taiwan (China); Zhang, Wenqi; Hong, Jia-Jian; Wong, Jie-Chen; Yeh, Wen-Kuan [Department of Electrical Engineering, National University of Kaohsiung, No. 700, Kaohsiung University Rd., Nanzih District, Kaohsiung City 811, Taiwan (China); Lin, Shih-Hung [Department of Biomedical Engineering, Hungkuang University, No. 1018, Sec. 6, Taiwan Boulevard, Shalu District, Taichung City 433, Taiwan (China)

    2014-02-24T23:59:59.000Z

    Degradation in fin field-effect transistor devices was investigated in detail under various hot-carrier stress conditions. The threshold voltage (V{sub TH}) shift, substrate current (I{sub B}), and subthreshold swing were extracted to determine the degradation of a device. The power-law time exponent of the V{sub TH} shift was largest at V{sub G}?=?0.3 V{sub D}, indicating that the V{sub TH} shift was dominated by interface state generation. Although the strongest impact ionization occurred at V{sub G}?=?V{sub D}, the V{sub TH} shift was mainly caused by electron trapping resulting from a large gate leakage current.

  20. Halogen-Based Plasma Etching of Novel Field-Effect Transistor Gate Materials

    E-Print Network [OSTI]

    Kiehlbaugh, Kasi Michelle

    2009-01-01T23:59:59.000Z

    Surface Interactions in Fluorocarbon Etching of Silicon2706. Xu, S.L. , et al. , Fluorocarbon polymer formation,

  1. Solution-gated graphene transistors for chemical and biological sensing applications

    E-Print Network [OSTI]

    Mailly, Benjamin

    2013-01-01T23:59:59.000Z

    Various fabrication processes were developed in order to make graphene-based chemical and biological sensors on different substrates. Single-layer graphene is grown by chemical vapor deposition and then transferred to ...

  2. Gate-Dependent Carrier Diffusion Length in Lead Selenide Quantum Dot Field-Effect Transistors

    E-Print Network [OSTI]

    Yu, Dong

    -generation solar panels. Strongly confined QDs such as lead selenide (PbSe) also have the potential to benefit from- generation photovoltaic devices and sensitive photodetec- tors.1-3 The potential for low fabrication cost improvements are still necessary for QD solar cells to compete with commercial technologies. In particular

  3. Halogen-Based Plasma Etching of Novel Field-Effect Transistor Gate Materials

    E-Print Network [OSTI]

    Kiehlbaugh, Kasi Michelle

    2009-01-01T23:59:59.000Z

    Factorial Design .in the fractional factorial design Table 2: Design matrixetch data from the full factorial design, including starting

  4. Radar Vehicle Detection Within Four Quadrant Gate Crossings

    E-Print Network [OSTI]

    Illinois at Urbana-Champaign, University of

    of the exit gate · Less delay between entry and exit gate descent · Extends the exit gate delay only) Methodology 4) Results 5) Conclusions 6) Acknowledgments Exit Gate Operating Modes (EGOM) Radar Vehicle

  5. A thin film transistor driven microchannel device

    E-Print Network [OSTI]

    Lee, Hyun Ho

    2005-02-17T23:59:59.000Z

    .1. Principle of Electrophoresis?????????????? 1.2. Capillary and Microchip Electrophoresis????????... 1.3. Electrophoresis of DNA???????????????.. 2. Plasma Thin Film Deposition Process???????????... 2.1. Fundamentals of Plasma?????????????.?? 2.2. Plasma... Phase Chemical Reactions???????????.. 2.3. Plasma Enhanced Chemical Vapor Deposition??????.. 2.4. PECVD Thin Film?????????????????.. 3. Thin Film Transistor??????????????????.. 7 7 12 17 20 20 23 24 25 29 III...

  6. Doping suppression and mobility enhancement of graphene transistors fabricated using an adhesion promoting dry transfer process

    SciTech Connect (OSTI)

    Cheol Shin, Woo; Hun Mun, Jeong; Yong Kim, Taek; Choi, Sung-Yool; Jin Cho, Byung, E-mail: bjcho@kaist.edu, E-mail: tskim1@kaist.ac.kr [Department of Electrical Engineering, Graphene Research Center, KAIST, 373-1 Guseong-dong, Yuseong-gu, Daejeon 305-701 (Korea, Republic of); Yoon, Taeshik; Kim, Taek-Soo, E-mail: bjcho@kaist.edu, E-mail: tskim1@kaist.ac.kr [Department of Mechanical Engineering, Graphene Research Center, KAIST, 373-1 Guseong-dong, Yuseong-gu, Daejeon 305-701 (Korea, Republic of)] [Department of Mechanical Engineering, Graphene Research Center, KAIST, 373-1 Guseong-dong, Yuseong-gu, Daejeon 305-701 (Korea, Republic of)

    2013-12-09T23:59:59.000Z

    We present the facile dry transfer of graphene synthesized via chemical vapor deposition on copper film to a functional device substrate. High quality uniform dry transfer of graphene to oxidized silicon substrate was achieved by exploiting the beneficial features of a poly(4-vinylphenol) adhesive layer involving a strong adhesion energy to graphene and negligible influence on the electronic and structural properties of graphene. The graphene field effect transistors (FETs) fabricated using the dry transfer process exhibit excellent electrical performance in terms of high FET mobility and low intrinsic doping level, which proves the feasibility of our approach in graphene-based nanoelectronics.

  7. Free electron gas primary thermometer: The bipolar junction transistor

    SciTech Connect (OSTI)

    Mimila-Arroyo, J., E-mail: jmimila@cinvestav.mx [Centro de Investigación y de Estudios Avanzados del Instituto Politécnico Nacional, Dpto. de Ing. Eléctrica-SEES, Av. Instituto Politécnico Nacional No 2508, México D.F. CP 07360 (Mexico)

    2013-11-04T23:59:59.000Z

    The temperature of a bipolar transistor is extracted probing its carrier energy distribution through its collector current, obtained under appropriate polarization conditions, following a rigorous mathematical method. The obtained temperature is independent of the transistor physical properties as current gain, structure (Homo-junction or hetero-junction), and geometrical parameters, resulting to be a primary thermometer. This proposition has been tested using off the shelf silicon transistors at thermal equilibrium with water at its triple point, the transistor temperature values obtained involve an uncertainty of a few milli-Kelvin. This proposition has been successfully tested in the temperature range of 77–450?K.

  8. ambipolar organic transistors: Topics by E-print Network

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    dichalcogenides, tungsten 280 Proposal and design of a new SiC-emitter lateral NPM Schottky collector bipolar transistor on Engineering Websites Summary: for VLSI...

  9. Rational Design and Preparation of Organic Semiconductors for use in Field Effect Transistors and Photovoltaic Cells

    E-Print Network [OSTI]

    Mauldin, Clayton Edward

    2010-01-01T23:59:59.000Z

    in thin film organic photovoltaic cells (OPVs) is presented.Effect Transistors and Photovoltaic Cells By Clayton EdwardEffect Transistors and Photovoltaic Cells By Clayton Edward

  10. InGaP/InGaAs doped-channel direct-coupled field-effect transistors logic with low supply voltage

    SciTech Connect (OSTI)

    Tsai, Jung-Hui, E-mail: jbtsai@nknucc.nknu.edu.tw [National Kaohsiung Normal University, Department of Electronic Engineering (China); Lour, Wen-Shiung [National Taiwan Ocean University, Department of Electrical Engineering (China); Weng Tzuyen; Li Chienming [National Kaohsiung Normal University (China)

    2010-02-15T23:59:59.000Z

    InGaP/InGaAs doped-channel direct-coupled field-effect transistor logic (DCFL) with relatively low supple voltage is demonstrated by two-dimensional analysis. In the integrated enhancement/depletion-mode transistors, subband and two-dimensional electron gas (2DEG) are formed in the InGaAs strain channels, which substantially increase the channel concentration and decrease the drain-to-source saturation voltage. The integrated devices show high turn-on voltage, high transconductance, broad gate voltage swing, and excellent high frequency performance, simultaneously. Furthermore, the integrated devices exhibit large noise margins for DCFL application with low supply voltage of 1.5 V attributed from the relatively small saturation voltages of the studied integrated devices.

  11. Design, fabrication, and analysis of p-channel arsenide/antimonide hetero-junction tunnel transistors

    SciTech Connect (OSTI)

    Rajamohanan, Bijesh, E-mail: bor5067@psu.edu; Mohata, Dheeraj; Hollander, Matthew; Datta, Suman [Department of Electrical Engineering, The Pennsylvania State University, University Park, Pennsylvania 16802 (United States); Zhu, Yan; Hudait, Mantu [Bradley Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, Virginia 24061 (United States); Jiang, Zhengping; Klimeck, Gerhard [Department of Electrical and Computer Engineering, Purdue University, West Lafayette, Indiana 47906 (United States)

    2014-01-28T23:59:59.000Z

    In this paper, we demonstrate InAs/GaSb hetero-junction (hetJ) and GaSb homo-junction (homJ) p-channel tunneling field effect transistors (pTFET) employing a low temperature atomic layer deposited high-? gate dielectric. HetJ pTFET exhibited drive current of 35 ?A/?m in comparison to homJ pTFET, which exhibited drive current of 0.3 ?A/?m at V{sub DS}?=??0.5?V under DC biasing conditions. Additionally, with pulsing of 1 ?s gate voltage, hetJ pTFET exhibited enhanced drive current of 85 ?A/?m at V{sub DS}?=??0.5?V, which is the highest reported in the category of III-V pTFET. Detailed device characterization was performed through analysis of the capacitance-voltage characteristics, pulsed current-voltage characteristics, and x-ray diffraction studies.

  12. Diamond logic inverter with enhancement-mode metal-insulator-semiconductor field effect transistor

    SciTech Connect (OSTI)

    Liu, J. W., E-mail: liu.jiangwei@nims.go.jp [International Center for Young Scientists (ICYS), National Institute for Materials Science (NIMS), 1-1 Namiki, Tsukuba, Ibaraki 305-0044 (Japan); Liao, M. Y.; Imura, M. [Optical and Electronic Materials Unit, NIMS, 1-1 Namiki, Tsukuba, Ibaraki 305-0044 (Japan); Watanabe, E.; Oosato, H. [Nanofabrication Platform, NIMS, 1-2-1 Sengen, Tsukuba, Ibaraki 305-0047 (Japan); Koide, Y., E-mail: koide.yasuo@nims.go.jp [Optical and Electronic Materials Unit, NIMS, 1-1 Namiki, Tsukuba, Ibaraki 305-0044 (Japan); Nanofabrication Platform, NIMS, 1-2-1 Sengen, Tsukuba, Ibaraki 305-0047 (Japan); Center of Materials Research for Low Carbon Emission, NIMS, 1-1 Namiki, Tsukuba, Ibaraki 305-0044 (Japan)

    2014-08-25T23:59:59.000Z

    A diamond logic inverter is demonstrated using an enhancement-mode hydrogenated-diamond metal-insulator-semiconductor field effect transistor (MISFET) coupled with a load resistor. The gate insulator has a bilayer structure of a sputtering-deposited LaAlO{sub 3} layer and a thin atomic-layer-deposited Al{sub 2}O{sub 3} buffer layer. The source-drain current maximum, extrinsic transconductance, and threshold voltage of the MISFET are measured to be ?40.7?mA·mm{sup ?1}, 13.2?±?0.1?mS·mm{sup ?1}, and ?3.1?±?0.1?V, respectively. The logic inverters show distinct inversion (NOT-gate) characteristics for input voltages ranging from 4.0 to ?10.0?V. With increasing the load resistance, the gain of the logic inverter increases from 5.6 to as large as 19.4. The pulse response against the high and low input voltages shows the inversion response with the low and high output voltages.

  13. Attosecond Temporal Gating with Elliptically Polarized Light

    SciTech Connect (OSTI)

    Dudovich, N.; Smirnova, O.; Ivanov, M. Yu.; Villeneuve, D. M.; Corkum, P. B. [Steacie Institute for Molecular Sciences, National Research Council of Canada, Ottawa, Ontario K1A 0R6 (Canada); Levesque, J. [Steacie Institute for Molecular Sciences, National Research Council of Canada, Ottawa, Ontario K1A 0R6 (Canada); INRS-EMT, 1650 boulevard Lionel-Boulet, CP 1020, Varennes, Quebec J3X 1S2 (Canada); Zeidler, D. [Steacie Institute for Molecular Sciences, National Research Council of Canada, Ottawa, Ontario K1A 0R6 (Canada); Carl Zeiss SMT AG, Oberkochen D-73447 (Germany); Comtois, D. [INRS-EMT, 1650 boulevard Lionel-Boulet, CP 1020, Varennes, Quebec J3X 1S2 (Canada)

    2006-12-22T23:59:59.000Z

    Temporal gating allows high accuracy time-resolved measurements of a broad range of ultrafast processes. By manipulating the interaction between an atom and an intense laser field, we extend gating into the nonlinear medium in which attosecond optical and electron pulses are generated. Our gate is an amplitude gate induced by ellipticity of the fundamental pulse. The gate modulates the spectrum of the high harmonic emission and we use the measured modulation to characterize the sub-laser-cycle dynamics of the recollision electron wave packet.

  14. Low-temperature processable amorphous In-W-O thin-film transistors with high mobility and stability

    SciTech Connect (OSTI)

    Kizu, Takio; Aikawa, Shinya; Mitoma, Nobuhiko; Shimizu, Maki; Gao, Xu; Lin, Meng-Fang; Tsukagoshi, Kazuhito, E-mail: TSUKAGOSHI.Kazuhito@nims.go.jp [International Center for Materials Nanoarchitectonics (WPI-MANA), National Institute for Materials Science (NIMS), 1-1 Namiki, Tsukuba, Ibaraki 305-0044 (Japan); Nabatame, Toshihide [MANA Foundry and MANA Advanced Device Materials Group, National Institute for Materials Science (NIMS), 1-1 Namiki, Tsukuba, Ibaraki 305-0044 (Japan)

    2014-04-14T23:59:59.000Z

    Thin-film transistors (TFTs) with a high stability and a high field-effect mobility have been achieved using W-doped indium oxide semiconductors in a low-temperature process (?150?°C). By incorporating WO{sub 3} into indium oxide, TFTs that were highly stable under a negative bias stress were reproducibly achieved without high-temperature annealing, and the degradation of the field-effect mobility was not pronounced. This may be due to the efficient suppression of the excess oxygen vacancies in the film by the high dissociation energy of the bond between oxygen and W atoms and to the different charge states of W ions.

  15. New approach to manufacturing field emitter arrays with sub-half-micron gate apertures

    E-Print Network [OSTI]

    Lee, Jong Duk

    insulator by local oxidation of silicon LOCOS , resulting in the reduction of the gate hole size due. Considering the cathode current level required for flat panel display applications and the measured emission-to-peak. © 1996 American Vacuum Society. I. INTRODUCTION Recently, much attention1,2 has been given to studying

  16. aluminum oxide thin: Topics by E-print Network

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    DEVICE LETTERS, VOL. 19, NO. 12, DECEMBER 1998 High-Performance Polycrystalline SiGe Thin-Film Materials Science Websites Summary: --The use of aluminum oxide as the gate...

  17. Composite two-qubit quantum gates

    E-Print Network [OSTI]

    Svetoslav S. Ivanov; Nikolay V. Vitanov

    2015-03-30T23:59:59.000Z

    We design composite two-qubit gates, based on the Ising-type interaction. The gates are robust against systematic errors in the qubits' interaction strength and the gate's implementation time. We give composite sequences, which cancel the error up to 6th order, and give a method to achieve even higher accuracy. Our sequences can compensate either relative or absolute errors. For relative error compensation the number of the ingredient gates grows linearly with the desired accuracy, while for absolute compensation only two gates are required to achieve infinitely accurate gates. We also consider an ion-trap implementation of our composite gates, where our sequences achieve simultaneous cancellation of the error in both the pulse area and the detuning.

  18. Radio frequency analog electronics based on carbon nanotube transistors

    E-Print Network [OSTI]

    Rogers, John A.

    Radio frequency analog electronics based on carbon nanotube transistors Coskun Kocabas*, Hoon properties of individ- ual tubes. We have implemented solutions to some of these challenges to yield radio band with power gains as high as 14 dB. As a demon- stration, we fabricated nanotube transistor radios

  19. Flexible Graphene Field-Effect Transistors for Microwave Electronics

    E-Print Network [OSTI]

    Shepard, Kenneth

    Flexible Graphene Field-Effect Transistors for Microwave Electronics Inanc Meric , Nicholas Petrone-frequency characteristics of graphene field-effect transistors (GFETs) has received significant interest due the very high carrier velocities in graphene. In addition to excellent electronic performance, graphene possesses

  20. Probing Organic Transistors with Infrared Beams

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    AFDC Printable Version Share this resource Send a link to EERE: Alternative Fuels Data Center Home Page to someone by E-mail Share EERE: Alternative Fuels Data Center Home Page on Facebook Tweet about EERE: Alternative Fuels Data Center Home Page on Twitter Bookmark EERE: Alternative1 First Use of Energy for All Purposes (Fuel and Nonfuel), 2002; Level:Energy: Grid Integration Redefining What's Possible forPortsmouth/Paducah47,193.70 Hg Mercury 35 Br Bromine 43Probing Organic Transistors

  1. Comparative study of InGaP/GaAs high electron mobility transistors with upper and lower delta-doped supplied layers

    SciTech Connect (OSTI)

    Tsai, Jung-Hui, E-mail: jhtsai@nknucc.nknu.edu.tw; Ye, Sheng-Shiun [National Kaohsiung Normal University, Department of Electronic Engineering, Taiwan (China); Guo, Der-Feng [Air Force Academy, Kaohsiung, Department of Electronic Engineering, Taiwan (China); Lour, Wen-Shiung [National Taiwan Ocean University, Department of Electrical Engineering, Taiwan (China)

    2012-04-15T23:59:59.000Z

    Influence corresponding to the position of {delta}-doped supplied layer on InGaP/GaAs high electron mobility transistors is comparatively studied by two-dimensional simulation analysis. The simulated results exhibit that the device with lower {delta}-doped supplied layer shows a higher gate potential barrier height, a higher saturation output current, a larger magnitude of negative threshold voltage, and broader gate voltage swing, as compared to the device with upper {delta}-doped supplied layer. Nevertheless, it has smaller transconductance and inferior high-frequency characteristics in the device with lower {delta}-doped supplied layer. Furthermore, a knee effect in current-voltage curves is observed at low drain-to-source voltage in the two devices, which is investigated in this article.

  2. Simulation and characterization of millimeter-wave InAlN/GaN high electron mobility transistors using Lombardi mobility model

    SciTech Connect (OSTI)

    Du, Jiangfeng, E-mail: jfdu@uestc.edu.cn; Yan, Hui; Yin, Chenggong; Yu, Qi [State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054 (China); Feng, Zhihong; Dun, Shaobo [Science and Technology of ASIC Lab, Hebei Semiconductor Research Institute, Shijiazhuang 050051 (China)

    2014-04-28T23:59:59.000Z

    A gate length of 0.2??m InAlN/GaN high electron mobility transistor on SiC substrate is obtained with a maximum current gain cutoff frequency (f{sub T}) of 65.8?GHz and a maximum power gain cutoff frequency (f{sub max}) of 143.6?GHz. Lombardi model, which takes interface roughness scattering into consideration, has been introduced to model the transconductance (g{sub m}) degradation. The simulated g{sub m} and f{sub T} with Lombardi model are 69% and 58% lower than the ones without considering interface roughness scattering, respectively. Further analysis show experimental g{sub m}, gate capacitance (C{sub g}), and f{sub T} are consistent with results based on Lombardi model.

  3. Remote controlled-NOT gate of d-dimension

    E-Print Network [OSTI]

    Gui-Fang Dang; Heng Fan

    2008-01-23T23:59:59.000Z

    Single qubit rotation gate and the controlled-NOT (CNOT) gate constitute a complete set of gates for universal quantum computation. In general the CNOT gate are only for two nearby qubits. For two qubits which are remote from each other, we need a series of swap gates to transfer these two qubits to the nearest neighboring sites, and then after the CNOT gate we should transfer them to their original sites again. However, a series of swap gates are resource for quantum information processing. One economy way which does not consume so much resource is to implement CNOT gate remotely. The remote CNOT gate is to implement the CNOT gate for two remotely separated qubits with the help of one additional maximally entangled state. The original remote CNOT gate is for two qubits, here we will present the d-dimensional remote CNOT gate. The role of quantum teleportation is identified in the process of the remote CNOT gate.

  4. 2006 29 1 New Capacitorless 1T DRAM Cells : Surrounding Gate and Double Gate MOSFET With

    E-Print Network [OSTI]

    Lee, Jong Duk

    storage node silicon body floating . , double gate back gate negative bias excess hole back induced drain leakage . hole body cell state "1" hole body-drain forward bias cell state "0 source/drain SiN lithography pillar fin pattern . gate channel implantation 0.1µm . SiN hard

  5. Digital Logic lTransistors (Design & Types)

    E-Print Network [OSTI]

    Badrinath, B. R.

    Switch closed: l Short circuit across switch l Current flows l Light is on l Vout is 0V Switch-based circuits #12;Simple Switch Circuit lSwitch open: l No current through circuit l Light is off l Vout is +2.9V l voltage, short circuit between #1 and #2 (switch closed) l when Gate has zero voltage, open circuit

  6. Bielectron vortices in gated graphene

    E-Print Network [OSTI]

    C. A. Downing; M. E. Portnoi

    2015-06-14T23:59:59.000Z

    We study the formation of bound two-particle states in gapless monolayer graphene in gated structures. We find that, even in the regime of massless Dirac fermions, coupling can occur at zero-energy for different or same charge quasiparticles. These bipartite states must have a non-zero internal angular momentum, meaning that they only exist as stationary vortices. We propose a new picture of the experimentally seen Fermi velocity renormalization as a manifestation of these pairs, suggest the possibility of a condensate of these novel quasiparticles.

  7. Gate Solar | Open Energy Information

    Open Energy Info (EERE)

    AFDC Printable Version Share this resource Send a link to EERE: Alternative Fuels Data Center Home Page to someone by E-mail Share EERE: Alternative Fuels Data Center Home Page on Facebook Tweet about EERE: Alternative Fuels Data Center Home Page on Twitter Bookmark EERE: Alternative Fuels Data Center Home Page onYou are now leaving Energy.gov You are now leaving Energy.gov You are being directedAnnual Siteof Energy 2,AUDIT REPORTEnergyFarms A SUK Place: Newport,Gate Solar Jump to:

  8. Cavity-QED-based quantum phase gate

    E-Print Network [OSTI]

    Zubairy, M. Suhail; Kim, M.; Scully, Marlan O.

    2003-01-01T23:59:59.000Z

    We describe a quantum phase gate in which the two qubits are represented by the photons in the two modes of the cavity field. The gate is implemented by passing a three-level atom in a cascade configuration through the cavity. The upper levels...

  9. Proposal for a phase-coherent thermoelectric transistor

    E-Print Network [OSTI]

    Giazotto, F.; Robinson, J. W. A.; Moodera, J. S.; Bergeret, F. S.

    2014-01-01T23:59:59.000Z

    solution since their near perfect electron-hole symmetry leads to a negligible thermoelectric response; however, here we demonstrate theoretically a superconducting thermoelectric transistor which offers unparalleled figures of merit of up to ~ 45...

  10. Axial SiGe Heteronanowire Tunneling Field-Effect Transistors...

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    tunneling field-effect transistors (TFETs), where on-state tunneling occurs in the Ge drain section, while off-state leakage is dominated by the Si junction in the source. Our...

  11. CHARACTERISING MICROWAVE TRANSISTOR DYNAMICS WITH SMALL-SIGNAL MEASUREMENTS

    E-Print Network [OSTI]

    current that settles over time -- that has been attributed to electron trapping and self-heating the possible links between transistor dynamic behaviour and the mechanisms of self-heating, impact ionization

  12. BN/Graphene/BN Transistors for RF Applications

    E-Print Network [OSTI]

    Taychatanapat, Thiti

    In this letter, we demonstrate the first BN/graphene/BN field-effect transistor for RF applications. This device structure can preserve the high mobility and the high carrier velocity of graphene, even when it is sandwiched ...

  13. Delay Analysis of Graphene Field-Effect Transistors

    E-Print Network [OSTI]

    Wang, Han

    In this letter, we analyze the carrier transit delay in graphene field-effect transistors (GFETs).The extraction of the intrinsic delay provides a new way to directly estimate carrier velocity from the experimental data, ...

  14. Fabrication of graphene-on-GaN vertical transistors

    E-Print Network [OSTI]

    Zubair, Ahmad, S.M. Massachusetts Institute of Technology

    2014-01-01T23:59:59.000Z

    The excellent transport properties of graphene make it an excellent option for very high frequency electronics. However, the poor output resistance and difficult lithography of lateral transistors significantly limit its ...

  15. An evaluation of indium antimonide quantum well transistor technology

    E-Print Network [OSTI]

    Liu, Jingwei, M. Eng. Massachusetts Institute of Technology

    2006-01-01T23:59:59.000Z

    Motivated by the super high electron mobility of Indium Antimonide (InSb), researchers have seen great potential to use this new material in high switching speed and low power transistors. In Dec, 2005, Intel and its ...

  16. Degradation mechanisms of GaN high electron mobility transistors

    E-Print Network [OSTI]

    Joh, Jungwoo

    2007-01-01T23:59:59.000Z

    In spite of their extraordinary performance, GaN high electron mobility transistors (HEMT) have still limited reliability. In RF power applications, GaN HEMTs operate at high voltage where good reliability is essential. ...

  17. Flexible, transparent thin film transistors raise hopes for flexible...

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    the thin-film transistor, fabricated using single-atom-thick layers of graphene and tungsten diselenide, among other materials. The white scale bar shows 5 microns, which is...

  18. High-performance Organic Thin-film Transistor 

    E-Print Network [OSTI]

    Jung, Yunbum

    2014-03-19T23:59:59.000Z

    the performance of OTFTs, three novel strategies are proposed in this work: submicron metal patterning, self-aligned structure, and metal semiconductor field-effect transistor (MESFET)-like structure. To realize the solutions, a new concept of lithography, dual...

  19. Substrate dielectric effects on graphene field effect transistors

    SciTech Connect (OSTI)

    Hu, Zhaoying; Prasad Sinha, Dhiraj; Ung Lee, Ji, E-mail: jlee1@albany.edu; Liehr, Michael [College of Nanoscale Science and Engineering, The State University of New York at Albany, Albany, New York 12203 (United States)

    2014-05-21T23:59:59.000Z

    Graphene is emerging as a promising material for future electronics and optoelectronics applications due to its unique electronic structure. Understanding the graphene-dielectric interaction is of vital importance for the development of graphene field effect transistors (FETs) and other novel graphene devices. Here, we extend the exploration of substrate dielectrics from conventionally used thermally grown SiO{sub 2} and hexagonal boron nitride films to technologically relevant deposited dielectrics used in semiconductor industry. A systematic analysis of morphology and optical and electrical properties was performed to study the effects of different substrates (SiO{sub 2}, HfO{sub 2}, Al{sub 2}O{sub 3}, tetraethyl orthosilicate (TEOS)-oxide, and Si{sub 3}N{sub 4}) on the carrier transport of chemical vapor deposition-derived graphene FET devices. As baseline, we use graphene FETs fabricated on thermal SiO{sub 2} with a relatively high carrier mobility of 10?000 cm{sup 2}/(V s). Among the deposited dielectrics studied, silicon nitride showed the highest mobility, comparable to the properties of graphene fabricated on thermal SiO{sub 2}. We conclude that this result comes from lower long range scattering and short range scattering rates in the nitride compared those in the other deposited films. The carrier fluctuation caused by substrates, however, seems to be the main contributing factor for mobility degradation, as a universal mobility-disorder density product is observed for all the dielectrics examined. The extrinsic doping trend is further confirmed by Raman spectra. We also provide, for the first time, correlation between the intensity ratio of G peak and 2D peak in the Raman spectra to the carrier mobility of graphene for different substrates.

  20. Gate-tunable exchange coupling between cobalt clusters on graphene...

    Office of Scientific and Technical Information (OSTI)

    Accepted Manuscript: Gate-tunable exchange coupling between cobalt clusters on graphene Citation Details Title: Gate-tunable exchange coupling between cobalt clusters on...

  1. University of Illinois at Urbana-Champaign's GATE Center for...

    Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

    Urbana-Champaign's GATE Center for Advanced Automotive Bio-Fuel Combustion Engines University of Illinois at Urbana-Champaign's GATE Center for Advanced Automotive Bio-Fuel...

  2. Vehicle Technologies Office Merit Review 2014: GATE: Energy Efficient...

    Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

    GATE: Energy Efficient Vehicles for Sustainable Mobility Vehicle Technologies Office Merit Review 2014: GATE: Energy Efficient Vehicles for Sustainable Mobility Presentation given...

  3. GATE Center for Automotive Fuel Cell Systems at Virginia Tech

    Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

    current density, requires an understanding of liquid water transport in gas diffusion media * Research by students that have completed GATE center coursework, used GATE labs,...

  4. Possible Dynamically Gated Conductance along Heme Wires in Bacterial...

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Possible Dynamically Gated Conductance along Heme Wires in Bacterial Multiheme Cytochromes. Possible Dynamically Gated Conductance along Heme Wires in Bacterial Multiheme...

  5. GATE Center of Excellence at UAB in Lightweight Materials for...

    Broader source: Energy.gov (indexed) [DOE]

    GATE Center of Excellence at UAB in Lightweight Materials for Automotive Applications GATE Center of Excellence at UAB in Lightweight Materials for Automotive Applications 2011 DOE...

  6. Vehicle Technologies Office Merit Review 2014: GATE Center of...

    Broader source: Energy.gov (indexed) [DOE]

    GATE Center of Excellence at UAB for Lightweight Materials and Manufacturing for Automotive, Truck and Mass Transit. ti026vaidya2014p.pdf More Documents & Publications GATE...

  7. Vehicle Technologies Office Merit Review 2015: Gate Driver Optimizatio...

    Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

    Gate Driver Optimization for WBG Applications Vehicle Technologies Office Merit Review 2015: Gate Driver Optimization for WBG Applications Presentation given by Oak Ridge National...

  8. GATE Center of Excellence at UAB in Lightweight Materials for...

    Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

    & Publications GATE Center of Excellence at UAB in Lightweight Materials for Automotive Applications GATE Center of Excellence at UAB in Lightweight Materials for...

  9. PENN STATE DOE GRADUATE AUTOMOTIVE TECHNOLOGY EDUCATION (GATE...

    Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

    PENN STATE DOE GRADUATE AUTOMOTIVE TECHNOLOGY EDUCATION (GATE) PROGRAM FOR PENN STATE DOE GRADUATE AUTOMOTIVE TECHNOLOGY EDUCATION (GATE) PROGRAM FOR 2009 DOE Hydrogen Program and...

  10. Simulation-based design of a strained graphene field effect transistor incorporating the pseudo magnetic field effect

    SciTech Connect (OSTI)

    Souma, Satofumi, E-mail: ssouma@harbor.kobe-u.ac.jp; Ueyama, Masayuki; Ogawa, Matsuto [Department of Electrical and Electronic Engineering, Kobe University, 1-1 Rokkodai, Nada, Kobe 657-8501 (Japan)

    2014-05-26T23:59:59.000Z

    We present a numerical study on the performance of strained graphene-based field-effect transistors. A local strain less than 10% is applied over a central channel region of the graphene to induce the shift of the Dirac point in the channel region along the transverse momentum direction. The left and the right unstrained graphene regions are doped to be either n-type or p-type. By using the atomistic tight-binding model and a Green's function method, we predict that the gate voltage applied to the central strained graphene region can switch the drain current on and off with an on/off ratio of more than six orders of magnitude at room temperature. This is in spite of the absence of a bandgap in the strained channel region. Steeper subthreshold slopes below 60?mV/decade are also predicted at room temperature because of a mechanism similar to the band-to-band tunneling field-effect transistors.

  11. The design of a frequency modulated transistor oscillator

    E-Print Network [OSTI]

    Fisher, Phil Dewey

    1959-01-01T23:59:59.000Z

    with temperature rise. c The germanium transistor, a Texas Instruments 3N365, has a maximum operating temperature of +75'C. Capacitor 06 and 0 were added to eliminate the high audio frequency noise generated by the heating of the thermistor and transistor... of the voltage applied to the modulator. The oscillator frequency deviations were measured 'by the communication receiver, crystal controlled oscillator, and electronic frequency counter method discussed on page 26. The voltage was varied in steps of 0. 0$ cf...

  12. Any correspondence concerning this service should be sent to the repository administrator: staff-oatao@inp-toulouse.fr

    E-Print Network [OSTI]

    Mailhes, Corinne

    and near oxide traps in small gate area MOS transistors (gate area ,1 mm2 ) lead to RTS noise which implies in order to maximise the pixel photosensitive area. This leads to an increase of MOS transistor low fre. Thus, this technique leads to a decrease of the image sensor sensitivity. In this Letter, we propose

  13. Oxygen migration in TiO{sub 2}-based higher-k gate stacks

    SciTech Connect (OSTI)

    Kim, Sang Bum; Brown, Stephen L.; Rossnagel, Stephen M.; Bruley, John; Copel, Matthew; Hopstaken, Marco J. P.; Narayanan, Vijay; Frank, Martin M. [IBM T.J. Watson Research Center, 1101 Kitchawan Road, Yorktown Heights, New York 10598 (United States)

    2010-03-15T23:59:59.000Z

    We report on the stability of high-permittivity (high-k) TiO{sub 2} films incorporated in metal-oxide-silicon capacitor structures with a TiN metal gate electrode, focusing on oxygen migration. Titanium oxide films are deposited by either Ti sputtering [physical vapor deposition (PVD)] followed by radical shower oxidation or by plasma-enhanced atomic layer deposition (PEALD) from titanium isopropoxide (Ti{l_brace}OCH(CH{sub 3}){sub 2{r_brace}4}) and O{sub 2} plasma. Both PVD and PEALD films result in near-stoichiometric TiO{sub 2} prior to high-temperature annealing. We find that dopant activation anneals of TiO{sub 2}-containing gate stacks at 1000 deg. C cause 5 A or more of additional SiO{sub 2} to be formed at the gate-dielectric/Si-channel interface. Furthermore, we demonstrate for the first time that oxygen released from TiO{sub 2} diffuses through the TiN gate electrode and oxidizes the poly-Si contact. The thickness of this upper SiO{sub 2} layer continues to increase with increasing TiO{sub 2} thickness, while the thickness of the regrown SiO{sub 2} at the gate-dielectric/Si interface saturates. The upper SiO{sub 2} layer degrades gate stack capacitance, and simultaneously the oxygen-deficient TiO{sub x} becomes a poor insulator. In an attempt to mitigate O loss from the TiO{sub 2}, top and bottom Al{sub 2}O{sub 3} layers are added to the TiO{sub 2} gate dielectric as oxygen barriers. However, they are found to be ineffective, due to Al{sub 2}O{sub 3}-TiO{sub 2} interdiffusion during activation annealing. Bottom HfO{sub 2}/Si{sub 3}N{sub 4} interlayers are found to serve as more effective oxygen barriers, reducing, though not preventing, oxygen downdiffusion.

  14. Extremely scaled high-k/In?.??Ga?.??As gate stacks with low leakage and low interface trap densities

    SciTech Connect (OSTI)

    Chobpattana, Varistha; Mikheev, Evgeny; Zhang, Jack Y.; Mates, Thomas E.; Stemmer, Susanne [Materials Department, University of California, Santa Barbara, California 93106-5050 (United States)

    2014-09-28T23:59:59.000Z

    Highly scaled gate dielectric stacks with low leakage and low interface trap densities are required for complementary metal-oxide-semiconductor technology with III-V semiconductor channels. Here, we show that a novel pre-deposition technique, consisting of alternating cycles of nitrogen plasma and tetrakis(dimethylamino)titanium, allows for HfO? and ZrO? gate stacks with extremely high accumulation capacitance densities of more than 5 ?F/cm? at 1 MHz, low leakage current, low frequency dispersion, and low midgap interface trap densities (10¹²cm?²eV?¹range). Using x-ray photoelectron spectroscopy, we show that the interface contains TiO? and small quantities of In?O?, but no detectable Ga- or As-oxides, or As-As bonding. The results allow for insights into the microscopic mechanisms that control leakage and frequency dispersion in high-k/III-V gate stacks.

  15. Graduate Automotive Technology Education (GATE) Center

    SciTech Connect (OSTI)

    Jeffrey Hodgson; David Irick

    2005-09-30T23:59:59.000Z

    The Graduate Automotive Technology Education (GATE) Center at the University of Tennessee, Knoxville has completed its sixth year of operation. During this period the Center has involved thirteen GATE Fellows and ten GATE Research Assistants in preparing them to contribute to advanced automotive technologies in the center's focus area: hybrid drive trains and control systems. Eighteen GATE students have graduated, and three have completed their course work requirements. Nine faculty members from three departments in the College of Engineering have been involved in the GATE Center. In addition to the impact that the Center has had on the students and faculty involved, the presence of the center has led to the acquisition of resources that probably would not have been obtained if the GATE Center had not existed. Significant industry interaction such as internships, equipment donations, and support for GATE students has been realized. The value of the total resources brought to the university (including related research contracts) exceeds $4,000,000. Problem areas are discussed in the hope that future activities may benefit from the operation of the current program.

  16. A p-cell approach to integer gate sizing

    E-Print Network [OSTI]

    Doddannagari, Uday

    2009-05-15T23:59:59.000Z

    uniformly spaced gate sizes would result in a large number of gate sizes and maintaining the huge volume of data for this number of gate sizes is difficult. This thesis aims to propose a practical approach to implement integer gate sizes. A parameterized...

  17. Nondestructive characterization of a TiN metal gate: Chemical and structural properties by means of standing-wave hard x-ray

    E-Print Network [OSTI]

    Fadley, Charles

    Nondestructive characterization of a TiN metal gate: Chemical and structural properties by means (HXPS, HAXPES) is applied to a thick (100 A° ) film of a metal gate TiN grown on top of a Si/MoSi2 of TiN, as well as the buried interface between TiN and the native oxide on top of the mirror

  18. Hydrogen passivation of electron trap in amorphous In-Ga-Zn-O thin-film transistors

    SciTech Connect (OSTI)

    Hanyu, Yuichiro, E-mail: y-hanyu@lucid.msl.titech.ac.jp; Domen, Kay [Materials and Structures Laboratory, Tokyo Institute of Technology, Yokohama (Japan)] [Materials and Structures Laboratory, Tokyo Institute of Technology, Yokohama (Japan); Nomura, Kenji [Frontier Research Center, Tokyo Institute of Technology, Yokohama (Japan)] [Frontier Research Center, Tokyo Institute of Technology, Yokohama (Japan); Hiramatsu, Hidenori; Kamiya, Toshio [Materials and Structures Laboratory, Tokyo Institute of Technology, Yokohama (Japan) [Materials and Structures Laboratory, Tokyo Institute of Technology, Yokohama (Japan); Materials Research Center for Element Strategy, Tokyo Institute of Technology, Yokohama (Japan); Kumomi, Hideya [Materials Research Center for Element Strategy, Tokyo Institute of Technology, Yokohama (Japan)] [Materials Research Center for Element Strategy, Tokyo Institute of Technology, Yokohama (Japan); Hosono, Hideo [Materials and Structures Laboratory, Tokyo Institute of Technology, Yokohama (Japan) [Materials and Structures Laboratory, Tokyo Institute of Technology, Yokohama (Japan); Frontier Research Center, Tokyo Institute of Technology, Yokohama (Japan); Materials Research Center for Element Strategy, Tokyo Institute of Technology, Yokohama (Japan)

    2013-11-11T23:59:59.000Z

    We report an experimental evidence that some hydrogens passivate electron traps in an amorphous oxide semiconductor, a-In-Ga-Zn-O (a-IGZO). The a-IGZO thin-film transistors (TFTs) annealed at 300?°C exhibit good operation characteristics; while those annealed at ?400?°C show deteriorated ones. Thermal desorption spectra (TDS) of H{sub 2}O indicate that this threshold annealing temperature corresponds to depletion of H{sub 2}O desorption from the a-IGZO layer. Hydrogen re-doping by wet oxygen annealing recovers the good TFT characteristic. The hydrogens responsible for this passivation have specific binding energies corresponding to the desorption temperatures of 300–430?°C. A plausible structural model is suggested.

  19. Low temperature atomic layer deposited ZnO photo thin film transistors

    SciTech Connect (OSTI)

    Oruc, Feyza B.; Aygun, Levent E.; Donmez, Inci; Biyikli, Necmi; Okyay, Ali K., E-mail: aokyay@ee.bilkent.edu.tr [Institute of Materials Science and Nanotechnology, Bilkent University, Bilkent, 06800 Ankara (Turkey); UNAM—National Nanotechnology Research Center, Bilkent University, Bilkent, 06800 Ankara (Turkey); Department of Electrical and Electronics Engineering, Bilkent University, Bilkent, 06800 Ankara (Turkey); Yu, Hyun Yong [The School of Electrical Engineering, Korea University, Seoul 136-701 (Korea, Republic of)

    2015-01-01T23:59:59.000Z

    ZnO thin film transistors (TFTs) are fabricated on Si substrates using atomic layer deposition technique. The growth temperature of ZnO channel layers are selected as 80, 100, 120, 130, and 250?°C. Material characteristics of ZnO films are examined using x-ray photoelectron spectroscopy and x-ray diffraction methods. Stoichiometry analyses showed that the amount of both oxygen vacancies and interstitial zinc decrease with decreasing growth temperature. Electrical characteristics improve with decreasing growth temperature. Best results are obtained with ZnO channels deposited at 80?°C; I{sub on}/I{sub off} ratio is extracted as 7.8 × 10{sup 9} and subthreshold slope is extracted as 0.116 V/dec. Flexible ZnO TFT devices are also fabricated using films grown at 80?°C. I{sub D}–V{sub GS} characterization results showed that devices fabricated on different substrates (Si and polyethylene terephthalate) show similar electrical characteristics. Sub-bandgap photo sensing properties of ZnO based TFTs are investigated; it is shown that visible light absorption of ZnO based TFTs can be actively controlled by external gate bias.

  20. Effect of buffer structures on AlGaN/GaN high electron mobility transistor reliability

    SciTech Connect (OSTI)

    Liu, L. [University of Florida, Gainesville; Xi, Y. Y. [University of Florida, Gainesville; Ren, F. [University of Florida; Pearton, S. J. [University of Florida; Laboutin, O. [Kopin Corporation, Taunton, MA; Cao, Yu [Kopin Corporation, Taunton, MA; Johnson, Wayne J. [Kopin Corporation, Taunton, MA; Kravchenko, Ivan I [ORNL

    2012-01-01T23:59:59.000Z

    AlGaN/GaN high electron mobility transistors (HEMTs) with three different types of buffer layers, including a GaN/AlGaN composite layer, or 1 or 2 lm GaN thick layers, were fabricated and their reliability compared. The HEMTs with the thick GaN buffer layer showed the lowest critical voltage (Vcri) during off-state drain step-stress, but this was increased by around 50% and 100% for devices with the composite AlGaN/GaN buffer layers or thinner GaN buffers, respectively. The Voff - state for HEMTs with thin GaN and composite buffers were 100 V, however, this degraded to 50 60V for devices with thick GaN buffers due to the difference in peak electric field near the gate edge. A similar trend was observed in the isolation breakdown voltage measurements, with the highest Viso achieved based on thin GaN or composite buffer designs (600 700 V), while a much smaller Viso of 200V was measured on HEMTs with the thick GaN buffer layers. These results demonstrate the strong influence of buffer structure and defect density on AlGaN/GaN HEMT performance and reliability.

  1. New fabrication method of silicon field emitter arrays using thermal oxidation

    E-Print Network [OSTI]

    Lee, Jong Duk

    Vacuum Society. I. INTRODUCTION For most applications of vacuum microelectronics such as flat panel array using pure thermal oxide as a gate insulator are described. Since the thermally grown oxide film has a better stoichiometry and is a better insulator than the evaporated oxide, the fabrication

  2. "The Road Ahead for Carbon Nanotube Transistors" Friday, June 21, 2013 @ 10:00am

    E-Print Network [OSTI]

    Holland, Jeffrey

    , supercapacitors, and photovoltaic cells. His Ph.D. research at Purdue was funded by a National Science Foundation for next-generation transistors. While some of the CNT field-effect transistor (CNTFET) research community

  3. Characterization of Schottky barrier carbon nanotube transistors and their applications to digital circuit design

    E-Print Network [OSTI]

    Cline, Julia Van Meter, 1979-

    2004-01-01T23:59:59.000Z

    The difficulty in shrinking silicon transistors past a certain feature size has been acknowledged for years. Carbon nanotubes (CNTs) offer a technology with an exciting solution to the scaling issues of transistors and ...

  4. Optimization of Integrated Transistors for Very High Frequency DC-DC Converters

    E-Print Network [OSTI]

    Sagneri, Anthony D.

    This paper presents a method to optimize integrated lateral double-diffused MOSFET transistors for use in very high frequency (VHF, 30-300 MHz) dc-dc converters. A transistor model valid at VHF switching frequencies is ...

  5. Investigation of the tunneling emitter bipolar transistor as spin-injector into silicon

    E-Print Network [OSTI]

    Van Veenhuizen, Marc Julien

    2010-01-01T23:59:59.000Z

    In this thesis is discussed the tunneling emitter bipolar transistor as a possible spin-injector into silicon. The transistor has a metallic emitter which as a spin-injector will be a ferromagnet. Spin-polarized electrons ...

  6. Graphene-on-Insulator Transistors Made Using C on Ni Chemical-Vapor Deposition

    E-Print Network [OSTI]

    Keast, Craig L.

    Graphene transistors are made by transferring a thin graphene film grown on Ni onto an insulating SiO[subscript 2] substrate. The properties and integration of these graphene-on-insulator transistors are presented and ...

  7. High level compilation for gate reconfigurable architectures

    E-Print Network [OSTI]

    Babb, Jonathan William

    2001-01-01T23:59:59.000Z

    A continuing exponential increase in the number of programmable elements is turning management of gate-reconfigurable architectures as "glue logic" into an intractable problem; it is past time to raise this abstraction ...

  8. Sandia National Laboratories: i-GATE

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    partners, investors, and technical resources isn't generally an easy task for start-up companies. But for clients of the i-GATE (Innovation for Green Advanced Transportation...

  9. GaTe semiconductor for radiation detection

    DOE Patents [OSTI]

    Payne, Stephen A. (Castro Valley, CA); Burger, Arnold (Nashville, TN); Mandal, Krishna C. (Ashland, MA)

    2009-06-23T23:59:59.000Z

    GaTe semiconductor is used as a room-temperature radiation detector. GaTe has useful properties for radiation detectors: ideal bandgap, favorable mobilities, low melting point (no evaporation), non-hygroscopic nature, and availability of high-purity starting materials. The detector can be used, e.g., for detection of illicit nuclear weapons and radiological dispersed devices at ports of entry, in cities, and off shore and for determination of medical isotopes present in a patient.

  10. Remote quantum gates mediated by spin chains

    E-Print Network [OSTI]

    R. Ronke; I. D'Amico; T. P. Spiller

    2010-03-09T23:59:59.000Z

    There has been much recent study on the application of spin chains to quantum state transfer and communication. Here we demonstrate that spin chains set up for perfect quantum state transfer can be utilised to generate remote quantum gates, between spin qubits injected at the ends of the chain. The natural evolution of the system across different excitation number sectors generates a maximally-entangling and universal gate between the injected qubits, independent of the length of the chain.

  11. Gate fidelity fluctuations and quantum process invariants

    SciTech Connect (OSTI)

    Magesan, Easwar; Emerson, Joseph [Institute for Quantum Computing and Department of Applied Mathematics, University of Waterloo, Waterloo, Ontario N2L 3G1 (Canada); Blume-Kohout, Robin [Theoretical Division, Los Alamos National Laboratory, Los Alamos, New Mexico 87545 (United States)

    2011-07-15T23:59:59.000Z

    We characterize the quantum gate fidelity in a state-independent manner by giving an explicit expression for its variance. The method we provide can be extended to calculate all higher order moments of the gate fidelity. Using these results, we obtain a simple expression for the variance of a single-qubit system and deduce the asymptotic behavior for large-dimensional quantum systems. Applications of these results to quantum chaos and randomized benchmarking are discussed.

  12. Polarity Switching and Transient Responses in Single Nanotube Nanofluidic Transistors Rohit Karnik,2

    E-Print Network [OSTI]

    Yang, Peidong

    Polarity Switching and Transient Responses in Single Nanotube Nanofluidic Transistors Rong Fan,1, can switch the nanofluidic transistors from p-type to ambipolar and n-type field effect transistors. Nanofluidic FETs have potential implications in subfemtoliter analytical technology and large

  13. Range gated strip proximity sensor

    DOE Patents [OSTI]

    McEwan, T.E.

    1996-12-03T23:59:59.000Z

    A range gated strip proximity sensor uses one set of sensor electronics and a distributed antenna or strip which extends along the perimeter to be sensed. A micro-power RF transmitter is coupled to the first end of the strip and transmits a sequence of RF pulses on the strip to produce a sensor field along the strip. A receiver is coupled to the second end of the strip, and generates a field reference signal in response to the sequence of pulse on the line combined with received electromagnetic energy from reflections in the field. The sensor signals comprise pulses of radio frequency signals having a duration of less than 10 nanoseconds, and a pulse repetition rate on the order of 1 to 10 MegaHertz or less. The duration of the radio frequency pulses is adjusted to control the range of the sensor. An RF detector feeds a filter capacitor in response to received pulses on the strip line to produce a field reference signal representing the average amplitude of the received pulses. When a received pulse is mixed with a received echo, the mixing causes a fluctuation in the amplitude of the field reference signal, providing a range-limited Doppler type signature of a field disturbance. 6 figs.

  14. Range gated strip proximity sensor

    DOE Patents [OSTI]

    McEwan, Thomas E. (Livermore, CA)

    1996-01-01T23:59:59.000Z

    A range gated strip proximity sensor uses one set of sensor electronics and a distributed antenna or strip which extends along the perimeter to be sensed. A micro-power RF transmitter is coupled to the first end of the strip and transmits a sequence of RF pulses on the strip to produce a sensor field along the strip. A receiver is coupled to the second end of the strip, and generates a field reference signal in response to the sequence of pulse on the line combined with received electromagnetic energy from reflections in the field. The sensor signals comprise pulses of radio frequency signals having a duration of less than 10 nanoseconds, and a pulse repetition rate on the order of 1 to 10 MegaHertz or less. The duration of the radio frequency pulses is adjusted to control the range of the sensor. An RF detector feeds a filter capacitor in response to received pulses on the strip line to produce a field reference signal representing the average amplitude of the received pulses. When a received pulse is mixed with a received echo, the mixing causes a fluctuation in the amplitude of the field reference signal, providing a range-limited Doppler type signature of a field disturbance.

  15. Carbon Nanotube Field-Effect Transistors with Integrated Ohmic

    E-Print Network [OSTI]

    Javey, Ali

    segments of the tube are electrostatically "doped" by a back gate and act effectively as source and drain as gate insulators, and electrostatically doped nanotube segments as source/drain electrodes for low OFF currents and suppressed ambipolar conduction. The doped source and drain approach resembles

  16. High-temperature stable W/GaAs interface and application to metal--semiconductor field-effect transistors and digital circuits

    SciTech Connect (OSTI)

    Josefowicz, J.Y.; Rensch, D.B.

    1987-11-01T23:59:59.000Z

    The thermal stability of the physical, chemical, and electrical properties of W thin films sputter deposited on GaAs were investigated. A variety of characterization methods, including thin film stress analysis, Auger analysis, Rutherford backscattering spectrometry (RBS) analysis, and Schottky barrier measurements showed that the W/GaAs interface remains stable after high-temperature furnace annealing at 900 /sup 0/C for 15 min or rapid-lamp annealing at 1000 /sup 0/C for 11 s. Some refractory metal compounds were also investigated, including, WSi, WN/sub x/, and TaSi/sub x/. Pure W films produced the best Schottky diode characteristics. The average Schottky barrier height was 0.70 +- 0.009 V across a 2-in wafer after furnace annealing at 800 /sup 0/C/15 min. Pure W self-aligned gate (SAG) metal-semiconductor field-effect transistors (MESFET) and digital circuits were also fabricated. Transconductances as high as 300 mS/mm (L/sub g/ = 1.0 ..mu..m) were measured for enhancement mode SAG MESFET's. Circuits were fabricated with SAG MESFET enhancement-resistor mode logic using pure W gates, including ring oscillators, with gate delay as low as 25 ps and divide-by-eight circuits that functioned at a frequency >1 GHz.

  17. Photo-modulated thin film transistor based on dynamic charge transfer within quantum-dots-InGaZnO interface

    SciTech Connect (OSTI)

    Liu, Xiang [Electronic Science and Engineering School, Southeast University, Nanjing (China); National Center for Nanoscience and Technology, Beijing (China); Yang, Xiaoxia; Liu, Mingju [National Center for Nanoscience and Technology, Beijing (China); Tao, Zhi; Wei, Lei, E-mail: lw@seu.edu.cn; Li, Chi, E-mail: lichi@seu.edu.cn; Zhang, Xiaobing; Wang, Baoping [Electronic Science and Engineering School, Southeast University, Nanjing (China); Dai, Qing, E-mail: daiq@nanoctr.cn [National Center for Nanoscience and Technology, Beijing (China); London Center for Nanotechnology, University College London, London WC1H 0AH (United Kingdom); Nathan, Arokia [Electronic Science and Engineering School, Southeast University, Nanjing (China); London Center for Nanotechnology, University College London, London WC1H 0AH (United Kingdom)

    2014-03-17T23:59:59.000Z

    The temporal development of next-generation photo-induced transistor across semiconductor quantum dots and Zn-related oxide thin film is reported in this paper. Through the dynamic charge transfer in the interface between these two key components, the responsibility of photocurrent can be amplified for scales of times (?10{sup 4}?A/W 450?nm) by the electron injection from excited quantum dots to InGaZnO thin film. And this photo-transistor has a broader waveband (from ultraviolet to visible light) optical sensitivity compared with other Zn-related oxide photoelectric device. Moreover, persistent photoconductivity effect can be diminished in visible waveband which lead to a significant improvement in the device's relaxation time from visible illuminated to dark state due to the ultrafast quenching of quantum dots. With other inherent properties such as integrated circuit compatible, low off-state current and high external quantum efficiency resolution, it has a great potential in the photoelectric device application, such as photodetector, phototransistor, and sensor array.

  18. Sliding-gate valve for use with abrasive materials

    DOE Patents [OSTI]

    Ayers, Jr., William J. (Morgantown, WV); Carter, Charles R. (Fairmont, WV); Griffith, Richard A. (Morgantown, WV); Loomis, Richard B. (Bruceton Mills, WV); Notestein, John E. (Morgantown, WV)

    1985-01-01T23:59:59.000Z

    The invention is a flow and pressure-sealing valve for use with abrasive solids. The valve embodies special features which provide for long, reliable operating lifetimes in solids-handling service. The valve includes upper and lower transversely slidable gates, contained in separate chambers. The upper gate provides a solids-flow control function, whereas the lower gate provides a pressure-sealing function. The lower gate is supported by means for (a) lifting that gate into sealing engagement with its seat when the gate is in its open and closed positions and (b) lowering the gate out of contact with its seat to permit abrasion-free transit of the gate between its open and closed positions. When closed, the upper gate isolates the lower gate from the solids. Because of this shielding action, the sealing surface of the lower gate is not exposed to solids during transit or when it is being lifted or lowered. The chamber containing the lower gate normally is pressurized slightly, and a sweep gas is directed inwardly across the lower-gate sealing surface during the vertical translation of the gate.

  19. 1120 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 5, MAY 2006 Theory of Interface-Trap-Induced NBTI Degradation

    E-Print Network [OSTI]

    Alam, Muhammad A.

    mechanisms that generate traps at the Si-channel/gate-oxide interface of MOSFETs during transistor operation. The semiconductor/oxide interface is a rough surface where the highly ordered crystalline channel and the amor lead to poor device performance; therefore, the transistors are annealed in hydrogen ambient during

  20. Sleep Transistor Sizing and Control for Resonant Supply

    E-Print Network [OSTI]

    Kim, Chris H.

    larger sleep transistors to improve performance · Considers only IR droop · Ignores the Ldi/dt noise Suppression of Resonance · Decap consumes large leakage and area · Adding resistors results in extra IR droop to avoid IR droop · Adjustable switching threshold VSW #12;12 · Suppression in both undershoot

  1. Amorphous silicon thin film transistor as nonvolatile device. 

    E-Print Network [OSTI]

    Nominanda, Helinda

    2008-10-10T23:59:59.000Z

    n-channel and p-channel amorphous-silicon thin-film transistors (a-Si:H TFTs) with copper electrodes prepared by a novel plasma etching process have been fabricated and studied. Their characteristics are similar to those of TFTs with molybdenum...

  2. Buffer Minimization in Pass Transistor Logic Advanced Technology Group

    E-Print Network [OSTI]

    Zhou, Hai

    function cells and four inverters with various drive capabilities. The approach in [2] also utilizesBuffer Minimization in Pass Transistor Logic Hai Zhou Advanced Technology Group Synopsys, Inc are inverters, where phase assignment need to be done with buffer insertion. Exper­ iments are done on MCNC

  3. Carbon Nanotube Transistor Arrays for Multistage Complementary Logic and

    E-Print Network [OSTI]

    Ural, Ant

    and resistors.5 Several issues need to be addressed in order to impart complexity and advanced functionality, Qian Wang, Ant Ural, Yiming Li, and Hongjie Dai* Department of Chemistry and Laboratory for AdVanced into field effect transistors (FETs)1 and intratube p-n junctions.3,4 Inverters, the simplest form of logic

  4. Engineering integrated photonics for heralded quantum gates

    E-Print Network [OSTI]

    T. Meany; D. N. Biggerstaff; M. A. Broome; A. Fedrizzi; M. Delanty; A. Gilchrist; G. D. Marshall; M. J. Steel; A. G. White; M. J. Withford

    2015-02-11T23:59:59.000Z

    Scaling up linear-optics quantum computing will require multi-photon gates which are compact, phase-stable, exhibit excellent quantum interference, and have success heralded by the detection of ancillary photons. We investigate implementation of the optimal known gate design which meets these requirements: the Knill controlled-Z gate, implemented in integrated laser-written waveguide arrays. We show that device performance is more sensitive to the small deviations in the coupler reflectivity, arising due to the tolerance values of the fabrication method, than phase variations in the circuit. The mode fidelity was also shown to be less sensitive to reflectivity and phase errors than process fidelity. Our best device achieves a fidelity of 0.931+/-0.001 with the ideal 4x4 unitary circuit and a process fidelity of 0.680+/-0.005 with the ideal computational-basis process.

  5. Prototypical Single-Molecule Chemical-Field-Effect Transistor with Nanometer-Sized Gates F. Jackel,1

    E-Print Network [OSTI]

    Peters, Achim

    strong electron acceptor sub- stituents [anthraquinone (AQ)], which can form charge transfer complexes

  6. Si-CMOS-Like Integration of AlGaN/GaN Dielectric-Gated High-Electron-Mobility Transistors

    E-Print Network [OSTI]

    Johnson, Derek Wade

    2014-07-31T23:59:59.000Z

    the engineering of high mobility, high carrier density channels at III-Nitride heterointerfaces. In order to seize market share from silicon, the cost of manufacturing GaN-based devices must be further reduced. With the successful realization of 200mm Ga...

  7. Si-CMOS-Like Integration of AlGaN/GaN Dielectric-Gated High-Electron-Mobility Transistors 

    E-Print Network [OSTI]

    Johnson, Derek Wade

    2014-07-31T23:59:59.000Z

    the engineering of high mobility, high carrier density channels at III-Nitride heterointerfaces. In order to seize market share from silicon, the cost of manufacturing GaN-based devices must be further reduced. With the successful realization of 200mm Ga...

  8. A Dual Platform for Selective Analyte Enrichment and Ionization in Mass Spectrometry Using Aptamer-Conjugated Graphene Oxide

    E-Print Network [OSTI]

    Tan, Weihong

    -Conjugated Graphene Oxide Basri Gulbakan, Emir Yasun, M. Ibrahim Shukoor, Zhi Zhu, Mingxu You, Xiaohong Tan,, Hernan: This study demonstrates the use of aptamer-conju- gated graphene oxide as an affinity extraction a matrix and with greatly improved signal- to-noise ratios. Aptamer-conjugated graphene oxide has clear

  9. abnormal sensorimotor gating: Topics by E-print Network

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    double dots can be effectively tuned from weak to strong regime by both the in-plane plunger gates and back gate. All the relevant energy scales and parameters of the bilayer...

  10. Fabrication and characterization of junctionless carbon nanotube field effect transistor for cholesterol detection

    SciTech Connect (OSTI)

    Barik, Md. Abdul, E-mail: abdulnpl@gmail.com; Dutta, Jiten Ch. [Department of Electronics and Communication Engineering, Tezpur University, Napaam, Tezpur, Assam 784028 (India)

    2014-08-04T23:59:59.000Z

    We have reported fabrication and characterization of polyaniline (PANI)/zinc oxide (ZnO) membrane-based junctionless carbon nanotube field effect transistor deposited on indium tin oxide glass plate for the detection of cholesterol (0.5–22.2?mM). Cholesterol oxidase (ChOx) has been immobilized on the PANI/ZnO membrane by physical adsorption technique. Electrical response has been recorded using digital multimeter (Agilent 3458A) in the presence of phosphate buffer saline of 50?mM, pH 7.0, and 0.9% NaCl contained in a glass pot. The results of response studies for cholesterol reveal linearity as 0.5–16.6?mM and improved sensitivity of 60?mV/decade in good agreement with Nernstian limit ?59.2?mV/decade. The life time of this sensor has been found up to 5 months and response time of 1?s. The limit of detection with regression coefficient (r) ? 0.998 and Michaelis-Menten constant (K{sub m}) were found to be ?0.25 and 1.4?mM, respectively, indicating high affinity of ChOx to cholesterol. The results obtained in this work show negligible interference with glucose and urea.

  11. Probing channel temperature profiles in Al{sub x}Ga{sub 1?x}N/GaN high electron mobility transistors on 200?mm diameter Si(111) by optical spectroscopy

    SciTech Connect (OSTI)

    Kyaw, L. M., E-mail: a0048661@nus.edu.sg [Department of Electrical and Computer Engineering, National University of Singapore, Singapore 117576 (Singapore); Institute of Materials Research and Engineering, A*STAR (Agency for Science, Technology, and Research), Singapore 117602 (Singapore); Bera, L. K.; Dolmanan, S. B.; Tan, H. R.; Bhat, T. N.; Tripathy, S., E-mail: tripathy-sudhiranjan@imre.a-star.edu.sg [Institute of Materials Research and Engineering, A*STAR (Agency for Science, Technology, and Research), Singapore 117602 (Singapore); Liu, Y.; Bera, M. K.; Singh, S. P.; Chor, E. F. [Department of Electrical and Computer Engineering, National University of Singapore, Singapore 117576 (Singapore)

    2014-08-18T23:59:59.000Z

    Using micro-Raman and photoluminescence (PL) techniques, the channel temperature profile is probed in Al{sub x}Ga{sub 1-x}N/GaN high electron mobility transistors (HEMTs) fabricated on a 200?mm diameter Si(111) substrate. In particular, RuO{sub x}-based gate is used due to the semitransparent nature to the optical excitation wavelengths, thus allowing much accurate thermal investigations underneath the gate. To determine the channel temperature profile in devices subjected to different electrical bias voltages, the GaN band-edge PL peak shift calibration with respect to temperature is used. PL analyses show a maximum channel temperature up to 435?K underneath the gate edge between gate and drain, where the estimated thermal resistance in such a HEMT structure is about 13.7 KmmW{sup ?1} at a power dissipation of ?10?W/mm. The temperature profiles from micro-Raman measurements are also addressed from the E{sub 2}-high optical phonon peak shift of GaN, and this method also probes the temperature-induced peak shifts of optical phonon from Si thus showing the nature of thermal characteristics at the AlN/Si substrate interface.

  12. Terahertz plasma wave resonance of two-dimensional electrons in InGaP/InGaAs/GaAs high-electron-mobility transistors

    SciTech Connect (OSTI)

    Otsuji, Taiichi; Hanabe, Mitsuhiro; Ogawara, Osamu [Kyushu Institute of Technology, Graduate School of Computer Science and Systems Engineering, 680-4 Kawazu, Iizuka, Fukuoka, 820-8502 (Japan)

    2004-09-13T23:59:59.000Z

    We have observed the frequency dependence of the plasma resonant intensity in the terahertz range for a short gate-length InGaP/InGaAs/GaAs pseudomorphic high-electron-mobility transistor. The plasma resonance excitation was performed by means of interband photoexcitation using the difference-frequency component of a photomixed laser beam. Under sufficient density of two-dimensional (2D) conduction electrons (>10{sup 12} cm{sup -2}) and a moderate modulation index (the ratio of the density of photoexcited electrons to the initial density of the 2D electrons) we clearly observed the plasma-resonant peaks at 1.9 and 5.8 THz corresponding to the fundamental and third-harmonic resonance at room temperature, which is in good agreement with theory.

  13. The influence of the AlN barrier thickness on the polarization Coulomb field scattering in AlN/GaN heterostructure field-effect transistors

    SciTech Connect (OSTI)

    Lv, Yuanjie; Feng, Zhihong, E-mail: ga917vv@163.com; Gu, Guodong; Han, Tingting; Yin, Jiayun; Liu, Bo; Cai, Shujun [National Key Laboratory of Application Specific Integrated Circuit (ASIC), Hebei Semiconductor Research Institute, Shijiazhuang 050051 (China); Lin, Zhaojun; Ji, Ziwu; Zhao, Jingtao [School of Physics, Shandong University, Jinan 250100 (China)

    2014-07-14T23:59:59.000Z

    The electron mobility scattering mechanisms in AlN/GaN heterostuctures with 3?nm and 6?nm AlN barrier thicknesses were investigated by temperature-dependent Hall measurements. The effect of interface roughness (IFR) scattering on the electron mobility was found to be enhanced by increasing AlN barrier thickness. Moreover, using the measured capacitance-voltage and current-voltage characteristics of the fabricated heterostructure field-effect transistors (HFETs) with different Schottky areas on the two heterostuctures, the variations of electron mobility with different gate biases were investigated. Due to enhanced IFR scattering, the influence of polarization Coulomb field (PCF) scattering on electron mobility was found to decrease with increasing AlN barrier layer thickness. However, the PCF scattering remained an important scattering mechanism in the AlN/GaN HFETs.

  14. Selective epitaxial growth of monolithically integrated GaN-based light emitting diodes with AlGaN/GaN driving transistors

    SciTech Connect (OSTI)

    Liu, Zhaojun; Ma, Jun; Huang, Tongde; Liu, Chao; May Lau, Kei, E-mail: eekmlau@ust.hk [Photonics Technology Center, Department of Electronic and Computer Engineering, Hong Kong University of Science and Technology, Clear Water Bay, Kowloon (Hong Kong)

    2014-03-03T23:59:59.000Z

    In this Letter, we report selective epitaxial growth of monolithically integrated GaN-based light emitting diodes (LEDs) with AlGaN/GaN high-electron-mobility transistor (HEMT) drivers. A comparison of two integration schemes, selective epitaxial removal (SER), and selective epitaxial growth (SEG) was made. We found the SER resulted in serious degradation of the underlying LEDs in a HEMT-on-LED structure due to damage of the p-GaN surface. The problem was circumvented using the SEG that avoided plasma etching and minimized device degradation. The integrated HEMT-LEDs by SEG exhibited comparable characteristics as unintegrated devices and emitted modulated blue light by gate biasing.

  15. Negative quantum capacitance in graphene nanoribbons with lateral gates

    E-Print Network [OSTI]

    Florian, Libisch

    Negative quantum capacitance in graphene nanoribbons with lateral gates R. Reiter1, , U. Derra2 , S numerical simulations of the capacitive coupling between graphene nanoribbons of various widths and gate electrodes in different configurations. We compare the influence of lateral metallic or graphene side gate

  16. Entangling power and local invariants of two-qubit gates

    E-Print Network [OSTI]

    S Balakrishnan; R Sankaranarayanan

    2010-09-07T23:59:59.000Z

    We show a simple relation connecting entangling power and local invariants of two-qubit gates. From the relation, a general condition under which gates have same entangling power is arrived. The relation also helps in finding the lower bound of entangling power for perfect entanglers, from which the classification of gates as perfect and nonperfect entanglers is obtained in terms of local invariants.

  17. Entangling power and local invariants of two-qubit gates

    E-Print Network [OSTI]

    Balakrishnan, S

    2010-01-01T23:59:59.000Z

    We show a simple relation connecting entangling power and local invariants of two-qubit gates. From the relation, a general condition under which gates have same entangling power is arrived. The relation also helps to find the lower bound of entangling power for perfect entangler, from which a new classification of gates in terms of local invariants is obtained.

  18. Clustering of cyclic-nucleotide-gated channels in olfactory cilia

    E-Print Network [OSTI]

    French, Donald A.

    Clustering of cyclic-nucleotide-gated channels in olfactory cilia Richard J. Flannery* , Donald A channel clusters in olfactory cilia Key words: olfaction, receptor neuron, cyclic-nucleotide-gated channel of olfactory signal transduction, including a high density of cyclic-nucleotide-gated (CNG) channels. CNG

  19. Quantum Logic Gates using q-deformed Oscillators

    E-Print Network [OSTI]

    Debashis Gangopadhyay; Mahendra Nath Sinha Roy

    2006-07-14T23:59:59.000Z

    We show that the quantum logic gates, {\\it viz.} the single qubit Hadamard and Phase Shift gates, can also be realised using q-deformed angular momentum states constructed via the Jordan-Schwinger mechanism with two q-deformed oscillators. {\\it Keywords :} quantum logic gates ; q-deformed oscillators ; quantum computation {\\it PACS:} 03.67.Lx ; 02.20.Uw

  20. The gated community: residents' crime experience and perception of safety behind gates and fences in the urban area

    E-Print Network [OSTI]

    Kim, Suk Kyung

    2006-10-30T23:59:59.000Z

    ' perceptions of safety. Gated community residents reported a higher crime rate than nongated community residents. In addition to gates and fences that define apartment territory, such elements as patrol services, bright lighting, direct emergency buttons...

  1. Quantum gates via relativistic remote control

    E-Print Network [OSTI]

    Eduardo Martin-Martinez; Chris Sutherland

    2014-10-30T23:59:59.000Z

    We harness general relativistic effects to gain quantum control on a stationary qubit in an optical cavity by controlling the non-inertial motion of a different probe atom. Furthermore, we show that by considering relativistic trajectories of the probe, we enhance the efficiency of the quantum control. We explore the possible use of these relativistic techniques to build universal quantum gates.

  2. Electron density and currents of AlN/GaN high electron mobility transistors with thin GaN/AlN buffer layer

    SciTech Connect (OSTI)

    Bairamis, A.; Zervos, Ch.; Georgakilas, A., E-mail: alexandr@physics.uoc.gr [Microelectronics Research Group, IESL, Foundation for Research and Technology-Hellas (FORTH), P.O. Box 1385, GR-71110 Heraklion, Crete (Greece); Department of Physics, University of Crete, P.O. Box 2208, GR-71003 Heraklion, Crete (Greece); Adikimenakis, A.; Kostopoulos, A.; Kayambaki, M.; Tsagaraki, K.; Konstantinidis, G. [Microelectronics Research Group, IESL, Foundation for Research and Technology-Hellas (FORTH), P.O. Box 1385, GR-71110 Heraklion, Crete (Greece)

    2014-09-15T23:59:59.000Z

    AlN/GaN high electron mobility transistor (HEMT) structures with thin GaN/AlN buffer layer have been analyzed theoretically and experimentally, and the effects of the AlN barrier and GaN buffer layer thicknesses on two-dimensional electron gas (2DEG) density and transport properties have been evaluated. HEMT structures consisting of [300?nm GaN/ 200?nm AlN] buffer layer on sapphire were grown by plasma-assisted molecular beam epitaxy and exhibited a remarkable agreement with the theoretical calculations, suggesting a negligible influence of the crystalline defects that increase near the heteroepitaxial interface. The 2DEG density varied from 6.8?×?10{sup 12} to 2.1 × 10{sup 13} cm{sup ?2} as the AlN barrier thickness increased from 2.2 to 4.5?nm, while a 4.5?nm AlN barrier would result to 3.1?×?10{sup 13} cm{sup ?2} on a GaN buffer layer. The 3.0?nm AlN barrier structure exhibited the highest 2DEG mobility of 900?cm{sup 2}/Vs for a density of 1.3?×?10{sup 13} cm{sup ?2}. The results were also confirmed by the performance of 1??m gate-length transistors. The scaling of AlN barrier thickness from 1.5?nm to 4.5?nm could modify the drain-source saturation current, for zero gate-source voltage, from zero (normally off condition) to 0.63?A/mm. The maximum drain-source current was 1.1?A/mm for AlN barrier thickness of 3.0?nm and 3.7?nm, and the maximum extrinsic transconductance was 320 mS/mm for 3.0?nm AlN barrier.

  3. Group-III nitride based high electron mobility transistor (HEMT) with barrier/spacer layer

    DOE Patents [OSTI]

    Chavarkar, Prashant; Smorchkova, Ioulia P.; Keller, Stacia; Mishra, Umesh; Walukiewicz, Wladyslaw; Wu, Yifeng

    2005-02-01T23:59:59.000Z

    A Group III nitride based high electron mobility transistors (HEMT) is disclosed that provides improved high frequency performance. One embodiment of the HEMT comprises a GaN buffer layer, with an Al.sub.y Ga.sub.1-y N (y=1 or y 1) layer on the GaN buffer layer. An Al.sub.x Ga.sub.1-x N (0.ltoreq.x.ltoreq.0.5) barrier layer on to the Al.sub.y Ga.sub.1-y N layer, opposite the GaN buffer layer, Al.sub.y Ga.sub.1-y N layer having a higher Al concentration than that of the Al.sub.x Ga.sub.1-x N barrier layer. A preferred Al.sub.y Ga.sub.1-y N layer has y=1 or y.about.1 and a preferred Al.sub.x Ga.sub.1-x N barrier layer has 0.ltoreq.x.ltoreq.0.5. A 2DEG forms at the interface between the GaN buffer layer and the Al.sub.y Ga.sub.1-y N layer. Respective source, drain and gate contacts are formed on the Al.sub.x Ga.sub.1-x N barrier layer. The HEMT can also comprising a substrate adjacent to the buffer layer, opposite the Al.sub.y Ga.sub.1-y N layer and a nucleation layer between the Al.sub.x Ga.sub.1-x N buffer layer and the substrate.

  4. High-frequency performance of graphene field effect transistors with saturating IV-characteristics

    E-Print Network [OSTI]

    Kim, Philip

    reported for top-gated (a) (b) Figure 1. GFET device structure. (a) Schematic illustration of the back, 6]. The GFETs characterized here are created with a back gate as shown in Fig. 1a. A split-beam patterning of source and drain contacts with approximately 50-nm gate- to-source and gate-to-drain spacings

  5. Characterizing the geometrical edges of nonlocal two-qubit gates

    E-Print Network [OSTI]

    S. Balakrishnan; R. Sankaranarayanan

    2009-05-30T23:59:59.000Z

    Nonlocal two-qubit gates are geometrically represented by tetrahedron known as Weyl chamber within which perfect entanglers form a polyhedron. We identify that all edges of the Weyl chamber and polyhedron are formed by single parametric gates. Nonlocal attributes of these edges are characterized using entangling power and local invariants. In particular, SWAP (power)alpha family of gates constitutes one edge of the Weyl chamber with SWAP-1/2 being the only perfect entangler. Finally, optimal constructions of controlled-NOT using SWAP-1/2 gate and gates belong to three edges of the polyhedron are presented.

  6. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 29, NO. 9, SEPTEMBER 2010 1409 Gate-Sizing-Based Single Vdd Test for Bridge

    E-Print Network [OSTI]

    Chakrabarty, Krishnendu

    complementary metal- oxide-semiconductor and can constitute 50% or more, of total defect count [1]. A bridge, SEPTEMBER 2010 1409 Gate-Sizing-Based Single Vdd Test for Bridge Defects in Multivoltage Designs Saqib design technique. Recent research has shown that testing for resistive bridging faults in such designs

  7. A Bio-Polymer Transistor: Electrical Amplification by Microtubules

    E-Print Network [OSTI]

    Avner Priel; Arnolt J. Ramos; Jack A. Tuszynski; Horacio F. Cantiello

    2006-06-09T23:59:59.000Z

    Microtubules (MTs) are important cytoskeletal structures, engaged in a number of specific cellular activities, including vesicular traffic, cell cyto-architecture and motility, cell division, and information processing within neuronal processes. MTs have also been implicated in higher neuronal functions, including memory, and the emergence of "consciousness". How MTs handle and process electrical information, however, is heretofore unknown. Here we show new electrodynamic properties of MTs. Isolated, taxol-stabilized microtubules behave as bio-molecular transistors capable of amplifying electrical information. Electrical amplification by MTs can lead to the enhancement of dynamic information, and processivity in neurons can be conceptualized as an "ionic-based" transistor, which may impact among other known functions, neuronal computational capabilities.

  8. Classification of transversal gates in qubit stabilizer codes

    E-Print Network [OSTI]

    Jonas T. Anderson; Tomas Jochym-O'Connor

    2014-09-29T23:59:59.000Z

    This work classifies the set of diagonal gates that can implement a single or two-qubit transversal logical gate for qubit stabilizer codes. We show that individual physical gates on the underlying qubits that compose the code are restricted to have entries of the form $e^{i \\pi c/2^k}$ along their diagonal, resulting in a similarly restricted class of logical gates that can be implemented in this manner. Moreover, we show that all diagonal logical gates that can be implemented transversally by individual physical diagonal gates must belong to the Clifford hierarchy. Furthermore, we can use this result to prove a conjecture about transversal gates made by Zeng et al. in 2007.

  9. Bottom-up graphene nanoribbon field-effect transistors

    SciTech Connect (OSTI)

    Bennett, Patrick B. [Applied Science and Technology, University of California, Berkeley, California 94720 (United States) [Applied Science and Technology, University of California, Berkeley, California 94720 (United States); Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, California 94720 (United States); Pedramrazi, Zahra [Department of Physics, University of California, Berkeley, California 94720 (United States)] [Department of Physics, University of California, Berkeley, California 94720 (United States); Madani, Ali [Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, California 94720 (United States)] [Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, California 94720 (United States); Chen, Yen-Chia; Crommie, Michael F. [Department of Physics, University of California, Berkeley, California 94720 (United States) [Department of Physics, University of California, Berkeley, California 94720 (United States); Materials Sciences Division, Lawrence Berkeley National Laboratories, Berkeley, California 94720 (United States); Oteyza, Dimas G. de [Department of Physics, University of California, Berkeley, California 94720 (United States) [Department of Physics, University of California, Berkeley, California 94720 (United States); Centro de Física de Materiales CSIC/UPV-EHU-Materials Physics Center, San Sebastián E-20018 (Spain); Chen, Chen [Department of Chemistry, University of California, Berkeley, California 94720 (United States)] [Department of Chemistry, University of California, Berkeley, California 94720 (United States); Fischer, Felix R. [Department of Chemistry, University of California, Berkeley, California 94720 (United States) [Department of Chemistry, University of California, Berkeley, California 94720 (United States); Materials Sciences Division, Lawrence Berkeley National Laboratories, Berkeley, California 94720 (United States); Bokor, Jeffrey, E-mail: jbokor@eecs.berkeley.edu [Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, California 94720 (United States) [Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, California 94720 (United States); Materials Sciences Division, Lawrence Berkeley National Laboratories, Berkeley, California 94720 (United States)

    2013-12-16T23:59:59.000Z

    Recently developed processes have enabled bottom-up chemical synthesis of graphene nanoribbons (GNRs) with precise atomic structure. These GNRs are ideal candidates for electronic devices because of their uniformity, extremely narrow width below 1?nm, atomically perfect edge structure, and desirable electronic properties. Here, we demonstrate nano-scale chemically synthesized GNR field-effect transistors, made possible by development of a reliable layer transfer process. We observe strong environmental sensitivity and unique transport behavior characteristic of sub-1?nm width GNRs.

  10. Scaling of SiGe Heterojunction Bipolar Transistors

    E-Print Network [OSTI]

    Rieh, Jae-Sung

    Scaling of SiGe Heterojunction Bipolar Transistors JAE-SUNG RIEH, SENIOR MEMBER, IEEE, DAVID-century. This paper inves- tigates the impacts of scaling on SiGe heterojunction bipolar tran- sistors (HBTs), which), epitaxial-base Si BJTs (Epi Si BJT), SiGe HBTs (SiGe HBT), and SiGe HBTs with carbon-doped base (SiGeC HBT

  11. Reliable strain measurement in transistor arrays by robust scanning transmission electron microscopy

    SciTech Connect (OSTI)

    Kim, Suhyun; Kim, Joong Jung; Jung, Younheum; Lee, Kyungwoo; Byun, Gwangsun; Hwang, KyoungHwan; Lee, Sunyoung; Lee, Kyupil [Memory Analysis Science and Engineering Group, Samsung Electronics, San 16, Hwasung City, Gyeonggi-Do 445-701 (Korea, Republic of)] [Memory Analysis Science and Engineering Group, Samsung Electronics, San 16, Hwasung City, Gyeonggi-Do 445-701 (Korea, Republic of)

    2013-09-15T23:59:59.000Z

    Accurate measurement of the strain field in the channels of transistor arrays is critical for strain engineering in modern electronic devices. We applied atomic-resolution high-angle annular dark-field scanning transmission electron microscopy to quantitative measurement of the strain field in transistor arrays. The quantitative strain profile over 20 transistors was obtained with high reliability and a precision of 0.1%. The strain field was found to form homogeneously in the channels of the transistor arrays. Furthermore, strain relaxation due to the thin foil effect was quantitatively investigated for thicknesses of 35 to 275 nm.

  12. Transistor-based filter for inhibiting load noise from entering a power supply

    DOE Patents [OSTI]

    Taubman, Matthew S

    2013-07-02T23:59:59.000Z

    A transistor-based filter for inhibiting load noise from entering a power supply is disclosed. The filter includes a first transistor having an emitter coupled to a power supply, a collector coupled to a load, and a base. The filter also includes a first capacitor coupled between the base of the first transistor and a ground terminal. The filter further includes an impedance coupled between the base and a node between the collector and the load, or a second transistor and second capacitor. The impedance can be a resistor or an inductor.

  13. Rational Design and Preparation of Organic Semiconductors for use in Field Effect Transistors and Photovoltaic Cells

    E-Print Network [OSTI]

    Mauldin, Clayton Edward

    2010-01-01T23:59:59.000Z

    in thin film organic photovoltaic cells (OPVs) is presented.efficient organic photovoltaic cells with power conversionEffect Transistors and Photovoltaic Cells By Clayton Edward

  14. Method for voltage-gated protein fractionation

    DOE Patents [OSTI]

    Hatch, Anson (Tracy, CA); Singh, Anup K. (Danville, CA)

    2012-04-24T23:59:59.000Z

    We report unique findings on the voltage dependence of protein exclusion from the pores of nanoporous polymer exclusion membranes. The pores are small enough that proteins are excluded from passage with low applied electric fields, but increasing the field enables proteins to pass through. The requisite field necessary for a change in exclusion is protein-specific with a correlation to protein size. The field-dependence of exclusion is important to consider for preconcentration applications. The ability to selectively gate proteins at exclusion membranes is also a promising means for manipulating and characterizing proteins. We show that field-gated exclusion can be used to selectively remove proteins from a mixture, or to selectively trap protein at one exclusion membrane in a series.

  15. Investigation of buffer traps in AlGaN/GaN-on-Si devices by thermally stimulated current spectroscopy and back-gating measurement

    SciTech Connect (OSTI)

    Yang, Shu; Zhou, Chunhua; Jiang, Qimeng; Chen, Kevin J., E-mail: eekjchen@ust.hk [Department of Electronic and Computer Engineering, The Hong Kong University of Science and Technology, Clear Water Bay, Kowloon (Hong Kong); Lu, Jianbiao; Huang, Baoling [Department of Mechanical and Aerospace Engineering, The Hong Kong University of Science and Technology, Clear Water Bay, Kowloon (Hong Kong)] [Department of Mechanical and Aerospace Engineering, The Hong Kong University of Science and Technology, Clear Water Bay, Kowloon (Hong Kong)

    2014-01-06T23:59:59.000Z

    Thermally stimulated current (TSC) spectroscopy and high-voltage back-gating measurement are utilized to study GaN buffer traps specific to AlGaN/GaN lateral heterojunction structures grown on a low-resistivity Si substrate. Three dominating deep-level traps in GaN buffer with activation energies of ?E{sub T1}???0.54?eV, ?E{sub T2}???0.65?eV, and ?E{sub T3}???0.75?eV are extracted from TSC spectroscopy in a vertical GaN-on-Si structure. High back-gate bias applied to the Si substrate could influence the drain current in an AlGaN/GaN-on-Si high-electron-mobility transistor in a way that cannot be explained with a simple field-effect model. By correlating the trap states identified in TSC with the back-gating measurement results, it is proposed that the ionization/deionization of both donor and acceptor traps are responsible for the generation of buffer space charges, which impose additional modulation to the 2DEG channel.

  16. A laser-programmable gate array

    E-Print Network [OSTI]

    Gullette, James Benjamin

    1985-01-01T23:59:59.000Z

    was investigated. A novel approach to the personalization of digital NMOS semicustom devices using laser re- structuring techinques was developed to expand the capabilities of current devices. A laser-programmable device offers logic designers an alternative... are determined the metal mask is designed and the final product is produced by completing the metallizat, ion on the preprocessed chips. B. Trade-ops Gate arrays have many advantages over fully custom integrated circuits 11''. This semicustom approach...

  17. The effect of Ta doping in polycrystalline TiO{sub x} and the associated thin film transistor properties

    SciTech Connect (OSTI)

    Ok, Kyung-Chul, E-mail: kchul2926@naver.com; Park, Yoseb, E-mail: jozeph.park@gmail.com; Park, Jin-Seong, E-mail: kbchung@dankook.ac.kr, E-mail: jsparklime@hanyang.ac.kr [Division of Materials Science and Engineering, Hanyang University, 222 Wangsimni-ro, Seongdong-gu, Seoul 133-791 (Korea, Republic of)] [Division of Materials Science and Engineering, Hanyang University, 222 Wangsimni-ro, Seongdong-gu, Seoul 133-791 (Korea, Republic of); Chung, Kwun-Bum, E-mail: kbchung@dankook.ac.kr, E-mail: jsparklime@hanyang.ac.kr [Department of Physics, Dankook University, 119 Dandae-ro, Dongnam-gu, Cheonan 330-714 (Korea, Republic of)] [Department of Physics, Dankook University, 119 Dandae-ro, Dongnam-gu, Cheonan 330-714 (Korea, Republic of)

    2013-11-18T23:59:59.000Z

    Tantalum (Ta) is suggested to act as an electron donor and crystal phase stabilizer in titanium oxide (TiO{sub x}). A transition occurs from an amorphous state to a crystalline phase at an annealing temperature above 300?°C in a vacuum ambient. As the annealing temperature increases from 300?°C to 450?°C, the mobility increases drastically from 0.07 cm{sup 2}/Vs to 0.61 cm{sup 2}/Vs. The remarkable enhancement of thin film transistor performance is suggested to be due to the splitting of Ti 3d band orbitals as well as the increase in Ta{sup 5+} ions that can act as electron donors.

  18. High-mobility, air stable bottom-contact n-channel thin film transistors based on N,N?-ditridecyl perylene diimide

    SciTech Connect (OSTI)

    Ma, Lanchao [Beijing National Laboratory for Molecular Sciences, CAS Key Laboratory of Organic Solids, Institute of Chemistry, Chinese Academy of Sciences, Beijing 100190 (China) [Beijing National Laboratory for Molecular Sciences, CAS Key Laboratory of Organic Solids, Institute of Chemistry, Chinese Academy of Sciences, Beijing 100190 (China); University of Chinese Academy of Sciences, Beijing 100049 (China); Guo, Yunlong; Wen, Yugeng; Liu, Yunqi, E-mail: xwzhan@iccas.ac.cn, E-mail: liuyq@iccas.ac.cn [Beijing National Laboratory for Molecular Sciences, CAS Key Laboratory of Organic Solids, Institute of Chemistry, Chinese Academy of Sciences, Beijing 100190 (China)] [Beijing National Laboratory for Molecular Sciences, CAS Key Laboratory of Organic Solids, Institute of Chemistry, Chinese Academy of Sciences, Beijing 100190 (China); Zhan, Xiaowei, E-mail: xwzhan@iccas.ac.cn, E-mail: liuyq@iccas.ac.cn [Beijing National Laboratory for Molecular Sciences, CAS Key Laboratory of Organic Solids, Institute of Chemistry, Chinese Academy of Sciences, Beijing 100190 (China) [Beijing National Laboratory for Molecular Sciences, CAS Key Laboratory of Organic Solids, Institute of Chemistry, Chinese Academy of Sciences, Beijing 100190 (China); Department of Materials Science and Engineering, College of Engineering, Peking University, Beijing 100871 (China)

    2013-11-11T23:59:59.000Z

    Bottom-gate bottom-contact (BGBC) organic thin film transistors (OTFTs) based on N,N?-ditridecyl perylene diimide exhibit electron mobility as high as 3.54?cm{sup 2}?V{sup ?1}?s{sup ?1} in nitrogen, higher than that (1?cm{sup 2} V{sup ?1}?s{sup ?1}) of bottom-gate top-contact devices. The better performance of BGBC configuration in N{sub 2} is attributed to lower contact resistance, which is further reduced by thermal annealing. After thermally annealing the BGBC OTFTs at 180?°C, electron mobility as high as 3.5?cm{sup 2}?V{sup ?1}?s{sup ?1}, current on/off ratio of 10{sup 6} and threshold voltage of 9?V are achieved in air, and the mobility retains above 1?cm{sup 2}?V{sup ?1}?s{sup ?1} after storage for two months in air. Thermal treatment enhanced crystalline grains, reduced grain boundaries, and suppressed the adsorption of H{sub 2}O and O{sub 2}, leading to excellent performance in air.

  19. First principles analysis of the initial oxidation of Si(001) and Si(111) surfaces terminated with H and CH3

    E-Print Network [OSTI]

    Wu, Zhigang

    ) Positive or negative gain: Role of thermal capture cross sections in impurity photovoltaic effect J. Appl in photovoltaics and micro-electronics research for over half a century. For example, precise control in metal-oxide semiconductor field effect transistors.1 In solar cells composed of crystalline Si, post

  20. Photovoltaic transistors based on a steady-state internal polarization effect in asymmetric semiconductor superlattices

    E-Print Network [OSTI]

    Luryi, Serge

    Photovoltaic transistors based on a steady-state internal polarization effect in asymmetric that a modified structure can generate a steady-state photovoltage. We then propose a new class of photovoltaic novelty is such a photovoltaic transistor (PVT) aspect. Our idea of the PVT arises from the well known

  1. Highly Stable Hysteresis-Free Carbon Nanotube Thin-Film Transistors by Fluorocarbon Polymer Encapsulation

    E-Print Network [OSTI]

    Javey, Ali

    Highly Stable Hysteresis-Free Carbon Nanotube Thin-Film Transistors by Fluorocarbon Polymer report hysteresis-free carbon nanotube thin-film transistors (CNT-TFTs) employing a fluorocarbon polymer (Teflon-AF) as an encapsulation layer. Such fluorocarbon encapsulation improves device uniformity

  2. Evaluation of the Radiation Tolerance of SiGe Heterojunction Bipolar Transistors Under

    E-Print Network [OSTI]

    California at Santa Cruz, University of

    in a modified 5HP process. The current gain as a function of collector current has been measured at several and for signal- level discrimination. We will discuss the behavior of both kinds of transistors bipolar transistors manufactured in a modified 5HP process, taken before and after irradiation at fluences

  3. Graphene Transistors Fabricated via Transfer-Printing In Device Active-Areas

    E-Print Network [OSTI]

    Graphene Transistors Fabricated via Transfer-Printing In Device Active-Areas on Large Wafer Xiaogan graphene islands from a graphite and then uses transfer printing to place the islands from the stamp from the printed graphene. The transistors show a hole and electron mobility of 3735 and 795 cm2/V

  4. Base-contact proximity effects in bipolar transistors with nitride-spacer technology

    E-Print Network [OSTI]

    Technische Universiteit Delft

    -lithographic dimensions. For example, in the double polysilicon bipolar transistor, spacers are used to separate the baseBase-contact proximity effects in bipolar transistors with nitride-spacer technology Henk van Zeijl-BJT's with spacer separated Al/Si emitter and base contacts are fabricated and characterized. Due to the proximity

  5. Photoconduction studies on GaN nanowire transistors under UV and polarized UV illumination

    E-Print Network [OSTI]

    Zhou, Chongwu

    Photoconduction studies on GaN nanowire transistors under UV and polarized UV illumination Song Han carried out with single crystal GaN nanowires. The nanowire transistors exhibited a sub- stantial increase was demonstrated and studied for GaN nanowires working as polarized UV detectors. The nanowire conductance varied

  6. Vertical design of cubic GaN-based high electron mobility transistors R. Granzner,1,a)

    E-Print Network [OSTI]

    As, Donat Josef

    Vertical design of cubic GaN-based high electron mobility transistors R. Granzner,1,a) E. Tschumak 2011; accepted 24 October 2011; published online 1 December 2011) Cubic (zinc blende) AlGaN=GaN heterostructures for application in GaN-based high electron mobility transistors are investigated theoretically

  7. Hybrid single-electron transistor as a source of quantized electric current

    E-Print Network [OSTI]

    Loss, Daniel

    system is that hybrid tunnel junctions suppress tunnelling in an energy range determined by the gapLETTERS Hybrid single-electron transistor as a source of quantized electric current JUKKA P. PEKOLA of a hybrid normal-metal­ superconductor turnstile in the form of a one-island single- electron transistor

  8. Self-aligned AlGaN/GaN transistors for sub-mm wave applications

    E-Print Network [OSTI]

    Saadat, Omair I

    2010-01-01T23:59:59.000Z

    This thesis describes work done towards realizing self-aligned AlGaN/GaN high electron mobility transistors (HEMTs). Self-aligned transistors are important for improving the frequency of AlGaN/GaN HEMTs by reducing source ...

  9. Measures of operator entanglement of two-qubit gates

    E-Print Network [OSTI]

    Balakrishnan, S

    2011-01-01T23:59:59.000Z

    Two different measures of operator entanglement of two-qubit gates, namely, Schmidt strength and linear entropy, are studied. While these measures are shown to have one-to-one relation between them for Schmidt number 2 class of gates, no such relation exists for Schmidt number 4 class, implying that the measures are inequivalent in general. Further, we establish a simple relation between linear entropy and local invariants of two-qubit gates. The implication of the relation is discussed.

  10. Classification of nonlocal two-qubit gates using Schmidt number

    E-Print Network [OSTI]

    S Balakrishnan; Leona J Felicia; R Sankaranarayanan

    2010-03-31T23:59:59.000Z

    It is known from Schmidt decomposition that Schmidt number of nonlocal two-qubit quantum gates is 2 or 4. We identify conditions on geometrical points of a gate to have Schmidt number 2. A simple analysis reveals that Schmidt number 2 corresponds to controlled unitary gates with CNOT being the only perfect entangler. Further, it is shown that Schmidt strength and entangling power are maximum only for CNOT in the controlled unitary family.

  11. Classification of nonlocal two-qubit gates using Schmidt number

    E-Print Network [OSTI]

    Balakrishnan, S; Sankaranarayanan, R

    2009-01-01T23:59:59.000Z

    It is known from Schmidt decomposition that Schmidt number of nonlocal two-qubit quantum gates is 2 or 4. We identify conditions on geometrical points of a gate to have Schmidt number 2. A simple analysis reveals that Schmidt number 2 corresponds to controlled unitary gates with CNOT being the only perfect entangler. Further, it is shown that Schmidt strength and entangling power are maximum only for CNOT in the controlled unitary family.

  12. Measures of operator entanglement of two-qubit gates

    E-Print Network [OSTI]

    S. Balakrishnan; R. Sankaranarayanan

    2011-06-21T23:59:59.000Z

    Two different measures of operator entanglement of two-qubit gates, namely, Schmidt strength and linear entropy, are studied. While these measures are shown to have one-to-one relation between them for Schmidt number 2 class of gates, no such relation exists for Schmidt number 4 class, implying that the measures are inequivalent in general. Further, we establish a simple relation between linear entropy and local invariants of two-qubit gates. The implication of the relation is discussed.

  13. Testing tri-state and pass transistor circuit structures

    E-Print Network [OSTI]

    Parikh, Shaishav Shailesh

    2005-11-01T23:59:59.000Z

    will cause some lines in the circuit to float and take unknown values. A stuck-on control line can cause fighting when the two drivers connected to the same node drive different values. This thesis develops new gate level fault models and dynamic test...

  14. PIA - Savannah River Nuclear Solution (SRNS) MedGate Occupational...

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    (OHS) (Includes the Drug and Alcohol Testing System (Assistant)) PIA - Savannah River Nuclear Solution (SRNS) MedGate Occupational Health and Safety Medical System (OHS)...

  15. Quantifying Cradle-to-Farm Gate Life Cycle Impacts Associated...

    Energy Savers [EERE]

    Life Cycle Impacts Associated with Fertilizer used for Corn, Soybean, and Stover Production Quantifying Cradle-to-Farm Gate Life Cycle Impacts Associated with Fertilizer used...

  16. GATE Center of Excellence at UAB in Lightweight Materials for...

    Broader source: Energy.gov (indexed) [DOE]

    February 28, 2008 GATE Center of Excellence at UAB in Lightweight Materials for Automotive Applications Uday Vaidya (Principal Investigator) & J. Barry Andrews (Project Director)...

  17. An elementary optical gate for expanding entanglement web

    E-Print Network [OSTI]

    Toshiyuki Tashima; Sahin Kaya Ozdemir; Takashi Yamamoto; Masato Koashi; Nobuyuki Imoto

    2008-03-13T23:59:59.000Z

    We introduce an elementary optical gate for expanding polarization entangled W states, in which every pair of photons are entangled alike. The gate is composed of a pair of 50:50 beamsplitters and ancillary photons in the two-photon Fock state. By seeding one of the photons in an $n$-photon W state into this gate, we obtain an $(n+2)$-photon W state after post-selection. This gate gives a better efficiency and a simpler implementation than previous proposals for $\\rm W$-state preparation.

  18. Optical Determination of Gate--Tunable Bandgap in Bilayer Graphene

    E-Print Network [OSTI]

    Zhang, Yuanbo

    2010-01-01T23:59:59.000Z

    Tunable Bandgap in Bilayer Graphene Yuanbo Zhang* 1 , Tsung-gate-tunable bandgap in graphene bilayers with magnitude asbands. In two- dimensional graphene bilayers this bandgap

  19. Vehicle Technologies Office Merit Review 2014: GATE Center of...

    Broader source: Energy.gov (indexed) [DOE]

    GATE Center of Excellence at UAB for Lightweight Materials and Manufacturing for Automotive, Truck and Mass Transit. lm081vaidya2014o.pdf More Documents & Publications...

  20. GATE Center of Excellence at UAB for Lightweight Materials and...

    Broader source: Energy.gov (indexed) [DOE]

    at UAB for Lightweight Materials and Manufacturing for Automotive, Truck and Mass Transit GATE Center of Excellence at UAB for Lightweight Materials and Manufacturing for...

  1. Penn State DOE Graduate Automotive Technology Education (Gate...

    Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

    State DOE Graduate Automotive Technology Education (Gate) Program for In-Vehicle, High-Power Energy Storage Systems Penn State DOE Graduate Automotive Technology Education...

  2. Gate Fidelities, Quantum Broadcasting, and Assessing Experimental Realization

    E-Print Network [OSTI]

    Hyang-Tag Lim; Young-Sik Ra; Yong-Su Kim; Yoon-Ho Kim; Joonwoo Bae

    2011-06-29T23:59:59.000Z

    We relate gate fidelities of experimentally realized quantum operations to the broadcasting property of their ideal operations, and show that the more parties a given quantum operation can broadcast to, the higher gate fidelities of its experimental realization are in general. This is shown by establishing the correspondence between two operational quantities, quantum state shareability and quantum broadcasting. This suggests that, to assess an experimental realization using gate fidelities, the worst case of realization such as noisy operations should be taken into account and then compared to obtained gate fidelities. In addition, based on the correspondence, we also translate results in quantum state shareability to their counterparts in quantum operations.

  3. An overview of the gate and panel industry

    E-Print Network [OSTI]

    Fisher, C. West

    2000-01-01T23:59:59.000Z

    OF CONTENTS I. Introduction II. Market Review lll Critical Factors IV. Gate and Panel Fvaluation A Table 1. Light Duty Gate B. Table 2. Medium Duty Gate C. Table 3. Heavy Duty Gate D. Table 4 Light Duty Panel B Table 5. Medium Duty Panel R Table 6... of their cost and convience. MARKET REVIEW There are a multitude of companies that manufacture portable handling facilities from the basic panel components to complete corral layouts. Just like with cattle breeds, there are a wide variety of manufactured...

  4. High-current, fast-switching transistor development

    SciTech Connect (OSTI)

    Hower, P.L.

    1981-03-15T23:59:59.000Z

    Work that shows how the results obtained under a previous contract (NAS3-18916) have been applied to a larger-diameter (33-mm) transistor are described. An improved base contact for equalizing the base-emitter voltage at high currents has been developed along with an improved emitter contact preform which increases the silicon area available for current conduction. The electrical performance achieved is consistent with the proposed optimum design. The device design, wafer-processing techniques, and various measurements which include forward SOA, dc characteristics, and switching times are described.

  5. Gate-teleportation-based blind quantum computation

    E-Print Network [OSTI]

    Mear M. R. Koochakie

    2014-12-25T23:59:59.000Z

    Blind quantum computation (BQC) is a model in which a computation is performed on a server by a client such that the server is kept blind about the input, the algorithm, and the output of the computation. Here we layout a general framework for BQC which, unlike the previous BQC models, does not constructed on specific computational model. A main ingredient of our construction is gate teleportation. We demonstrate that our framework can be straightforwardly implemented on circuit-based models as well as measurement-based models of quantum computation. We illustrate our construction by showing that universal BQC is possible on correlation-space measurement-based quantum computation models.

  6. Gates, Oregon: Energy Resources | Open Energy Information

    Open Energy Info (EERE)

    AFDC Printable Version Share this resource Send a link to EERE: Alternative Fuels Data Center Home Page to someone by E-mail Share EERE: Alternative Fuels Data Center Home Page on Facebook Tweet about EERE: Alternative Fuels Data Center Home Page on Twitter Bookmark EERE: Alternative Fuels Data Center Home Page onYou are now leaving Energy.gov You are now leaving Energy.gov You are8COaBulkTransmissionSitingProcess.pdf Jump1946865°,Park, Texas: EnergyGarvin County,|GasconadeOhio: EnergyGates,

  7. Gallium phosphide high-temperature bipolar junction transistor

    SciTech Connect (OSTI)

    Zipperian, T.E.; Dawson, L.R.; Caffin, R.J.

    1981-03-01T23:59:59.000Z

    Preliminary results are reported on the development of a high-temperature (> 350/sup 0/C) gallium phosphide bipolar junction transistor (BJT) for goethermal and other energy applications. This four-layer p/sup +/n/sup -/pp/sup +/ structure was fromed by liquid phase epitaxy using a supercooling technique to insure uniform nucleation of the thin layers. Magnesium was used as the p-type dopant to avoid excessive out-diffusion into the lightly doped base. By appropriate choice of electrodes, the device may also be driven as an n-channel junction field-effect transistor. The gallium phosphide BJT is observed to have a common-emitter current gain peaking in the range of 6 to 10 (for temperatures from 20/sup 0/C to 400/sup 0/C) and a room-temperature, punchthrough-limited, collector-emitter breakdown voltage of approximately -6V. Other parameters of interest include an f/sub/ = 400 KHz (at 20/sup 0/C) and a collector base leakage current = 200 ..mu..A (at 350/sup 0/C).

  8. Analysis of local carrier modulation in InAs semiconductor nanowire transistors

    E-Print Network [OSTI]

    Wang, Deli

    , and drain compared with that of back gate. Com- pared to a surrounding-gate geometry, a top-gate structure as a function of probe tip position, at both high and low drain bias, reveal that carrier and current modulation is strongest when the probe tip is near the source and drain nanowire contacts, and decreases at greater tip

  9. An FPGA Architecture Supporting Dynamically Controlled Power Gating

    E-Print Network [OSTI]

    Wilton, Steve

    An FPGA Architecture Supporting Dynamically Controlled Power Gating Assem A. M. Bsoul 1 and Steven at reducing leakage power. However, previous techniques focus on statically- controlled power gating. In this paper, we propose a modification to the fabric of an FPGA that enables dynamically-controlled power

  10. DEFINITION OF MOTIONLESS PHASES FOR MONITORING GATED RECONSTRUCTION

    E-Print Network [OSTI]

    Boyer, Edmond

    of gating signals that are generated from an abdominal pressure variation signal. This method is considering at the beginning of steady phase of studied organs Objectives Study Protocol Abdominal pressure signal and Gating Average period of pressure variation µ0 = 770, 86 ms Standard deviation 10 = 72,25 ms : High value due

  11. University of Illinois at Urbana Champaigns GATE Center forAdvanced...

    Energy Savers [EERE]

    of Illinois at Urbana Champaigns GATE Center forAdvanced Automotive Bio-Fuel Combustion Engines University of Illinois at Urbana Champaigns GATE Center forAdvanced...

  12. University of Illinois at Urbana-Champaigns GATE Center for...

    Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

    Urbana-Champaigns GATE Center for Advanced Automotive Bio-Fuel Combustion Engines University of Illinois at Urbana-Champaigns GATE Center for Advanced Automotive Bio-Fuel...

  13. US DOE Sponsored Graduate Automotive Technology Education (GATE) Program at Penn State Emphasizing

    E-Print Network [OSTI]

    Lee, Dongwon

    US DOE Sponsored Graduate Automotive Technology Education (GATE) Program at Penn State Emphasizing in the automotive industry and academia. Develop relationships between GATE students, faculty, employers

  14. Low frequency noise in GaN metal semiconductor and metal oxide semiconductor field effect transistors

    E-Print Network [OSTI]

    Pala, Nezih

    , and Systems Engineering and Center for Integrated Electronics and Electronics Manufacturing, CII 9017, University of South Carolina, Columbia, South Carolina 29208 Received 22 January 2001; accepted American Institute of Physics. DOI: 10.1063/1.1372364 I. INTRODUCTION A recent report on GaN highly doped

  15. Influence of an anomalous dimension effect on thermal instability in amorphous-InGaZnO thin-film transistors

    SciTech Connect (OSTI)

    Liu, Kuan-Hsien; Chou, Wu-Ching, E-mail: tcchang3708@gmail.com, E-mail: wuchingchou@mail.nctu.edu.tw [Department of Electrophysics, National Chiao Tung University, Hsin-chu 300, Taiwan (China); Chang, Ting-Chang, E-mail: tcchang3708@gmail.com, E-mail: wuchingchou@mail.nctu.edu.tw [Department of Physics, National Sun Yat-Sen University, Kaohsiung 804, Taiwan (China); Advanced Optoelectronics Technology Center, National Cheng Kung University, Taiwan (China); Chen, Hua-Mao; Tai, Ya-Hsiang [Department of Photonics and Institute of Electro-Optical Engineering, National Chiao Tung University, Hsin-chu 300, Taiwan (China); Tsai, Ming-Yen; Hung, Pei-Hua; Chu, Ann-Kuo [Department of Photonics, National Sun Yat-Sen University, Kaohsiung 804, Taiwan (China); Wu, Ming-Siou; Hung, Yi-Syuan [Department of Electronics Engineering, National Chiao Tung University, Hsin-Chu 300, Taiwan (China); Hsieh, Tien-Yu [Department of Physics, National Sun Yat-Sen University, Kaohsiung 804, Taiwan (China); Yeh, Bo-Liang [Advanced Display Technology Research Center, AU Optronics, No.1, Li-Hsin Rd. 2, Hsinchu Science Park, Hsin-Chu 30078, Taiwan (China)

    2014-10-21T23:59:59.000Z

    This paper investigates abnormal dimension-dependent thermal instability in amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors. Device dimension should theoretically have no effects on threshold voltage, except for in short channel devices. Unlike short channel drain-induced source barrier lowering effect, threshold voltage increases with increasing drain voltage. Furthermore, for devices with either a relatively large channel width or a short channel length, the output drain current decreases instead of saturating with an increase in drain voltage. Moreover, the wider the channel and the shorter the channel length, the larger the threshold voltage and output on-state current degradation that is observed. Because of the surrounding oxide and other thermal insulating material and the low thermal conductivity of the IGZO layer, the self-heating effect will be pronounced in wider/shorter channel length devices and those with a larger operating drain bias. To further clarify the physical mechanism, fast I{sub D}-V{sub G} and modulated peak/base pulse time I{sub D}-V{sub D} measurements are utilized to demonstrate the self-heating induced anomalous dimension-dependent threshold voltage variation and on-state current degradation.

  16. Graphene terahertz modulators by ionic liquid gating

    E-Print Network [OSTI]

    Wu, Yang; Qiu, Xuepeng; Liu, Jingbo; Deorani, Praveen; Banerjee, Karan; Son, Jaesung; Chen, Yuanfu; Chia, Elbert E M; Yang, Hyunsoo

    2015-01-01T23:59:59.000Z

    Graphene based THz modulators are promising due to the conical band structure and high carrier mobility of graphene. Here, we tune the Fermi level of graphene via electrical gating with the help of ionic liquid to control the THz transmittance. It is found that, in the THz range, both the absorbance and reflectance of the device increase proportionately to the available density of states due to intraband transitions. Compact, stable, and repeatable THz transmittance modulation up to 93% (or 99%) for a single (or stacked) device has been demonstrated in a broad frequency range from 0.1 to 2.5 THz, with an applied voltage of only 3 V at room temperature.

  17. Decomposition of bipartite and multipartite unitary gates into the product of controlled unitary gates

    E-Print Network [OSTI]

    Lin Chen; Li Yu

    2015-03-18T23:59:59.000Z

    We show that any unitary operator on the $d_A\\times d_B$ system ($d_A\\ge 2$) can be decomposed into the product of at most $4d_A-5$ controlled unitary operators. The number can be reduced to $2d_A-1$ when $d_A$ is a power of two. We also prove that three controlled unitaries can implement a bipartite complex permutation operator, and discuss the connection to an analogous result on classical reversible circuits. We further show that any $n$-partite unitary on the space $\\mathbb{C}^{d_1}\\otimes...\\otimes\\mathbb{C}^{d_n}$ is the product of at most $[2\\prod^{n-1}_{j=1}(2d_j-2)-1]$ controlled unitary gates, each of which is controlled from $n-1$ systems. The number can be further reduced for $n=4$. We also decompose any bipartite unitary into the product of a simple type of bipartite gates and some local unitaries. We derive dimension-independent upper bounds for the CNOT-gate cost or entanglement cost of bipartite permutation unitaries (with the help of ancillas of fixed size) as functions of the Schmidt rank of the unitary. It is shown that such costs under a simple protocol are related to the log-rank conjecture in communication complexity theory via the link of nonnegative rank.

  18. Engineering the (In, Al, Ga)N back-barrier to achieve high channel-conductivity for extremely scaled channel-thicknesses in N-polar GaN high-electron-mobility-transistors

    SciTech Connect (OSTI)

    Lu, Jing, E-mail: jing@ece.ucsb.edu; Zheng, Xun; Guidry, Matthew; Denninghoff, Dan; Ahmadi, Elahe; Lal, Shalini; Keller, Stacia; Mishra, Umesh K. [Department of Electrical and Computer Engineering, University of California, Santa Barbara, California 93106 (United States); DenBaars, Steven P. [Department of Electrical and Computer Engineering, University of California, Santa Barbara, California 93106 (United States); Materials Department, University of California, Santa Barbara, California 93106 (United States)

    2014-03-03T23:59:59.000Z

    Scaling down the channel-thickness (t{sub ch}) in GaN/(In, Al, Ga)N high-electron-mobility-transistors (HEMTs) is essential to eliminating short-channel effects in sub 100?nm gate length HEMTs. However, this scaling can degrade both charge density (n{sub s}) and mobility (?), thereby reducing channel-conductivity. In this study, the back-barrier design in N-polar GaN/(In, Al, Ga)N was engineered to achieve highly conductive-channels with t{sub ch}?

  19. Layered CU-based electrode for high-dielectric constant oxide thin film-based devices

    DOE Patents [OSTI]

    Auciello, Orlando

    2010-05-11T23:59:59.000Z

    A layered device including a substrate; an adhering layer thereon. An electrical conducting layer such as copper is deposited on the adhering layer and then a barrier layer of an amorphous oxide of TiAl followed by a high dielectric layer are deposited to form one or more of an electrical device such as a capacitor or a transistor or MEMS and/or a magnetic device.

  20. Nanowire-based ternary transistor by threshold-voltage manipulation

    SciTech Connect (OSTI)

    Han, Junebeom; Lim, Taekyung; Bong, Jihye; Seo, Keumyoung; Ju, Sanghyun, E-mail: shju@kgu.ac.kr [Department of Physics, Kyonggi University, Suwon, Gyeonggi-Do 443-760 (Korea, Republic of); Kim, Sunkook [Department of Electronics and Radio Engineering, Kyung Hee University, Yongin, Gyeonggi-Do 446-701 (Korea, Republic of)

    2014-04-07T23:59:59.000Z

    We report on a ternary device consisting of two nanowire channels that have different threshold voltage (V{sub th}) values and show that three current stages can be produced. A microscale laser-beam shot was utilized to selectively anneal the nanowire channel area to be processed, and the amount of V{sub th} shift could be controlled by adjusting the laser wavelength. Microscale laser annealing process could control V{sub th} of the individual nanowire transistors while maintaining the other parameters the constant, such as the subthreshold slope, on–off current ratio, and mobility. This result could provide a potential for highly integrated and high-speed ternary circuits.

  1. Millimeter-wave GaN high electron mobility transistors and their integration with silicon electronics

    E-Print Network [OSTI]

    Chung, Jinwook W. (Jinwook Will)

    2011-01-01T23:59:59.000Z

    In spite of the great progress in performance achieved during the last few years, GaN high electron mobility transistors (HEMTs) still have several important issues to be solved for millimeter-wave (30 ~ 300 GHz) applications. ...

  2. RF Power Degradation of GaN High Electron Mobility Transistors

    E-Print Network [OSTI]

    Joh, Jungwoo

    We have developed a versatile methodology to systematically investigate the RF reliability of GaN High-Electron Mobility Transistors. Our technique utilizes RF and DC figures of merit to diagnose the degradation of RF ...

  3. General Purpose NPN Transistor Array The CA3046 consists of five general purpose silicon NPN

    E-Print Network [OSTI]

    Ravikumar, B.

    · Custom Designed Differential Amplifiers · Temperature Compensated Amplifiers · See Application Note, AN of applications in low power systems in the DC through VHF range. They may be used as discrete transistors Match. . . . . . . . . . . . . . . . . . . . . . . . . . . . .2A (Max) · Low Noise Figure

  4. Nanoscale organic transistors that use sourcedrain electrodes supported by high resolution rubber stamps

    E-Print Network [OSTI]

    Rogers, John A.

    Nanoscale organic transistors that use sourceÕdrain electrodes supported by high resolution rubber resolution rubber stamps bilayers of two different types of the elastomer polydimethylsiloxane 3,4 by casting

  5. arsenide junction-field-effect transistors: Topics by E-print...

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    25 Next Page Last Page Topic Index 201 Proposal and design of a new SiC-emitter lateral NPM Schottky collector bipolar transistor on Engineering Websites Summary: for VLSI...

  6. Terahertz radiation detection by field effect transistor in magnetic field S. Boubanga-Tombet,1,a

    E-Print Network [OSTI]

    Levelut, Claire

    Terahertz radiation detection by field effect transistor in magnetic field S. Boubanga-Tombet,1,a M; accepted 30 July 2009; published online 19 August 2009 We report on terahertz radiation detection with In

  7. Simulation and fabrication of GaN-based vertical and lateral normally-off power transistors

    E-Print Network [OSTI]

    Zhang, Yuhao, S.M. Massachusetts Institute of Technology

    2013-01-01T23:59:59.000Z

    This thesis is divided in two parts. First, self-consistent electro-thermal simulations have been performed for single finger and multi-finger GaN-based vertical and lateral power transistors and were validated with ...

  8. Reliability of GaN high electron mobility transistors on silicon substrates

    E-Print Network [OSTI]

    Demirtas, Sefa

    2009-01-01T23:59:59.000Z

    GaN High Electron Mobility Transistors are promising devices for high power and high frequency applications such as cellular base stations, radar and wireless network systems, due to the high bandgap and high breakdown ...

  9. Measurement of Channel Temperature in GaN High-Electron Mobility Transistors

    E-Print Network [OSTI]

    Joh, Jungwoo

    In this paper, a simple and reliable method to estimate the channel temperature of GaN high-electron mobility transistors (HEMTs) is proposed. The technique is based on electrical measurements of performance-related figures ...

  10. The bias-stress effect in pentacene organic thin-film transistors

    E-Print Network [OSTI]

    Ryu, Kyungbum

    2010-01-01T23:59:59.000Z

    Organic thin-film transistors (OTFTs) are promising for flexible large-area electronics. However, the bias-stress effect (BSE) in OTFTs causes operational instability that limits the usefulness of the OTFT technology in a ...

  11. Gated x-ray detector for the National Ignition Facility

    SciTech Connect (OSTI)

    Oertel, John A.; Aragonez, Robert; Archuleta, Tom; Barnes, Cris; Casper, Larry; Fatherley, Valerie; Heinrichs, Todd; King, Robert; Landers, Doug; Lopez, Frank; Sanchez, Phillip; Sandoval, George; Schrank, Lou; Walsh, Peter; Bell, Perry; Brown, Matt; Costa, Robert; Holder, Joe; Montelongo, Sam; Pederson, Neal [Los Alamos National Laboratory, Los Alamos, New Mexico 87544 (United States); Lawrence Livermore National Laboratory, Livermore, California 94551-0808 (United States); VI Control Systems Ltd., Los Alamos, New Mexico 87544 (United States)

    2006-10-15T23:59:59.000Z

    Two new gated x-ray imaging cameras have recently been designed, constructed, and delivered to the National Ignition Facility in Livermore, CA. These gated x-Ray detectors are each designed to fit within an aluminum airbox with a large capacity cooling plane and are fitted with an array of environmental housekeeping sensors. These instruments are significantly different from earlier generations of gated x-ray images due, in part, to an innovative impedance matching scheme, advanced phosphor screens, pulsed phosphor circuits, precision assembly fixturing, unique system monitoring, and complete remote computer control. Preliminary characterization has shown repeatable uniformity between imaging strips, improved spatial resolution, and no detectable impedance reflections.

  12. Low Voltage, Low Power Organic Light Emitting Transistors for AMOLED Displays

    SciTech Connect (OSTI)

    McCarthy, M. A. [University of Florida, Gainesville; Liu, B. [University of Florida, Gainesville; Donoghue, E. P. [University of Florida, Gainesville; Kravchenko, Ivan I [ORNL; Kim, D. Y. [University of Florida, Gainesville; Reynolds, J. R. [University of Florida, Gainesville; So, Franky [University of Florida, Gainesville; Rinzler, A. G. [University of Florida, Gainesville

    2011-01-01T23:59:59.000Z

    Low voltage, low power dissipation, high aperture ratio organic light emitting transistors are demonstrated. The high level of performance is enabled by a carbon nanotube source electrode that permits integration of the drive transistor and the organic light emitting diode into an efficient single stacked device. Given the demonstrated performance, this technology could break the technical logjam holding back widespread deployment of active matrix organic light emitting displays at flat panel screen sizes.

  13. Device and circuit-level models for carbon nanotube and graphene nanoribbon transistors

    E-Print Network [OSTI]

    Tan, Michael Loong Peng

    2011-06-07T23:59:59.000Z

    industry. Circuit simulation time has been substantially reduced through algorithm improvement and hardware enhancement through high performance computing (HPC) platforms. Given its ‘industry standard’ status for computer aided design and analysis... performance computation with digital logic. When current Si transistor features cannot be scaled to smaller sizes to keep improving performance, alternative material based transistors come into focus. Carbon nanotubes are essentially a rolled-up sheet...

  14. Effect of reduction of trap charge carrier density in organic field effect transistors by surface treatment of dielectric layer

    SciTech Connect (OSTI)

    Dagar, Janardan; Yadav, Vandana; Kumar Singh, Rajiv; Suman, C. K.; Srivastava, Ritu, E-mail: ritu@mail.nplindia.org [Physics of Energy Harvesting Division, CSIR-National Physical Laboratory, CSIR-Network of Institute for Solar Energy (NISE), Dr. K.S.Krishnan Road, New Delhi 110012 (India); Tyagi, Priyanka [Physics of Energy Harvesting Division, CSIR-National Physical Laboratory, CSIR-Network of Institute for Solar Energy (NISE), Dr. K.S.Krishnan Road, New Delhi 110012 (India); Center for Applied Research in Electronics, Indian Institute of Technology Delhi, New Delhi 110016 (India)

    2013-12-14T23:59:59.000Z

    In this work, we have studied the effect of surface treatment of SiO{sub 2} dielectric layer on the reduction of the trap charge carrier density at dielectric/semiconducting interface by fabricating a metal–insulator–semiconductor (MIS) device using ?, ?-dihexylcarbonylquaterthiophene as semiconducting layer. SiO{sub 2} dielectric layer has been treated with 1,1,1,3,3,3-hexamethyldisilazane (HMDS) to modify the chemical group acting as charge traps. Capacitance-voltage measurements have been performed on MIS devices fabricated on SiO{sub 2} and HMDS treated SiO{sub 2}. These data have been used for the calculation of trap charge carrier density and Debye length at the dielectric-semiconductor interface. The calculated trap charge carrier density has been found to reduce from (2.925?±?0.049) × 10{sup 16}?cm{sup ?3} to (2.025?±?0.061) × 10{sup 16}?cm{sup ?3} for the MIS device with HMDS treated SiO{sub 2} dielectric in comparison to that of untreated SiO{sub 2}. Next, the effect of reduction in trap charge carrier density has been studied on the performance of organic field effect transistors. The improvement in the device parameters like mobility, on/off ratio, and gate leakage current has been obtained with the effect of the surface treatment. The charge carrier mobility has been improved by a factor of 2 through this treatment. Further, the influence of the treatment was observed by atomic force microscope and Fourier transform infrared spectroscopy techniques.

  15. Scanning Gate Spectroscopy and Its Application to Carbon Nanotube Defects

    E-Print Network [OSTI]

    Collins, Philip G

    2011-01-01T23:59:59.000Z

    24) Sarid, D. Exploring Scanning Probe Microscopy withS. V. ; Gruverman, A. Scanning probe microscopy: electricalLETTER pubs.acs.org/NanoLett Scanning Gate Spectroscopy and

  16. Micro-mechanical logic for field produceable gate arrays

    E-Print Network [OSTI]

    Prakash, Manu

    2005-01-01T23:59:59.000Z

    A paradigm of micro-mechanical gates for field produceable logic is explored. A desktop manufacturing system is sought after which is capable of printing functional logic devices in the field. A logic scheme which induces ...

  17. A comprehensive test method for reprogammable field programmable gate arrays

    E-Print Network [OSTI]

    Ashen, David Glen

    1996-01-01T23:59:59.000Z

    In this thesis, a new test algorithm for reprogrammable field programmable gate arrays (FPGAs) is developed. The fault models consisting of stuck-at faults, bridge faults, programmable switch stuck-on, and stuck-off faults, are utilized. Both...

  18. Rapidly reconfigurable all-optical universal logic gate

    DOE Patents [OSTI]

    Goddard, Lynford L. (Hayward, CA); Bond, Tiziana C. (Livermore, CA); Kallman, Jeffrey S. (Pleasanton, CA)

    2010-09-07T23:59:59.000Z

    A new reconfigurable cascadable all-optical on-chip device is presented. The gate operates by combining the Vernier effect with a novel effect, the gain-index lever, to help shift the dominant lasing mode from a mode where the laser light is output at one facet to a mode where it is output at the other facet. Since the laser remains above threshold, the speed of the gate for logic operations as well as for reprogramming the function of the gate is primarily limited to the small signal optical modulation speed of the laser, which can be on the order of up to about tens of GHz. The gate can be rapidly and repeatedly reprogrammed to perform any of the basic digital logic operations by using an appropriate analog optical or electrical signal at the gate selection port. Other all-optical functionality includes wavelength conversion, signal duplication, threshold switching, analog to digital conversion, digital to analog conversion, signal routing, and environment sensing. Since each gate can perform different operations, the functionality of such a cascaded circuit grows exponentially.

  19. Filter design for hybrid spin gates

    E-Print Network [OSTI]

    Andreas Albrecht; Martin B. Plenio

    2015-04-14T23:59:59.000Z

    The impact of control sequences on the environmental coupling of a quantum system can be described in terms of a filter. Here we analyze how the coherent evolution of two interacting spins subject to periodic control pulses, at the example of a nitrogen vacancy center coupled to a nuclear spin, can be described in the filter framework in both the weak and the strong coupling limit. A universal functional dependence around the filter resonances then allows for tuning the coupling type and strength. Originally limited to small rotation angles, we show how the validity range of the filter description can be extended to the long time limit by time-sliced evolution sequences. Based on that insight, the construction of tunable, noise decoupled, conditional gates composed of alternating pulse sequences is proposed. In particular such an approach can lead to a significant improvement in fidelity as compared to a strictly periodic control sequence. Moreover we analyze the decoherence impact, the relation to the filter for classical noise known from dynamical decoupling sequences, and we outline how an alternating sequence can improve spin sensing protocols.

  20. Impulse radar with swept range gate

    DOE Patents [OSTI]

    McEwan, Thomas E. (Livermore, CA)

    1998-09-08T23:59:59.000Z

    A radar range finder and hidden object locator is based on ultra-wide band radar with a high resolution swept range gate. The device generates an equivalent time amplitude scan with a typical range of 4 inches to 20 feet, and an analog range resolution as limited by a jitter of on the order of 0.01 inches. A differential sampling receiver is employed to effectively eliminate ringing and other aberrations induced in the receiver by the near proximity of the transmit antenna (10), so a background subtraction is not needed, simplifying the circuitry while improving performance. Techniques are used to reduce clutter in the receive signal, such as decoupling the receive (24) and transmit cavities (22) by placing a space between them, using conductive or radiative damping elements on the cavities, and using terminating plates on the sides of the openings. The antennas can be arranged in a side-by-side parallel spaced apart configuration or in a coplanar opposed configuration which significantly reduces main bang coupling.

  1. Impulse radar with swept range gate

    DOE Patents [OSTI]

    McEwan, T.E.

    1998-09-08T23:59:59.000Z

    A radar range finder and hidden object locator is based on ultra-wide band radar with a high resolution swept range gate. The device generates an equivalent time amplitude scan with a typical range of 4 inches to 20 feet, and an analog range resolution as limited by a jitter of on the order of 0.01 inches. A differential sampling receiver is employed to effectively eliminate ringing and other aberrations induced in the receiver by the near proximity of the transmit antenna, so a background subtraction is not needed, simplifying the circuitry while improving performance. Techniques are used to reduce clutter in the receive signal, such as decoupling the receive and transmit cavities by placing a space between them, using conductive or radiative damping elements on the cavities, and using terminating plates on the sides of the openings. The antennas can be arranged in a side-by-side parallel spaced apart configuration or in a coplanar opposed configuration which significantly reduces main bang coupling. 25 figs.

  2. Novel concepts of superconductive optoelectronic devices: Resonances of photoconductivity in the Cu{sub 2}O gate region

    SciTech Connect (OSTI)

    Masumi, Taizo; Isobe, Masakatsu [Gunma Univ., Kiryu, Gunma (Japan). Dept. of Electronic Engineering

    1996-12-31T23:59:59.000Z

    On the basis of the discoveries of anomalous photoconductivity of insulators correlated with high-{Tc} superconductivity, the authors introduce novel concepts of superconductive optoelectronic devices. They have proposed that one must be able to fabricate a new type of device by combining these photoconductors for the gate region and relevant superconductors for the source and drain regions, both effective below their Tc`s. They have been continuing a series of further experimental studies seeking actual possibilities by utilizing the basic substance Cu{sub 2}O for the gate material and superconductive LBCO, LSCO and YBCO for the source and drain materials, e.g., YBCO/Cu{sub 2}O/YBCO. Here, they report an observation of resonant and hybrid emergences of photoconductivity of Cu{sub 2}O in the gate region peculiarly in conjugation with the high-Tc superconductivity utilized in the source and drain regions in superconductive optoelectronic devices. Microwave photosignals at 35 GHz guarantee a high-speed operation of the device in the n-sec region. They feed these results in a Nano-engineering back to basic Physics of Oxide Superconductor in order to shed a new light on substantial natures of the Cu-O based high-{Tc} superconductivity.

  3. Thickness-dependent in situ studies of trap states in pentacene thin film transistors

    E-Print Network [OSTI]

    Ludwig-Maximilians-Universität, München

    from +40 to 40 V off-to-on gate-sweeps and back, at a constant source-drain-voltage VSD of 20 V- strate, which serves as the back gate, with 150 nm SiO2 on top. In order to avoid OH. Subsequently, a single conductance source- drain-voltage sweep from 0 to 40 V is performed at a con- stant gate

  4. A laser-programmable gate array 

    E-Print Network [OSTI]

    Gullette, James Benjamin

    1985-01-01T23:59:59.000Z

    process with double layer polysilicon, typicaHy used for capacitors, and single layer metal. The laser techniques used to program the devices were the interconnection of the over- lapping polysilicon layers and the cutting of metal and polysilicon links... Array The VLSI program at Texas A&M University was provided with a standard double-poly N-channel Metal Oxide Semiconductor (NMOS) process. It has been found that certain laser personalization techniques for creating and deleting con- nections...

  5. Ge MOS Characteristics with CVD HfO2 Gate Dielectrics and TaN Gate Electrode W. P. Bai*, N. Lu*, J. Liu*, A. Ramirez**, D. L. Kwong*, D. Wristers**, A. Ritenour#

    E-Print Network [OSTI]

    Ge MOS Characteristics with CVD HfO2 Gate Dielectrics and TaN Gate Electrode W. P. Bai*, N. Lu*, J, we report for the first time Ge MOS characteristics with ultra thin rapid thermal CVD HfO2 gate dielectrics and TaN gate electrode. Using the newly developed pre- gate cleaning and NH3-based Ge surface

  6. Oxidation catalyst

    DOE Patents [OSTI]

    Ceyer, Sylvia T. (Cambridge, MA); Lahr, David L. (Cambridge, MA)

    2010-11-09T23:59:59.000Z

    The present invention generally relates to catalyst systems and methods for oxidation of carbon monoxide. The invention involves catalyst compositions which may be advantageously altered by, for example, modification of the catalyst surface to enhance catalyst performance. Catalyst systems of the present invention may be capable of performing the oxidation of carbon monoxide at relatively lower temperatures (e.g., 200 K and below) and at relatively higher reaction rates than known catalysts. Additionally, catalyst systems disclosed herein may be substantially lower in cost than current commercial catalysts. Such catalyst systems may be useful in, for example, catalytic converters, fuel cells, sensors, and the like.

  7. The effects of buffer layers on the performance and stability of flexible InGaZnO thin film transistors on polyimide substrates

    SciTech Connect (OSTI)

    Ok, Kyung-Chul; Park, Jin-Seong, E-mail: hkim-2@naver.com, E-mail: jsparklime@hanyang.ac.kr [Division of Materials Science and Engineering, Hanyang University, 222, Wangsimni-ro, Seongdong-gu, Seoul 133-791 (Korea, Republic of); Ko Park, Sang-Hee; Kim, H., E-mail: hkim-2@naver.com, E-mail: jsparklime@hanyang.ac.kr [Department of Materials Science and Engineering, Korea Advanced Institute of Science and Technology, 291 Daehak-ro, Yuseong-gu, Daejeon 305-701 (Korea, Republic of); Hwang, Chi-Sun [Transparent Electronics Team, ETRI, Daejeon 305-350 (Korea, Republic of); Soo Shin, Hyun; Bae, Jonguk [LG Display R and D Center, LG Display Co., Ltd., Paju 413-811 (Korea, Republic of)

    2014-02-10T23:59:59.000Z

    We demonstrated the fabrication of flexible amorphous indium gallium zinc oxide thin-film transistors (TFTs) on high-temperature polyimide (PI) substrates, which were debonded from the carrier glass after TFT fabrication. The application of appropriate buffer layers on the PI substrates affected the TFT performance and stability. The adoption of the SiN{sub x}/AlO{sub x} buffer layers as water and hydrogen diffusion barriers significantly improved the device performance and stability against the thermal annealing and negative bias stress, compared to single SiN{sub x} or SiO{sub x} buffer layers. The substrates could be bent down to a radius of curvature of 15?mm and the devices remained normally functional.

  8. Growth of AlGaN/GaN heterojunction field effect transistors on semi-insulating GaN using an AlGaN interlayer

    SciTech Connect (OSTI)

    Chen, Z.; Denbaars, S. P. [Electrical and Computer Engineering, University of California, Santa Barbara, California 93106 (United States); Materials Department, University of California, Santa Barbara, California 93106 (United States); Pei, Y.; Newman, S.; Chu, R.; Brown, D.; Keller, S.; Mishra, U. K. [Electrical and Computer Engineering, University of California, Santa Barbara, California 93106 (United States); Chung, R.; Nakamura, S. [Materials Department, University of California, Santa Barbara, California 93106 (United States)

    2009-03-16T23:59:59.000Z

    Semi-insulating (SI) GaN layers were grown on 4H-SiC substrates by inserting an AlGaN layer between the AlN buffer and the GaN layer. Secondary ion mass spectroscopy measurements showed that the AlGaN layer prevented Si from diffusing from the substrate into the GaN layer. X-ray diffraction and atomic force microscopy analyses showed that an optimized AlGaN interlayer does not degrade the crystal quality or surface morphology of the SI GaN. The room temperature mobility of an AlGaN/GaN heterostructure using this SI GaN was 2200 cm{sup 2}/V s. High electron mobility transistors (HEMTs) with 0.65 {mu}m long gates were also fabricated on these SI GaN buffers. A power density of 19.0 W/mm with a power added efficiency of 48% was demonstrated at 10 GHz at a drain bias of 78 V. These HEMTs also exhibited sharp pinch off, low leakage, and negligible dispersion.

  9. Helicity sensitive terahertz radiation detection by field effect transistors C. Drexler, N. Dyakonova, P. Olbrich, J. Karch, M. Schafberger et al.

    E-Print Network [OSTI]

    Levelut, Claire

    Helicity sensitive terahertz radiation detection by field effect transistors C. Drexler, N sensitive terahertz radiation detection by field effect transistors C. Drexler,1 N. Dyakonova,2 P. Olbrich,1

  10. Subthreshold-swing physics of tunnel field-effect transistors Wei Cao, Deblina Sarkar, Yasin Khatami, Jiahao Kang, and Kaustav Banerjee

    E-Print Network [OSTI]

    Subthreshold-swing physics of tunnel field-effect transistors Wei Cao, Deblina Sarkar, Yasin) Subthreshold-swing physics of tunnel field-effect transistors Wei Cao, Deblina Sarkar, Yasin Khatami, Jiahao

  11. Preparation of gallium nitride surfaces for atomic layer deposition of aluminum oxide

    SciTech Connect (OSTI)

    Kerr, A. J. [Department of Electrical and Computer Engineering, University of California, San Diego, La Jolla, California 92093 (United States); Department of Chemistry and Biochemistry, University of California, San Diego, La Jolla, California 92093 (United States); Chagarov, E.; Kaufman-Osborn, T.; Kummel, A. C., E-mail: akummel@ucsd.edu [Department of Chemistry and Biochemistry, University of California, San Diego, La Jolla, California 92093 (United States); Gu, S.; Wu, J.; Asbeck, P. M. [Department of Electrical and Computer Engineering, University of California, San Diego, La Jolla, California 92093 (United States); Madisetti, S.; Oktyabrsky, S. [Department of Nanoscale Science and Engineering, University at Albany–State University of New York, Albany, New York 12222 (United States)

    2014-09-14T23:59:59.000Z

    A combined wet and dry cleaning process for GaN(0001) has been investigated with XPS and DFT-MD modeling to determine the molecular-level mechanisms for cleaning and the subsequent nucleation of gate oxide atomic layer deposition (ALD). In situ XPS studies show that for the wet sulfur treatment on GaN(0001), sulfur desorbs at room temperature in vacuum prior to gate oxide deposition. Angle resolved depth profiling XPS post-ALD deposition shows that the a-Al{sub 2}O{sub 3} gate oxide bonds directly to the GaN substrate leaving both the gallium surface atoms and the oxide interfacial atoms with XPS chemical shifts consistent with bulk-like charge. These results are in agreement with DFT calculations that predict the oxide/GaN(0001) interface will have bulk-like charges and a low density of band gap states. This passivation is consistent with the oxide restoring the surface gallium atoms to tetrahedral bonding by eliminating the gallium empty dangling bonds on bulk terminated GaN(0001)

  12. Free-surface flow simulations for discharge-based operation of hydraulic structure gates

    E-Print Network [OSTI]

    Erdbrink, C D; Sloot, P M A

    2014-01-01T23:59:59.000Z

    We combine non-hydrostatic flow simulations of the free surface with a discharge model based on elementary gate flow equations for decision support in operation of hydraulic structure gates. A water level-based gate control used in most of today's general practice does not take into account the fact that gate operation scenarios producing similar total discharged volumes and similar water levels may have different local flow characteristics. Accurate and timely prediction of local flow conditions around hydraulic gates is important for several aspects of structure management: ecology, scour, flow-induced gate vibrations and waterway navigation. The modelling approach is described and tested for a multi-gate sluice structure regulating discharge from a river to the sea. The number of opened gates is varied and the discharge is stabilized with automated control by varying gate openings. The free-surface model was validated for discharge showing a correlation coefficient of 0.994 compared to experimental data. A...

  13. Strained Sistrained Ge dual-channel heterostructures on relaxed Si0.5Ge0.5 for symmetric mobility p-type and n-type metal-oxide-semiconductor

    E-Print Network [OSTI]

    Strained SiÕstrained Ge dual-channel heterostructures on relaxed Si0.5Ge0.5 for symmetric mobility By growing heterostructures that combine a surface strained Si layer with a buried strained Ge layer on Si0.5Ge0.5 , we have fabricated metal-oxide-semiconductor field-effect transistors with mobility

  14. Proposal for a phase-coherent thermoelectric transistor

    SciTech Connect (OSTI)

    Giazotto, F., E-mail: giazotto@sns.it [NEST, Instituto Nanoscienze-CNR and Scuola Normale Superiore, I-56127 Pisa (Italy); Robinson, J. W. A., E-mail: jjr33@cam.ac.uk [Department of Materials Science and Metallurgy, University of Cambridge, 27 Charles Babbage Road, Cambridge CB3 0FS (United Kingdom); Moodera, J. S. [Department of Physics and Francis Bitter Magnet Lab, Massachusetts Institute of Technology, Cambridge, Massachusetts 02139 (United States); Bergeret, F. S., E-mail: sebastian-bergeret@ehu.es [Centro de Física de Materiales (CFM-MPC), Centro Mixto CSIC-UPV/EHU, Manuel de Lardizabal 4, E-20018 San Sebastián (Spain); Donostia International Physics Center (DIPC), Manuel de Lardizabal 5, E-20018 San Sebastián (Spain)

    2014-08-11T23:59:59.000Z

    Identifying materials and devices which offer efficient thermoelectric effects at low temperature is a major obstacle for the development of thermal management strategies for low-temperature electronic systems. Superconductors cannot offer a solution since their near perfect electron-hole symmetry leads to a negligible thermoelectric response; however, here we demonstrate theoretically a superconducting thermoelectric transistor which offers unparalleled figures of merit of up to ?45 and Seebeck coefficients as large as a few mV/K at sub-Kelvin temperatures. The device is also phase-tunable meaning its thermoelectric response for power generation can be precisely controlled with a small magnetic field. Our concept is based on a superconductor-normal metal-superconductor interferometer in which the normal metal weak-link is tunnel coupled to a ferromagnetic insulator and a Zeeman split superconductor. Upon application of an external magnetic flux, the interferometer enables phase-coherent manipulation of thermoelectric properties whilst offering efficiencies which approach the Carnot limit.

  15. Identification of a reversible quantum gate: assessing the resources

    E-Print Network [OSTI]

    Giulio Chiribella; Giacomo Mauro D'Ariano; Martin Roetteler

    2014-09-12T23:59:59.000Z

    We assess the resources needed to identify a reversible quantum gate among a finite set of alternatives, including in our analysis both deterministic and probabilistic strategies. Among the probabilistic strategies we consider unambiguous gate discrimination, where errors are not tolerated but inconclusive outcomes are allowed, and we prove that parallel strategies are sufficient to unambiguously identify the unknown gate with minimum number of queries. This result is used to provide upper and lower bounds on the query complexity and on the minimum ancilla dimension. In addition, we introduce the notion of generalized t-designs, which includes unitary t-designs and group representations as special cases. For gates forming a generalized t-design we give an explicit expression for the maximum probability of correct gate identification and we prove that there is no gap between the performances of deterministic strategies an those of probabilistic strategies. Hence, evaluating of the query complexity of perfect deterministic discrimination is reduced to the easier problem of evaluating the query complexity of unambiguous discrimination. Finally, we consider discrimination strategies where the use of ancillas is forbidden, providing upper bounds on the number of additional queries needed to make up for the lack of entanglement with the ancillas.

  16. 1070 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, NO. 6, JUNE 2002 A New Lateral PNM Schottky Collector Bipolar Transistor

    E-Print Network [OSTI]

    Kumar, M. Jagadesh

    Collector Bipolar Transistor (SCBT) on SOI for Nonsaturating VLSI Logic Design M. Jagadesh Kumar and D. The collector-base junction of the proposed lateral PNM transistor consists of a Schottky junction between n PNM, numerical simulation, Schottky collector, silicon-on-insulator (SOI). I. INTRODUCTION Because

  17. RF Power Degradation of GaN High Electron Mobility Transistors Jungwoo Joh and Jess A. del Alamo

    E-Print Network [OSTI]

    del Alamo, Jesús A.

    RF Power Degradation of GaN High Electron Mobility Transistors Jungwoo Joh and Jesús A. del Alamo Transistors. Our technique utilizes RF and DC figures of merit to diagnose the degradation of RF stressed and to introduce new degradation modes. At high power level, RF stress induces a prominent trapping

  18. Proposal and design of a new SiC-emitter lateral NPM Schottky collector bipolar transistor on

    E-Print Network [OSTI]

    Kumar, M. Jagadesh

    Proposal and design of a new SiC-emitter lateral NPM Schottky collector bipolar transistor on SOI, a SiC emitter lateral NPM Schottky collector bipolar transistor (SCBT) with a silicon-on-insulator (SOI on simulation results, the authors demonstrate for the first time that the proposed SiC emitter lateral NPM

  19. SiGe quantum dot single-hole transistor fabricated by atomic force microscope nanolithography and silicon epitaxial-regrowth

    E-Print Network [OSTI]

    Rokhinson, Leonid

    SiGe quantum dot single-hole transistor fabricated by atomic force microscope nanolithography; published online 10 November 2006 A SiGe quantum dot single-hole transistor passivated by silicon epitaxial are reproducible, in sharp contrast with the noisy and irreproducible I-V characteristics of unpassivated SiGe

  20. A New SiGe Base Lateral PNM Schottky Collector Bipolar Transistor on SOI for Non-Saturating

    E-Print Network [OSTI]

    Kumar, M. Jagadesh

    A New SiGe Base Lateral PNM Schottky Collector Bipolar Transistor on SOI for Non-Saturating VLSI Logic Design Abstract- A novel bipolar transistor structure, namely, SiGe base lateral PNM Schottky is presented. Based on our simulation results, we demonstrate for the first time that the proposed SiGe base

  1. Temperature dependence of 1/f noise mechanisms in silicon nanowire biochemical field effect transistors

    E-Print Network [OSTI]

    Reed, Mark

    drain bias and at different temperatures 100­300 K . We observe a change in the noise mechanism.g., Hooge parameter compared to dry etching techniques.14 The devices are used in the back- gated configuration, where the gate voltage Vg is applied to the handle layer of the SOI wafer. The source-drain bias

  2. Field Dependent Transport Properties in InAs Nanowire Field Effect Transistors

    E-Print Network [OSTI]

    Wang, Deli

    highlights the potential of such nanoscale devices for high performance electronic applications. Indeed, back transport properties have been reported. However,thevertical(gate-channel)andlateral(source-drain) field drain length, is considered to be the active portion of the NWFET device. Top-gated devices

  3. Design Aspects of Carry Lookahead Adders with Vertically-Stacked Nanowire Transistors

    E-Print Network [OSTI]

    De Micheli, Giovanni

    advanced processing and additional effort in the evaluation of the state-of-the-art technology. One] or used for new functionalities [6]. However, only a few works have assessed the impact of nanowire gates, such as an inverter. Then Section IV reports on the assumptions and the modeling for logic gate

  4. Characterizing the geometrical edges of nonlocal two-qubit gates

    E-Print Network [OSTI]

    Balakrishnan, S

    2009-01-01T23:59:59.000Z

    Nonlocal two-qubit gates are geometrically represented by tetrahedron known as Weyl chamber within which the perfect entanglers form a polyhedron. We study the entangling power and local invariants of all the edges of the Weyl chamber and polyhedron. It is found that SWAP -alpha- family of gates with constitute one edge of the Weyl chamber. Using circuit equivalence, it is shown that Controlled-NOT can be constructed from SWAP-1/2, the only perfect entangler in the above family. Further, the three edges of the polyhedron possessing the entangling power of 1/6 are also capable of constructing CNOT. It is observed that all the edges of the geometry are formed by single parametric two-qubit gates.

  5. High performance transistors via aligned polyfluorene-sorted carbon nanotubes

    SciTech Connect (OSTI)

    Brady, Gerald J.; Joo, Yongho; Singha Roy, Susmit; Gopalan, Padma; Arnold, Michael S., E-mail: msarnold@wisc.edu [Department of Materials Science and Engineering, University of Wisconsin-Madison, 1509 University Avenue, Madison, Wisconsin 53706 (United States)

    2014-02-24T23:59:59.000Z

    We evaluate the performance of exceptionally electronic-type sorted, semiconducting, aligned single-walled carbon nanotubes (s-SWCNTs) in field effect transistors (FETs). High on-conductance and high on/off conductance modulation are simultaneously achieved at channel lengths which are both shorter and longer than individual s-SWCNTs. The s-SWCNTs are isolated from heterogeneous mixtures using a polyfluorene-derivative as a selective agent and aligned on substrates via dose-controlled, floating evaporative self-assembly at densities of ?50 s-SWCNTs ?m{sup ?1}. At a channel length of 9??m the s-SWCNTs percolate to span the FET channel, and the on/off ratio and charge transport mobility are 2.2?×?10{sup 7} and 46?cm{sup 2}?V{sup ?1}?s{sup ?1}, respectively. At a channel length of 400?nm, a large fraction of the s-SWCNTs directly span the channel, and the on-conductance per width is 61??S??m{sup ?1} and the on/off ratio is 4?×?10{sup 5}. These results are considerably better than previous solution-processed FETs, which have suffered from poor on/off ratio due to spurious metallic nanotubes that bridge the channel. 4071 individual and small bundles of s-SWCNTs are tested in 400?nm channel length FETs, and all show semiconducting behavior, demonstrating the high fidelity of polyfluorenes as selective agents and the promise of assembling s-SWCNTs from solution to create high performance semiconductor electronic devices.

  6. Controlled-NOT Gate Interferometer with a Thermal Source

    E-Print Network [OSTI]

    Vincenzo Tamma; Johannes Seiler

    2015-05-05T23:59:59.000Z

    We demonstrate a multiphoton interferometer able to reproduce, by using only a thermal source, the operation of a quantum logic gate known as controlled-NOT gate. We show how 100%-visibility correlations typical of any Bell state can be obtained by performing polarization correlation measurements in the fluctuation of the number of photons at the interferometer output. The physics of multiphoton interference at the heart of this proposal can be readily used, in general, for the implementation of arbitrary-dimension bosonic networks leading to arbitrary-order entanglement-like correlations.

  7. Isolated-attosecond-pulse generation with infrared double optical gating

    SciTech Connect (OSTI)

    Lan Pengfei; Takahashi, Eiji J.; Midorikawa, Katsumi [Extreme Photonics Research Group, RIKEN Advanced Science Institute, 2-1 Hirosawa, Wako, Saitama 351-0198 (Japan)

    2011-06-15T23:59:59.000Z

    We propose and theoretically demonstrate an infrared two-color polarization gating scheme for generating an intense isolated attosecond pulse (IAP) in the multicycle regime. Our simulations show that an IAP can be produced using a multicycle two-color driving pulse with a duration up to 60 fs. Moreover, the carrier-envelope phase (CEP) of the driving laser is not required to be stabilized, although the IAP intensity changes with the CEP slip. Such a gating scheme significantly relaxes the requirements for driving lasers and opens the door to easily create intense IAPs with a high-power conventional multicycle laser pulse.

  8. Self-aligned submicron gate length gallium arsenide MESFET 

    E-Print Network [OSTI]

    Huang, Hsien-Ching

    1987-01-01T23:59:59.000Z

    38 21. Proximity cap annealing . 22. Temperature profile of post implant anneal 46 47 23. 24. 25. 26. 27. 28. 29. 30. "Pits" or holes in GaAs post implant anneal without sacrificial cap Silicon monoxide source (bafile box) used.... 16(b)). The bottom resist layer is then further etched in the oxygen plasma to produce undercutting for the desire gate structure. The amount of undercut is determined by the desired length of the gate and is the width of the remaining resist...

  9. Fabrication of a gated gallium arsenide heterostructure resonant tunneling diode

    E-Print Network [OSTI]

    Kinard, William Brian

    1989-01-01T23:59:59.000Z

    , . ' 'CONTACT PAD' PLANAR I ZED POLYAM I DE RECTIFYI CONTACT N DBHS Pig. 2. f'utavvay vieiv of a gated gallium arsenide heterostructure resonant tunneling diode 1018 graded from 10 18 io" 10? (lightly doped) units=cm 8 ?graded from 10 to 18...FABRICATION OF A GATED GALLIL". tl ARSEXIDE HETEROSTRL CTL RF. RESONANT TF'XXELI'XG DIODE A Thesis bt ttrILLIAAI BRIA'. s KI'iARD Subnut ted to the Office of Graduate Studies of Texas AE;M Eniverstty tn partial fulfillment of the requirements...

  10. SAVE THIS | EMAIL THIS | Close Bill and Melinda Gates go back to school

    E-Print Network [OSTI]

    Knaust, Helmut

    Powered by SAVE THIS | EMAIL THIS | Close Bill and Melinda Gates go back to school Their crusade, is essential, Melinda Gates insisted, "if we're going to make any dent in poverty in America." The idea

  11. UC Davis Fuel Cell, Hydrogen, and Hybrid Vehicle (FCH2V) GATE...

    Energy Savers [EERE]

    UC Davis Fuel Cell, Hydrogen, and Hybrid Vehicle (FCH2V) GATE Center of Excellence UC Davis Fuel Cell, Hydrogen, and Hybrid Vehicle (FCH2V) GATE Center of Excellence Presentation...

  12. Penn State DOE GATE Center of Exellence for In-Vehicle, High...

    Energy Savers [EERE]

    Penn State DOE GATE Center of Exellence for In-Vehicle, High-Power Energy Storage Systems Penn State DOE GATE Center of Exellence for In-Vehicle, High-Power Energy Storage Systems...

  13. Highly specific and sensitive non-enzymatic determination of uric acid in serum and urine by extended gate field effect transistor sensors

    E-Print Network [OSTI]

    Reed, Mark

    , such as gout, Lesch­Nyhan syndrome, cardiovas- cular disease, type 2 diabetes, metabolic syndrome and kidney

  14. A FOUR-QUADRANT FLOATING-GATE SYNAPSE Paul Hasler, Chris Diorio, and Bradley A. Minch

    E-Print Network [OSTI]

    Diorio, Chris

    and to the drain. We present experi- mental measurements from a oating-gate synapse that si- multaniously computes, typical of hebbian and backpropagation learning rules, between the input and drain voltages. Our four gate; the form of this rule depends on how various error signals are fed back to the oating gate. 1

  15. Worry Is Associated With Impaired Gating of Threat From Working Memory

    E-Print Network [OSTI]

    Larson, Christine L.

    Emotion Worry Is Associated With Impaired Gating of Threat From Working Memory Daniel M. Stout, C. L. (2014, August 25). Worry Is Associated With Impaired Gating of Threat From Working Memory Is Associated With Impaired Gating of Threat From Working Memory Daniel M. Stout University of Wisconsin

  16. Learning Methods for Lung Tumor Markerless Gating in Image-Guided Radiotherapy

    E-Print Network [OSTI]

    Dy, Jennifer G.

    Learning Methods for Lung Tumor Markerless Gating in Image-Guided Radiotherapy Ying Cui Dept. For gated lung cancer radiotherapy, it is difficult to generate ac- curate gating signals due to the large techniques, we apply them on five sequences of fluoroscopic images from five lung cancer patients against

  17. Optical gating of perylene bisimide fluorescence using dithienylcyclopentene photochromic switches

    SciTech Connect (OSTI)

    Pärs, Martti; Köhler, Jürgen, E-mail: juergen.koehler@uni-bayreuth.de [Experimental Physics IV, University of Bayreuth, 95440 Bayreuth (Germany)] [Experimental Physics IV, University of Bayreuth, 95440 Bayreuth (Germany); Gräf, Katja; Bauer, Peter; Thelakkat, Mukundan [Applied Functional Polymers, University of Bayreuth, 95440 Bayreuth (Germany)] [Applied Functional Polymers, University of Bayreuth, 95440 Bayreuth (Germany)

    2013-11-25T23:59:59.000Z

    The emission of millions of fluorescence photons from a chromophore is controlled by the absorption of a few tens of photons in a photochromic molecule. The parameters that determine the efficiency of this process are investigated, providing insights for the development of an all-optical gate.

  18. Gating and regulation of connexin 43 (Cx43) hemichannels

    E-Print Network [OSTI]

    Newman, Eric A.

    Gating and regulation of connexin 43 (Cx43) hemichannels Jorge E. Contreras* , Juan C. Sa Connexin 43 (Cx43) nonjunctional or ``unapposed'' hemichannels can open under physiological or pathological conditions. We char- acterize hemichannels comprised of Cx43 or Cx43-EGFP (Cx43 with enhanced GFP fused

  19. Advanced Gate Drive for the SNS High Voltage Converter Modulator

    SciTech Connect (OSTI)

    Nguyen, M.N.; Burkhart, C.; Kemp, M.A.; /SLAC; Anderson, D.E.; /Oak Ridge

    2009-05-07T23:59:59.000Z

    SLAC National Accelerator Laboratory is developing a next generation H-bridge switch plate [1], a critical component of the SNS High Voltage Converter Modulator [2]. As part of that effort, a new IGBT gate driver has been developed. The drivers are an integral part of the switch plate, which are essential to ensuring fault-tolerant, high-performance operation of the modulator. The redesigned driver improves upon the existing gate drive in several ways. The new gate driver has improved fault detection and suppression capabilities; suppression of shoot-through and over-voltage conditions, monitoring of dI/dt and Vce(sat) for fast over-current detection and suppression, and redundant power isolation are some of the added features. In addition, triggering insertion delay is reduced by a factor of four compared to the existing driver. This paper details the design and performance of the new IGBT gate driver. A simplified schematic and description of the construction are included. The operation of the fast over-current detection circuits, active IGBT over-voltage protection circuit, shoot-through prevention circuitry, and control power isolation breakdown detection circuit are discussed.

  20. Three-qubit phase gate based on cavity quantum electrodynamics

    E-Print Network [OSTI]

    Chang, Jun-Tao; Zubairy, M. Suhail

    2008-01-01T23:59:59.000Z

    We describe a three-qubit quantum phase gate which is implemented by passing a four-level atom in a cascade configuration initially in its ground state through a three-mode optical cavity. The three qubits are represented by the photons in the three...

  1. Review Article Gate-Level Circuit Reliability Analysis: A Survey

    E-Print Network [OSTI]

    Chen, Chunhong

    electronic components (such as single electron devices) have demonstrated their nondeterministic characReview Article Gate-Level Circuit Reliability Analysis: A Survey Ran Xiao and Chunhong Chen. Circuit reliability has become a growing concern in today's nanoelectronics, which motivates strong

  2. ECG Gated Tomographic reconstruction for 3-D Rotational Coronary Angiography

    E-Print Network [OSTI]

    Paris-Sud XI, Université de

    imaging techniques to improve both the safety and the efficacy of coronary angiography interventions the ground for a platform dedicated to the planning and execution of percutaneous coronary inter- ventionsECG Gated Tomographic reconstruction for 3-D Rotational Coronary Angiography Yining HU, Lizhe XIE

  3. An overview of the gate and panel industry 

    E-Print Network [OSTI]

    Fisher, C. West

    2000-01-01T23:59:59.000Z

    acquiring raw materials, its pre-fabrication, welding, touch-up, and delivery of the product. My first major responsibility for Texas Gate and Panel was to expand its sales territory. It soon became obvious that a thorough knowledge of my competitors...

  4. Controlling Wild Mobile Robots Using Virtual Gates and Discrete Transitions

    E-Print Network [OSTI]

    LaValle, Steven M.

    Controlling Wild Mobile Robots Using Virtual Gates and Discrete Transitions Leonardo Bobadilla purposely design them to execute wild motions, which means each will strike every open set infinitely often, "wildly behaving" robots that move more-or-less straight until a wall is contacted. They then pick

  5. TECH FORUM: [VERIFIED RTL TO GATES] Efficient RC power grid

    E-Print Network [OSTI]

    Najm, Farid N.

    TECH FORUM: [VERIFIED RTL TO GATES] Efficient RC power grid verification using node elimination proposes a novel approach to systematically reduce the power grid and accurately compute an upper bound on the voltage drops at power grid nodes that are retained. Furthermore, acriterion for the safety of nodes

  6. Compressed sensing quantum process tomography for superconducting quantum gates

    E-Print Network [OSTI]

    Andrey V. Rodionov; Andrzej Veitia; R. Barends; J. Kelly; Daniel Sank; J. Wenner; John M. Martinis; Robert L. Kosut; Alexander N. Korotkov

    2014-07-03T23:59:59.000Z

    We apply the method of compressed sensing (CS) quantum process tomography (QPT) to characterize quantum gates based on superconducting Xmon and phase qubits. Using experimental data for a two-qubit controlled-Z gate, we obtain an estimate for the process matrix $\\chi$ with reasonably high fidelity compared to full QPT, but using a significantly reduced set of initial states and measurement configurations. We show that the CS method still works when the amount of used data is so small that the standard QPT would have an underdetermined system of equations. We also apply the CS method to the analysis of the three-qubit Toffoli gate with numerically added noise, and similarly show that the method works well for a substantially reduced set of data. For the CS calculations we use two different bases in which the process matrix $\\chi$ is approximately sparse, and show that the resulting estimates of the process matrices match each ther with reasonably high fidelity. For both two-qubit and three-qubit gates, we characterize the quantum process by not only its process matrix and fidelity, but also by the corresponding standard deviation, defined via variation of the state fidelity for different initial states.

  7. CBC Reduction in InP Heterojunction Bipolar Transistor with Selectively Implanted Collector Pedestal

    E-Print Network [OSTI]

    Rodwell, Mark J. W.

    CBC Reduction in InP Heterojunction Bipolar Transistor with Selectively Implanted Collector-3812 Fax: (805) 893-8714 Email: yingda@ece.ucsb.edu The base-collector junction capacitance (Cbc) is a key with a collector pedestal under the HBT's intrinsic region by using selective ion implantation and MBE regrowth

  8. Organic Transistors on Fiber: A first step towards electronic textiles Josephine B. Lee and Vivek Subramanian

    E-Print Network [OSTI]

    California at Irvine, University of

    incorporation of interconnects into the fiber eliminates the need for switching back and forth from fiber, source/drain top contacts were patterned using orthogonal over-woven 50 µm diameter wires (Fig 1, top source/drain contact pads. Figure 1: (top) Masking process used to fabricate transistors on fiber

  9. Protection des transistors MOS en rgime de deuxime claquage H. Tranduc et P. Rossel

    E-Print Network [OSTI]

    Paris-Sud XI, Université de

    state, is proposed : the current crowding mechanism is avoided by using the electrical feed back'état de deuxième claquage. - Lorsqu'on augmente la tension drain- substrat d'un transistor Métal d'avalanche. Si on continue à faire croître le courant drain, il apparaît, à partir d'un certain

  10. SELF-HEATING PROCESS IN MICROWAVE TRANSISTORS Anthony E. Parker(1) and James G. Rathmell(2)

    E-Print Network [OSTI]

    SELF-HEATING PROCESS IN MICROWAVE TRANSISTORS Anthony E. Parker(1) and James G. Rathmell(2) (1 of self-heating. The impact on circuit performance is that distortion and intermodulation, which vary with bias and load conditions, additionally vary with self-heating. This additional dependence is overlooked

  11. Title of Dissertation: MASKLESS FABRICATION OF JUNCTION FIELD EFFECT TRANSISTORS VIA FOCUSED ION BEAMS

    E-Print Network [OSTI]

    Anlage, Steven

    ABSTRACT Title of Dissertation: MASKLESS FABRICATION OF JUNCTION FIELD EFFECT TRANSISTORS VIA FOCUSED ION BEAMS Anthony John De Marco, Doctor of Philosophy, 2004 Dissertation directed by: Professor Dissertation submitted to the Faculty of the Graduate School of the University of Maryland, College Park

  12. Bendable single crystal silicon thin film transistors formed by printing on plastic substrates

    E-Print Network [OSTI]

    Rogers, John A.

    Bendable single crystal silicon thin film transistors formed by printing on plastic substrates E on plastic substrates using an efficient dry transfer printing technique. In these devices, free standing-Si is then transferred, to a specific location and with a controlled orientation, onto a thin plastic sheet

  13. Very high frequency GaAlAs laser field-effect transistor monolithic integrated circuit

    SciTech Connect (OSTI)

    Ury, I.; Lau, K.Y.; Bar-Chaim, N.; Yariv, A.

    1982-07-15T23:59:59.000Z

    A very low threshold GaAlAs buried heterostructure laser has been monolithically integrated with a recessed structure metal-semiconductor field-effect transistor on a semi-insulating substrate. At cw operation, the device has a direct modulation bandwidth of at least 4 GHz.

  14. Ambient induced degradation and chemically activated recovery in copper phthalocyanine thin film transistors

    E-Print Network [OSTI]

    Kummel, Andrew C.

    Ambient induced degradation and chemically activated recovery in copper phthalocyanine thin film 2009 The electrical degradation aging of copper phthalocyanine CuPc organic thin film transistors OTFTs layer.6,17,18 A systematic approach to iso- lating the cause of device degradation "aging" in copper

  15. AN ADAPTIVE MIXED SCHEME FOR ENERGY-TRANSPORT SIMULATIONS OF FIELD-EFFECT TRANSISTORS

    E-Print Network [OSTI]

    Pietra, Paola

    AN ADAPTIVE MIXED SCHEME FOR ENERGY-TRANSPORT SIMULATIONS OF FIELD-EFFECT TRANSISTORS #3; STEFAN HOLST, ANSGAR J  UNGEL y AND PAOLA PIETRA z Abstract. Energy-transport models are used in semiconductor and energy of the electrons, coupled to the Poisson equation for the electrostatic potential. The movement

  16. NPN RF Transistor This device is designed for use in low noise UHF/VHF amplifiers

    E-Print Network [OSTI]

    Berns, Hans-Gerd

    NPN RF Transistor This device is designed for use in low noise UHF/VHF amplifiers with collector currents in the 100 µA to 30 mA range in common emitter or common base mode of operation, and in low degrees C. 2) These are steady state limits. The factory should be consulted on applications involving

  17. Terahertz responsivity of field effect transistors versus their static channel conductivity and loading effects

    E-Print Network [OSTI]

    Levelut, Claire

    . Teppe,1 and W. Knap1 1 Laboratoire Charles Coulomb UMR 5221 and TERALAB, Universite´ Montpellier2 for terahertz imaging. This article gives prospects for electrical simulation of these transistors field is rectified like in square law detectors and a constant (dc) source-to-drain voltage appears

  18. DNA Sensing by Field-Effect Transistors Based on Networks of Carbon Nanotubes

    E-Print Network [OSTI]

    Rogers, John A.

    DNA Sensing by Field-Effect Transistors Based on Networks of Carbon Nanotubes Ee Ling Gui, Lain mechanism of electrical detection of deoxyribonucleic acid (DNA) hybridization for Au- and Cr level alignment between electrode and SWCNTs can be affected by DNA immobilization and hybridization

  19. 54 IRE TRANSACTIONS-CIRCUIT THEORY March Solution of a Transistor Transient Response Problem*

    E-Print Network [OSTI]

    Macdonald, James Ross

    of the response to a unit step or unit impulse (delta function) of voltage or current applied at the input54 IRE TRANSACTIONS-CIRCUIT THEORY March Solution of a Transistor Transient Response Problem* INTRODUCTION /7 OOD TRANSIENT response I J. R. MACDONALD? is desirable `in many k.J high

  20. Schottky-Drain Technology for AlGaN/GaN High-Electron Mobility Transistors

    E-Print Network [OSTI]

    Lu, Bin

    In this letter, we demonstrate 27% improvement in the buffer breakdown voltage of AlGaN/GaN high-electron mobility transistors (HEMTs) grown on Si substrate by using a new Schottky-drain contact technology. Schottky-drain ...

  1. Jet-printed electrodes and semiconducting oligomers for elaboration of organic thin-film transistors

    E-Print Network [OSTI]

    Hone, James

    demonstrated the possibility to fabricate inexpensive OTFTs by direct writing paving the way toward using candidates to make organic thin-film transistors (OTFTs) active components for the fab- rication of low-cost], and OTFT display backplanes [3]. However, the carrying out of OTFTs does not attain the low-cost expected

  2. Measuring bi-directional current through a field-effect transistor by virtue of drain-to-source voltage measurement

    DOE Patents [OSTI]

    Turner, Steven Richard

    2006-12-26T23:59:59.000Z

    A method and apparatus for measuring current, and particularly bi-directional current, in a field-effect transistor (FET) using drain-to-source voltage measurements. The drain-to-source voltage of the FET is measured and amplified. This signal is then compensated for variations in the temperature of the FET, which affects the impedance of the FET when it is switched on. The output is a signal representative of the direction of the flow of current through the field-effect transistor and the level of the current through the field-effect transistor. Preferably, the measurement only occurs when the FET is switched on.

  3. VARIABLE-ANGLE SPECTROSCOPIC ELLIPSOMETRY OF InAlP NATIVE OXIDE GATE DIELECTRIC LAYERS

    E-Print Network [OSTI]

    AlP-ox, In0.49Ga0.51P (InGaP), and InAlP have been determined by VASE measurements using a photon energy of the Optical Constants of InAlP-ox, InAlP, InGaP.......... 12 3.1 OverviewAlP and InGaP Optical Constants....................................... 26 Chapter 4: Characterizing

  4. THE GROWTH MECHANISMS OF ULTRATHIN GATE DIELECTRICS ON SILICON

    E-Print Network [OSTI]

    Gustafsson, Torgny

    in the passive oxidation regime, while etching in the active oxidation regime made the surface slightly rougher. A roughening regime is also observed in between the active and passive oxidation regimes and causes, I was fortunate to share a house with Alex See, from whom Qing-Tang heard about me and recruited me

  5. A real-time respiration position based passive breath gating equipment for gated radiotherapy: A preclinical evaluation

    SciTech Connect (OSTI)

    Hu Weigang; Xu Anjie; Li Guichao; Zhang Zhen; Housley, Dave; Ye Jinsong [Department of Radiation Oncology, Fudan University Shanghai Cancer Center and Department of Oncology, Shanghai Medical College, Fudan University, Shanghai 200032 (China); Department of Radiation Oncology, Swedish Cancer Institute, Seattle, Washington 98104 (United States)

    2012-03-15T23:59:59.000Z

    Purpose: To develop a passive gating system incorporating with the real-time position management (RPM) system for the gated radiotherapy. Methods: Passive breath gating (PBG) equipment, which consists of a breath-hold valve, a controller mechanism, a mouthpiece kit, and a supporting frame, was designed. A commercial real-time positioning management system was implemented to synchronize the target motion and radiation delivery on a linear accelerator with the patient's breathing cycle. The respiratory related target motion was investigated by using the RPM system for correlating the external markers with the internal target motion while using PBG for passively blocking patient's breathing. Six patients were enrolled in the preclinical feasibility and efficiency study of the PBG system. Results: PBG equipment was designed and fabricated. The PBG can be manually triggered or released to block or unblock patient's breathing. A clinical workflow was outlined to integrate the PBG with the RPM system. After implementing the RPM based PBG system, the breath-hold period can be prolonged to 15-25 s and the treatment delivery efficiency for each field can be improved by 200%-400%. The results from the six patients showed that the diaphragm motion caused by respiration was reduced to less than 3 mm and the position of the diaphragm was reproducible for difference gating periods. Conclusions: A RPM based PBG system was developed and implemented. With the new gating system, the patient's breath-hold time can be extended and a significant improvement in the treatment delivery efficiency can also be achieved.

  6. Experimental implementation of optimal linear-optical controlled-unitary gates

    E-Print Network [OSTI]

    Karel Lemr; Karol Bartkiewicz; Antonín ?ernoch; Miloslav Dušek; Jan Soubusta

    2014-10-16T23:59:59.000Z

    We show that it is possible to reduce the number of two-qubit gates needed for the construction of an arbitrary controlled-unitary transformation by up to two times using a tunable controlled-phase gate. On the platform of linear optics, where two-qubit gates can only be achieved probabilistically, our method significantly reduces the amount of components and increases success probability of a two-qubit gate. The experimental implementation of our technique presented in this paper for a controlled single-qubit unitary gate demonstrates that only one tunable controlled-phase gate is needed instead of two standard controlled-NOT gates. Thus, not only do we increase success probability by about one order of magnitude (with the same resources), but also avoid the need for conducting quantum non-demolition measurement otherwise required to join two probabilistic gates. Subsequently, we generalize our method to a higher order, showing that n-times controlled gates can be optimized by replacing blocks of controlled-NOT gates with tunable controlled-phase gates.

  7. Asphalt Oxidation Kinetics and Pavement Oxidation Modeling

    E-Print Network [OSTI]

    Jin, Xin

    2012-07-16T23:59:59.000Z

    Most paved roads in the United States are surfaced with asphalt. These asphalt pavements suffer from fatigue cracking and thermal cracking, aggravated by the oxidation and hardening of asphalt. This negative impact of asphalt oxidation on pavement...

  8. Mixing at 50 GHz using a single-walled carbon nanotube transistor Sami Rosenblatt,a

    E-Print Network [OSTI]

    McEuen, Paul L.

    . The nanotubes were contacted with 50-nm-thick Pd.4 For probing, pads were made with a 5 nm Cr adhesion layer, 50 nm Au, and 10 nm Au­Pd alloy. Evaporation of 10 nm of evaporated silicon dioxide for the gate insulator16 was fol- lowed by evaporation of 50 nm Al for the top gate electrode. The source-drain contact

  9. Effectiveness of Using Supply Voltage as Back-Gate Bias in Ground Plane SOI Chris H. Kim1

    E-Print Network [OSTI]

    Kim, Chris H.

    -gate insulator thickness (2nm) for low drain-to-back- gate capacitance and effective tuning of Vt. The front gateEffectiveness of Using Supply Voltage as Back-Gate Bias in Ground Plane SOI MOSFET's Chris H. Kim1 designer has to ensure that this forward bias current through the psub-nwell and drain-body junctions (Fig

  10. Presented at the 2003 USSD Annual Lecture, Charleston, South Carolina. April 2003. SPILLWAY GATE RELIABILITY IN THE CONTEXT OF

    E-Print Network [OSTI]

    Bowles, David S.

    and operations are listed and illustrated through their application to the Thames Flood Barrier gates

  11. Role of the dielectric for the charging dynamics of the dielectric/barrier interface in AlGaN/GaN based metal-insulator-semiconductor structures under forward gate bias stress

    SciTech Connect (OSTI)

    Lagger, P., E-mail: peter.lagger@infineon.com [Infineon Technologies Austria AG, Siemensstraße 2, 9500 Villach (Austria); Institute of Solid State Electronics, Vienna University of Technology, Floragasse 7, 1040 Wien (Austria); Steinschifter, P.; Reiner, M.; Stadtmüller, M.; Denifl, G.; Ostermaier, C. [Infineon Technologies Austria AG, Siemensstraße 2, 9500 Villach (Austria); Naumann, A.; Müller, J.; Wilde, L.; Sundqvist, J. [Fraunhofer IPMS-CNT, Königsbrücker Straße 178, 01099 Dresden (Germany); Pogany, D. [Institute of Solid State Electronics, Vienna University of Technology, Floragasse 7, 1040 Wien (Austria)

    2014-07-21T23:59:59.000Z

    The high density of defect states at the dielectric/III-N interface in GaN based metal-insulator-semiconductor structures causes tremendous threshold voltage drifts, ?V{sub th}, under forward gate bias conditions. A comprehensive study on different dielectric materials, as well as varying dielectric thickness t{sub D} and barrier thickness t{sub B}, is performed using capacitance-voltage analysis. It is revealed that the density of trapped electrons, ?N{sub it}, scales with the dielectric capacitance under spill-over conditions, i.e., the accumulation of a second electron channel at the dielectric/AlGaN barrier interface. Hence, the density of trapped electrons is defined by the charging of the dielectric capacitance. The scaling behavior of ?N{sub it} is explained universally by the density of accumulated electrons at the dielectric/III-N interface under spill-over conditions. We conclude that the overall density of interface defects is higher than what can be electrically measured, due to limits set by dielectric breakdown. These findings have a significant impact on the correct interpretation of threshold voltage drift data and are of relevance for the development of normally off and normally on III-N/GaN high electron mobility transistors with gate insulation.

  12. Current limiters based on silicon pillar un-gated FET for field emission application

    E-Print Network [OSTI]

    Niu, Ying, M. Eng. Massachusetts Institute of Technology

    2009-01-01T23:59:59.000Z

    This research investigates the use of vertical silicon ungated field effect transistors (FETs) as current limiters to individuallycontrol emission current in a field emitter and provide a simple solution to three problems ...

  13. Glow Discharge Characteristics of Non-thermal Microplasmas at above Atmospheric Pressures and their Applications in Microscale Plasma Transistors

    E-Print Network [OSTI]

    Wakim, Dani Ghassan

    2013-07-25T23:59:59.000Z

    A microscale plasma transistor capable of high speed switching was manufactured using microfabrication techniques and operated using microplasma discharges. Such a device has feature sizes on the order of 25 ?m, is robust against spikes in power...

  14. A compact transport and charge model for GaN-based high electron mobility transistors for RF applications

    E-Print Network [OSTI]

    Radhakrishna, Ujwal

    2013-01-01T23:59:59.000Z

    Gallium Nitride (GaN)-based high electron mobility transistors (HEMTs) are rapidly emerging as front-runners in high-power mm-wave circuit applications. For circuit design with current devices and to allow sensible future ...

  15. Galen Sasaki EE 361 University of Hawaii 1 Memory technologies

    E-Print Network [OSTI]

    Sasaki, Galen H.

    faster #12;Galen Sasaki EE 361 University of Hawaii 5 Components: CMOS drain source gate n-channel transistor drain source gate p-channel transistor gate = `1' --> close gate = `0' --> open gate = `1 · Write bit back after a read Capacitor Passive transistor Word line Bit line A cell Word line

  16. Galen Sasaki EE 361 University of Hawaii 1 Memory technologies

    E-Print Network [OSTI]

    Sasaki, Galen H.

    faster #12;3 Galen Sasaki EE 361 University of Hawaii 5 Components: CMOS drain source gate n-channel transistor drain source gate p-channel transistor gate = `1' --> close gate = `0' --> open gate = `1 · Write bit back after a read Capacitor Passive transistor Word line Bit line A

  17. Fast adiabatic qubit gates using only $?_z$ control

    E-Print Network [OSTI]

    John M. Martinis; Michael R. Geller

    2014-07-17T23:59:59.000Z

    A controlled-phase gate was demonstrated in superconducting Xmon transmon qubits with fidelity reaching 99.4%, relying on the adiabatic interaction between the |11> and |02> states. Here we explain the theoretical concepts behind this protocol that achieves fast gate times with only $\\sigma_z$ control of the Hamiltonian, based on a theory of non-linear mapping of state errors to a power spectral density and use of optimal window functions. With a solution given in the Fourier basis, optimization is shown to be straightforward for practical cases of an arbitrary state change and finite bandwidth of control signals. We find that errors below $10^{-4}$ are readily achievable for realistic control waveforms.

  18. Improved phase gate reliability in systems with neutral Ising anyons

    E-Print Network [OSTI]

    David J. Clarke; Kirill Shtengel

    2010-09-01T23:59:59.000Z

    Recent proposals using heterostructures of superconducting and either topologically insulating or semiconducting layers have been put forth as possible platforms for topological quantum computation. These systems are predicted to contain Ising anyons and share the feature of having only neutral edge excitations. In this note, we show that these proposals can be combined with the recently proposed "sack geometry" for implementation of a phase gate in order to conduct robust universal quantum computation. In addition, we propose a general method for adjusting edge tunneling rates in such systems, which is necessary for the control of interferometric devices. The error rate for the phase gate in neutral Ising systems is parametrically smaller than for a similar geometry in which the edge modes carry charge: it goes as $T^3$ rather than $T$ at low temperatures. At zero temperature, the phase variance becomes constant at long times rather than carrying a logarithmic divergence.

  19. Gate-Tunable Graphene Quantum Dot and Dirac Oscillator

    E-Print Network [OSTI]

    Abdelhadi Belouad; Ahmed Jellal; Youness Zahidi

    2015-05-29T23:59:59.000Z

    We obtain the solution of the Dirac equation in (2+1) dimensions in the presence of a constant magnetic field normal to the plane together with a two-dimensional Dirac-oscillator potential coupling. We study the energy spectrum of graphene quantum dot (QD) defined by electrostatic gates. We give discussions of our results based on different physical settings, whether the cyclotron frequency is similar or larger/smaller compared to the oscillator frequency. This defines an effective magnetic field that produces the effective quantized Landau levels. We study analytically such field in gate-tunable graphene QD and show that our structure allow us to control the valley degeneracy. Finally, we compare our results with already published work and also discuss the possible applications of such QD.

  20. Gate-Tunable Graphene Quantum Dot and Dirac Oscillator

    E-Print Network [OSTI]

    Belouad, Abdelhadi; Zahidi, Youness

    2015-01-01T23:59:59.000Z

    We obtain the solution of the Dirac equation in (2+1) dimensions in the presence of a constant magnetic field normal to the plane together with a two-dimensional Dirac-oscillator potential coupling. We study the energy spectrum of graphene quantum dot (QD) defined by electrostatic gates. We give discussions of our results based on different physical settings, whether the cyclotron frequency is similar or larger/smaller compared to the oscillator frequency. This defines an effective magnetic field that produces the effective quantized Landau levels. We study analytically such field in gate-tunable graphene QD and show that our structure allow us to control the valley degeneracy. Finally, we compare our results with already published work and also discuss the possible applications of such QD.

  1. Reducing the quantum computing overhead with complex gate distillation

    E-Print Network [OSTI]

    Guillaume Duclos-Cianci; David Poulin

    2014-03-20T23:59:59.000Z

    In leading fault-tolerant quantum computing schemes, accurate transformation are obtained by a two-stage process. In a first stage, a discrete, universal set of fault-tolerant operations is obtained by error-correcting noisy transformations and distilling resource states. In a second stage, arbitrary transformations are synthesized to desired accuracy by combining elements of this set into a circuit. Here, we present a scheme which merges these two stages into a single one, directly distilling complex transformations. We find that our scheme can reduce the total overhead to realize certain gates by up to a few orders of magnitude. In contrast to other schemes, this efficient gate synthesis does not require computationally intensive compilation algorithms, and a straightforward generalization of our scheme circumvents compilation and synthesis altogether.

  2. Two-dimensional electron gases in strained quantum wells for AlN/GaN/AlN double heterostructure field-effect transistors on AlN

    SciTech Connect (OSTI)

    Li, Guowang; Song, Bo; Ganguly, Satyaki; Zhu, Mingda; Wang, Ronghua; Yan, Xiaodong; Verma, Jai; Protasenko, Vladimir; Grace Xing, Huili; Jena, Debdeep, E-mail: djena@nd.edu [Department of Electrical Engineering, University of Notre Dame, Indiana 46556 (United States)

    2014-05-12T23:59:59.000Z

    Double heterostructures of strained GaN quantum wells (QWs) sandwiched between relaxed AlN layers provide a platform to investigate the quantum-confined electronic and optical properties of the wells. The growth of AlN/GaN/AlN heterostructures with varying GaN quantum well thicknesses on AlN by plasma molecular beam epitaxy (MBE) is reported. Photoluminescence spectra provide the optical signature of the thin GaN QWs. Reciprocal space mapping in X-ray diffraction shows that a GaN layer as thick as ?28 nm is compressively strained to the AlN layer underneath. The density of the polarization-induced two-dimensional electron gas (2DEG) in the undoped heterostructures increases with the GaN QW thickness, reaching ?2.5?×?10{sup 13}/cm{sup 2}. This provides a way to tune the 2DEG channel density without changing the thickness of the top barrier layer. Electron mobilities less than ?400 cm{sup 2}/Vs are observed, leaving ample room for improvement. Nevertheless, owing to the high 2DEG density, strained GaN QW field-effect transistors with MBE regrown ohmic contacts exhibit an on-current density ?1.4?A/mm, a transconductance ?280 mS/mm, and a cut off frequency f{sub T}?104?GHz for a 100-nm-gate-length device. These observations indicate high potential for high-speed radio frequency and high voltage applications that stand to benefit from the extreme-bandgap and high thermal conductivity of AlN.

  3. Entangling characterization of (SWAP)1/m and Controlled unitary gates

    E-Print Network [OSTI]

    Balakrishnan, S

    2008-01-01T23:59:59.000Z

    We study the entangling power and perfect entangler nature of (SWAP)1/m, for m>=1, and controlled unitary (CU) gates. It is shown that (SWAP)1/2 is the only perfect entangler in the family. On the other hand, a subset of CU which is locally equivalent to CNOT is identified. It is shown that the subset, which is a perfect entangler, must necessarily possess the maximum entangling power.

  4. Entangling characterization of (SWAP)1/m and Controlled unitary gates

    E-Print Network [OSTI]

    S. Balakrishnan; R. Sankaranarayanan

    2009-01-05T23:59:59.000Z

    We study the entangling power and perfect entangler nature of (SWAP)1/m, for m>=1, and controlled unitary (CU) gates. It is shown that (SWAP)1/2 is the only perfect entangler in the family. On the other hand, a subset of CU which is locally equivalent to CNOT is identified. It is shown that the subset, which is a perfect entangler, must necessarily possess the maximum entangling power.

  5. Photon-photon gates in Bose-Einstein condensates

    E-Print Network [OSTI]

    Arnaud Rispe; Bing He; Christoph Simon

    2010-09-30T23:59:59.000Z

    It has recently been shown that light can be stored in Bose-Einstein condensates for over a second. Here we propose a method for realizing a controlled phase gate between two stored photons. The photons are both stored in the ground state of the effective trapping potential inside the condensate. The collision-induced interaction is enhanced by adiabatically increasing the trapping frequency and by using a Feshbach resonance. A controlled phase shift of $\\pi$ can be achieved in one second.

  6. Polar Express Cards Can Only Exit Onto 3rd Ave at the Main Entry/Exit Gate, Not on 2nd Ave gate.

    E-Print Network [OSTI]

    Wagner, Diane

    Polar Express Cards Can Only Exit Onto 3rd Ave at the Main Entry/Exit Gate, Not on 2nd Ave gate Parking with UAF Polar Express Cards: Basic Explanation: Use Your Polar Express Card for Entry and Exit. Problems? If card entry doesn't work, just pull a normal parking ticket and stop in at the booth or main

  7. Gate dielectric degradation: Pre-existing vs. generated defects

    SciTech Connect (OSTI)

    Veksler, Dmitry, E-mail: Dmitry.Veksler@sematech.org, E-mail: gennadi.bersuker@sematech.org; Bersuker, Gennadi, E-mail: Dmitry.Veksler@sematech.org, E-mail: gennadi.bersuker@sematech.org [SEMATECH Inc., 257 Fuller Rd., Albany, New York 12203 (United States)

    2014-01-21T23:59:59.000Z

    We consider the possibility that degradation of the electrical characteristics of high-k gate stacks under low voltage stresses of practical interest is caused primarily by activation of pre-existing defects rather than generation of new ones. In nFETs in inversion, in particular, defect activation is suggested to be associated with the capture of an injected electron: in this charged state, defects can participate in a fast exchange of charge carriers with the carrier reservoir (substrate or gate electrode) that constitutes the physical process underlying a variety of electrical measurements. The degradation caused by the activation of pre-existing defects, as opposed to that of new defect generation, is both reversible and exhibits a tendency to saturate through the duration of stress. By using the multi-phonon assisted charge transport description, it is demonstrated that the trap activation concept allows reproducing a variety of experimental results including stress time dependency of the threshold voltage, leakage current, charge pumping current, and low frequency noise. Continuous, long-term degradation described by the power law time dependency is shown to be determined by the activation of defects located in the interfacial SiO{sub 2} layer of the high-k gate stacks. The findings of this study can direct process optimization efforts towards reduction of as-grown precursors of the charge trapping defects as the major factor affecting reliability.

  8. GATE Center for Automotive Fuel Cell Systems at Virginia Tech

    SciTech Connect (OSTI)

    Douglas Nelson

    2011-05-31T23:59:59.000Z

    The Virginia Tech GATE Center for Automotive Fuel Cell Systems (CAFCS) achieved the following objectives in support of the domestic automotive industry: â?¢ Expanded and updated fuel cell and vehicle technologies education programs; â?¢ Conducted industry directed research in three thrust areas â?? development and characterization of materials for PEM fuel cells; performance and durability modeling for PEM fuel cells; and fuel cell systems design and optimization, including hybrid and plug-in hybrid fuel cell vehicles; â?¢ Developed MS and Ph.D. engineers and scientists who are pursuing careers related to fuel cells and automotive applications; â?¢ Published research results that provide industry with new knowledge which contributes to the advancement of fuel cell and vehicle systems commercialization. With support from the Dept. of Energy, the CAFCS upgraded existing graduate course offerings; introduced a hands-on laboratory component that make use of Virginia Techâ??s comprehensive laboratory facilities, funded 15 GATE Fellowships over a five year period; and expanded our program of industry interaction to improve student awareness of challenges and opportunities in the automotive industry. GATE Center graduate students have a state-of-the-art research experience preparing them for a career to contribute to the advancement fuel cell and vehicle technologies.

  9. Use of dMLC for implementation of dynamic respiratory-gated radiation therapy

    SciTech Connect (OSTI)

    Pepin, Eric W.; Wu, Huanmei [Purdue School of Engineering Technology, IUPUI, Indianapolis, Indiana 46202 (United States)] [Purdue School of Engineering Technology, IUPUI, Indianapolis, Indiana 46202 (United States); Shirato, Hiroki [Hokkaido University School of Medicine, Sapporo 060-8638 (Japan)] [Hokkaido University School of Medicine, Sapporo 060-8638 (Japan)

    2013-10-15T23:59:59.000Z

    Purpose: To simulate and evaluate the use of dynamic multileaf collimators (dMLC) in respiratory gating to compensate for baseline drift.Methods: Tumor motion tracking data from 30 lung tumors over 322 treatment fractions was analyzed with the finite state model. A dynamic respiratory gating window was established in real-time by determining the average positions during the previous two end-of-expiration breathing phases and centering the dMLC aperture on a weighted average of these positions. A simulated dMLC with physical motion constraints was used in dynamic gating treatment simulations. Fluence maps were created to provide a statistical description of radiation delivery for each fraction. Duty cycle was also calculated for each fraction.Results: The average duty cycle was 2.3% greater under dynamic gating conditions. Dynamic gating also showed higher fluences and less tumor obstruction. Additionally, dynamic gating required fewer beam toggles and each delivery period was longer on average than with static gating.Conclusions: The use of dynamic gating showed better performance than static gating and the physical constraints of a dMLC were shown to not be an impediment to dynamic gating.

  10. Enhancement of thermal stability and water resistance in yttrium-doped GeO{sub 2}/Ge gate stack

    SciTech Connect (OSTI)

    Lu, Cimang, E-mail: cimang@adam.t.u-tokyo.ac.jp; Hyun Lee, Choong; Zhang, Wenfeng; Nishimura, Tomonori; Nagashio, Kosuke; Toriumi, Akira [Department of Materials Engineering, The University of Tokyo, 7-3-1 Hongo, Tokyo 113-8656 (Japan); JST, CREST, 7-3-1 Hongo, Tokyo 113-8656 (Japan)

    2014-03-03T23:59:59.000Z

    We have systematically investigated the material and electrical properties of yttrium-doped GeO{sub 2} (Y-GeO{sub 2}) on Germanium (Ge). A significant improvement of both thermal stability and water resistance were demonstrated by Y-GeO{sub 2}/Ge stack, compared to that of pure GeO{sub 2}/Ge stack. The excellent electrical properties of Y-GeO{sub 2}/Ge stacks with low D{sub it} were presented as well as enhancement of dielectric constant in Y-GeO{sub 2} layer, which is beneficial for further equivalent oxide thickness scaling of Ge gate stack. The improvement of thermal stability and water resistance are discussed both in terms of the Gibbs free energy lowering and network modification of Y-GeO{sub 2}.

  11. Photo-oxidation catalysts

    DOE Patents [OSTI]

    Pitts, J. Roland (Lakewood, CO); Liu, Ping (Irvine, CA); Smith, R. Davis (Golden, CO)

    2009-07-14T23:59:59.000Z

    Photo-oxidation catalysts and methods for cleaning a metal-based catalyst are disclosed. An exemplary catalyst system implementing a photo-oxidation catalyst may comprise a metal-based catalyst, and a photo-oxidation catalyst for cleaning the metal-based catalyst in the presence of light. The exposure to light enables the photo-oxidation catalyst to substantially oxidize absorbed contaminants and reduce accumulation of the contaminants on the metal-based catalyst. Applications are also disclosed.

  12. Nanoporous carbon tunable resistor/transistor and methods of production thereof

    DOE Patents [OSTI]

    Biener, Juergen; Baumann, Theodore F; Dasgupta, Subho; Hahn, Horst

    2014-04-22T23:59:59.000Z

    In one embodiment, a tunable resistor/transistor includes a porous material that is electrically coupled between a source electrode and a drain electrode, wherein the porous material acts as an active channel, an electrolyte solution saturating the active channel, the electrolyte solution being adapted for altering an electrical resistance of the active channel based on an applied electrochemical potential, wherein the active channel comprises nanoporous carbon arranged in a three-dimensional structure. In another embodiment, a method for forming the tunable resistor/transistor includes forming a source electrode, forming a drain electrode, and forming a monolithic nanoporous carbon material that acts as an active channel and selectively couples the source electrode to the drain electrode electrically. In any embodiment, the electrolyte solution saturating the nanoporous carbon active channel is adapted for altering an electrical resistance of the nanoporous carbon active channel based on an applied electrochemical potential.

  13. Thin film transistors on plastic substrates with reflective coatings for radiation protection

    DOE Patents [OSTI]

    Wolfe, Jesse D. (Fairfield, CA); Theiss, Steven D. (Woodbury, MN); Carey, Paul G. (Mountain View, CA); Smith, Patrick M. (San Ramon, CA); Wickbold, Paul (Walnut Creek, CA)

    2006-09-26T23:59:59.000Z

    Fabrication of silicon thin film transistors (TFT) on low-temperature plastic substrates using a reflective coating so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The TFT can be used in large area low cost electronics, such as flat panel displays and portable electronics such as video cameras, personal digital assistants, and cell phones.

  14. Thin film transistors on plastic substrates with reflective coatings for radiation protection

    DOE Patents [OSTI]

    Wolfe, Jesse D.; Theiss, Steven D.; Carey, Paul G.; Smith, Patrick M.; Wickboldt, Paul

    2003-11-04T23:59:59.000Z

    Fabrication of silicon thin film transistors (TFT) on low-temperature plastic substrates using a reflective coating so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The TFT can be used in large area low cost electronics, such as flat panel displays and portable electronics such as video cameras, personal digital assistants, and cell phones.

  15. The fabrication and characteristics of a Vertical V-grove Field-Effect Transistor

    E-Print Network [OSTI]

    Simpson, Dale Alan

    1980-01-01T23:59:59.000Z

    for a higher transconductance and cutoff frequency which is a paradox. Lower channel resistance results in higher depletion region capacitance and vice versa. Dacey and Ross kept the channel resistance high in order to keep the pinch-off potential... Effect Transistor, JFET, has seen many improvements. Several have been the result of silicon technology which has taken noisy discrete JFETs and turned them into high yield, integrated devices. Finer line widths and proper optimization have further...

  16. The influence of a doping profile on the characteristics of an ion-implanted GaAs field-effect transistor with a Schottky barrier

    SciTech Connect (OSTI)

    Shestakov, A. K., E-mail: shestakov@thermo.isp.nsc.ru; Zhuravlev, K. S. [Russian Academy of Sciences, Rzhanov Institute of Semiconductor Physics, Siberian Branch (Russian Federation)

    2011-12-15T23:59:59.000Z

    A GaAs field-effect ion-implanted transistor with a Schottky barrier is simulated. The doping profile obtained when doping through an insulator mask is determined and the dependences of the static transistor characteristics on the parameters of the doping profile are calculated and analyzed. The physical processes controlling the transistor characteristics in the case of a variation in the parameters of its doping profile and the coefficient of compensation of the substrate are studied. Based on calculations, the optimal doping-profile parameters ensuring the best characteristics for transistors are predicted.

  17. Operator-Schmidt decomposition and the geometrical edges of two-qubit gates

    E-Print Network [OSTI]

    S. Balakrishnan; R. Sankaranarayanan

    2011-06-30T23:59:59.000Z

    Nonlocal two-qubit quantum gates are represented by canonical decomposition or equivalently by operator-Schmidt decomposition. The former decomposition results in geometrical representation such that all the two-qubit gates form tetrahedron within which perfect entanglers form a polyhedron. On the other hand, it is known from the later decomposition that Schmidt number of nonlocal gates can be either 2 or 4. In this work, some aspects of later decomposition are investigated. It is shown that two gates differing by local operations possess same set of Schmidt coefficients. Employing geometrical method, it is established that Schmidt number 2 corresponds to controlled unitary gates. Further, all the edges of tetrahedron and polyhedron are characterized using Schmidt strength, a measure of operator entanglement. It is found that one edge of the tetrahedron possesses the maximum Schmidt strength, implying that all the gates in the edge are maximally entangled.

  18. Operator-Schmidt decomposition and the geometrical edges of two-qubit gates

    E-Print Network [OSTI]

    Balakrishnan, S

    2010-01-01T23:59:59.000Z

    Nonlocal two-qubit quantum gates are represented by canonical decomposition or equivalently by operator-Schmidt decomposition. The former decomposition results in geometrical representation such that all the two-qubit gates form tetrahedron within which perfect entanglers form a polyhedron. On the other hand, it is known from the later decomposition that Schmidt number of nonlocal gates can be either 2 or 4. In this work, some aspects of later decomposition are investigated. It is shown that two gates differing by local operations possess same set of Schmidt coefficients. Employing geometrical method, it is established that Schmidt number 2 corresponds to controlled unitary gates. Further, all the edges of tetrahedron and polyhedron are characterized using Schmidt strength, a measure of operator entanglement. It is found that one edge of the tetrahedron possesses the maximum Schmidt strength, implying that all the gates in the edge are maximally entangled.

  19. Use of a hard mask for formation of gate and dielectric via nanofilament field emission devices

    DOE Patents [OSTI]

    Morse, Jeffrey D. (Martinez, CA); Contolini, Robert J. (Lake Oswego, OR)

    2001-01-01T23:59:59.000Z

    A process for fabricating a nanofilament field emission device in which a via in a dielectric layer is self-aligned to gate metal via structure located on top of the dielectric layer. By the use of a hard mask layer located on top of the gate metal layer, inert to the etch chemistry for the gate metal layer, and in which a via is formed by the pattern from etched nuclear tracks in a trackable material, a via is formed by the hard mask will eliminate any erosion of the gate metal layer during the dielectric via etch. Also, the hard mask layer will protect the gate metal layer while the gate structure is etched back from the edge of the dielectric via, if such is desired. This method provides more tolerance for the electroplating of a nanofilament in the dielectric via and sharpening of the nanofilament.

  20. Modulation and amplification of radiative far field heat transfer : towards a simple radiative thermal transistor

    E-Print Network [OSTI]

    Joulain, Karl; Drevillon, Jeremie; Ben-Abdallah, Philippe

    2015-01-01T23:59:59.000Z

    We show in this article that phase change materials (PCM) exhibiting a phase transition between a dielectric state and a metallic state are good candidates to perform modulation as well as amplification of radiative thermal flux. We propose a simple situation in plane parallel geometry where a so-called radiative thermal transistor could be achieved. In this configuration, we put a PCM between two blackbodies at different temperatures. We show that the transistor effect can be achieved easily when this material has its critical temperature between the two blackbody temperatures. We also see, that the more the material is reflective in the metallic state, the more switching effect is realized whereas the more PCM transition is stiff in temperature, the more thermal amplification is high. We finally take the example of VO2 that exhibits an insulator-metallic transition at 68{\\textdegree}C. We show that a demonstrator of a radiative transistor could easily be achieved in view of the heat flux levels predicted. F...