National Library of Energy BETA

Sample records for transistor gate oxide

  1. Looking at Transistor Gate Oxide Formation in Real Time

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Looking at Transistor Gate Oxide Formation in Real Time Print The oxide gate layer is critical to every transistor, and present-day layer thicknesses are in the 10-20 range (1-2...

  2. Characterization and production metrology of thin transistor gate oxide lms

    E-Print Network [OSTI]

    Garfunkel, Eric

    Review Characterization and production metrology of thin transistor gate oxide ®lms Alain C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 4. XRR and NR characterization of thin oxide ®lms . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 5.2. Optical models of thin gate ®lms

  3. Looking at Transistor Gate Oxide Formation in Real Time

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    using this beamline were able to chart the rate of oxidation of silicon in the gate oxide layer for the first time. Understanding the rate of oxidation in this crucial layer...

  4. Looking at Transistor Gate Oxide Formation in Real Time

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    AFDC Printable Version Share this resource Send a link to EERE: Alternative Fuels Data Center Home Page to someone by E-mail Share EERE: Alternative Fuels Data Center Home Page on Facebook Tweet about EERE: Alternative Fuels Data Center Home Page on Twitter Bookmark EERE: Alternative Fuels Data Center Homesum_a_epg0_fpd_mmcf_m.xls" ,"Available from WebQuantityBonneville Power Administration would likeUniverseIMPACTThousand CubicResourcelogo and-E CChinaC L SLooking at Transistor Gate

  5. Looking at Transistor Gate Oxide Formation in Real Time

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    AFDC Printable Version Share this resource Send a link to EERE: Alternative Fuels Data Center Home Page to someone by E-mail Share EERE: Alternative Fuels Data Center Home Page on Facebook Tweet about EERE: Alternative Fuels Data Center Home Page on Twitter Bookmark EERE: Alternative Fuels Data Center Homesum_a_epg0_fpd_mmcf_m.xls" ,"Available from WebQuantityBonneville Power Administration would likeUniverseIMPACTThousand CubicResourcelogo and-E CChinaC L SLooking at Transistor

  6. Looking at Transistor Gate Oxide Formation in Real Time

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    AFDC Printable Version Share this resource Send a link to EERE: Alternative Fuels Data Center Home Page to someone by E-mail Share EERE: Alternative Fuels Data Center Home Page on Facebook Tweet about EERE: Alternative Fuels Data Center Home Page on Twitter Bookmark EERE: Alternative Fuels Data Center Homesum_a_epg0_fpd_mmcf_m.xls" ,"Available from WebQuantityBonneville Power Administration would likeUniverseIMPACTThousand CubicResourcelogo and-E CChinaC L SLooking at TransistorLooking

  7. Top-gate zinc tin oxide thin-film transistors with high bias and environmental stress stability

    SciTech Connect (OSTI)

    Fakhri, M.; Theisen, M.; Behrendt, A.; Görrn, P.; Riedl, T. [Institute of Electronic Devices, University of Wuppertal, Wuppertal 42119 (Germany)

    2014-06-23

    Top gated metal-oxide thin-film transistors (TFTs) provide two benefits compared to their conventional bottom-gate counterparts: (i) The gate dielectric may concomitantly serve as encapsulation layer for the TFT channel. (ii) Damage of the dielectric due to high-energetic particles during channel deposition can be avoided. In our work, the top-gate dielectric is prepared by ozone based atomic layer deposition at low temperatures. For ultra-low gas permeation rates, we introduce nano-laminates of Al{sub 2}O{sub 3}/ZrO{sub 2} as dielectrics. The resulting TFTs show a superior environmental stability even at elevated temperatures. Their outstanding stability vs. bias stress is benchmarked against bottom-gate devices with encapsulation.

  8. Recovery from ultraviolet-induced threshold voltage shift in indium gallium zinc oxide thin film transistors by positive gate bias

    SciTech Connect (OSTI)

    Liu, P.; Chen, T. P.; Li, X. D.; Wong, J. I.; Liu, Z.; Liu, Y.; Leong, K. C.

    2013-11-11

    The effect of short-duration ultraviolet (UV) exposure on the threshold voltage (V{sub th}) of amorphous indium gallium zinc oxide thin film transistors (TFTs) and its recovery characteristics were investigated. The V{sub th} exhibited a significant negative shift after UV exposure. The V{sub th} instability caused by UV illumination is attributed to the positive charge trapping in the dielectric layer and/or at the channel/dielectric interface. The illuminated devices showed a slow recovery in threshold voltage without external bias. However, an instant recovery can be achieved by the application of positive gate pulses, which is due to the elimination of the positive trapped charges as a result of the presence of a large amount of field-induced electrons in the interface region.

  9. Advanced insulated gate bipolar transistor gate drive

    DOE Patents [OSTI]

    Short, James Evans (Monongahela, PA); West, Shawn Michael (West Mifflin, PA); Fabean, Robert J. (Donora, PA)

    2009-08-04

    A gate drive for an insulated gate bipolar transistor (IGBT) includes a control and protection module coupled to a collector terminal of the IGBT, an optical communications module coupled to the control and protection module, a power supply module coupled to the control and protection module and an output power stage module with inputs coupled to the power supply module and the control and protection module, and outputs coupled to a gate terminal and an emitter terminal of the IGBT. The optical communications module is configured to send control signals to the control and protection module. The power supply module is configured to distribute inputted power to the control and protection module. The control and protection module outputs on/off, soft turn-off and/or soft turn-on signals to the output power stage module, which, in turn, supplies a current based on the signal(s) from the control and protection module for charging or discharging an input capacitance of the IGBT.

  10. High Performance Electrolyte Gated Carbon Nanotube Transistors

    E-Print Network [OSTI]

    Gore, Jeff

    High Performance Electrolyte Gated Carbon Nanotube Transistors Sami Rosenblatt, Yuval Yaish, Jiwoong Park,, Jeff Gore, Vera Sazonova, and Paul L. McEuen*, Laboratory of Atomic and Solid State Physics to grow the tubes, annealing to improve the contacts, and an electrolyte as a gate, we obtain very high

  11. Electroluminescence in ion gel gated organic polymer semiconductor transistors

    E-Print Network [OSTI]

    Bhat, Shrivalli

    2011-07-12

    This thesis reports the light emission in ion gel gated, thin film organic semiconductor transistors and investigates the light emission mechanism behind these devices. We report that ion gel gated organic polymer semiconductor transistors emit...

  12. High mobility field effect transistor based on BaSnO{sub 3} with Al{sub 2}O{sub 3} gate oxide

    SciTech Connect (OSTI)

    Park, Chulkwon; Kim, Useong; Ju, Chan Jong; Park, Ji Sung; Kim, Young Mo; Char, Kookrin

    2014-11-17

    We fabricated an n-type accumulation-mode field effect transistor based on BaSnO{sub 3} transparent perovskite semiconductor, taking advantage of its high mobility and oxygen stability. We used the conventional metal-insulator-semiconductor structures: (In,Sn){sub 2}O{sub 3} as the source, drain, and gate electrodes, Al{sub 2}O{sub 3} as the gate insulator, and La-doped BaSnO{sub 3} as the semiconducting channel. The Al{sub 2}O{sub 3} gate oxide was deposited by atomic layer deposition technique. At room temperature, we achieved the field effect mobility value of 17.8?cm{sup 2}/Vs and the I{sub on}/I{sub off} ratio value higher than 10{sup 5} for V{sub DS}?=?1?V. These values are higher than those previously reported on other perovskite oxides, in spite of the large density of threading dislocations in the BaSnO{sub 3} on SrTiO{sub 3} substrates. However, a relatively large subthreshold swing value was found, which we attribute to the large density of charge traps in the Al{sub 2}O{sub 3} as well as the threading dislocations.

  13. Electron-beam patterning of polymer electrolyte films to make multiple nanoscale gates for nanowire transistors

    E-Print Network [OSTI]

    D. J. Carrad; A. M. Burke; R. W. Lyttleton; H. J. Joyce; H. H. Tan; C. Jagadish; K. Storm; H. Linke; L. Samuelson; A. P. Micolich

    2014-04-08

    We report an electron-beam based method for the nanoscale patterning of the poly(ethylene oxide)/LiClO$_{4}$ polymer electrolyte. We use the patterned polymer electrolyte as a high capacitance gate dielectric in single nanowire transistors and obtain subthreshold swings comparable to conventional metal/oxide wrap-gated nanowire transistors. Patterning eliminates gate/contact overlap which reduces parasitic effects and enables multiple, independently controllable gates. The method's simplicity broadens the scope for using polymer electrolyte gating in studies of nanowires and other nanoscale devices.

  14. Graphene arch gate SiO2 shell silicon nanowire core field effect transistors

    E-Print Network [OSTI]

    Hwang, Sung Woo

    graphene into more complementary metal oxide semiconductor (CMOS)-friendly architectures. FurthermoreGraphene arch gate SiO2 shell silicon nanowire core field effect transistors J. E. Jin, J. H. Lee) metal-semiconductor field-effect transistors on single-crystal -Ga2O3 (010) substrates Appl. Phys. Lett

  15. Characterization of the gate oxide of an AlGaN/GaN high electron mobility transistor

    E-Print Network [OSTI]

    Florida, University of

    2011; published online 21 March 2011 A subnanometer thick interfacial oxide layer present between used to characterize a Ni/AlGaN interfacial oxide layer with subnanometer thickness. The semiconducting

  16. The Difficulty of Gate Control in Molecular Transistors

    E-Print Network [OSTI]

    D. Hou; J. H. Wei

    2011-09-27

    The electrostatic gating effects on molecular transistors are investigated using the density functional theory (DFT) combined with the nonequilibrium Green's function (NEGF) method. When molecular energy levels are away from the Fermi energy they can be linearly shifted by the gate voltage, which is consistent with recent experimental observations [Nature 462, 1039 (2009)]. However, when they move near to the Fermi energy (turn-on process), the shifts become extremely small and almost independent of the gate voltage. The fact that the conductance may be beyond the gate control in the "ON" state will challenge the implementation of molecular transistors.

  17. Electron-electron scattering-induced channel hot electron injection in nanoscale n-channel metal-oxide-semiconductor field-effect-transistors with high-k/metal gate stacks

    SciTech Connect (OSTI)

    Tsai, Jyun-Yu; Liu, Kuan-Ju; Lu, Ying-Hsin; Liu, Xi-Wen [Department of Physics, National Sun Yat-Sen University, Kaohsiung, Taiwan (China); Chang, Ting-Chang [Department of Physics, National Sun Yat-Sen University, Kaohsiung, Taiwan (China); Advanced Optoelectronics Technology Center, National Cheng Kung University, Tainan, Taiwan (China); Chen, Ching-En; Ho, Szu-Han; Tseng, Tseung-Yuen [Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan (China); Cheng, Osbert; Huang, Cheng-Tung; Lu, Ching-Sen [Device Department, United Microelectronics Corporation, Tainan Science Park, Tainan, Taiwan (China)

    2014-10-06

    This work investigates electron-electron scattering (EES)-induced channel hot electron (CHE) injection in nanoscale n-channel metal-oxide-semiconductor field-effect-transistors (n-MOSFETs) with high-k/metal gate stacks. Many groups have proposed new models (i.e., single-particle and multiple-particle process) to well explain the hot carrier degradation in nanoscale devices and all mechanisms focused on Si-H bond dissociation at the Si/SiO{sub 2} interface. However, for high-k dielectric devices, experiment results show that the channel hot carrier trapping in the pre-existing high-k bulk defects is the main degradation mechanism. Therefore, we propose a model of EES-induced CHE injection to illustrate the trapping-dominant mechanism in nanoscale n-MOSFETs with high-k/metal gate stacks.

  18. Design, Simulation and Modeling of Insulated Gate Bipolar Transistor 

    E-Print Network [OSTI]

    Gupta, Kaustubh

    2013-07-09

    The market for Insulated Gate Bipolar Transistor (IGBT) is growing and there is a need for techniques to improve the design, modeling and simulation of IGBT. In this thesis, we first developed a new method to optimize the layout and dimensions...

  19. Proton conducting sodium alginate electrolyte laterally coupled low-voltage oxide-based transistors

    SciTech Connect (OSTI)

    Liu, Yang Hui; Wan, Qing; Qiang Zhu, Li; Shi, Yi

    2014-03-31

    Solution-processed sodium alginate electrolyte film shows a high proton conductivity of ?5.5?×?10{sup ?3} S/cm and a high lateral electric-double-layer (EDL) capacitance of ?2.0??F/cm{sup 2} at room temperature with a relative humidity of 57%. Low-voltage in-plane-gate indium-zinc-oxide-based EDL transistors laterally gated by sodium alginate electrolytes are fabricated on glass substrates. The field-effect mobility, current ON/OFF ratio, and subthreshold swing of such EDL transistors are estimated to be 4.2 cm{sup 2} V{sup ?1} s{sup ?1}, 2.8?×?10{sup 6}, and 130?mV/decade, respectively. At last, a low-voltage driven resistor-load inverter is also demonstrated. Such in-plane-gate EDL transistors have potential applications in portable electronics and low-cost biosensors.

  20. Quantum Insights in Gate Oxide Charge-Trapping Dynamics in Nanoscale MOSFETs

    E-Print Network [OSTI]

    Dimov, Ivan

    , in this paper we investigate the trapping of a single electron in the gate oxide of a 25nm transistor including and scattering phenomena. Keywords--Reliability; Tunneling; Scattering; NBTI; RTN; Wigner Function; charge-trapping. The evolution of an initial electron packet subject to the action of device channel potential and the oxide trap

  1. Electrolyte-gated graphene field-effect transistors : modeling and applications

    E-Print Network [OSTI]

    Mackin, Charles Edward

    2015-01-01

    This work presents a model for electrolyte-gated graphene field-effect transistors (EGFETs) that incorporates the effects of the double layer capacitance and the quantum capacitance of graphene. The model is validated ...

  2. Influence of Electrolyte Composition on Liquid-Gated Carbon Nanotube and Graphene Transistors

    E-Print Network [OSTI]

    Dekker, Cees

    Influence of Electrolyte Composition on Liquid-Gated Carbon Nanotube and Graphene Transistors Iddo-walled carbon nanotubes (SWNTs) and graphene can function as highly sensitive nanoscale (bio)sensors in solution. Here, we compare experimentally how SWNT and graphene transistors respond to changes in the composition

  3. Piezoelectric Potential Gated Field-Effect Transistor Based on a Free-Standing

    E-Print Network [OSTI]

    Huang, Yanyi

    -standing piezoelectric FET has potential applications like hearing aids, atomic force microscopy (AFM) cantileversPiezoelectric Potential Gated Field-Effect Transistor Based on a Free-Standing ZnO Wire Peng Fei report an external force triggered field-effect transistor based on a free-standing piezoelectric fine

  4. Graphene field-effect transistors based on boron nitride gate dielectrics Inanc Meric1

    E-Print Network [OSTI]

    Shepard, Kenneth

    Graphene field-effect transistors based on boron nitride gate dielectrics Inanc Meric1 , Cory Dean1, 10027 Tel: (212) 854-2529, Fax: (212) 932-9421, Email: shepard@ee.columbia.edu Abstract Graphene field of graphene, as the gate dielectric. The devices ex- hibit mobility values exceeding 10,000 cm2 /V

  5. High performance electrolyte-gated carbon nanotube transistors Sami Rosenblatt1

    E-Print Network [OSTI]

    McEuen, Paul L.

    1 High performance electrolyte-gated carbon nanotube transistors Sami Rosenblatt1 , Yuval Yaish1 , Jiwoong Park1,2 , Jeff Gore2 , Vera Sazonova1 , and Paul L. McEuen1 1 Laboratory of Atomic and Solid State, annealing to improve the contacts, and an electrolyte as a gate, we obtain very high device mobilites

  6. Hafnium-doped tantalum oxide high-k gate dielectric films for future CMOS technology 

    E-Print Network [OSTI]

    Lu, Jiang

    2007-04-25

    A novel high-k gate dielectric material, i.e., hafnium-doped tantalum oxide (Hf-doped TaOx), has been studied for the application of the future generation metal-oxidesemiconductor field effect transistor (MOSFET). The film's electrical, chemical...

  7. Coherent molecular transistor: Control through variation of the gate wave function

    SciTech Connect (OSTI)

    Ernzerhof, Matthias

    2014-03-21

    In quantum interference transistors (QUITs), the current through the device is controlled by variation of the gate component of the wave function that interferes with the wave function component joining the source and the sink. Initially, mesoscopic QUITs have been studied and more recently, QUITs at the molecular scale have been proposed and implemented. Typically, in these devices the gate lead is subjected to externally adjustable physical parameters that permit interference control through modifications of the gate wave function. Here, we present an alternative model of a molecular QUIT in which the gate wave function is directly considered as a variable and the transistor operation is discussed in terms of this variable. This implies that we specify the gate current as well as the phase of the gate wave function component and calculate the resulting current through the source-sink channel. Thus, we extend on prior works that focus on the phase of the gate wave function component as a control parameter while having zero or certain discrete values of the current. We address a large class of systems, including finite graphene flakes, and obtain analytic solutions for how the gate wave function controls the transistor.

  8. Ambipolar graphene field effect transistors by local metal side gates J. F. Tian,1,2,a

    E-Print Network [OSTI]

    Chen, Yong P.

    the Dirac point where the valence and conduction bands meet, making graphene a zero-gap semiconductor. BothAmbipolar graphene field effect transistors by local metal side gates J. F. Tian,1,2,a L. A ambipolar graphene field effect transistors individually controlled by local metal side gates. The side

  9. Choosing a gate dielectric for graphene based transistors

    E-Print Network [OSTI]

    Hsu, Pei-Lan, M. Eng. Massachusetts Institute of Technology

    2008-01-01

    Much attention has recently been focused on graphene as an alternative semiconductor to silicon. Transistors with graphene conduction channels have only recently been fabricated and their performance remains to be optimized. ...

  10. Low-frequency electronic noise in the double-gate single-layer graphene transistors

    E-Print Network [OSTI]

    Low-frequency electronic noise in the double-gate single-layer graphene transistors G. Liu,1 W The authors report the results of an experimental investigation of the low-frequency noise in the double by 20 nm of HfO2 from the single-layer graphene channels. The measurements revealed low flicker noise

  11. High-performance carbon-nanotube-based complementary field-effect-transistors and integrated circuits with yttrium oxide

    SciTech Connect (OSTI)

    Liang, Shibo; Zhang, Zhiyong, E-mail: zyzhang@pku.edu.cn; Si, Jia; Zhong, Donglai; Peng, Lian-Mao, E-mail: lmpeng@pku.edu.cn [Key Laboratory for the Physics and Chemistry of Nanodevices, Department of Electronics, Peking University, Beijing 100871 (China)

    2014-08-11

    High-performance p-type carbon nanotube (CNT) transistors utilizing yttrium oxide as gate dielectric are presented by optimizing oxidization and annealing processes. Complementary metal-oxide-semiconductor (CMOS) field-effect-transistors (FETs) are then fabricated on CNTs, and the p- and n-type devices exhibit symmetrical high performances, especially with low threshold voltage near to zero. The corresponding CMOS CNT inverter is demonstrated to operate at an ultra-low supply voltage down to 0.2?V, while displaying sufficient voltage gain, high noise margin, and low power consumption. Yttrium oxide is proven to be a competitive gate dielectric for constructing high-performance CNT CMOS FETs and integrated circuits.

  12. Dirac point and transconductance of top-gated graphene field-effect transistors operating at elevated temperature

    SciTech Connect (OSTI)

    Hopf, T.; Vassilevski, K. V., E-mail: k.vasilevskiy@ncl.ac.uk; Escobedo-Cousin, E.; King, P. J.; Wright, N. G.; O'Neill, A. G.; Horsfall, A. B.; Goss, J. P. [School of Electrical and Electronic Engineering, Newcastle University, Newcastle upon Tyne NE1 7RU (United Kingdom); Wells, G. H.; Hunt, M. R. C. [Department of Physics, Durham University, Durham DH1 3LE (United Kingdom)

    2014-10-21

    Top-gated graphene field-effect transistors (GFETs) have been fabricated using bilayer epitaxial graphene grown on the Si-face of 4H-SiC substrates by thermal decomposition of silicon carbide in high vacuum. Graphene films were characterized by Raman spectroscopy, Atomic Force Microscopy, Scanning Tunnelling Microscopy, and Hall measurements to estimate graphene thickness, morphology, and charge transport properties. A 27?nm thick Al?O? gate dielectric was grown by atomic layer deposition with an e-beam evaporated Al seed layer. Electrical characterization of the GFETs has been performed at operating temperatures up to 100?°C limited by deterioration of the gate dielectric performance at higher temperatures. Devices displayed stable operation with the gate oxide dielectric strength exceeding 4.5 MV/cm at 100?°C. Significant shifting of the charge neutrality point and an increase of the peak transconductance were observed in the GFETs as the operating temperature was elevated from room temperature to 100?°C.

  13. Suspended InAs nanowire gate-all-around field-effect transistors

    SciTech Connect (OSTI)

    Li, Qiang; Huang, Shaoyun, E-mail: syhuang@pku.edu.cn, E-mail: hqxu@pku.edu.cn; Wang, Jingyun [Key Laboratory for the Physics and Chemistry of Nanodevices and Department of Electronics, Peking University, Beijing 100871 (China); Pan, Dong; Zhao, Jianhua [State Key Laboratory for Superlattices and Microstructures, Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083 (China); Xu, H. Q., E-mail: syhuang@pku.edu.cn, E-mail: hqxu@pku.edu.cn [Key Laboratory for the Physics and Chemistry of Nanodevices and Department of Electronics, Peking University, Beijing 100871 (China); Division of Solid-State Physics, Lund University, Box 118, Lund S-221 00 (Sweden)

    2014-09-15

    Gate-all-around field-effect transistors are realized with thin, single-crystalline, pure-phase InAs nanowires grown by molecular beam epitaxy. At room temperature, the transistors show a desired high on-state current I{sub on} of ?10??A and an on-off current ratio I{sub on}/I{sub off} of as high as 10{sup 6} at source-drain bias voltage of 50?mV and gate length of 1??m with a gate underlap spacing of 1??m from the source and from the drain. At low temperatures, the on-state current I{sub on} is only slightly reduced, while the ratio I{sub on}/I{sub off} is increased to 10{sup 7}. The field-effect mobility in the nanowire channels is also investigated and found to be ?1500?cm{sup 2}/V s at room temperature and ?2000?cm{sup 2}/V s at low temperatures. The excellent performance of the transistors is explained in terms of strong electrostatic and quantum confinements of carriers in the nanowires.

  14. Surface mobility near threshold and other parameters of insulated gate field effect transistors

    E-Print Network [OSTI]

    Gnadinger, Alfred P.

    1970-01-01

    in detail. The IGFETs are made on standard 1­V diameter n­type silicon wafers with a starting resistivity of 3 ­ 7 ohm­cm corresponding to a 1 fx ~3 1 s —3 doping density of 7 x 10 cm to 1.5 x 10 cm . After cleaning, the... MOBILITY NEAR THRESHOLD AND OTHER PARAMETERS OF INSULATED GATE FIELD EFFECT TRANSISTORS BY Alfred P. Gnadinger Dipl. El. Ing. ETH Swiss Federal Institute of Technology, Zurich, 1965 M.S.E.E, University of Kansas, Lawrence, 1968 Submitted to the Department of Electrical v Engineering...

  15. Naphthacene Based Organic Thin Film Transistor With Rare Earth Oxide

    SciTech Connect (OSTI)

    Konwar, K. [Department of Physics, Digboi College, Digboi-786171, Assam (India); Baishya, B. [Department of Physics, Dibrugarh University, Dibrugarh-786004, Assam (India)

    2010-12-01

    Naphthacene based organic thin film transistors (OTFTs) have been fabricated using La{sub 2}O{sub 3}, as the gate insulator. All the OTFTs have been fabricated by the process of thermal evaporation in vacuum on perfectly cleaned glass substrates with aluminium as source-drain and gate electrodes. The naphthacene film morphology on the glass substrate has been studied by XRD and found to be polycrystalline in nature. The field effect mobility, output resistance, amplification factor, transconductance and gain bandwidth product of the OTFTs have been calculated by using theoretical TFT model. The highest value of field effect mobility is found to be 0.07x10{sup -3} cm{sup 2}V{sup -1}s{sup -1} for the devices annealed in vacuum at 90 deg. C for 5 hours.

  16. Double-metal-gate nanocrystalline Si thin film transistors with flexible threshold voltage controllability

    SciTech Connect (OSTI)

    Chiou, Uio-Pu; Pan, Fu-Ming, E-mail: fmpan@faculty.nctu.edu.tw [Department of Materials Science and Engineering, National Chiao-Tung University, Hsinchu 30050, Taiwan (China)] [Department of Materials Science and Engineering, National Chiao-Tung University, Hsinchu 30050, Taiwan (China); Shieh, Jia-Min, E-mail: jmshieh@narlabs.org.tw, E-mail: jmshieh@faculty.nctu.edu.tw [National Nano Device Laboratories, No. 26, Prosperity Road 1, Hsinchu 30078, Taiwan (China) [National Nano Device Laboratories, No. 26, Prosperity Road 1, Hsinchu 30078, Taiwan (China); Departments of Photonics and Institute of Electro-Optical Engineering, National Chiao-Tung University, Hsinchu 30010, Taiwan (China); Yang, Chih-Chao [National Nano Device Laboratories, No. 26, Prosperity Road 1, Hsinchu 30078, Taiwan (China)] [National Nano Device Laboratories, No. 26, Prosperity Road 1, Hsinchu 30078, Taiwan (China); Huang, Wen-Hsien [Department of Materials Science and Engineering, National Chiao-Tung University, Hsinchu 30050, Taiwan (China) [Department of Materials Science and Engineering, National Chiao-Tung University, Hsinchu 30050, Taiwan (China); National Nano Device Laboratories, No. 26, Prosperity Road 1, Hsinchu 30078, Taiwan (China); Kao, Yo-Tsung [Departments of Photonics and Institute of Electro-Optical Engineering, National Chiao-Tung University, Hsinchu 30010, Taiwan (China)] [Departments of Photonics and Institute of Electro-Optical Engineering, National Chiao-Tung University, Hsinchu 30010, Taiwan (China)

    2013-11-11

    We fabricated nano-crystalline Si (nc-Si:H) thin-film transistors (TFTs) with a double-metal-gate structure, which showed a high electron-mobility (?{sub FE}) and adjustable threshold voltages (V{sub th}). The nc-Si:H channel and source/drain (S/D) of the multilayered TFT were deposited at 375?°C by inductively coupled plasma chemical vapor deposition. The low grain-boundary defect density of the channel layer is responsible for the high ?{sub FE} of 370 cm{sup 2}/V-s, a steep subthreshold slope of 90?mV/decade, and a low V{sub th} of ?0.64?V. When biased with the double-gate driving mode, the device shows a tunable V{sub th} value extending from ?1?V up to 2.7?V.

  17. Contact resistance improvement using interfacial silver nanoparticles in amorphous indium-zinc-oxide thin film transistors

    SciTech Connect (OSTI)

    Xu, Rui; He, Jian [School of Engineering, Brown University, Providence, Rhode Island 02912 (United States); State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China (UESTC), Chengdu 610054 (China); Song, Yang [Department of Physics, Brown University, Providence, Rhode Island 02912 (United States); Li, Wei [State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China (UESTC), Chengdu 610054 (China); Zaslavsky, A. [School of Engineering, Brown University, Providence, Rhode Island 02912 (United States); Department of Physics, Brown University, Providence, Rhode Island 02912 (United States); Paine, D. C., E-mail: David-Paine@brown.edu [School of Engineering, Brown University, Providence, Rhode Island 02912 (United States)

    2014-09-01

    We describe an approach to reduce the contact resistance at compositional conducting/semiconducting indium-zinc-oxide (IZO) homojunctions used for contacts in thin film transistors (TFTs). By introducing silver nanoparticles (Ag NPs) at the homojunction interface between the conducting IZO electrodes and the amorphous IZO channel, we reduce the specific contact resistance, obtained by transmission line model measurements, down to ?10{sup ?2?}??cm{sup 2}, ?3 orders of magnitude lower than either NP-free homojunction contacts or solid Ag metal contacts. The resulting back-gated TFTs with Ag NP contacts exhibit good field effect mobility of ?27?cm{sup 2}/V?s and an on/off ratio >10{sup 7}. We attribute the improved contact resistance to electric field concentration by the Ag NPs.

  18. A Strained Organic Field-Effect-Transistor with a Gate-Tunable Superconducting Channel

    E-Print Network [OSTI]

    Hiroshi M. Yamamoto; Masaki Nakano; Masayuki Suda; Yoshihiro Iwasa; Masashi Kawasaki; Reizo Kato

    2013-09-02

    In state-of-the-art silicon devices, mobility of the carrier is enhanced by the lattice strain from the back substrate. Such an extra control of device performance is significant in realizing high performance computing and should be valid for electric-field-induced superconducting devices, too. However, so far, the carrier density is the sole parameter for field-induced superconducting interfaces. Here we show an active organic superconducting field-effect-transistor whose lattice is modulated by the strain from the substrate. The soft organic lattice allows tuning of the strain by a choice of the back substrate to make an induced superconducting state accessible at low temperature with a paraelectric solid gate. An active three terminal Josephson junction device thus realized is useful both in advanced computing and in elucidating a direct connection between filling-controlled and bandwidth-controlled superconducting phases in correlated materials.

  19. Light-induced hysteresis and recovery behaviors in photochemically activated solution-processed metal-oxide thin-film transistors

    SciTech Connect (OSTI)

    Jo, Jeong-Wan; Park, Sung Kyu E-mail: skpark@cau.ac.kr; Kim, Yong-Hoon E-mail: skpark@cau.ac.kr

    2014-07-28

    In this report, photo-induced hysteresis, threshold voltage (V{sub T}) shift, and recovery behaviors in photochemically activated solution-processed indium-gallium-zinc oxide (IGZO) thin-film transistors (TFTs) are investigated. It was observed that a white light illumination caused negative V{sub T} shift along with creation of clockwise hysteresis in electrical characteristics which can be attributed to photo-generated doubly ionized oxygen vacancies at the semiconductor/gate dielectric interface. More importantly, the photochemically activated IGZO TFTs showed much reduced overall V{sub T} shift compared to thermally annealed TFTs. Reduced number of donor-like interface states creation under light illumination and more facile neutralization of ionized oxygen vacancies by electron capture under positive gate potential are claimed to be the origin of the less V{sub T} shift in photochemically activated TFTs.

  20. Si and SiGe based double top gated accumulation mode single electron transistors for quantum bits.

    SciTech Connect (OSTI)

    Wendt, Joel Robert; Ten Eyck, Gregory A.; Childs, Kenton David; Celler, G. (SOITEC); Eng, Kevin; Eriksson, Mark A. (University of Wisconsin); Kluskiewicz, Dan (University of New Mexico); Stevens, Jeffrey; Carroll, Malcolm S.; Nordberg, Eric; Lilly, Michael Patrick; Lemp, Thomas; Sheng, Josephine Juin-Jye

    2008-10-01

    There is significant interest in forming quantum bits (qubits) out of single electron devices for quantum information processing (QIP). Information can be encoded using properties like charge or spin. Spin is appealing because it is less strongly coupled to the solid-state environment so it is believed that the quantum state can better be preserved over longer times (i.e., that is longer decoherence times may be achieved). Long spin decoherence times would allow more complex qubit operations to be completed with higher accuracy. Recently spin qubits were demonstrated by several groups using electrostatically gated modulation doped GaAs double quantum dots (DQD) [1], which represented a significant breakthrough in the solid-state field. Although no Si spin qubit has been demonstrated to date, work on Si and SiGe based spin qubits is motivated by the observation that spin decoherence times can be significantly longer than in GaAs. Spin decoherence times in GaAs are in part limited by the random spectral diffusion of the non-zero nuclear spins of the Ga and As that couple to the electron spin through the hyperfine interaction. This effect can be greatly suppressed by using a semiconductor matrix with a near zero nuclear spin background. Near zero nuclear spin backgrounds can be engineered using Si by growing {sup 28}Si enriched epitaxy. In this talk, we will present fabrication details and electrical transport results of an accumulation mode double top gated Si metal insulator semiconductor (MIS) nanostructure, Fig 1 (a) & (b). We will describe how this single electron device structure represent a path towards forming a Si based spin qubit similar in design as that demonstrated in GaAs. Potential advantages of this novel qubit structure relative to previous approaches include the combination of: no doping (i.e., not modulation doped); variable two-dimensional electron gas (2DEG) density; CMOS compatible processes; and relatively small vertical length scales to achieve smaller dots. A primary concern in this structure is defects at the insulator-silicon interface. The Sandia National Laboratories 0.35 {micro}m fab line was used for critical processing steps including formation of the gate oxide to examine the utility of a standard CMOS quality oxide silicon interface for the purpose of fabricating Si qubits. Large area metal oxide silicon (MOS) structures showed a peak mobility of 15,000 cm{sup 2}/V-s at electron densities of {approx}1 x 10{sup 12} cm{sup -2} for an oxide thickness of 10 nm. Defect density measured using standard C-V techniques was found to be greater with decreasing oxide thickness suggesting a device design trade-off between oxide thickness and quantum dot size. The quantum dot structure is completed using electron beam lithography and poly-silicon etch to form the depletion gates, Fig 1 (a). The accumulation gate is added by introducing a second insulating Al{sub 2}O{sub 3} layer, deposited by atomic layer deposition, followed by an Al top gate deposition, Fig. 1 (b). Initial single electron transistor devices using SiO{sub 2} show significant disorder in structures with relatively large critical dimensions of the order of 200-300 nm, Fig 2. This is not uncommon for large silicon structures and has been cited in the literature [2]. Although smaller structures will likely minimize the effect of disorder and well controlled small Si SETs have been demonstrated [3], the design constraints presented by disorder combined with long term concerns about effects of defects on spin decoherence time (e.g., paramagnetic centers) motivates pursuit of a 2nd generation structure that uses a compound semiconductor approach, an epitaxial SiGe barrier as shown in Fig. 2 (c). SiGe may be used as an electron barrier when combined with tensilely strained Si. The introduction of strained-Si into the double top gated device structure, however, represents additional fabrication challenges. Thermal budget is potentially constrained due to concerns related to strain relaxation. Fabrication details related to the introduction of st

  1. Looking at Transistor Gate Oxide Formation in Real Time

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    and S.-K Kim (Seoul National University, Korea). Research funding: the U.S. Department of Energy; the Humboldt Foundation (Germany); the Helmholtz Association (Germany); the...

  2. Looking at Transistor Gate Oxide Formation in Real Time

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    AFDC Printable Version Share this resource Send a link to EERE: Alternative Fuels Data Center Home Page to someone by E-mail Share EERE: Alternative Fuels Data Center Home Page on Facebook Tweet about EERE: Alternative Fuels Data Center Home Page on Twitter Bookmark EERE: Alternative Fuels Data Center Homesum_a_epg0_fpd_mmcf_m.xls" ,"Available from WebQuantity ofkandz-cm11 Outreach Home Room NewsInformationJesse BergkampCenter (LMI-EFRC)Lodging LodgingLogisticsLong-Term

  3. Looking at Transistor Gate Oxide Formation in Real Time

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    AFDC Printable Version Share this resource Send a link to EERE: Alternative Fuels Data Center Home Page to someone by E-mail Share EERE: Alternative Fuels Data Center Home Page on Facebook Tweet about EERE: Alternative Fuels Data Center Home Page on Twitter Bookmark EERE: Alternative Fuels Data Center Homesum_a_epg0_fpd_mmcf_m.xls" ,"Available from WebQuantity ofkandz-cm11 Outreach Home Room NewsInformationJesse BergkampCenter (LMI-EFRC)Lodging LodgingLogisticsLong-TermLooking at

  4. Looking at Transistor Gate Oxide Formation in Real Time

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    AFDC Printable Version Share this resource Send a link to EERE: Alternative Fuels Data Center Home Page to someone by E-mail Share EERE: Alternative Fuels Data Center Home Page on Facebook Tweet about EERE: Alternative Fuels Data Center Home Page on Twitter Bookmark EERE: Alternative Fuels Data Center Homesum_a_epg0_fpd_mmcf_m.xls" ,"Available from WebQuantity ofkandz-cm11 Outreach Home Room NewsInformationJesse BergkampCenter (LMI-EFRC)Lodging LodgingLogisticsLong-TermLooking

  5. Looking at Transistor Gate Oxide Formation in Real Time

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    AFDC Printable Version Share this resource Send a link to EERE: Alternative Fuels Data Center Home Page to someone by E-mail Share EERE: Alternative Fuels Data Center Home Page on Facebook Tweet about EERE: Alternative Fuels Data Center Home Page on Twitter Bookmark EERE: Alternative Fuels Data Center Homesum_a_epg0_fpd_mmcf_m.xls" ,"Available from WebQuantityBonneville Power Administration would likeUniverseIMPACTThousand CubicResourcelogo and-E CChinaC L SLooking at

  6. Looking at Transistor Gate Oxide Formation in Real Time

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    AFDC Printable Version Share this resource Send a link to EERE: Alternative Fuels Data Center Home Page to someone by E-mail Share EERE: Alternative Fuels Data Center Home Page on Facebook Tweet about EERE: Alternative Fuels Data Center Home Page on Twitter Bookmark EERE: Alternative Fuels Data Center Homesum_a_epg0_fpd_mmcf_m.xls" ,"Available from WebQuantityBonneville Power Administration would likeUniverseIMPACTThousand CubicResourcelogo and-E CChinaC L SLooking atLooking at

  7. Physics of gate leakage current in N-polar InAlN/GaN heterojunction field effect transistors

    SciTech Connect (OSTI)

    Goswami, Arunesh; Trew, Robert J.; Bilbro, Griff L.

    2014-10-28

    A physics based model of the gate leakage current in N-polar InAlN/GaN heterojunction field effect transistors is demonstrated. The model is based on the space charge limited current flow dominated by the effects of deep traps in the InAlN surface layer. The model predicts accurately the gate-leakage measurement data of the N-polar InAlN/GaN device with InAlN cap layer. In the pinch-off state, the gate leakage current conduction through the surface of the device in the drain access region dominates the current flow through the two dimensional electron gas channel. One deep trap level and two levels of shallow traps are extracted by fitting the model results with measurement data.

  8. Tradeoffs between Gate Oxide Leakage and Delay for Dual ToxToxTox Circuits

    E-Print Network [OSTI]

    Sapatnekar, Sachin

    lead to gate oxide leakage current (Igate), are coming into play from the 90nm node onwards. AccordingTradeoffs between Gate Oxide Leakage and Delay for Dual ToxToxTox Circuits Anup Kumar Sultania Department of ECE University of Minnesota Minneapolis, MN 55455. sachin@ece.umn.edu ABSTRACT Gate oxide

  9. Reconciliation of Different Gate-Voltage Dependencies of 1/f Noise in n-MOS and p-MOS Transistors

    E-Print Network [OSTI]

    Scofield, John H.

    approaches the valence band edge. It is evidently these differences in Dt(E) that lead to differences noise of metal- oxide-semiconductor field-effect transistors (MOSFETs) suggests that their noise of the noise of many fluctuators leads to the ubiquitous inverse frequency dependence commonly observed

  10. Thin Film Transistors On Plastic Substrates

    DOE Patents [OSTI]

    Carey, Paul G. (Mountain View, CA); Smith, Patrick M. (San Ramon, CA); Sigmon, Thomas W. (Portola Valley, CA); Aceves, Randy C. (Livermore, CA)

    2004-01-20

    A process for formation of thin film transistors (TFTs) on plastic substrates replaces standard thin film transistor fabrication techniques, and uses sufficiently lower processing temperatures so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The silicon based thin film transistor produced by the process includes a low temperature substrate incapable of withstanding sustained processing temperatures greater than about 250.degree. C., an insulating layer on the substrate, a layer of silicon on the insulating layer having sections of doped silicon, undoped silicon, and poly-silicon, a gate dielectric layer on the layer of silicon, a layer of gate metal on the dielectric layer, a layer of oxide on sections of the layer of silicon and the layer of gate metal, and metal contacts on sections of the layer of silicon and layer of gate metal defining source, gate, and drain contacts, and interconnects.

  11. Schottky barrier source-gated ZnO thin film transistors by low temperature atomic layer deposition

    SciTech Connect (OSTI)

    Ma, Alex M.; Gupta, Manisha; Shoute, Gem; Tsui, Ying Y.; Barlage, Douglas W., E-mail: barlage@ualberta.ca [Department of Electrical and Computer Engineering, University of Alberta, Edmonton, Alberta T6G 2V4 (Canada); Afshar, Amir; Cadien, Kenneth C. [Department of Chemical and Materials Engineering, University of Alberta, Edmonton, Alberta T6G 2V4 (Canada)] [Department of Chemical and Materials Engineering, University of Alberta, Edmonton, Alberta T6G 2V4 (Canada)

    2013-12-16

    We have fabricated ZnO source-gated thin film transistors (SGTFTs) with a buried TiW source Schottky barrier and a top gate contact. The ZnO active channel and thin high-? HfO{sub 2} dielectric utilized are both grown by atomic layer deposition at temperatures less than 130?°C, and their material and electronic properties are characterized. These SGTFTs demonstrate enhancement-mode operation with a threshold voltage of 0.91?V, electron mobility of 3.9 cm{sup 2} V{sup ?1} s{sup ?1}, and low subthreshold swing of 192?mV/decade. The devices also exhibit a unique combination of high breakdown voltages (>20?V) with low output conductances.

  12. Low-voltage and hysteresis-free organic thin-film transistors employing solution-processed hybrid bilayer gate dielectrics

    SciTech Connect (OSTI)

    Ha, Tae-Jun [Department of Electronic Materials Engineering, Kwangwoon University, Seoul 139-701 (Korea, Republic of)

    2014-07-28

    This study presents a promising approach to realize low-voltage (<3?V) organic thin-film transistors (OTFTs) exhibiting improved electrical and optical stability. Such device performance results from the use of solution-processed hybrid bilayer gate dielectrics consisting of zirconium dioxide (high-k dielectric) and amorphous fluoropolymer, CYTOP{sup ®} (low-k dielectric). Employing a very thin amorphous fluoropolymer film reduces interfacial defect-states by repelling water molecules and other aqueous chemicals from an organic semiconductor active layer due to the hydrophobic surface-property. The chemically clean interface, stemming from decrease in density of trap states improves all the key device properties such as field-effect mobility, threshold voltage, and sub-threshold swing. Furthermore, degradation by electrical bias-stress and photo-induced hysteresis were suppressed in OTFTs employing hybrid bilayer gate dielectrics.

  13. Palladium nanoparticle decorated silicon nanowire field-effect transistor with side-gates for hydrogen gas detection

    SciTech Connect (OSTI)

    Ahn, Jae-Hyuk; Yun, Jeonghoon; Park, Inkyu; KI for the NanoCentury, KAIST, Daejeon 305-701; Mobile Sensor and IT Convergence Center, KAIST, Daejeon 305-701 ; Choi, Yang-Kyu

    2014-01-06

    A silicon nanowire field-effect transistor (SiNW FET) with local side-gates and Pd surface decoration is demonstrated for hydrogen (H{sub 2}) detection. The SiNW FETs are fabricated by top-down method and functionalized with palladium nanoparticles (PdNPs) through electron beam evaporation for H{sub 2} detection. The drain current of the PdNP-decorated device reversibly responds to H{sub 2} at different concentrations. The local side-gates allow individual addressing of each sensor and enhance the sensitivity by adjusting the working region to the subthreshold regime. A control experiment using a non-functionalized device verifies that the hydrogen-sensitivity is originated from the PdNPs functionalized on the SiNW surface.

  14. Interpretation of electron beam induced charging of oxide layers in a transistor studied using electron holography

    E-Print Network [OSTI]

    Dunin-Borkowski, Rafal E.

    Interpretation of electron beam induced charging of oxide layers in a transistor studied using in the electron beam direction. The technique offers the prospect of mapping dopant potentials in semiconductors electron beam irradiation in the TEM. Here we attempt to understand the magnitude, location

  15. L{sub g}?=?100?nm In{sub 0.7}Ga{sub 0.3}As quantum well metal-oxide semiconductor field-effect transistors with atomic layer deposited beryllium oxide as interfacial layer

    SciTech Connect (OSTI)

    Koh, D., E-mail: dh.koh@utexas.edu, E-mail: Taewoo.Kim@sematech.org [Department of Electrical and Computer Engineering, Microelectronics Research Center, The University of Texas at Austin, Austin, Texas 78758 (United States); SEMATECH, Inc., Albany, New York 12203 (United States); Kwon, H. M. [Department of Electronics Engineering, Chungnam National University, Daejeon 305-764 (Korea, Republic of); Kim, T.-W., E-mail: dh.koh@utexas.edu, E-mail: Taewoo.Kim@sematech.org; Veksler, D.; Gilmer, D.; Kirsch, P. D. [SEMATECH, Inc., Albany, New York 12203 (United States); Kim, D.-H. [SEMATECH, Inc., Albany, New York 12203 (United States); GLOBALFOUNDRIES, Malta, New York 12020 (United States); Hudnall, Todd W. [Department of Chemistry and Biochemistry, Texas State University, San Marcos, Texas, 78666 (United States); Bielawski, Christopher W. [Department of Chemistry and Biochemistry, The University of Texas at Austin, Austin, Texas 78712 (United States); Maszara, W. [GLOBALFOUNDRIES, Santa Clara, California 95054 (United States); Banerjee, S. K. [Department of Electrical and Computer Engineering, Microelectronics Research Center, The University of Texas at Austin, Austin, Texas 78758 (United States)

    2014-04-21

    In this study, we have fabricated nanometer-scale channel length quantum-well (QW) metal-oxide-semiconductor field effect transistors (MOSFETs) incorporating beryllium oxide (BeO) as an interfacial layer. BeO has high thermal stability, excellent electrical insulating characteristics, and a large band-gap, which make it an attractive candidate for use as a gate dielectric in making MOSFETs. BeO can also act as a good diffusion barrier to oxygen owing to its small atomic bonding length. In this work, we have fabricated In{sub 0.53}Ga{sub 0.47}As MOS capacitors with BeO and Al{sub 2}O{sub 3} and compared their electrical characteristics. As interface passivation layer, BeO/HfO{sub 2} bilayer gate stack presented effective oxide thickness less 1 nm. Furthermore, we have demonstrated In{sub 0.7}Ga{sub 0.3}As QW MOSFETs with a BeO/HfO{sub 2} dielectric, showing a sub-threshold slope of 100?mV/dec, and a transconductance (g{sub m,max}) of 1.1 mS/?m, while displaying low values of gate leakage current. These results highlight the potential of atomic layer deposited BeO for use as a gate dielectric or interface passivation layer for III–V MOSFETs at the 7?nm technology node and/or beyond.

  16. Charging dynamics of a floating gate transistor with site-controlled quantum dots

    SciTech Connect (OSTI)

    Maier, P. Hartmann, F.; Emmerling, M.; Schneider, C.; Höfling, S.; Kamp, M.; Worschech, L.

    2014-08-04

    A quantum dot memory based on a GaAs/AlGaAs quantum wire with site-controlled InAs quantum dots was realized by means of molecular beam epitaxy and etching techniques. By sampling of different gate voltage sweeps for the determination of charging and discharging thresholds, it was found that discharging takes place at short time scales of ?s, whereas several seconds of waiting times within a distinct negative gate voltage range were needed to charge the quantum dots. Such quantum dot structures have thus the potential to implement logic functions comprising charge and time dependent ingredients such as counting of signals or learning rules.

  17. Molybdenum as a contact material in zinc tin oxide thin film transistors

    SciTech Connect (OSTI)

    Hu, W.; Peterson, R. L., E-mail: blpeters@umich.edu [Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, Michigan 48109-2122 (United States)

    2014-05-12

    Amorphous oxide semiconductors are of increasing interest for a variety of thin film electronics applications. Here, the contact properties of different source/drain electrode materials to solution-processed amorphous zinc tin oxide (ZTO) thin-film transistors are studied using the transmission line method. The width-normalized contact resistance between ZTO and sputtered molybdenum is measured to be 8.7 ?-cm, which is 10, 20, and 600 times smaller than that of gold/titanium, indium tin oxide, and evaporated molybdenum electrodes, respectively. The superior contact formed using sputtered molybdenum is due to a favorable work function lineup, an insulator-free interface, bombardment of ZTO during molybdenum sputtering, and trap-assisted tunneling. The transfer length of the sputtered molybdenum/ZTO contact is 0.34??m, opening the door to future radio-frequency sub-micron molybdenum/ZTO thin film transistors.

  18. Dual operation characteristics of resistance random access memory in indium-gallium-zinc-oxide thin film transistors

    SciTech Connect (OSTI)

    Yang, Jyun-Bao; Chen, Yu-Ting; Chu, Ann-Kuo [Department of Photonics, National Sun Yat-Sen University, Kaohsiung, Taiwan (China); Chang, Ting-Chang, E-mail: tcchang@mail.phys.nsysu.edu.tw [Department of Photonics, National Sun Yat-Sen University, Kaohsiung, Taiwan (China); Department of Physics, National Sun Yat-Sen University, Kaohsiung, Taiwan (China); Advanced Optoelectronics Technology Center, National Cheng Kung University, Taiwan (China); Huang, Jheng-Jie; Chen, Yu-Chun; Tseng, Hsueh-Chih [Department of Physics, National Sun Yat-Sen University, Kaohsiung, Taiwan (China); Sze, Simon M. [Department of Physics, National Sun Yat-Sen University, Kaohsiung, Taiwan (China); Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan (China)

    2014-04-14

    In this study, indium-gallium-zinc-oxide thin film transistors can be operated either as transistors or resistance random access memory devices. Before the forming process, current-voltage curve transfer characteristics are observed, and resistance switching characteristics are measured after a forming process. These resistance switching characteristics exhibit two behaviors, and are dominated by different mechanisms. The mode 1 resistance switching behavior is due to oxygen vacancies, while mode 2 is dominated by the formation of an oxygen-rich layer. Furthermore, an easy approach is proposed to reduce power consumption when using these resistance random access memory devices with the amorphous indium-gallium-zinc-oxide thin film transistor.

  19. Gate Length Reduction Technology for Pseudomorphic In0:52Al0:48As/In0:7Ga0:3As High Electron Mobility Transistors

    E-Print Network [OSTI]

    Seo, Kwang Seok

    Gate Length Reduction Technology for Pseudomorphic In0:52Al0:48As/In0:7Ga0:3As High Electron, 2006; accepted November 29, 2006; published online April 24, 2007) Gate length reduction technology was developed for pseudomorphic high-electron-mobility transistors (P-HEMTs) applicable to nano

  20. High-Performance Contacts in Plastic Transistors and Logic Gates That Use Printed Electrodes of

    E-Print Network [OSTI]

    Rogers, John A.

    be difficult to achieve with conventional inorganic materials and processing technologies. Progress associated with chemical incom- patibilities that commonly arise in solution-processed multi- layer plastic. The devices use flexible poly(ethylene terephthalate) (PET; 175 lm thick) substrates, indium tin oxide (ITO

  1. Thermal Activation and Quantum Field Emission in a Sketch-Based Oxide Nano Transistor

    E-Print Network [OSTI]

    Cheng Cen; Daniela Bogorin; Jeremy Levy

    2010-09-13

    We report direct measurements of the potential barriers and electronic coupling between nanowire segments within a sketch-based oxide nanotransistor (SketchFET) device. Near room temperature, switching is governed by thermally activation across a potential barrier controlled by the nanowire gate. Below T=150 K, a crossover to quantum field emission is observed that is sensitive to structural phase transitions in the SrTiO3 layer. This direct measurement of the source-drain and gate-drain energy barriers is crucial for the development of room-temperature logic and memory elements and low-temperature quantum devices.

  2. Effect of edge roughness on electronic transport in graphene nanoribbon channel metal-oxide-semiconductor field-effect transistors

    E-Print Network [OSTI]

    Gilbert, Matthew

    Effect of edge roughness on electronic transport in graphene nanoribbon channel metal-oxide-semiconductor on transport in graphene nanoribbon metal-oxide-semiconductor field-effect transistors MOSFETs are reported of Physics. DOI: 10.1063/1.2839330 Graphene has recently generated considerable interest as a semiconductor

  3. Alumina nanoparticle/polymer nanocomposite dielectric for flexible amorphous indium-gallium-zinc oxide thin film transistors on plastic substrate with superior stability

    SciTech Connect (OSTI)

    Lai, Hsin-Cheng [Department of Electrical Engineering, National Chung Hsing University, Taichung 40227, Taiwan (China); Pei, Zingway, E-mail: zingway@dragon.nchu.edu.tw [Department of Electrical Engineering, National Chung Hsing University, Taichung 40227, Taiwan (China); Graduate Institute of Optoelectronic Engineering, National Chung Hsing University, Taichung 40227, Taiwan (China); Center of Nanoscience and Nanotechnology, National Chung Hsing University, Taichung 40227, Taiwan (China); Jian, Jyun-Ruri; Tzeng, Bo-Jie [Graduate Institute of Optoelectronic Engineering, National Chung Hsing University, Taichung 40227, Taiwan (China)

    2014-07-21

    In this study, the Al{sub 2}O{sub 3} nanoparticles were incorporated into polymer as a nono-composite dielectric for used in a flexible amorphous Indium-Gallium-Zinc Oxide (a-IGZO) thin-film transistor (TFT) on a polyethylene naphthalate substrate by solution process. The process temperature was well below 100?°C. The a-IGZO TFT exhibit a mobility of 5.13?cm{sup 2}/V s on the flexible substrate. After bending at a radius of 4?mm (strain?=?1.56%) for more than 100 times, the performance of this a-IGZO TFT was nearly unchanged. In addition, the electrical characteristics are less altered after positive gate bias stress at 10?V for 1500?s. Thus, this technology is suitable for use in flexible displays.

  4. Abstract--Bias temperature instability, hot-carrier injection, and gate-oxide wearout will cause severe lifetime degradation in

    E-Print Network [OSTI]

    Lipasti, Mikko H.

    affect device performance and lead to timing violations; as well as gate-oxide wearout [3] which can probability of oxide breakdown, leading to a hard failure of a device that exceeds its intended (or targetedAbstract--Bias temperature instability, hot-carrier injection, and gate-oxide wearout will cause

  5. Radiation-hardened transistor and integrated circuit

    DOE Patents [OSTI]

    Ma, Kwok K. (Albuquerque, NM)

    2007-11-20

    A composite transistor is disclosed for use in radiation hardening a CMOS IC formed on an SOI or bulk semiconductor substrate. The composite transistor has a circuit transistor and a blocking transistor connected in series with a common gate connection. A body terminal of the blocking transistor is connected only to a source terminal thereof, and to no other connection point. The blocking transistor acts to prevent a single-event transient (SET) occurring in the circuit transistor from being coupled outside the composite transistor. Similarly, when a SET occurs in the blocking transistor, the circuit transistor prevents the SET from being coupled outside the composite transistor. N-type and P-type composite transistors can be used for each and every transistor in the CMOS IC to radiation harden the IC, and can be used to form inverters and transmission gates which are the building blocks of CMOS ICs.

  6. Effect of varying gate-drain distance on the RF power performance of pseudomorphic high electron mobility transistors

    E-Print Network [OSTI]

    Wong, Melinda F

    2005-01-01

    AIGaAs/lnGaAs Pseudomorphic High Electron Mobility Transistors (PHEMTs) are widely used in satellite communications, military and commercial radar, cellular telephones, and other RF power applications. One key figure of ...

  7. Real-time detection of mercury ions in water using a reduced graphene oxide/DNA field-effect transistor with assistance of a passivation layer

    DOE Public Access Gateway for Energy & Science Beta (PAGES Beta)

    Chang, Jingbo; Zhou, Guihua; Gao, Xianfeng; Mao, Shun; Cui, Shumao; Ocola, Leonidas E.; Yuan, Chris; Chen, Junhong

    2015-08-01

    Field-effect transistor (FET) sensors based on reduced graphene oxide (rGO) for detecting chemical species provide a number of distinct advantages, such as ultrasensitivity, label-free, and real-time response. However, without a passivation layer, channel materials directly exposed to an ionic solution could generate multiple signals from ionic conduction through the solution droplet, doping effect, and gating effect. Therefore, a method that provides a passivation layer on the surface of rGO without degrading device performance will significantly improve device sensitivity, in which the conductivity changes solely with the gating effect. In this work, we report rGO FET sensor devices with Hg2+-dependent DNAmore »as a probe and the use of an Al2O3 layer to separate analytes from conducting channel materials. The device shows good electronic stability, excellent lower detection limit (1 nM), and high sensitivity for real-time detection of Hg2+ in an underwater environment. Our work shows that optimization of an rGO FET structure can provide significant performance enhancement and profound fundamental understanding for the sensor mechanism.« less

  8. Self-Aligned, Extremely High Frequency III-V Metal-Oxide-Semiconductor Field-Effect Transistors on Rigid and Flexible

    E-Print Network [OSTI]

    Javey, Ali

    Self-Aligned, Extremely High Frequency III-V Metal-Oxide- Semiconductor Field-Effect Transistors. The results demonstrate the potential of III-V-on-insulator platform for extremely high-frequency (EHF mobility transistors (HEMTs).15-20 The record-high cutoff frequency (ft) for InAs-based HEMTs has already

  9. New SRAM Cell Design for Low Power and High Reliability using 32nm Independent Gate FinFET Technology

    E-Print Network [OSTI]

    Ayers, Joseph

    gate voltage (VGb). This is similar to the body effect in a bulk transistor. An independent-gate Fin

  10. Effect of tunnel injection through the Schottky gate on the static and noise behavior of GaInAs/AlInAs high electron mobility transistor

    SciTech Connect (OSTI)

    Moro-Melgar, Diego; Mateos, Javier González, Tomás Vasallo, Beatriz G.

    2014-12-21

    By using a Monte Carlo simulator, the influence of the tunnel injection through the Schottky contact at the gate electrode of a GaInAs/AlInAs High Electron Mobility Transistor (HEMT) has been studied in terms of the static and noise performance. The method used to characterize the quantum tunnel current has been the Wentzel-Kramers-Brillouin (WKB) approach. The possibility of taking into account the influence of the image charge effect in the potential barrier height has been included as well. Regarding the static behavior, tunnel injection leads to a decrease in the drain current I{sub D} due to an enhancement of the potential barrier controlling the carrier transport through the channel. However, the pinch-off is degraded due to the tunneling current. Regarding the noise behavior, since the fluctuations in the potential barrier height caused by the tunnel-injected electrons are strongly coupled with the drain current fluctuations, a significant increase in the drain-current noise takes place, even when the tunnel effect is hardly noticeable in the static I-V characteristics, fact that must be taken into account when designing scaled HEMT for low-noise applications. In addition, tunnel injection leads to the appearance of full shot noise in the gate current.

  11. High-performance pentacene field-effect transistors using Al2O3 gate dielectrics prepared by atomic

    E-Print Network [OSTI]

    Wang, Zhong L.

    fabricated using Al2O3 as a gate dielectric material grown by atomic layer deposition (ALD). Hole mobility is also desirable to allow for fabri- cation on plastic substrates. Atomic layer deposition (ALD layer deposition (ALD) Xiao-Hong Zhang a , Benoit Domercq a , Xudong Wang b , Seunghyup Yoo a , Takeshi

  12. Impact of total ionizing dose irradiation on electrical property of ferroelectric-gate field-effect transistor

    SciTech Connect (OSTI)

    Yan, S. A.; Tang, M. H. Xiao, Y. G.; Zhang, W. L.; Ding, H.; Chen, J. W.; Zhou, Y. C.; Xiong, Y.; Li, Z.; Zhao, W.; Guo, H. X.

    2014-05-28

    P-type channel metal-ferroelectric-insulator-silicon field-effect transistors (FETs) with a 300?nm thick SrBi{sub 2}Ta{sub 2}O{sub 9} ferroelectric film and a 10?nm thick HfTaO layer on silicon substrate were fabricated and characterized. The prepared FeFETs were then subjected to {sup 60}Co gamma irradiation in steps of three dose levels. Irradiation-induced degradation on electrical characteristics of the fabricated FeFETs was observed after 1 week annealing at room temperature. The possible irradiation-induced degradation mechanisms were discussed and simulated. All the irradiation experiment results indicated that the stability and reliability of the fabricated FeFETs for nonvolatile memory applications will become uncontrollable under strong irradiation dose and/or long irradiation time.

  13. Ionizing radiation induced leakage current on ultra-thin gate oxides

    SciTech Connect (OSTI)

    Scarpa, A.; Paccagnella, A.; Montera, F.; Ghibaudo, G.; Pananakakis, G.; Fuochi, P.G.

    1997-12-01

    MOS capacitors with a 4.4 nm thick gate oxide have been exposed to {gamma} radiation from a Co{sup 60} source. As a result, the authors have measured a stable leakage current at fields lower than those required for Fowler-Nordheim tunneling. This Radiation Induced Leakage Current (RILC) is similar to the usual Stress Induced Leakage Currents (SILC) observed after electrical stresses of MOS devices. They have verified that these two currents share the same dependence on the oxide field, and the RILC contribution can be normalized to an equivalent injected charge for Constant Current Stresses. They have also considered the dependence of the RILC from the cumulative radiation dose, and from the applied bias during irradiation, suggesting a correlation between RILC and the distribution of trapped holes and neutral levels in the oxide layer.

  14. Charge Noise in Graphene Transistors Iddo Heller,,

    E-Print Network [OSTI]

    Dekker, Cees

    Charge Noise in Graphene Transistors Iddo Heller,,§ Sohail Chatoor, Jaan Ma¨nnik, Marcel A. G an experimental study of 1/f noise in liquid-gated graphene transistors. We show that the gate dependence to the graphene, while at high carrier density it is consistent with noise due to scattering in the channel

  15. Strained Ge channel p-type metal-oxide-semiconductor field-effect transistors grown on Siâ?â??xGex/Si virtual substrates

    E-Print Network [OSTI]

    Lee, Minjoo L.

    We have fabricated strained Ge channel p-type metal-oxide-semiconductor field-effect transistors (p-MOSFETs) on Siâ??.â??Geâ??.â?? virtual substrates. The poor interface between silicon dioxide (SiOâ??) and the Ge channel ...

  16. IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 45, NO. 6, JUNE 1998 1361 Degradation of Thin Tunnel Gate Oxide

    E-Print Network [OSTI]

    Schroder, Dieter K.

    IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 45, NO. 6, JUNE 1998 1361 Degradation of Thin Tunnel. Schroder, Fellow, IEEE Abstract-- The degradation of thin tunnel gate oxide under constant Fowler charge trapping is usually dominant at low QQQinjinjinj followed by negative charge trapping at high

  17. Novel Nanocrystal Floating Gate Memory

    E-Print Network [OSTI]

    Zhou, Huimei

    2012-01-01

    nanocrystals and tunnel oxide layer with a novel structure.of subsequent control oxide layer. Metal-oxide-semiconductorthe transistor has two oxide layers separated by Si. Top one

  18. Enhanced stability against bias-stress of metal-oxide thin film transistors deposited at elevated temperatures

    SciTech Connect (OSTI)

    Fakhri, M.; Goerrn, P.; Riedl, T. [Institute of Electronic Devices, University of Wuppertal, Rainer-Gruenter-St. 21, 42119 Wuppertal (Germany); Weimann, T.; Hinze, P. [Physikalisch-Technische Bundesanstalt Braunschweig, Bundesallee 100, 38116 Braunschweig (Germany)

    2011-09-19

    Transparent zinc-tin-oxide (ZTO) thin film transistors (TFTs) have been prepared by DC magnetron sputtering. Compared to reference devices with a channel deposited at room temperature and subsequently annealing at 400 deg. C, a substantially enhanced stability against bias stress is evidenced for devices with in-situ substrate heating during deposition (400 deg. C). A reduced density of sub-gap defect states in TFT channels prepared with in-situ substrate heating is found. Concomitantly, a reduced sensitivity to the adsorption of ambient gases is evidenced for the in-situ heated devices. This finding is of particular importance for an application as driver electronics for organic light emitting diode displays.

  19. Detection of saliva-range glucose concentrations using organic thin-film transistors

    SciTech Connect (OSTI)

    Elkington, D.; Belcher, W. J.; Dastoor, P. C.; Zhou, X. J.

    2014-07-28

    We describe the development of a glucose sensor through direct incorporation of an enzyme (glucose oxidase) into the gate of an organic thin film transistor (OTFT). We show that glucose diffusion is the key determinant of the device response time and present a mechanism of glucose sensing in these devices that involves protonic doping of the transistor channel via enzymatic oxidation of glucose. The integrated OTFT sensor is sensitive across 4 decades of glucose concentration; a range that encompasses both the blood and salivary glucose concentration levels. As such, this work acts as a proof-of-concept for low-cost printed biosensors for salivary glucose.

  20. Rapid low-temperature processing of metal-oxide thin film transistors with combined far ultraviolet and thermal annealing

    SciTech Connect (OSTI)

    Leppäniemi, J. Ojanperä, K.; Kololuoma, T.; Huttunen, O.-H.; Majumdar, H.; Alastalo, A.; Dahl, J.; Tuominen, M.; Laukkanen, P.

    2014-09-15

    We propose a combined far ultraviolet (FUV) and thermal annealing method of metal-nitrate-based precursor solutions that allows efficient conversion of the precursor to metal-oxide semiconductor (indium zinc oxide, IZO, and indium oxide, In{sub 2}O{sub 3}) both at low-temperature and in short processing time. The combined annealing method enables a reduction of more than 100?°C in annealing temperature when compared to thermally annealed reference thin-film transistor (TFT) devices of similar performance. Amorphous IZO films annealed at 250?°C with FUV for 5?min yield enhancement-mode TFTs with saturation mobility of ?1?cm{sup 2}/(V·s). Amorphous In{sub 2}O{sub 3} films annealed for 15?min with FUV at temperatures of 180?°C and 200?°C yield TFTs with low-hysteresis and saturation mobility of 3.2?cm{sup 2}/(V·s) and 7.5?cm{sup 2}/(V·s), respectively. The precursor condensation process is clarified with x-ray photoelectron spectroscopy measurements. Introducing the FUV irradiation at 160?nm expedites the condensation process via in situ hydroxyl radical generation that results in the rapid formation of a continuous metal-oxygen-metal structure in the film. The results of this paper are relevant in order to upscale printed electronics fabrication to production-scale roll-to-roll environments.

  1. Gate dielectric development for flexible electronics

    SciTech Connect (OSTI)

    Joshi, P. C.; Voutsas, A. T.; Hartzell, J. W. [LCD Process Technology Laboratories, SHARP Laboratories of America, Inc., 5700 NW Pacific Rim Blvd., Camas, Washington 98607 (United States)

    2007-07-15

    Thin film transistors integrated on flexible substrates are becoming increasingly attractive for low cost displays, sensors, and rf communication applications. The successful development of the flexible devices will be dictated by the enhancement in the thermal stability of the substrates and the low temperature (<300 deg. C) processing of the gate dielectric. The plasma-enhanced chemical-vapor deposition (PECVD) technique has successfully met the demands of the gate dielectric for display devices at processing temperatures lower than 600 deg. C. However, a further reduction in the processing temperatures below 300 deg. C is essential to realize low cost, highly functional devices on flexible substrates. The low temperature processing of gate dielectric films necessitates the development of processes and techniques with plasma controlled reaction kinetics dominating the thin film growth rather than the thermal state of the substrate. In the present work, the authors report on the processing of high quality gate dielectric films by high density PECVD technique at process temperatures lower than 300 deg. C. The bulk and interfacial electrical quality and reliability of the metal-oxide-semiconductor capacitors as a function of process temperature are discussed in this article. A comparison with the high temperature gate oxide films deposited by PECVD technique employing capacitively coupled plasma source has been made to establish the film quality and reliability. The films processed at low temperatures have shown good electrical performance and reliability as evaluated in terms of the leakage current, flatband voltage, midgap interface trap concentration, and bias temperature stress reliability characteristics.

  2. A low temperature amorphous oxide thin film transistor (TFT) backplane technology for flexible organic light emitting diode (OLED) displays has been developed to create 4.1-in. diagonal backplanes. The critical steps in

    E-Print Network [OSTI]

    organic light emitting diode (OLED) displays has been developed to create 4.1-in. diagonal backplanes organic light emitting diode (OLED) displays. Mixed oxide semiconductor thin film transistors (TFT

  3. Low temperature lithographically patterned metal oxide transistors for large area electronics

    E-Print Network [OSTI]

    Wang, Annie I. (Annie I-Jen), 1981-

    2011-01-01

    Optically transparent, wide bandgap metal oxide semiconductors are a promising candidate for large-area electronics technologies that require lightweight, temperature-sensitive flexible substrates. Because these thin films ...

  4. Nanocrystals Embedded Zirconium-doped Hafnium Oxide High-k Gate Dielectric Films 

    E-Print Network [OSTI]

    Lin, Chen-Han

    2012-10-19

    nanoparticles. These results can be important to the novel metal gate/high-k/Si MOS structure. The Ru-modified ZrHfO gate dielectric film showed a large breakdown voltage and a long lifetime. The conventional polycrystalline Si (poly-Si) charge trapping layer...

  5. Characteristics of SiO2 Film Grown by Atomic Layer Deposition as the Gate Insulator of Low-Temperature Polysilicon Thin-Film Transistors

    E-Print Network [OSTI]

    Cao, Guozhong

    Characteristics of SiO2 Film Grown by Atomic Layer Deposition as the Gate Insulator of Low a Corresponding author: skrha@hanbat.ac.kr Keywords: atomic layer deposition (ALD), silicon dioxide (SiO2), dichlorosilane (SiH2Cl2), ozone (O3) Abstract. SiO2 films were prepared by atomic layer deposition (ALD

  6. Atomistic characterization of SAM coatings as gate insulators in Si-based FET devices

    SciTech Connect (OSTI)

    Gala, F. [Universitá di Roma La Sapienza, Via Scarpa 14-16, 00161 Rome (Italy); Zollo, G. [Universitá di Roma La Sapienza', Via Scarpa 14-16, 00161 Rome (Italy)

    2014-06-19

    Many nano-material systems are currently under consideration as possible candidates for gate dielectric insulators in both metal-oxide-semiconductor (MOSFET) and organic (OFET) field-effect transistors. In this contribution, the possibility of employing self-assembled monolayers (SAMs) of hydroxylated octadecyltrichlorosilane (OTS) chains on a (111) Si substrate as gate dielectrics is discussed; in particular ab initio theoretical simulations have been employed to study the structural properties, work function modifications, and the insulating properties of OTS thin film coatings on Si substrates.

  7. Comprehensive study and design of scaled metal/high-k/Ge gate stacks with ultrathin aluminum oxide interlayers

    SciTech Connect (OSTI)

    Asahara, Ryohei; Hideshima, Iori; Oka, Hiroshi; Minoura, Yuya; Hosoi, Takuji Shimura, Takayoshi; Watanabe, Heiji; Ogawa, Shingo; Yoshigoe, Akitaka; Teraoka, Yuden

    2015-06-08

    Advanced metal/high-k/Ge gate stacks with a sub-nm equivalent oxide thickness (EOT) and improved interface properties were demonstrated by controlling interface reactions using ultrathin aluminum oxide (AlO{sub x}) interlayers. A step-by-step in situ procedure by deposition of AlO{sub x} and hafnium oxide (HfO{sub x}) layers on Ge and subsequent plasma oxidation was conducted to fabricate Pt/HfO{sub 2}/AlO{sub x}/GeO{sub x}/Ge stacked structures. Comprehensive study by means of physical and electrical characterizations revealed distinct impacts of AlO{sub x} interlayers, plasma oxidation, and metal electrodes serving as capping layers on EOT scaling, improved interface quality, and thermal stability of the stacks. Aggressive EOT scaling down to 0.56?nm and very low interface state density of 2.4?×?10{sup 11?}cm{sup ?2}eV{sup ?1} with a sub-nm EOT and sufficient thermal stability were achieved by systematic process optimization.

  8. Method of making self-aligned lightly-doped-drain structure for MOS transistors

    DOE Patents [OSTI]

    Weiner, Kurt H. (San Jose, CA); Carey, Paul G. (Mountain View, CA)

    2001-01-01

    A process for fabricating lightly-doped-drains (LDD) for short-channel metal oxide semiconductor (MOS) transistors. The process utilizes a pulsed laser process to incorporate the dopants, thus eliminating the prior oxide deposition and etching steps. During the process, the silicon in the source/drain region is melted by the laser energy. Impurities from the gas phase diffuse into the molten silicon to appropriately dope the source/drain regions. By controlling the energy of the laser, a lightly-doped-drain can be formed in one processing step. This is accomplished by first using a single high energy laser pulse to melt the silicon to a significant depth and thus the amount of dopants incorporated into the silicon is small. Furthermore, the dopants incorporated during this step diffuse to the edge of the MOS transistor gate structure. Next, many low energy laser pulses are used to heavily dope the source/drain silicon only in a very shallow region. Because of two-dimensional heat transfer at the MOS transistor gate edge, the low energy pulses are inset from the region initially doped by the high energy pulse. By computer control of the laser energy, the single high energy laser pulse and the subsequent low energy laser pulses are carried out in a single operational step to produce a self-aligned lightly-doped-drain-structure.

  9. Radiation induced leakage current and stress induced leakage current in ultra-thin gate oxides

    SciTech Connect (OSTI)

    Ceschia, M.; Paccagnella, A.; Cester, A.; Scarpa, A.; Ghidini, G.

    1998-12-01

    Low-field leakage current has been measured in thin oxides after exposure to ionizing radiation. This Radiation Induced Leakage Current (RILC) can be described as an inelastic tunneling process mediated by neutral traps in the oxide, with an energy loss of about 1 eV. The neutral trap distribution is influenced by the oxide field applied during irradiation, thus indicating that the precursors of the neutral defects are charged, likely being defects associated to trapped holes. The maximum leakage current is found under zero-field condition during irradiation, and it rapidly decreases as the field is enhanced, due to a displacement of the defect distribution across the oxide towards the cathodic interface. The RILC kinetics are linear with the cumulative dose, in contrast with the power law found on electrically stressed devices.

  10. Effects of low-temperature (120?°C) annealing on the carrier concentration and trap density in amorphous indium gallium zinc oxide thin film transistors

    SciTech Connect (OSTI)

    Kim, Jae-sung; Piao, Mingxing; Jang, Ho-Kyun; Kim, Gyu-Tae; Oh, Byung Su; Joo, Min-Kyu; Ahn, Seung-Eon

    2014-12-28

    We report an investigation of the effects of low-temperature annealing on the electrical properties of amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs). X-ray photoelectron spectroscopy was used to characterize the charge carrier concentration, which is related to the density of oxygen vacancies. The field-effect mobility was found to decrease as a function of the charge carrier concentration, owing to the presence of band-tail states. By employing the transmission line method, we show that the contact resistance did not significantly contribute to the changes in device performance after annealing. In addition, using low-frequency noise analyses, we found that the trap density decreased by a factor of 10 following annealing at 120?°C. The switching operation and on/off ratio of the a-IGZO TFTs improved considerably after low-temperature annealing.

  11. Gate-all-around silicon nanowire MOSFETs : top-down fabrication and transport enhancement techniques

    E-Print Network [OSTI]

    Hashemi, Pouya

    2010-01-01

    Scaling MOSFETs beyond 15 nm gate lengths is extremely challenging using a planar device architecture due to the stringent criteria required for the transistor switching. The top-down fabricated, gate-all-around architecture ...

  12. Photoresponsive nanoscale columnar transistors Xuefeng Guoa,1

    E-Print Network [OSTI]

    -assembly Fabrication of molecule-scaled transport junctions that enable the measurement of the electrical modulation and higher gate efficiency. More interestingly, when the devices were exposed to visible light sensing and solar energy harvesting. chemistry field effect transistor nanofabrication nanoscience self

  13. Charge noise analysis of metal oxide semiconductor dual-gate Si/SiGe quantum point contacts

    SciTech Connect (OSTI)

    Kamioka, J.; Oda, S.; Kodera, T.; Takeda, K.; Obata, T.; Tarucha, S.

    2014-05-28

    The frequency dependence of conductance noise through a gate-defined quantum point contact fabricated on a Si/SiGe modulation doped wafer is characterized. The 1/f{sup 2} noise, which is characteristic of random telegraph noise, is reduced by application of a negative bias on the global top gate to reduce the local gate voltage. Direct leakage from the large global gate voltage also causes random telegraph noise, and therefore, there is a suitable point to operate quantum dot measurement.

  14. Electronic Structure of Low-Temperature Solution-Processed Amorphous Metal Oxide Semiconductors for Thin-Film Transistor Applications

    E-Print Network [OSTI]

    Socratous, Josephine; Banger, Kulbinder K.; Vaynzof, Yana; Sadhanala, Aditya; Brown, Adam D.; Sepe, Alessandro; Steiner, Ullrich; Sirringhaus, Henning

    2015-02-18

    of vehicles or build- ings. [ 3 ] Most of the research so far, has focused on oxides deposited via low- temperature sputtering techniques and a wide range of ternary and quaternary elemental compositions has been explored with InGaZnO (IGZO) being one... annealing temperature. Figure S5 (Supporting Information) shows corroborating electrical data for the quaternary oxide IGZO for different gallium doping. The presence of gallium is known to suppress oxygen vacan- cies due to its strong bond with oxygen...

  15. Physical understanding of electron mobility in asymmetrically strained InGaAs-on-insulator metal-oxide-semiconductor field-effect transistors fabricated by lateral strain relaxation

    SciTech Connect (OSTI)

    Kim, SangHyeon, E-mail: dadembyora@mosfet.t.u-tokyo.ac.jp, E-mail: sh-kim@kist.re.kr; Yokoyama, Masafumi; Ikku, Yuki; Nakane, Ryosho; Takenaka, Mitsuru; Takagi, Shinichi [Department of Electrical Engineering and Information Systems, The University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656 (Japan); Ichikawa, Osamu; Osada, Takenori; Hata, Masahiko [Sumitomo Chemical Co. Ltd., 6 Kitahara, Tsukuba, Ibaraki 300-3294 (Japan)

    2014-03-17

    In this paper, we fabricated asymmetrically tensile-strained In{sub 0.53}Ga{sub 0.47}As-on-insulator (-OI) metal-oxide-semiconductor field-effect transistors (MOSFETs) using a lateral strain relaxation technique. A stripe-like line structure, fabricated in biaxially strained In{sub 0.53}Ga{sub 0.47}As-OI can lead to the lateral strain relaxation and asymmetric strain configuration in In{sub 0.53}Ga{sub 0.47}As-OI with the channel width of 100?nm. We have found that the effective mobility (?{sub eff}) enhancement in In{sub 0.53}Ga{sub 0.47}As-OI MOSFETs with uniaxial-like asymmetric strain becomes smaller than that in In{sub 0.53}Ga{sub 0.47}As-OI MOSFETs with biaxial strain. We have clarified from a systematic analysis between the strain values and the ?{sub eff} characteristics that this mobility behavior can be understood by the change of the energy level of the conduction band minimum due to the lateral strain relaxation.

  16. High-performance self-aligned inversion-channel In{sub 0.53}Ga{sub 0.47}As metal-oxide-semiconductor field-effect-transistors by in-situ atomic-layer-deposited HfO{sub 2}

    SciTech Connect (OSTI)

    Lin, T. D.; Chang, W. H.; Chang, Y. C.; Hong, M., E-mail: raynien@phys.nthu.edu.tw, E-mail: mhong@phys.ntu.edu.tw [Graduate Institute of Applied Physics and Department of Physics, National Taiwan University, Taipei 10617, Taiwan (China); Chu, R. L.; Chang, Y. H. [Department of Materials Science and Engineering, National Tsing Hua University, Hsinchu 30013, Taiwan (China)] [Department of Materials Science and Engineering, National Tsing Hua University, Hsinchu 30013, Taiwan (China); Lee, M. Y.; Hong, P. F.; Chen, Min-Cheng [National Nano Device Laboratories, Hsinchu 30076, Taiwan (China)] [National Nano Device Laboratories, Hsinchu 30076, Taiwan (China); Kwo, J., E-mail: raynien@phys.nthu.edu.tw, E-mail: mhong@phys.ntu.edu.tw [Department of Physics, National Tsing Hua University, Hsinchu 30013, Taiwan (China)

    2013-12-16

    Self-aligned inversion-channel In{sub 0.53}Ga{sub 0.47}As metal-oxide-semiconductor field-effect-transistors (MOSFETs) have been fabricated using the gate dielectrics of in-situ directly atomic-layer-deposited (ALD) HfO{sub 2} followed by ALD-Al{sub 2}O{sub 3}. There were no surface pretreatments and no interfacial passivation/barrier layers prior to the ALD. TiN/Al{sub 2}O{sub 3} (4?nm)/HfO{sub 2} (1?nm)/In{sub 0.53}Ga{sub 0.47}As/InP MOS capacitors exhibited well-behaved capacitance-voltage characteristics with true inversion behavior, low leakage current densities of ?10{sup ?8}?A/cm{sup 2} at ±1?MV/cm, and thermodynamic stability at high temperatures. Al{sub 2}O{sub 3} (3?nm)/HfO{sub 2} (1?nm)/In{sub 0.53}Ga{sub 0.47}As MOSFETs of 1 ?m gate length, with 700?°C–800?°C rapid thermal annealing in source/drain activation, have exhibited high extrinsic drain current (I{sub D}) of 1.5?mA/?m, transconductance (G{sub m}) of 0.84 mS/?m, I{sub ON}/I{sub OFF} of ?10{sup 4}, low sub-threshold swing of 103?mV/decade, and field-effect electron mobility of 1100 cm{sup 2}/V?·?s. The devices have also achieved very high intrinsic I{sub D} and G{sub m} of 2?mA/?m and 1.2?mS/?m, respectively.

  17. Compact modeling of quantum effects in double gate MOSFETs

    E-Print Network [OSTI]

    Wang, Wei

    2007-01-01

    However, ultrathin gate oxide will lead to high gate leakagethe high enough oxide barrier confinement leads to zero waveoxide becomes significant. The random dopant fluctuation effects increase with shrinking device size and leads

  18. A Heteroepitaxial Perovskite Metal-Base Transistor

    SciTech Connect (OSTI)

    Yajima, T.; Hikita, Y.; Hwang, H.Y.; ,

    2011-08-11

    'More than Moore' captures a concept for overcoming limitations in silicon electronics by incorporating new functionalities in the constituent materials. Perovskite oxides are candidates because of their vast array of physical properties in a common structure. They also enable new electronic devices based on strongly-correlated electrons. The field effect transistor and its derivatives have been the principal oxide devices investigated thus far, but another option is available in a different geometry: if the current is perpendicular to the interface, the strong internal electric fields generated at back-to-back heterojunctions can be used for oxide electronics, analogous to bipolar transistors. Here we demonstrate a perovskite heteroepitaxial metal-base transistor operating at room temperature, enabled by interface dipole engineering. Analysis of many devices quantifies the evolution from hot-electron to permeable-base behaviour. This device provides a platform for incorporating the exotic ground states of perovskite oxides, as well as novel electronic phases at their interfaces.

  19. Integration of pentacene-based thin film transistors via photolithography for low and high voltage applications

    E-Print Network [OSTI]

    Smith, Melissa Alyson

    2012-01-01

    An organic thin film transistor (OTFT) technology platform has been developed for flexible integrated circuits applications. OTFT performance is tuned by engineering the dielectric constant of the gate insulator and the ...

  20. Sample size requirements for estimating effective dose from computed tomography using solid-state metal-oxide-semiconductor field-effect transistor dosimetry

    SciTech Connect (OSTI)

    Trattner, Sigal; Cheng, Bin; Pieniazek, Radoslaw L.; Hoffmann, Udo; Douglas, Pamela S.; Einstein, Andrew J.

    2014-04-15

    Purpose: Effective dose (ED) is a widely used metric for comparing ionizing radiation burden between different imaging modalities, scanners, and scan protocols. In computed tomography (CT), ED can be estimated by performing scans on an anthropomorphic phantom in which metal-oxide-semiconductor field-effect transistor (MOSFET) solid-state dosimeters have been placed to enable organ dose measurements. Here a statistical framework is established to determine the sample size (number of scans) needed for estimating ED to a desired precision and confidence, for a particular scanner and scan protocol, subject to practical limitations. Methods: The statistical scheme involves solving equations which minimize the sample size required for estimating ED to desired precision and confidence. It is subject to a constrained variation of the estimated ED and solved using the Lagrange multiplier method. The scheme incorporates measurement variation introduced both by MOSFET calibration, and by variation in MOSFET readings between repeated CT scans. Sample size requirements are illustrated on cardiac, chest, and abdomen–pelvis CT scans performed on a 320-row scanner and chest CT performed on a 16-row scanner. Results: Sample sizes for estimating ED vary considerably between scanners and protocols. Sample size increases as the required precision or confidence is higher and also as the anticipated ED is lower. For example, for a helical chest protocol, for 95% confidence and 5% precision for the ED, 30 measurements are required on the 320-row scanner and 11 on the 16-row scanner when the anticipated ED is 4 mSv; these sample sizes are 5 and 2, respectively, when the anticipated ED is 10 mSv. Conclusions: Applying the suggested scheme, it was found that even at modest sample sizes, it is feasible to estimate ED with high precision and a high degree of confidence. As CT technology develops enabling ED to be lowered, more MOSFET measurements are needed to estimate ED with the same precision and confidence.

  1. Transistor roadmap projection using predictive full-band atomistic modeling

    SciTech Connect (OSTI)

    Salmani-Jelodar, M., E-mail: m.salmani@gmail.com; Klimeck, G. [Network for Computational Nanotechnology and School of Electrical and Computer Engineering, Purdue University, West Lafayette, Indiana 47907 (United States); Kim, S. [Intel Corporation, 2501 Northwest 229th Avenue, Hillsboro, Oregon 97124 (United States); Ng, K. [Semiconductor Research Corporation (SRC), 1101 Slater Rd, Durham, North Carolina 27703 (United States)

    2014-08-25

    In this letter, a full band atomistic quantum transport tool is used to predict the performance of double gate metal-oxide-semiconductor field-effect transistors (MOSFETs) over the next 15?years for International Technology Roadmap for Semiconductors (ITRS). As MOSFET channel lengths scale below 20?nm, the number of atoms in the device cross-sections becomes finite. At this scale, quantum mechanical effects play an important role in determining the device characteristics. These quantum effects can be captured with the quantum transport tool. Critical results show the ON-current degradation as a result of geometry scaling, which is in contrast to previous ITRS compact model calculations. Geometric scaling has significant effects on the ON-current by increasing source-to-drain (S/D) tunneling and altering the electronic band structure. By shortening the device gate length from 20?nm to 5.1?nm, the ratio of S/D tunneling current to the overall subthreshold OFF-current increases from 18% to 98%. Despite this ON-current degradation by scaling, the intrinsic device speed is projected to increase at a rate of at least 8% per year as a result of the reduction of the quantum capacitance.

  2. A thermalization energy analysis of the threshold voltage shift in amorphous indium gallium zinc oxide thin film transistors under simultaneous negative gate bias and illumination

    E-Print Network [OSTI]

    Flewitt, Andrew J.; Powell, M.J.

    2014-01-01

    crystal to organic light emitting diode technology and with requirements for larger areas and higher resolutions. A number of alternative material systems to a-Si:H have emerged, including organic semiconductors,2 nanocrystalline silicon...

  3. Al{sub 2}O{sub 3}/GeO{sub x} gate stack on germanium substrate fabricated by in situ cycling ozone oxidation method

    SciTech Connect (OSTI)

    Yang, Xu; Zeng, Zhen-Hua [Advanced Photonics Center, School of Electronic Science and Engineering, Southeast University, Nanjing 210096 (China); Microwave Device and IC Department, Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029 (China); Wang, Sheng-Kai, E-mail: wangshengkai@ime.ac.cn, E-mail: xzhang62@aliyun.com, E-mail: liuhonggang@ime.ac.cn; Sun, Bing; Zhao, Wei; Chang, Hu-Dong; Liu, Honggang, E-mail: wangshengkai@ime.ac.cn, E-mail: xzhang62@aliyun.com, E-mail: liuhonggang@ime.ac.cn [Microwave Device and IC Department, Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029 (China); Zhang, Xiong, E-mail: wangshengkai@ime.ac.cn, E-mail: xzhang62@aliyun.com, E-mail: liuhonggang@ime.ac.cn [Advanced Photonics Center, School of Electronic Science and Engineering, Southeast University, Nanjing 210096 (China)

    2014-09-01

    Al{sub 2}O{sub 3}/GeO{sub x}/Ge gate stack fabricated by an in situ cycling ozone oxidation (COO) method in the atomic layer deposition (ALD) system at low temperature is systematically investigated. Excellent electrical characteristics such as minimum interface trap density as low as 1.9?×?10{sup 11?}cm{sup ?2?}eV{sup ?1} have been obtained by COO treatment. The impact of COO treatment against the band alignment of Al{sub 2}O{sub 3} with respect to Ge is studied by x-ray photoelectron spectroscopy (XPS) and spectroscopic ellipsometry (SE). Based on both XPS and SE studies, the origin of gate leakage in the ALD-Al{sub 2}O{sub 3} is attributed to the sub-gap states, which may be correlated to the OH-related groups in Al{sub 2}O{sub 3} network. It is demonstrated that the COO method is effective in repairing the OH-related defects in high-k dielectrics as well as forming superior high-k/Ge interface for high performance Ge MOS devices.

  4. Amorphorized tantalum-nickel binary films for metal gate applications

    SciTech Connect (OSTI)

    Ouyang, Jiaomin; Wongpiya, Ranida; Clemens, Bruce M.; Deal, Michael D.; Nishi, Yoshio

    2015-04-13

    Amorphous metal gates have the potential to eliminate the work function variation due to grain orientation for poly-crystalline metal gate materials, which is a leading contributor to threshold voltage variation for small transistors. Structural and electrical properties of TaNi alloys using co-sputtering with different compositions and multilayer structures with different thicknesses are investigated in this work. It is found that TaNi films are amorphous for a wide range of compositions as deposited, and the films stay amorphous after annealing at 400?°C in RTA for 1?min and up to at least 700?°C depending on the composition. The amorphous films eventually crystallize into Ni, Ta, and TaNi{sub 3} phases at high enough temperature. For multilayer Ta/Ni structures, samples with individual layer thickness of 0.12?nm and 1.2?nm are amorphous as deposited due to intermixing during deposition, and stay amorphous until annealed at 500?°C. The resistivity of the films as-deposited are around 200 ??·cm. The work function of the alloy is fixed at close to the Ta work function of 4.6?eV for a wide range of compositions. This is attributed to the segregation of Ta at the metal-oxide interface, which is confirmed by XPS depth profile. Overall, the excellent thermal stability and low resistivity makes this alloy system a promising candidate for eliminating work function variation for gate last applications, as compared to crystalline Ta or TiN gates.

  5. Visible-light-induced instability in amorphous metal-oxide based TFTs for transparent electronics

    SciTech Connect (OSTI)

    Ha, Tae-Jun

    2014-10-15

    We investigate the origin of visible-light-induced instability in amorphous metal-oxide based thin film transistors (oxide-TFTs) for transparent electronics by exploring the shift in threshold voltage (V{sub th}). A large hysteresis window in amorphous indium-gallium-zinc-oxide (a-IGZO) TFTs possessing large optical band-gap (?3 eV) was observed in a visible-light illuminated condition whereas no hysteresis window was shown in a dark measuring condition. We also report the instability caused by photo irradiation and prolonged gate bias stress in oxide-TFTs. Larger V{sub th} shift was observed after photo-induced stress combined with a negative gate bias than the sum of that after only illumination stress and only negative gate bias stress. Such results can be explained by trapped charges at the interface of semiconductor/dielectric and/or in the gate dielectric which play a role in a screen effect on the electric field applied by gate voltage, for which we propose that the localized-states-assisted transitions by visible-light absorption can be responsible.

  6. Fabrication and electrical characteristics of high-performance ZnO nanorod field-effect transistors

    E-Print Network [OSTI]

    Lee, Hu-Jong

    and then dispersed on SiO2/Si. A 250-nm-thick silicon oxide layer was employed as an insu- lating gate oxide layer

  7. Detection of terahertz radiation by tightly concatenated InGaAs field-effect transistors integrated on a single chip

    SciTech Connect (OSTI)

    Popov, V. V., E-mail: popov-slava@yahoo.co.uk [Kotelnikov Institute of Radio Engineering and Electronics (Saratov Branch), Russian Academy of Sciences, Saratov 410019 (Russian Federation); Yermolaev, D. M.; Shapoval, S. Yu. [Institute of Microelectronic Technology and High-Purity Materials, Russian Academy of Sciences, Chernogolovka, Moscow Region 142432 (Russian Federation); Maremyanin, K. V.; Gavrilenko, V. I. [Institute for Physics of Microstructures, Russian Academy of Sciences, Nizhny Novgorod 603950 (Russian Federation); Lobachevsky State University of Nizhni Novgorod, Nizhni Novgorod 603950 (Russian Federation); Zemlyakov, V. E.; Bespalov, V. A.; Yegorkin, V. I. [National Research University of Electronic Technology, Zelenograd, Moscow 124498 (Russian Federation); Maleev, N. A.; Ustinov, V. M. [Ioffe Physical Technical Institute, Russian Academy of Sciences, St. Petersburg 194021 (Russian Federation)

    2014-04-21

    A tightly concatenated chain of InGaAs field-effect transistors with an asymmetric T-gate in each transistor demonstrates strong terahertz photovoltaic response without using supplementary antenna elements. We obtain the responsivity above 1000?V/W and up to 2000?V/W for unbiased and drain-biased transistors in the chain, respectively, with the noise equivalent power below 10{sup ?11} W/Hz{sup 0.5} in the unbiased mode of the detector operation.

  8. Vertical graphene base transistor

    E-Print Network [OSTI]

    2012-01-01

    M. Baus, and H. Kurz, “A graphene ?eld-effect device,” IEEERooks, and P. Avouris, “Graphene nano- ribbon electronics,”High-frequency, scaled graphene transistors on diamond- like

  9. Gate Access

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    AFDC Printable Version Share this resource Send a link to EERE: Alternative Fuels Data Center Home Page to someone by E-mail Share EERE: Alternative Fuels Data Center Home Page on Facebook Tweet about EERE: Alternative Fuels Data Center Home Page on Twitter Bookmark EERE: Alternative Fuels Data Center Homesum_a_epg0_fpd_mmcf_m.xls" ,"Available from WebQuantity of NaturalDukeWakefieldSulfateSciTechtail.Theory ofDid you not find whatGasEnergyfeatureCleanperformanceCareersGate Access Gate

  10. Transparently wrap-gated semiconductor nanowire arrays for studies of gate-controlled photoluminescence

    SciTech Connect (OSTI)

    Nylund, Gustav; Storm, Kristian; Torstensson, Henrik; Wallentin, Jesper; Borgström, Magnus T.; Hessman, Dan; Samuelson, Lars

    2013-12-04

    We present a technique to measure gate-controlled photoluminescence (PL) on arrays of semiconductor nanowire (NW) capacitors using a transparent film of Indium-Tin-Oxide (ITO) wrapping around the nanowires as the gate electrode. By tuning the wrap-gate voltage, it is possible to increase the PL peak intensity of an array of undoped InP NWs by more than an order of magnitude. The fine structure of the PL spectrum reveals three subpeaks whose relative peak intensities change with gate voltage. We interpret this as gate-controlled state-filling of luminescing quantum dot segments formed by zincblende stacking faults in the mainly wurtzite NW crystal structure.

  11. Method for formation of thin film transistors on plastic substrates

    DOE Patents [OSTI]

    Carey, P.G.; Smith, P.M.; Sigmon, T.W.; Aceves, R.C.

    1998-10-06

    A process for formation of thin film transistors (TFTs) on plastic substrates replaces standard thin film transistor fabrication techniques, and uses sufficiently lower processing temperatures so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The process relies on techniques for depositing semiconductors, dielectrics, and metals at low temperatures; crystallizing and doping semiconductor layers in the TFT with a pulsed energy source; and creating top-gate self-aligned as well as back-gate TFT structures. The process enables the fabrication of amorphous and polycrystalline channel silicon TFTs at temperatures sufficiently low to prevent damage to plastic substrates. The process has use in large area low cost electronics, such as flat panel displays and portable electronics. 5 figs.

  12. Method for formation of thin film transistors on plastic substrates

    DOE Patents [OSTI]

    Carey, Paul G. (Mountain View, CA); Smith, Patrick M. (San Ramon, CA); Sigmon, Thomas W. (Portola Valley, CA); Aceves, Randy C. (Livermore, CA)

    1998-10-06

    A process for formation of thin film transistors (TFTs) on plastic substrates replaces standard thin film transistor fabrication techniques, and uses sufficiently lower processing temperatures so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The process relies on techniques for depositing semiconductors, dielectrics, and metals at low temperatures; crystallizing and doping semiconductor layers in the TFT with a pulsed energy source; and creating top-gate self-aligned as well as back-gate TFT structures. The process enables the fabrication of amorphous and polycrystalline channel silicon TFTs at temperatures sufficiently low to prevent damage to plastic substrates. The process has use in large area low cost electronics, such as flat panel displays and portable electronics.

  13. Printed inorganic transistors

    E-Print Network [OSTI]

    Ridley, Brent (Brent Alan), 1974-

    2003-01-01

    Forty years of exponential growth of semiconductor technology have been predicated on the miniaturization of the transistors that comprise integrated circuits. While complexity has greatly increased within a given area of ...

  14. Lifetime of high-k gate dielectrics and analogy with strength of quasibrittle Jia-Liang Le,1

    E-Print Network [OSTI]

    Bazant, Martin Z.

    for breakdown lifetime increases in proportion to the thickness of the oxide layer and suggests new ideas in the gate oxide layer induces the trap-assisted tunneling process, which leads to the gate leakage current

  15. High gain, low noise, fully complementary logic inverter based on bi-layer WSe{sub 2} field effect transistors

    SciTech Connect (OSTI)

    Das, Saptarshi; Roelofs, Andreas; Dubey, Madan

    2014-08-25

    In this article, first, we show that by contact work function engineering, electrostatic doping and proper scaling of both the oxide thickness and the flake thickness, high performance p- and n-type WSe{sub 2} field effect transistors (FETs) can be realized. We report record high drive current of 98??A/?m for the electron conduction and 110 ?A/?m for the hole conduction in Schottky barrier WSe{sub 2} FETs. Then, we combine high performance WSe{sub 2} PFET with WSe{sub 2} NFET in double gated transistor geometry to demonstrate a fully complementary logic inverter. We also show that by adjusting the threshold voltages for the NFET and the PFET, the gain and the noise margin of the inverter can be significantly enhanced. The maximum gain of our chemical doping free WSe{sub 2} inverter was found to be ?25 and the noise margin was close to its ideal value of ?2.5?V for a supply voltage of V{sub DD}?=?5.0?V.

  16. The benzene molecule as a molecular resonant-tunneling transistor M. Di Ventraa)

    E-Print Network [OSTI]

    Pantelides, Sokrates T.

    The benzene molecule as a molecular resonant-tunneling transistor M. Di Ventraa) and S. T of transport through a benzene-1, 4-dithiolate molecule with a third capacitive terminal gate . We find rectification was demonstrated in 1993.2 More recently, Reed et al. investigated the benzene-1, 4-dithiol rings

  17. Low interface defect density of atomic layer deposition BeO with self-cleaning reaction for InGaAs metal oxide semiconductor field effect transistors

    SciTech Connect (OSTI)

    Shin, H. S. [Department of Electronics Engineering, Chungnam National University, Daejeon (Korea, Republic of) [Department of Electronics Engineering, Chungnam National University, Daejeon (Korea, Republic of); SEMATECH, 2706 Montopolis Dr., Austin, Texas 78741 (United States); The University of Texas, Austin, Texas 78758 (United States); Yum, J. H. [SEMATECH, 2706 Montopolis Dr., Austin, Texas 78741 (United States) [SEMATECH, 2706 Montopolis Dr., Austin, Texas 78741 (United States); The University of Texas, Austin, Texas 78758 (United States); Johnson, D. W. [SEMATECH, 2706 Montopolis Dr., Austin, Texas 78741 (United States) [SEMATECH, 2706 Montopolis Dr., Austin, Texas 78741 (United States); Texas A and M University College Station, Texas 77843 (United States); Harris, H. R. [Texas A and M University College Station, Texas 77843 (United States)] [Texas A and M University College Station, Texas 77843 (United States); Hudnall, Todd W. [Texas State University, 601 University Drive, San Marcos, Texas 78666 (United States)] [Texas State University, 601 University Drive, San Marcos, Texas 78666 (United States); Oh, J. [Yonsei University, Incheon, 406-840 (Korea, Republic of)] [Yonsei University, Incheon, 406-840 (Korea, Republic of); Kirsch, P.; Wang, W.-E. [SEMATECH, 2706 Montopolis Dr., Austin, Texas 78741 (United States)] [SEMATECH, 2706 Montopolis Dr., Austin, Texas 78741 (United States); Bielawski, C. W.; Banerjee, S. K.; Lee, J. C. [The University of Texas, Austin, Texas 78758 (United States)] [The University of Texas, Austin, Texas 78758 (United States); Lee, H. D. [Department of Electronics Engineering, Chungnam National University, Daejeon (Korea, Republic of)] [Department of Electronics Engineering, Chungnam National University, Daejeon (Korea, Republic of)

    2013-11-25

    In this paper, we discuss atomic configuration of atomic layer deposition (ALD) beryllium oxide (BeO) using the quantum chemistry to understand the theoretical origin. BeO has shorter bond length, higher reaction enthalpy, and larger bandgap energy compared with those of ALD aluminum oxide. It is shown that the excellent material properties of ALD BeO can reduce interface defect density due to the self-cleaning reaction and this contributes to the improvement of device performance of InGaAs MOSFETs. The low interface defect density and low leakage current of InGaAs MOSFET were demonstrated using X-ray photoelectron spectroscopy and the corresponding electrical results.

  18. Gating of Permanent Molds for ALuminum Casting

    SciTech Connect (OSTI)

    David Schwam; John F. Wallace; Tom Engle; Qingming Chang

    2004-03-30

    This report summarizes a two-year project, DE-FC07-01ID13983 that concerns the gating of aluminum castings in permanent molds. The main goal of the project is to improve the quality of aluminum castings produced in permanent molds. The approach taken was determine how the vertical type gating systems used for permanent mold castings can be designed to fill the mold cavity with a minimum of damage to the quality of the resulting casting. It is evident that somewhat different systems are preferred for different shapes and sizes of aluminum castings. The main problems caused by improper gating are entrained aluminum oxide films and entrapped gas. The project highlights the characteristic features of gating systems used in permanent mold aluminum foundries and recommends gating procedures designed to avoid common defects. The study also provides direct evidence on the filling pattern and heat flow behavior in permanent mold castings.

  19. Electrical behavior of atomic layer deposited high quality SiO{sub 2} gate dielectric

    SciTech Connect (OSTI)

    Pradhan, Sangram K.; Tanyi, Ekembu K.; Skuza, Jonathan R.; Xiao, Bo; Pradhan, Aswini K., E-mail: apradhan@nsu.edu [Center for Materials Research, Norfolk State University, 700 Park Ave., Norfolk, Virginia 23504 (United States)

    2015-01-01

    Comprehensive and systematic electrical studies were performed on fabrication of high quality SiO{sub 2} thin films MOS capacitor using the robust, novel, and simple atomic layer deposition (ALD) technique using highly reactive ozone and tris (dimethylamino) silane (TDMAS) precursors. Ideal capacitance–voltage curve exhibits a very small frequency dispersion and hysteresis behavior of the SiO{sub 2} MOS capacitor grown at 1?s TDMAS pulse, suggesting excellent interfacial quality and purity of the film as probed using x-ray photoelectron studies. The flat-band voltage of the device shifted from negative toward positive voltage axis with increase of TDMAS pulses from 0.2 to 2 s. Based on an equivalent oxide thickness point of view, all SiO{sub 2} films have gate leakage current density of (5.18?×?10{sup ?8} A/cm{sup 2}) as well as high dielectric break down fields of more than (?10 MV/cm), which is better and comparable to that of thermally grown SiO{sub 2} at temperatures above 800?°C. These appealing electrical properties of ALD grown SiO{sub 2} thin films enable its potential applications such as high-quality gate insulators for thin film MOS transistors, as well as insulators for sensor and nanostructures on nonsilicon substrates.

  20. Electrical characterization of native-oxide InAlPGaAs metal-oxide-semiconductor heterostructures using

    E-Print Network [OSTI]

    Electrical characterization of native-oxide InAlPÕGaAs metal-oxide-semiconductor heterostructures 8 December 2003; accepted 20 January 2004 InAIP native oxide/GaAs metal-oxide-semiconductor MOS of Schottky gates can lead to excessive gate leakage current and also restrict the forward gate bias to only

  1. Strained Ge channel p-type metaloxidesemiconductor field-effect transistors grown on Si1xGex Si virtual substrates

    E-Print Network [OSTI]

    Strained Ge channel p-type metal­oxide­semiconductor field-effect transistors grown on Si1ÀxGex ÕSi 2001; accepted for publication 29 August 2001 We have fabricated strained Ge channel p-type metal­oxide­semiconductor field-effect transistors (p-MOSFETs) on Si0.3Ge0.7 virtual substrates. The poor interface between

  2. INTERBAND TUNNEL TRANSISTORS A Dissertation

    E-Print Network [OSTI]

    D and 2D semiconductors.................................13 2.3 Comparison of Zener tunneling current the design and modeling of semiconducting and graphene nanoribbon-based tunnel transistors, to understand-dimensional semiconductors are derived to establish the guidelines for tunnel transistor design. An analytic expression

  3. A photonic transistor device based on photons and phonons in a cavity electromechanical system

    E-Print Network [OSTI]

    Cheng Jiang; Ka-Di Zhu

    2012-09-21

    We present a scheme for photonic transistors based on photons and phonons in a cavity electromechanical system, which is consisted of a superconducting microwave cavity coupled to a nanomechanical resonator. Control of the propagation of photons is achieved through the interaction of microwave field (photons) and nanomechanical vibrations (phonons). By calculating the transmission spectrum of the signal field, we show that the signal field can be efficiently attenuated or amplified, depending on the power of a second `gating'(pump) field. This scheme may be a promising candidate for single-photon transistors and pave the way for numerous applications in telecommunication and quantum information technologies.

  4. A photonic transistor device based on photons and phonons in a cavity electromechanical system

    E-Print Network [OSTI]

    Jiang, Cheng

    2012-01-01

    We present a scheme for photonic transistors based on photons and phonons in a cavity electromechanical system, which is consisted of a superconducting microwave cavity coupled to a nanomechanical resonator. Control of the propagation of photons is achieved through the interaction of microwave field (photons) and nanomechanical vibrations (phonons). By calculating the transmission spectrum of the signal field, we show that the signal field can be efficiently attenuated or amplified, depending on the power of a second `gating'(pump) field. This scheme may be a promising candidate for single-photon transistors and pave the way for numerous applications in telecommunication and quantum information technologies.

  5. Nonvolatile memory disturbs due to gate and junction leakage currents

    E-Print Network [OSTI]

    Schroder, Dieter K.

    leakage currents induced by stress due to LOCOS and trap- assisted tunneling (TAT). * Corresponding author Department of Electrical Engineering and Center for Solid State Electronics Research, Arizona State) from traps within the gate oxides. Such low gate leakage currents can lead to sufficient charge

  6. Range gated imaging experiments using gated intensifiers

    SciTech Connect (OSTI)

    McDonald, T.E. Jr.; Yates, G.J.; Cverna, F.H.; Gallegos, R.A.; Jaramillo, S.A.; Numkena, D.M.; Payton, J.; Pena-Abeyta, C.R.

    1999-03-01

    A variety of range gated imaging experiments using high-speed gated/shuttered proximity focused microchannel plate image intensifiers (MCPII) are reported. Range gated imaging experiments were conducted in water for detection of submerged mines in controlled turbidity tank test and in sea water for the Naval Coastal Sea Command/US Marine Corps. Field experiments have been conducted consisting of kilometer range imaging of resolution targets and military vehicles in atmosphere at Eglin Air Force Base for the US Air Force, and similar imaging experiments, but in smoke environment, at Redstone Arsenal for the US Army Aviation and Missile Command (AMCOM). Wavelength of the illuminating laser was 532 nm with pulse width ranging from 6 to 12 ns and comparable gate widths. These tests have shown depth resolution in the tens of centimeters range from time phasing reflected LADAR images with MCPII shutter opening.

  7. Demonstrating 1 nm-oxide-equivalent-thickness HfO{sub 2}/InSb structure with unpinning Fermi level and low gate leakage current density

    SciTech Connect (OSTI)

    Trinh, Hai-Dang [Department of Materials Science and Engineering, National Chiao Tung University, 1001 University Road, Hsinchu, Taiwan (China) [Department of Materials Science and Engineering, National Chiao Tung University, 1001 University Road, Hsinchu, Taiwan (China); Department of Physics, Hanoi National University of Education, 136 Xuan Thuy, Cau Giay, Hanoi (Viet Nam); Lin, Yueh-Chin; Nguyen, Hong-Quan; Luc, Quang-Ho [Department of Materials Science and Engineering, National Chiao Tung University, 1001 University Road, Hsinchu, Taiwan (China)] [Department of Materials Science and Engineering, National Chiao Tung University, 1001 University Road, Hsinchu, Taiwan (China); Nguyen, Minh-Thuy; Duong, Quoc-Van; Nguyen, Manh-Nghia [Department of Physics, Hanoi National University of Education, 136 Xuan Thuy, Cau Giay, Hanoi (Viet Nam)] [Department of Physics, Hanoi National University of Education, 136 Xuan Thuy, Cau Giay, Hanoi (Viet Nam); Wang, Shin-Yuan [Department of Electronic Engineering, National Chiao Tung University 1001, University Rd., Hsinchu 300, Taiwan (China)] [Department of Electronic Engineering, National Chiao Tung University 1001, University Rd., Hsinchu 300, Taiwan (China); Yi Chang, Edward [Department of Materials Science and Engineering, National Chiao Tung University, 1001 University Road, Hsinchu, Taiwan (China) [Department of Materials Science and Engineering, National Chiao Tung University, 1001 University Road, Hsinchu, Taiwan (China); Department of Electronic Engineering, National Chiao Tung University 1001, University Rd., Hsinchu 300, Taiwan (China)

    2013-09-30

    In this work, the band alignment, interface, and electrical characteristics of HfO{sub 2}/InSb metal-oxide-semiconductor structure have been investigated. By using x-ray photoelectron spectroscopy analysis, the conduction band offset of 1.78 ± 0.1 eV and valence band offset of 3.35 ± 0.1 eV have been extracted. The transmission electron microscopy analysis has shown that HfO{sub 2} layer would be a good diffusion barrier for InSb. As a result, 1 nm equivalent-oxide-thickness in the 4 nm HfO{sub 2}/InSb structure has been demonstrated with unpinning Fermi level and low leakage current of 10{sup ?4} A/cm{sup ?2}. The D{sub it} value of smaller than 10{sup 12} eV{sup ?1}cm{sup ?2} has been obtained using conduction method.

  8. Charge Storage Behavior of Nanowire Transistors Functionalized with Bis(terpyridine)-Fe(II) Molecules: Dependence on Molecular Structure

    E-Print Network [OSTI]

    Zhou, Chongwu

    a floating gate can be charged or discharged via electron tunneling through a thin oxide layer.3 Replacing the insulating oxide layer with molecular components will further reduce device size and simplify fabrication

  9. Nonlinear photoresponse of field effect transistors terahertz detectors at high irradiation intensities

    SciTech Connect (OSTI)

    But, D. B.; Drexler, C.; Ganichev, S. D.; Sakhno, M. V.; Sizov, F. F.; Dyakonova, N.; Drachenko, O.; Gutin, A.; Knap, W.

    2014-04-28

    Terahertz power dependence of the photoresponse of field effect transistors, operating at frequencies from 0.1 to 3 THz for incident radiation power density up to 100?kW/cm{sup 2} was studied for Si metal–oxide–semiconductor field-effect transistors and InGaAs high electron mobility transistors. The photoresponse increased linearly with increasing radiation intensity up to the kW/cm{sup 2} range. Nonlinearity followed by saturation of the photoresponse was observed for all investigated field effect transistors for intensities above several kW/cm{sup 2}. The observed photoresponse nonlinearity is explained by nonlinearity and saturation of the transistor channel current. A theoretical model of terahertz field effect transistor photoresponse at high intensity was developed. The model explains quantitative experimental data both in linear and nonlinear regions. Our results show that dynamic range of field effect transistors is very high and can extend over more than six orders of magnitudes of power densities (from ?0.5 mW/cm{sup 2} to ?5?kW/cm{sup 2})

  10. Silicon-on-insulator field effect transistor with improved body ties for rad-hard applications

    DOE Patents [OSTI]

    Schwank, James R. (Albuquerque, NM); Shaneyfelt, Marty R. (Albuquerque, NM); Draper, Bruce L. (Albuquerque, NM); Dodd, Paul E. (Tijeras, NM)

    2001-01-01

    A silicon-on-insulator (SOI) field-effect transistor (FET) and a method for making the same are disclosed. The SOI FET is characterized by a source which extends only partially (e.g. about half-way) through the active layer wherein the transistor is formed. Additionally, a minimal-area body tie contact is provided with a short-circuit electrical connection to the source for reducing floating body effects. The body tie contact improves the electrical characteristics of the transistor and also provides an improved single-event-upset (SEU) radiation hardness of the device for terrestrial and space applications. The SOI FET also provides an improvement in total-dose radiation hardness as compared to conventional SOI transistors fabricated without a specially prepared hardened buried oxide layer. Complementary n-channel and p-channel SOI FETs can be fabricated according to the present invention to form integrated circuits (ICs) for commercial and military applications.

  11. IEEE ELECTRON DEVICE LETTERS, VOL. 29, NO. 2, FEBRUARY 2008 183 Externally Assembled Gate-All-Around Carbon

    E-Print Network [OSTI]

    IEEE ELECTRON DEVICE LETTERS, VOL. 29, NO. 2, FEBRUARY 2008 183 Externally Assembled Gate-All-Around Carbon Nanotube Field-Effect Transistor Zhihong Chen, Member, IEEE, Damon Farmer, Sheng Xu, Roy Gordon, Phaedon Avouris, Member, IEEE, and Joerg Appenzeller, Senior Member, IEEE Abstract--In this letter, we

  12. Elimination of NonSimultaneous Triggering Effects in Fingertype ESD Protection Transistors Using

    E-Print Network [OSTI]

    Dutton, Robert W.

    and the source connected to ground, the n + =p diode at the drain is in reverse bias until avalanche breakdown shallow junctions, silicided contacts, higher well doping, thinner gate oxides and more compact layouts

  13. Elimination of Non-Simultaneous Triggering E ects in Finger-type ESD Protection Transistors Using

    E-Print Network [OSTI]

    Dutton, Robert W.

    connected to ground, the n+=p diode at the drain is in reverse bias until avalanche breakdown occurs junctions, silicided contacts, higher well doping, thinner gate oxides and more compact layouts. A proposed

  14. Charge Trapping Characteristics of SONOS Capacitors with Control Gates of Different Work Functions during Program/Erase Operations

    E-Print Network [OSTI]

    Lee, Jong Duk

    (3.2 eV), which gives higher probability of the electron tunneling from control gate to the silicon traps as its program mechanism. When a positive bias stress is applied on the control gate, electrons gate and top oxide tunnel into the silicon nitride layer and recombine with holes which are trapped

  15. Optical XOR gate

    DOE Patents [OSTI]

    Vawter, G. Allen

    2013-11-12

    An optical XOR gate is formed as a photonic integrated circuit (PIC) from two sets of optical waveguide devices on a substrate, with each set of the optical waveguide devices including an electroabsorption modulator electrically connected in series with a waveguide photodetector. The optical XOR gate utilizes two digital optical inputs to generate an XOR function digital optical output. The optical XOR gate can be formed from III-V compound semiconductor layers which are epitaxially deposited on a III-V compound semiconductor substrate, and operates at a wavelength in the range of 0.8-2.0 .mu.m.

  16. Representative Control Gates

    E-Print Network [OSTI]

    Rhoads, James

    Representative Staffing & Management Reviews & Control Gates The NASA Program/Project Life Cycle Concept C Concept/Design Evaluation Criteria ° Feasibility Assessment ° Life Cycle Cost Estimates ° Trade Requirements Establish Optimum System Design Analyze Mission Requirements Establish Optimum Architecture

  17. Reliability of AlGaN/GaN high electron mobility transistors on low dislocation density bulk GaN substrate: Implications of surface step edges

    SciTech Connect (OSTI)

    Killat, N., E-mail: Nicole.Killat@bristol.ac.uk, E-mail: Martin.Kuball@bristol.ac.uk; Montes Bajo, M.; Kuball, M., E-mail: Nicole.Killat@bristol.ac.uk, E-mail: Martin.Kuball@bristol.ac.uk [Center for Device Thermography and Reliability (CDTR), H.H. Wills Physics Laboratory, Tyndall Avenue, Bristol BS8 1TL (United Kingdom); Paskova, T. [Kyma Technologies, Inc., Raleigh, North Carolina 27617 (United States) [Kyma Technologies, Inc., Raleigh, North Carolina 27617 (United States); Materials Science and Engineering Department, North Carolina State University, Raleigh, North Carolina 27695 (United States); Evans, K. R. [Kyma Technologies, Inc., Raleigh, North Carolina 27617 (United States)] [Kyma Technologies, Inc., Raleigh, North Carolina 27617 (United States); Leach, J. [Kyma Technologies, Inc., Raleigh, North Carolina 27617 (United States) [Kyma Technologies, Inc., Raleigh, North Carolina 27617 (United States); Electrical and Computer Engineering Department, Virginia Commonwealth University, Richmond, Virginia 23284 (United States); Li, X.; Özgür, Ü.; Morkoç, H. [Electrical and Computer Engineering Department, Virginia Commonwealth University, Richmond, Virginia 23284 (United States)] [Electrical and Computer Engineering Department, Virginia Commonwealth University, Richmond, Virginia 23284 (United States); Chabak, K. D.; Crespo, A.; Gillespie, J. K.; Fitch, R.; Kossler, M.; Walker, D. E.; Trejo, M.; Via, G. D.; Blevins, J. D. [Air Force Research Laboratory, Wright-Patterson Air Force Base, Dayton, Ohio 45433 (United States)] [Air Force Research Laboratory, Wright-Patterson Air Force Base, Dayton, Ohio 45433 (United States)

    2013-11-04

    To enable gaining insight into degradation mechanisms of AlGaN/GaN high electron mobility transistors, devices grown on a low-dislocation-density bulk-GaN substrate were studied. Gate leakage current and electroluminescence (EL) monitoring revealed a progressive appearance of EL spots during off-state stress which signify the generation of gate current leakage paths. Atomic force microscopy evidenced the formation of semiconductor surface pits at the failure location, which corresponds to the interaction region of the gate contact edge and the edges of surface steps.

  18. Semianalytical quantum model for graphene field-effect transistors

    SciTech Connect (OSTI)

    Pugnaghi, Claudio; Grassi, Roberto Gnudi, Antonio; Di Lecce, Valerio; Gnani, Elena; Reggiani, Susanna; Baccarani, Giorgio

    2014-09-21

    We develop a semianalytical model for monolayer graphene field-effect transistors in the ballistic limit. Two types of devices are considered: in the first device, the source and drain regions are doped by charge transfer with Schottky contacts, while, in the second device, the source and drain regions are doped electrostatically by a back gate. The model captures two important effects that influence the operation of both devices: (i) the finite density of states in the source and drain regions, which limits the number of states available for transport and can be responsible for negative output differential resistance effects, and (ii) quantum tunneling across the potential steps at the source-channel and drain-channel interfaces. By comparison with a self-consistent non-equilibrium Green's function solver, we show that our model provides very accurate results for both types of devices, in the bias region of quasi-saturation as well as in that of negative differential resistance.

  19. IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 4, NO. 5, SEPTEMBER 2005 599 Quantum Interference in Fully Depleted Tri-Gate

    E-Print Network [OSTI]

    Gilbert, Matthew

    and drain dimen- sions. A uniform 1-nm oxide layer covers the top and sides of the device to isolate the gates from the semiconductor. Under the device is a 100-nm-thick oxide layer. This device is studied

  20. Tetracene air-gap single-crystal field-effect transistors Yu Xia, Vivek Kalihari, and C. Daniel Frisbiea

    E-Print Network [OSTI]

    Rogers, John A.

    Tetracene air-gap single-crystal field-effect transistors Yu Xia, Vivek Kalihari, and C. Daniel FETs utilizing an air or vacuum gap as the gate dielectric. The linear mobility of the device can be as high as 1.6 cm2 /V s in air, with a subthreshold slope lower than 0.5 V nF/decade cm2 . By changing

  1. Single-transistor-clocked flip-flop

    DOE Patents [OSTI]

    Zhao, Peiyi; Darwish, Tarek; Bayoumi, Magdy

    2005-08-30

    The invention provides a low power, high performance flip-flop. The flip-flop uses only one clocked transistor. The single clocked transistor is shared by the first and second branches of the device. A pulse generator produces a clock pulse to trigger the flip-flop. In one preferred embodiment the device can be made as a static explicit pulsed flip-flop which employs only two clocked transistors.

  2. All-optical polariton transistor

    E-Print Network [OSTI]

    Ballarini, Dario; Cancellieri, Emiliano; Houdré, Romuald; Giacobino, Elisabeth; Cingolani, Roberto; Bramati, Alberto; Gigli, Giuseppe; Sanvitto, Daniele

    2013-01-01

    While optical technology provides the best solution for the transmission of information, optical logics is still in its infancy. In particular, energy considerations impose to reduce the power required for nonlinear interactions in future optical devices, which, in addition, should be compatible with present semiconductor technology. Exciton-polaritons are composite particles, resulting from the strong coupling between excitons and photons, which have recently demonstrated exceptional properties like huge non-linearities, condensation and superfluidity. Here we experimentally demonstrate a switching scheme for polaritons moving in the plane of a microcavity which satisfy all the requirements for an all-optical transistor. Two laser beams are converted into polariton quasi-particles, which are used as input states for generating and controlling the output, obtaining up to 19 times amplification. Moreover this polariton transistor shows to work with an interchangeable input-output signal, and needing an energy ...

  3. Complementary junction heterostructure field-effect transistor

    DOE Patents [OSTI]

    Baca, A.G.; Drummond, T.J.; Robertson, P.J.; Zipperian, T.E.

    1995-12-26

    A complimentary pair of compound semiconductor junction heterostructure field-effect transistors and a method for their manufacture are disclosed. The p-channel junction heterostructure field-effect transistor uses a strained layer to split the degeneracy of the valence band for a greatly improved hole mobility and speed. The n-channel device is formed by a compatible process after removing the strained layer. In this manner, both types of transistors may be independently optimized. Ion implantation is used to form the transistor active and isolation regions for both types of complimentary devices. The invention has uses for the development of low power, high-speed digital integrated circuits. 10 figs.

  4. Probing Organic Transistors with Infrared Beams

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    transistors are well-understood, basic components of contemporary electronic technology. In contrast, there is growing need for the development of electronic devices...

  5. Complementary junction heterostructure field-effect transistor

    DOE Patents [OSTI]

    Baca, Albert G. (Albuquerque, NM); Drummond, Timothy J. (Albuquerque, NM); Robertson, Perry J. (Albuquerque, NM); Zipperian, Thomas E. (Albuquerque, NM)

    1995-01-01

    A complimentary pair of compound semiconductor junction heterostructure field-effect transistors and a method for their manufacture are disclosed. The p-channel junction heterostructure field-effect transistor uses a strained layer to split the degeneracy of the valence band for a greatly improved hole mobility and speed. The n-channel device is formed by a compatible process after removing the strained layer. In this manner, both types of transistors may be independently optimized. Ion implantation is used to form the transistor active and isolation regions for both types of complimentary devices. The invention has uses for the development of low power, high-speed digital integrated circuits.

  6. Compact modeling of Double-Gate MOSFETs

    E-Print Network [OSTI]

    Lu, Huaxin

    2006-01-01

    Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering," in Symposium on VLSI Technology

  7. Sulfur surface chemistry on the platinum gate of a silicon carbide based hydrogen sensor

    E-Print Network [OSTI]

    Tobin, Roger G.

    Sulfur surface chemistry on the platinum gate of a silicon carbide based hydrogen sensor Yung Ho September 2007 We have investigated the effects of sulfur contamination on a Pt-gate silicon carbide based monitoring, solid-oxide fuel cells, and coal gasification, require operation at much higher temperatures than

  8. High-Aspect Ratio Deep Sub-Micron -Si Gate Etch Process Control

    E-Print Network [OSTI]

    Grizzle, Jessy W.

    .-M. Park Mask U of M Industry Industry Goal · High throughput · Good morphology · Minimum gate oxide damage1 High-Aspect Ratio Deep Sub-Micron -Si Gate Etch Process Control H.-M. Park, T. L. Brock, D · Blank sample ·Patterned sample · Conclusion H.-M. Park #12;3 Etching Process of Deep Sub

  9. Silicon field-effect transistors as radiation detectors for the Sub-THz range

    SciTech Connect (OSTI)

    But, D. B., E-mail: but.dmitry@gmail.com; Golenkov, O. G.; Sakhno, N. V.; Sizov, F. F.; Korinets, S. V.; Gumenjuk-Sichevska, J. V.; Reva, V. P.; Bunchuk, S. G. [National Academy of Sciences of Ukraine, Lashkaryov Institute of Semiconductor Physics (Ukraine)

    2012-05-15

    The nonresonance response of silicon metal-oxide-semiconductor field-effect transistors (Si-MOSFETs) with a long channel (1-20 {mu}m) to radiation in the frequency range 43-135 GHz is studied. The transistors are fabricated by the standard CMOS technology with 1-{mu}m design rules. The volt-watt sensitivity and the noise equivalent power (NEP) for such detectors are estimated with the calculated effective area of the detecting element taken into account. It is shown that such transistors can operate at room temperature as broadband direct detectors of sub-THz radiation. In the 4-5 mm range of wavelengths, the volt-watt sensitivity can be as high as tens of kV/W and the NEP can amount to 10{sup -11} - 10{sup -12}W/{radical}Hz . The parameters of detectors under study can be improved by the optimization of planar antennas.

  10. Universal power transistor base drive control unit

    DOE Patents [OSTI]

    Gale, Allan R. (Allen Park, MI); Gritter, David J. (Racine, WI)

    1988-01-01

    A saturation condition regulator system for a power transistor which achieves the regulation objectives of a Baker clamp but without dumping excess base drive current into the transistor output circuit. The base drive current of the transistor is sensed and used through an active feedback circuit to produce an error signal which modulates the base drive current through a linearly operating FET. The collector base voltage of the power transistor is independently monitored to develop a second error signal which is also used to regulate base drive current. The current-sensitive circuit operates as a limiter. In addition, a fail-safe timing circuit is disclosed which automatically resets to a turn OFF condition in the event the transistor does not turn ON within a predetermined time after the input signal transition.

  11. Universal power transistor base drive control unit

    DOE Patents [OSTI]

    Gale, A.R.; Gritter, D.J.

    1988-06-07

    A saturation condition regulator system for a power transistor is disclosed which achieves the regulation objectives of a Baker clamp but without dumping excess base drive current into the transistor output circuit. The base drive current of the transistor is sensed and used through an active feedback circuit to produce an error signal which modulates the base drive current through a linearly operating FET. The collector base voltage of the power transistor is independently monitored to develop a second error signal which is also used to regulate base drive current. The current-sensitive circuit operates as a limiter. In addition, a fail-safe timing circuit is disclosed which automatically resets to a turn OFF condition in the event the transistor does not turn ON within a predetermined time after the input signal transition. 2 figs.

  12. Giant amplification of tunnel magnetoresistance in a molecular junction: Molecular spin-valve transistor

    SciTech Connect (OSTI)

    Dhungana, Kamal B.; Pati, Ranjit, E-mail: patir@mtu.edu [Department of Physics, Michigan Technological University, Houghton, Michigan 49931 (United States)

    2014-04-21

    Amplification of tunnel magnetoresistance by gate field in a molecular junction is the most important requirement for the development of a molecular spin valve transistor. Herein, we predict a giant amplification of tunnel magnetoresistance in a single molecular spin valve junction, which consists of Ru-bis-terpyridine molecule as a spacer between two ferromagnetic nickel contacts. Based on the first-principles quantum transport approach, we show that a modest change in the gate field that is experimentally accessible can lead to a substantial amplification (320%) of tunnel magnetoresistance. The origin of such large amplification is attributed to the spin dependent modification of orbitals at the molecule-lead interface and the resultant Stark effect induced shift in channel position with respect to the Fermi energy.

  13. Countering Aging Effects through Field Gate Sizing 

    E-Print Network [OSTI]

    Henrichson, Trenton D.

    2010-01-14

    Transistor aging through negative bias temperature instability (NBTI) has become a major lifetime constraint in VLSI circuits. We propose a technique that uses antifuses to widen PMOS transistors later in a circuit?s life cycle to combat aging...

  14. Gate complexity using Dynamic Programming

    E-Print Network [OSTI]

    Srinivas Sridharan; Mile Gu; Matthew R. James

    2008-07-03

    The relationship between efficient quantum gate synthesis and control theory has been a topic of interest in the quantum control literature. Motivated by this work, we describe in the present article how the dynamic programming technique from optimal control may be used for the optimal synthesis of quantum circuits. We demonstrate simulation results on an example system on SU(2), to obtain plots related to the gate complexity and sample paths for different logic gates.

  15. Gate-induced Barrier Field Effect Transistor (GBFET) A New Thin Film Transistor for Active Matrix Liquid Crystal Display Systems

    E-Print Network [OSTI]

    Kumar, M. Jagadesh

    , Semnan University, Semnan, Iran E-mail: mamidala@ieee.org aliorouji@ee.iitd.ac.in Abstract Using two the number of grains in the channel using excimer laser annealing [4,5]. Since the grain size increases, for example, pulsed wave laser annealing, we can still induce large potential barriers in the channel using

  16. Method of fabrication of display pixels driven by silicon thin film transistors

    DOE Patents [OSTI]

    Carey, Paul G. (Mountain View, CA); Smith, Patrick M. (San Ramon, CA)

    1999-01-01

    Display pixels driven by silicon thin film transistors are fabricated on plastic substrates for use in active matrix displays, such as flat panel displays. The process for forming the pixels involves a prior method for forming individual silicon thin film transistors on low-temperature plastic substrates. Low-temperature substrates are generally considered as being incapable of withstanding sustained processing temperatures greater than about 200.degree. C. The pixel formation process results in a complete pixel and active matrix pixel array. A pixel (or picture element) in an active matrix display consists of a silicon thin film transistor (TFT) and a large electrode, which may control a liquid crystal light valve, an emissive material (such as a light emitting diode or LED), or some other light emitting or attenuating material. The pixels can be connected in arrays wherein rows of pixels contain common gate electrodes and columns of pixels contain common drain electrodes. The source electrode of each pixel TFT is connected to its pixel electrode, and is electrically isolated from every other circuit element in the pixel array.

  17. Spin effects in single-electron transistors

    E-Print Network [OSTI]

    Granger, Ghislain

    2005-01-01

    Basic electron transport phenomena observed in single-electron transistors (SETs) are introduced, such as Coulomb-blockade diamonds, inelastic cotunneling thresholds, the spin-1/2 Kondo effect, and Fano interference. With ...

  18. David Gates home page

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    AFDC Printable Version Share this resource Send a link to EERE: Alternative Fuels Data Center Home Page to someone by E-mail Share EERE: Alternative Fuels Data Center Home Page on Facebook Tweet about EERE: Alternative Fuels Data Center Home Page on Twitter Bookmark EERE: Alternative Fuels Data Center Homesum_a_epg0_fpd_mmcf_m.xls" ,"Available from WebQuantityBonneville Power Administration would like submit theCovalent Bonding Low-Cost2 DOE HQSiteoC. DoranDatabaseDepartment ofGates

  19. A thin film transistor driven microchannel device 

    E-Print Network [OSTI]

    Lee, Hyun Ho

    2005-02-17

    THIN FILM TRANSISTOR DRIVEN MICROCHANNEL DEVICE FOR PROTEIN AND DNA ELECTROPHORESIS A Dissertation by HYUN HO LEE Submitted to the Office of Graduate Studies of Texas A&M University in partial fulfillment of the requirements... for the degree of DOCTOR OF PHILOSOPHY December 2004 Major Subject: Chemical Engineering A THIN FILM TRANSISTOR DRIVEN MICROCHANNEL DEVICE FOR PROTEIN AND DNA ELECTROPHORESIS A Dissertation by HYUN HO LEE Submitted to Texas A...

  20. Penn State DOE GATE Program

    SciTech Connect (OSTI)

    Anstrom, Joel

    2012-08-31

    The Graduate Automotive Technology Education (GATE) Program at The Pennsylvania State University (Penn State) was established in October 1998 pursuant to an award from the U.S. Department of Energy (U.S. DOE). The focus area of the Penn State GATE Program is advanced energy storage systems for electric and hybrid vehicles.

  1. Low temperature thin film transistors with hollow cathode plasma-assisted atomic layer deposition based GaN channels

    SciTech Connect (OSTI)

    Bolat, S. E-mail: aokyay@ee.bilkent.edu.tr; Tekcan, B.; Ozgit-Akgun, C.; Biyikli, N.; Okyay, A. K. E-mail: aokyay@ee.bilkent.edu.tr

    2014-06-16

    We report GaN thin film transistors (TFT) with a thermal budget below 250?°C. GaN thin films are grown at 200?°C by hollow cathode plasma-assisted atomic layer deposition (HCPA-ALD). HCPA-ALD-based GaN thin films are found to have a polycrystalline wurtzite structure with an average crystallite size of 9.3?nm. TFTs with bottom gate configuration are fabricated with HCPA-ALD grown GaN channel layers. Fabricated TFTs exhibit n-type field effect characteristics. N-channel GaN TFTs demonstrated on-to-off ratios (I{sub ON}/I{sub OFF}) of 10{sup 3} and sub-threshold swing of 3.3?V/decade. The entire TFT device fabrication process temperature is below 250?°C, which is the lowest process temperature reported for GaN based transistors, so far.

  2. Resonant Body Transistors in IBM's 32nm SOI CMOS technology

    E-Print Network [OSTI]

    Marathe, Radhika A.

    This work presents an unreleased CMOS-integrated MEMS resonators fabricated at the transistor level of IBM's 32SOI technology and realized without the need for any post-processing or packaging. These Resonant Body Transistors ...

  3. Technology and market evaluation for semiconductor nanowire transistors

    E-Print Network [OSTI]

    Omampuliyur, Rajamouly Swaminathan

    2008-01-01

    Information processing systems have been getting more powerful over the course of the past three decades due to the scaling of transistor dimensions. Scaling of transistor dimension causes a plethora of technological ...

  4. 224 IEEE ELECTRON DEVICE LETTERS, VOL. 23, NO. 4, APRIL 2002 Gate Length Dependent Polysilicon Depletion Effects

    E-Print Network [OSTI]

    Dutton, Robert W.

    - tribution effect, MOSFET, polydepletion, polysilicon depletion ef- fect. I. INTRODUCTION IN THE dual n -p impurity penetration through the gate oxide, while maintaining the required source/drain junction depths [2

  5. Graphene nanopore field effect transistors

    SciTech Connect (OSTI)

    Qiu, Wanzhi; Skafidas, Efstratios, E-mail: sskaf@unimelb.edu.au [Centre for Neural Engineering, The University of Melbourne, 203 Bouverie Street, Carlton, Victoria 3053 (Australia); Department of Electrical and Electronic Engineering, The University of Melbourne, Parkville, Victoria 3010 (Australia)

    2014-07-14

    Graphene holds great promise for replacing conventional Si material in field effect transistors (FETs) due to its high carrier mobility. Previously proposed graphene FETs either suffer from low ON-state current resulting from constrained channel width or require complex fabrication processes for edge-defecting or doping. Here, we propose an alternative graphene FET structure created on intrinsic metallic armchair-edged graphene nanoribbons with uniform width, where the channel region is made semiconducting by drilling a pore in the interior, and the two ends of the nanoribbon act naturally as connecting electrodes. The proposed GNP-FETs have high ON-state currents due to seamless atomic interface between the channel and electrodes and are able to be created with arbitrarily wide ribbons. In addition, the performance of GNP-FETs can be tuned by varying pore size and ribbon width. As a result, their performance and fabrication process are more predictable and controllable in comparison to schemes based on edge-defects and doping. Using first-principle transport calculations, we show that GNP-FETs can achieve competitive leakage current of ?70?pA, subthreshold swing of ?60?mV/decade, and significantly improved On/Off current ratios on the order of 10{sup 5} as compared with other forms of graphene FETs.

  6. Avalanche spin-valve transistor K. J. Russell,a)

    E-Print Network [OSTI]

    Russell, Kasey

    Avalanche spin-valve transistor K. J. Russell,a) Ian Appelbaum,b) Wei Yi, D. J. Monsma, F. Capasso, California 93106 (Received 11 June 2004; accepted 10 September 2004) A spin-valve transistor with a Ga allow fabrication of spin-valve transistors with high gain in a variety of materials. © 2004 American

  7. Stretchable transistors with buckled carbon nanotube films as conducting channels

    DOE Patents [OSTI]

    Arnold, Michael S; Xu, Feng

    2015-03-24

    Thin-film transistors comprising buckled films comprising carbon nanotubes as the conductive channel are provided. Also provided are methods of fabricating the transistors. The transistors, which are highly stretchable and bendable, exhibit stable performance even when operated under high tensile strains.

  8. Strong Room-temperature Negative Transconductance In An Axial Si/Ge Hetero-nanowire Tunneling Field-effect Transistor

    SciTech Connect (OSTI)

    Zhang, Peng; Le, Son T.; Hou, Xiaoxiao; Zaslavsky, A.; Perea, Daniel E.; Dayeh, Shadi A.; Picraux, Samuel T.

    2014-08-11

    We report on room-temperature negative transconductance (NTC) in axial Si/Ge hetero-nanowire tunneling field-effect transistors (TFETs). The NTC produces a current peak-to-valley ratio > 45, a high value for a Si-based device. We characterize the NTC characteristics over a range of gate VG and drain VD voltages, finding that NTC persists down to VD = –50 mV. The physical mechanism responsible for the NTC is the VG-induced depletion in the p-Ge section that eventually reduces the maximum electric field that triggers the tunneling ID, as confirmed via three-dimensional TCAD simulations.

  9. Ultra-low noise high electron mobility transistors for high-impedance and low-frequency deep cryogenic readout electronics

    SciTech Connect (OSTI)

    Dong, Q.; Liang, Y. X.; Ferry, D.; Cavanna, A.; Gennser, U.; Couraud, L.; Jin, Y.

    2014-07-07

    We report on the results obtained from specially designed high electron mobility transistors at 4.2?K: the gate leakage current can be limited lower than 1 aA, and the equivalent input noise-voltage and noise-current at 1?Hz can reach 6.3 nV/Hz{sup 1?2} and 20 aA/Hz{sup 1?2}, respectively. These results open the way to realize high performance low-frequency readout electronics under very low-temperature conditions.

  10. High-Performance Organic Field-Effect Transistors with Dielectric and Active Layers Printed Sequentially by Ultrasonic Spraying

    SciTech Connect (OSTI)

    Shao, Ming [ORNL; Sanjib, Das [University of Tennessee, Knoxville (UTK); Chen, Jihua [ORNL; Keum, Jong Kahk [ORNL; Ivanov, Ilia N [ORNL; Gu, Gong [University of Tennessee, Knoxville (UTK); Geohegan, David B [ORNL; Xiao, Kai [ORNL

    2013-01-01

    High-performance, flexible organic field-effect transistors (OFETs) are reported with PVP dielectric and TIPS-PEN active layers sequentially deposited by ultrasonic spray-coating on plastic substrate. OFETs fabricated in ambient air with a bottom-gate/top-contact geometry are shown to achieve on/off ratios of >104 and mobilities as high as 0.35 cm2/Vs. These rival the characteristics of the best solution-processible small molecule FETs fabricated by other fabrication methods such as drop casting and ink-jet printing.

  11. Magnetic field effect on the terahertz emission from nanometer InGaAs/AlInAs high electron mobility transistors

    SciTech Connect (OSTI)

    Dyakonova, N.; Teppe, F.; Lusakowski, J.; Knap, W.; Levinshtein, M.; Dmitriev, A.P.; Shur, M.S.; Bollaert, S.; Cappy, A.

    2005-06-01

    The influence of the magnetic field on the excitation of plasma waves in InGaAs/AlInAs lattice matched high electron mobility transistors is reported. The threshold source-drain voltage of the excitation of the terahertz emission shifts to higher values under a magnetic field increasing from 0 to 6 T. We show that the main change of the emission threshold in relatively low magnetic fields (smaller than approximately 4 T) is due to the magnetoresistance of the ungated parts of the channel. In higher magnetic fields, the effect of the magnetic field on the gated region of the device becomes important.

  12. Fermi-level shifts in graphene transistors with dual-cut channels scraped by atomic force microscope tips

    SciTech Connect (OSTI)

    Lin, Meng-Yu [Institute of Electronics, National Taiwan University, Taipei 10617, Taiwan (China); Research Center for Applied Sciences, Academia Sinica, Taipei 11529, Taiwan (China); Chen, Yen-Hao [Department of Photonics, National Chiao Tung University, Hsinchu 30010, Taiwan (China); Su, Chen-Fung [College of Photonics, National Chiao Tung University, Tainan 71150, Taiwan (China); Chang, Shu-Wei [Research Center for Applied Sciences, Academia Sinica, Taipei 11529, Taiwan (China); Department of Photonics, National Chiao Tung University, Hsinchu 30010, Taiwan (China); Lee, Si-Chen [Institute of Electronics, National Taiwan University, Taipei 10617, Taiwan (China); Lin, Shih-Yen, E-mail: shihyen@gate.sinica.edu.tw [Institute of Electronics, National Taiwan University, Taipei 10617, Taiwan (China); Research Center for Applied Sciences, Academia Sinica, Taipei 11529, Taiwan (China); Department of Photonics, National Chiao Tung University, Hsinchu 30010, Taiwan (China)

    2014-01-13

    We investigate the electronic properties of p-type graphene transistors on silicon dioxide with dual-cut channels that were scraped using atomic force microscope tips. In these devices, the current is forced to squeeze into the path between the two cuts rather than flow directly through the graphene sheet. We observe that the gate voltages with minimum current shift toward zero bias as the sizes of the dual-cut regions increase. These phenomena suggest that the Fermi levels in the dual-cut regions are shifted toward the Dirac points after the mechanical scraping process.

  13. SF Gate Home Today's News

    E-Print Network [OSTI]

    Savrasov, Sergej Y.

    SF Gate Home Today's News Sports Entertainment Technology Live Views Traffic Weather Health Clues to Behavior of Plutonium / Research may help safety of storing ... 9/5/2003file://E:\\Homepages\\SavrasovHome

  14. Air-gap gating of MgZnO/ZnO heterostructures

    SciTech Connect (OSTI)

    Tambo, T.; Falson, J. Kozuka, Y.; Maryenko, D.; Tsukazaki, A.; Kawasaki, M.

    2014-08-28

    The adaptation of “air-gap” dielectric based field-effect transistor technology to controlling the MgZnO/ZnO heterointerface confined two-dimensional electron system (2DES) is reported. We find it possible to tune the charge density of the 2DES via a gate electrode spatially separated from the heterostructure surface by a distance of 5??m. Under static gating, the observation of the quantum Hall effect suggests that the charge carrier density remains homogeneous, with the 2DES in the 3?mm square sample the sole conductor. The availability of this technology enables the exploration of the charge carrier density degree of freedom in the pristine sample limit.

  15. Control of Emergent Properties at a Correlated Oxide Interface with You Zhou,*,

    E-Print Network [OSTI]

    transitions.1-3 Electrolyte gating utilizes the electric- double layer (EDL) that forms at the liquid-solid 02138, United States *S Supporting Information ABSTRACT: Electrolyte gating of complex oxides enables of electrolyte gated VO2 devices can be deterministically controlled by inserting a monolayer of graphene

  16. Gallium nitride junction field-effect transistor

    DOE Patents [OSTI]

    Zolper, J.C.; Shul, R.J.

    1999-02-02

    An ion implanted gallium-nitride (GaN) junction field-effect transistor (JFET) and method of making the same are disclosed. Also disclosed are various ion implants, both n- and p-type, together with or without phosphorus co-implantation, in selected III-V semiconductor materials. 19 figs.

  17. Gallium nitride junction field-effect transistor

    DOE Patents [OSTI]

    Zolper, John C. (Albuquerque, NM); Shul, Randy J. (Albuquerque, NM)

    1999-01-01

    An all-ion implanted gallium-nitride (GaN) junction field-effect transistor (JFET) and method of making the same. Also disclosed are various ion implants, both n- and p-type, together with or without phosphorous co-implantation, in selected III-V semiconductor materials.

  18. Heterostructure unipolar spin transistors M. E. Flatta

    E-Print Network [OSTI]

    Flatte, Michael E.

    of integrating the nonvolatility of metallic magnetoelectronics with the gain properties of semiconductor charge­12 have been proposed, although the desired material properties needed for these devices have yet semiconductor electronics and spin-based unipolar electronics by considering unipolar spin transistors

  19. Structural and electrical characterization of CoTiN metal gates

    SciTech Connect (OSTI)

    Wongpiya, Ranida; Ouyang, Jiaomin; Chung, Chia-Jung; Duong, Duc T.; Clemens, Bruce; Deal, Michael; Nishi, Yoshio

    2015-02-21

    As the gate size continues to decrease in nanoscale transistors, having metal gates with amorphous or near amorphous structures can potentially reduce grain-induced work function variation. Furthermore, amorphous materials are known to have superior diffusion barrier properties, which can help prevent work function change due to the diffusion of metals in contact with the gate. In this work we show that with the addition of cobalt, thin films of polycrystalline TiN become more amorphous with a smaller grain size. Co{sub x}(TiN){sub 1-x} films, where x?=?60–80%, appear to consist of nanocrystals embedded in an amorphous matrix, and are thermally stable with no significant crystallization up to an annealing temperature of at least 600?°C. Reducing the nitrogen gas flow ratio during sputter deposition from 9% to 2.5% further decreases the films' crystallinity, which is apparent by more sparse and even smaller nanocrystals. In addition to being partially amorphous, these CoTiN films also exhibit good thermal stability, low resistivity, low roughness, and have the potential for atomic layer deposition compatibility. Even though these materials are not completely amorphous, their small crystal size and amorphous matrix can potentially reduce work function variation and improve their diffusion barrier property. These properties make CoTiN a good candidate as a gate material for future nanoelectronic devices and technology.

  20. Low Power Band to Band Tunnel Transistors

    E-Print Network [OSTI]

    Bowonder, Anupama

    2010-01-01

    DD Scaling Path for Future Low Power ICs”, VLSI Technology,la-doping on the reliability of low V th high-k/metal gateDD Scaling Path for Future Low Power ICs”, VLSI Technology,

  1. Microscopic origin of low frequency noise in MoS{sub 2} field-effect transistors

    SciTech Connect (OSTI)

    Ghatak, Subhamoy; Jain, Manish; Ghosh, Arindam; Mukherjee, Sumanta; Sarma, D. D.

    2014-09-01

    We report measurement of low frequency 1/f noise in molybdenum di-sulphide (MoS{sub 2}) field-effect transistors in multiple device configurations including MoS{sub 2} on silicon dioxide as well as MoS{sub 2}-hexagonal boron nitride (hBN) heterostructures. All as-fabricated devices show similar magnitude of noise with number fluctuation as the dominant mechanism at high temperatures and density, although the calculated density of traps is two orders of magnitude higher than that at the SiO{sub 2} interface. Measurements on the heterostructure devices with vacuum annealing and dual gated configuration reveals that along with the channel, metal-MoS{sub 2} contacts also play a significant role in determining noise magnitude in these devices.

  2. Examination of hot-carrier stress induced degradation on fin field-effect transistor

    SciTech Connect (OSTI)

    Yang, Yi-Lin Yen, Tzu-Sung; Ku, Chao-Chen; Wu, Tai-Hsuan; Wang, Tzuo-Li; Li, Chien-Yi; Wu, Bing-Tze; Zhang, Wenqi; Hong, Jia-Jian; Wong, Jie-Chen; Yeh, Wen-Kuan; Lin, Shih-Hung

    2014-02-24

    Degradation in fin field-effect transistor devices was investigated in detail under various hot-carrier stress conditions. The threshold voltage (V{sub TH}) shift, substrate current (I{sub B}), and subthreshold swing were extracted to determine the degradation of a device. The power-law time exponent of the V{sub TH} shift was largest at V{sub G}?=?0.3 V{sub D}, indicating that the V{sub TH} shift was dominated by interface state generation. Although the strongest impact ionization occurred at V{sub G}?=?V{sub D}, the V{sub TH} shift was mainly caused by electron trapping resulting from a large gate leakage current.

  3. Manipulation of transport hysteresis on graphene field effect transistors with Ga ion irradiation

    SciTech Connect (OSTI)

    Wang, Quan, E-mail: wangq@mail.ujs.edu.cn [School of Mechanical Engineering, Jiangsu University, Zhenjiang 212013 (China); State Key Laboratory of Transducer Technology, Chinese Academy of Sciences, Shanghai 200050 (China); Liu, Shuai; Ren, Naifei [School of Mechanical Engineering, Jiangsu University, Zhenjiang 212013 (China)

    2014-09-29

    We have studied the effect of Ga ion irradiation on the controllable hysteretic behavior of graphene field effect transistors fabricated on Si/SO{sub 2} substrates. The various densities of defects in graphene were monitored by Raman spectrum. It was found that the Dirac point shifted to the positive gate voltage constantly, while the hysteretic behavior was enhanced first and then weakened, with the dose of ion irradiation increasing. By contrasting the trap charges density induced by dopant and the total density of effective trap charges, it demonstrated that adsorbate doping was not the decisive factor that induced the hysteretic behavior. The tunneling between the defect sites induced by ion irradiation was also an important cause for the hysteresis.

  4. Solution-gated graphene transistors for chemical and biological sensing applications

    E-Print Network [OSTI]

    Mailly, Benjamin

    2013-01-01

    Various fabrication processes were developed in order to make graphene-based chemical and biological sensors on different substrates. Single-layer graphene is grown by chemical vapor deposition and then transferred to ...

  5. Halogen-Based Plasma Etching of Novel Field-Effect Transistor Gate Materials

    E-Print Network [OSTI]

    Kiehlbaugh, Kasi Michelle

    2009-01-01

    access to the pumps inside for maintenance and repair. Afterand easy maintenance. The inlet to each mechanical pump was

  6. Halogen-Based Plasma Etching of Novel Field-Effect Transistor Gate Materials

    E-Print Network [OSTI]

    Kiehlbaugh, Kasi Michelle

    2009-01-01

    for the main etch step: Adding fluorine-bearing species tothe main etch. It was included as an alternative F-bearing

  7. Gate-Dependent Carrier Diffusion Length in Lead Selenide Quantum Dot Field-Effect Transistors

    E-Print Network [OSTI]

    Yu, Dong

    - generation photovoltaic devices and sensitive photodetec- tors.1-3 The potential for low fabrication cost investigated for their potential use in novel electronic devices. Of particular interest is their use in third using scalable manufacturing processes such as ink jet printing make them attractive candidates for next-generation

  8. Trapped ion scaling with pulsed fast gates

    E-Print Network [OSTI]

    C. D. B. Bentley; A. R. R. Carvalho; J. J. Hope

    2015-07-10

    Fast entangling gates for trapped ions offer vastly improved gate operation times relative to implemented gates, as well as approaches to trap scaling. Gates on neighbouring ions only involve local ions when performed sufficiently fast, and we find that even a fast gate between distant ions with few degrees of freedom restores all the motional modes given more stringent gate speed conditions. We compare pulsed fast gate schemes, defined by a timescale faster than the trap period, and find that our proposed scheme has less stringent requirements on laser repetition rate for achieving arbitrary gate time targets and infidelities well below $10^{-4}$. By extending gate schemes to ion crystals, we explore the effect of ion number on gate fidelity for coupling neighbouring pairs of ions in large crystals. Inter-ion distance determines the gate time, and a factor of five increase in repetition rate, or correspondingly the laser power, reduces the infidelity by almost two orders of magnitude. We also apply our fast gate scheme to entangle the first and last ions in a crystal. As the number of ions in the crystal increases, significant increases in the laser power are required to provide the short gate times corresponding to fidelity above 0.99.

  9. Trends and Challenges of SRAM Reliability in the Nano-scale Era

    E-Print Network [OSTI]

    problems [3]. The most critical reliability failure mechanisms for transistors are related to oxide layer (PMOS) transistor negative oxide field produce interface traps at silicon-oxide layers (Si-SiO2) inter across the gate oxide layer degrades the oxide material and results in the formation of conducting path

  10. Rational Design and Preparation of Organic Semiconductors for use in Field Effect Transistors and Photovoltaic Cells

    E-Print Network [OSTI]

    Mauldin, Clayton Edward

    2010-01-01

    Effect Transistors and Photovoltaic Cells By Clayton EdwardEffect Transistors and Photovoltaic Cells By Clayton Edwardin thin film organic photovoltaic cells (OPVs) is presented.

  11. Rational Design and Preparation of Organic Semiconductors for use in Field Effect Transistors and Photovoltaic Cells

    E-Print Network [OSTI]

    Mauldin, Clayton Edward

    2010-01-01

    in thin film organic photovoltaic cells (OPVs) is presented.Effect Transistors and Photovoltaic Cells By Clayton EdwardEffect Transistors and Photovoltaic Cells By Clayton Edward

  12. Doping suppression and mobility enhancement of graphene transistors fabricated using an adhesion promoting dry transfer process

    SciTech Connect (OSTI)

    Cheol Shin, Woo; Hun Mun, Jeong; Yong Kim, Taek; Choi, Sung-Yool; Jin Cho, Byung, E-mail: bjcho@kaist.edu, E-mail: tskim1@kaist.ac.kr [Department of Electrical Engineering, Graphene Research Center, KAIST, 373-1 Guseong-dong, Yuseong-gu, Daejeon 305-701 (Korea, Republic of); Yoon, Taeshik; Kim, Taek-Soo, E-mail: bjcho@kaist.edu, E-mail: tskim1@kaist.ac.kr [Department of Mechanical Engineering, Graphene Research Center, KAIST, 373-1 Guseong-dong, Yuseong-gu, Daejeon 305-701 (Korea, Republic of)] [Department of Mechanical Engineering, Graphene Research Center, KAIST, 373-1 Guseong-dong, Yuseong-gu, Daejeon 305-701 (Korea, Republic of)

    2013-12-09

    We present the facile dry transfer of graphene synthesized via chemical vapor deposition on copper film to a functional device substrate. High quality uniform dry transfer of graphene to oxidized silicon substrate was achieved by exploiting the beneficial features of a poly(4-vinylphenol) adhesive layer involving a strong adhesion energy to graphene and negligible influence on the electronic and structural properties of graphene. The graphene field effect transistors (FETs) fabricated using the dry transfer process exhibit excellent electrical performance in terms of high FET mobility and low intrinsic doping level, which proves the feasibility of our approach in graphene-based nanoelectronics.

  13. Planning a cost-effective gate rehab

    SciTech Connect (OSTI)

    Rudolph, R.M.; Gundry, J.A. [American Society of Civil Engineers, Nashville, TN (United States)

    1996-04-01

    Hydropower project owners are devoting increasing attention to the condition and safety of spillway gates and related equipment. With careful inspection and planning, owners can develop a rehabilitation program that improves gate performance and minimizes cost. The July 1995 failure of a spillway gate at Folsom Dam has spurred increased attention on inspection and rehabilitation of gates. This article explains an approach taken by Northern States Power Company in rehabilitating aged gates at its Wisota Dam project. An update on measures being taken in response to the Folsom Dam incident is also included.

  14. Tunnel Field-Effect Transistors in 2D Transition Metal Dichalcogenide Materials

    E-Print Network [OSTI]

    Ilatikhameneh, Hesameddin; Novakovic, Bozidar; Klimeck, Gerhard; Rahman, Rajib; Appenzeller, Joerg

    2015-01-01

    In this work, the performance of Tunnel Field-Effect Transistors (TFETs) based on two-dimensional Transition Metal Dichalcogenide (TMD) materials is investigated by atomistic quantum transport simulations. One of the major challenges of TFETs is their low ON-currents. 2D material based TFETs can have tight gate control and high electric fields at the tunnel junction, and can in principle generate high ON-currents along with a sub-threshold swing smaller than 60 mV/dec. Our simulations reveal that high performance TMD TFETs, not only require good gate control, but also rely on the choice of the right channel material with optimum band gap, effective mass and source/drain doping level. Unlike previous works, a full band atomistic tight binding method is used self-consistently with 3D Poisson equation to simulate ballistic quantum transport in these devices. The effect of the choice of TMD material on the performance of the device and its transfer characteristics are discussed. Moreover, the criteria for high ON...

  15. Can p-channel tunnel field-effect transistors perform as good as n-channel?

    SciTech Connect (OSTI)

    Verhulst, A. S. Pourghaderi, M. A.; Collaert, N.; Thean, A. V.-Y.; Verreck, D.; Van de Put, M.; Groeseneken, G.; Sorée, B.

    2014-07-28

    We show that bulk semiconductor materials do not allow perfectly complementary p- and n-channel tunnel field-effect transistors (TFETs), due to the presence of a heavy-hole band. When tunneling in p-TFETs is oriented towards the gate-dielectric, field-induced quantum confinement results in a highest-energy subband which is heavy-hole like. In direct-bandgap IIIV materials, the most promising TFET materials, phonon-assisted tunneling to this subband degrades the subthreshold swing and leads to at least 10× smaller on-current than the desired ballistic on-current. This is demonstrated with quantum-mechanical predictions for p-TFETs with tunneling orthogonal to the gate, made out of InP, In{sub 0.53}Ga{sub 0.47}As, InAs, and a modified version of In{sub 0.53}Ga{sub 0.47}As with an artificially increased conduction-band density-of-states. We further show that even if the phonon-assisted current would be negligible, the build-up of a heavy-hole-based inversion layer prevents efficient ballistic tunneling, especially at low supply voltages. For p-TFET, a strongly confined n-i-p or n-p-i-p configuration is therefore recommended, as well as a tensily strained line-tunneling configuration.

  16. Enhanced Biosensing Resolution with Foundry Fabricated Individually Addressable Dual-Gated ISFETs

    E-Print Network [OSTI]

    Bashir, Rashid

    small signals and increase the sensor accuracy when monitoring small pH dynamics in biological reactions reactions into electrical signals.1,2 In an ISFET, the gate region is exposed to an electrolyte, making,8,9 and ISFETs made with metal oxides and polymers are used to monitor biological activity.10

  17. Luminescent spin-valve transistor Ian Appelbaum,a)

    E-Print Network [OSTI]

    Russell, Kasey

    , the spin- valve transistor SVT , modulates a hot-electron current passing perpendicularly throughLuminescent spin-valve transistor Ian Appelbaum,a) K. J. Russell, D. J. Monsma, V. Narayanamurti Received 29 July 2003; accepted 7 October 2003 A magneto-optical sensor, the luminescent spin-valve

  18. Radio frequency analog electronics based on carbon nanotube transistors

    E-Print Network [OSTI]

    Rogers, John A.

    Radio frequency analog electronics based on carbon nanotube transistors Coskun Kocabas*, Hoon properties of individ- ual tubes. We have implemented solutions to some of these challenges to yield radio band with power gains as high as 14 dB. As a demon- stration, we fabricated nanotube transistor radios

  19. Vertical scaling in heterojunction bipolar transistors with nonequilibrium base transport

    E-Print Network [OSTI]

    Levi, Anthony F. J.

    a departure from conventional scaling of current gain B with base thickness xs in abrupt junction n-p of fi on base thickness xs in abrupt junction n-p-n heterojunction bipolar transistors (HBTs electron transport. In a classical n-p-n homojunction (and graded-juno tion) bipolar transistor, electrons

  20. Graphene and Nanowire Transistors for Cellular Interfaces and Electrical Recording

    E-Print Network [OSTI]

    Xie, Xiaoliang Sunney

    Graphene and Nanowire Transistors for Cellular Interfaces and Electrical Recording Tzahi Cohen interfaces with cell membranes. Graphene has also been shown to be an attractive building block for nanoscale the first studies of graphene field effect transistors (Gra-FETs) as well as combined Gra- and NW

  1. Realising high-current gain p-n-p transistors using a novel surface accumulation layer transistor

    E-Print Network [OSTI]

    Kumar, M. Jagadesh

    of minority carrier transit time caused by the presence of the high-low junction[7]. While high gain lateral p-n-pRealising high-current gain p-n-p transistors using a novel surface accumulation layer transistor (SALTran) concept M. Jagadesh Kumar and V. Parihar Abstract: The authors report a new p-n-p surface

  2. Probing Organic Transistors with Infrared Beams

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    AFDC Printable Version Share this resource Send a link to EERE: Alternative Fuels Data Center Home Page to someone by E-mail Share EERE: Alternative Fuels Data Center Home Page on Facebook Tweet about EERE: Alternative Fuels Data Center Home Page on Twitter Bookmark EERE: Alternative Fuels Data Center Homesum_a_epg0_fpd_mmcf_m.xls" ,"Available from WebQuantityBonneville Power Administration wouldMass mapSpeedingProgramExemptions | National NuclearProbing Organic Transistors with

  3. Probing Organic Transistors with Infrared Beams

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    AFDC Printable Version Share this resource Send a link to EERE: Alternative Fuels Data Center Home Page to someone by E-mail Share EERE: Alternative Fuels Data Center Home Page on Facebook Tweet about EERE: Alternative Fuels Data Center Home Page on Twitter Bookmark EERE: Alternative Fuels Data Center Homesum_a_epg0_fpd_mmcf_m.xls" ,"Available from WebQuantityBonneville Power Administration wouldMass mapSpeedingProgramExemptions | National NuclearProbing Organic Transistors withProbing

  4. Probing Organic Transistors with Infrared Beams

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    AFDC Printable Version Share this resource Send a link to EERE: Alternative Fuels Data Center Home Page to someone by E-mail Share EERE: Alternative Fuels Data Center Home Page on Facebook Tweet about EERE: Alternative Fuels Data Center Home Page on Twitter Bookmark EERE: Alternative Fuels Data Center Homesum_a_epg0_fpd_mmcf_m.xls" ,"Available from WebQuantityBonneville Power Administration wouldMass mapSpeedingProgramExemptions | National NuclearProbing Organic Transistors

  5. Stage-Gate Innovation Management Guidelines

    Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

    It is critical, therefore, that there is an effective pathway for innovative technology and new technical information to reach the end-user. The Stage-Gate Innovation...

  6. Towards Magneto-Logic Gates in Graphene

    E-Print Network [OSTI]

    Wen, Hua

    2014-01-01

    using graphene based spintronic logic gates. Proc. SPIE,applications using spintronic devices for logic operationa leading candidate for spintronic applications due to its

  7. Technology Review: Angle Speeds Plastic Transistor http://www.technologyreview.com/articles/rnb_041304.asp 1 of 2 4/14/2004 8:24 PM

    E-Print Network [OSTI]

    Rogers, John A.

    Technology Review: Angle Speeds Plastic Transistor http > COMPUTERS AND ELECTRONICS > SEMICONDUCTORS Angle Speeds Plastic Transistor Technology Research News April 13. #12;Technology Review: Angle Speeds Plastic Transistor http

  8. Bielectron vortices in gated graphene

    E-Print Network [OSTI]

    C. A. Downing; M. E. Portnoi

    2015-06-14

    We study the formation of bound two-particle states in gapless monolayer graphene in gated structures. We find that, even in the regime of massless Dirac fermions, coupling can occur at zero-energy for different or same charge quasiparticles. These bipartite states must have a non-zero internal angular momentum, meaning that they only exist as stationary vortices. We propose a new picture of the experimentally seen Fermi velocity renormalization as a manifestation of these pairs, suggest the possibility of a condensate of these novel quasiparticles.

  9. Gate Solar | Open Energy Information

    Open Energy Info (EERE)

    AFDC Printable Version Share this resource Send a link to EERE: Alternative Fuels Data Center Home Page to someone by E-mail Share EERE: Alternative Fuels Data Center Home Page on Facebook Tweet about EERE: Alternative Fuels Data Center Home Page on Twitter Bookmark EERE: Alternative Fuels Data Center Home Page on Google Bookmark EERE: Alternative Fuels Data Center Home Page on QA:QA J-E-1 SECTION J APPENDIX E LIST OFAMERICA'SHeavy ElectricalsFTL SolarGate Solar Jump to: navigation, search Name:

  10. Asynchronous Balanced Gates Tolerant to Interconnect Variability

    E-Print Network [OSTI]

    Karpovsky, Mark

    values and transitions to ensure that it does not produce a data-dependent power signature which can switching at the output of the gate. However, in the existing designs the data-independent power consumption and the unavoidable variation due to manufacture. We present gate designs which have data-independent power

  11. Retaining latch for a water pit gate

    DOE Patents [OSTI]

    Beale, A.R.

    1997-11-18

    A retaining latch is described for use in a hazardous materials storage or handling facility to adjustably retain a water pit gate in a gate frame. A retaining latch is provided comprising a latch plate which is rotatably mounted to each end of the top of the gate and a recessed opening, formed in the gate frame, for engaging an edge of the latch plate. The latch plate is circular in profile with one side cut away or flat, such that the latch plate is D-shaped. The remaining circular edge of the latch plate comprises steps of successively reduced thickness. The stepped edge of the latch plate fits inside a recessed opening formed in the gate frame. As the latch plate is rotated, alternate steps of the latch plate are engaged by the recessed opening. When the latch plate is rotated such that the flat portion of the latch plate faces the recessed opening in the gate frame, there is no connection between the opening and the latch plate and the gate is unlatched from the gate frame. 4 figs.

  12. An efficient atomistic quantum mechanical simulation on InAs band-to-band tunneling field-effect transistors

    SciTech Connect (OSTI)

    Wang, Zhi [State Key Laboratory for Superlattices and Microstructures, Institute of Semiconductors, Chinese Academy of Sciences, P.O. Box 912, Beijing 100083 (China); Jiang, Xiang-Wei; Li, Shu-Shen [State Key Laboratory for Superlattices and Microstructures, Institute of Semiconductors, Chinese Academy of Sciences, P.O. Box 912, Beijing 100083 (China); Synergetic Innovation Center of Quantum Information and Quantum Physics, University of Science and Technology of China, Hefei, Anhui 230026 (China); Wang, Lin-Wang, E-mail: lwwang@lbl.gov [Material Sciences Division, Lawrence Berkeley National Laboratory, Berkeley, California 94720 (United States)

    2014-03-24

    We have presented a fully atomistic quantum mechanical simulation method on band-to-band tunneling (BTBT) field-effect transistors (FETs). Our simulation approach is based on the linear combination of bulk band method with empirical pseudopotentials, which is an atomist method beyond the effective-mass approximation or k.p perturbation method, and can be used to simulate real-size devices (?10{sup 5} atoms) efficiently (?5 h on a few computational cores). Using this approach, we studied the InAs dual-gate BTBT FETs. The I-V characteristics from our approach agree very well with the tight-binding non-equilibrium Green's function results, yet our method costs much less computationally. In addition, we have studied ways to increase the tunneling current and analyzed the effects of different mechanisms for that purpose.

  13. Electron tunneling spectroscopy study of electrically active traps in AlGaN/GaN high electron mobility transistors

    SciTech Connect (OSTI)

    Yang, Jie Cui, Sharon; Ma, T. P.; Hung, Ting-Hsiang; Nath, Digbijoy; Krishnamoorthy, Sriram; Rajan, Siddharth

    2013-11-25

    We investigate the energy levels of electron traps in AlGaN/GaN high electron mobility transistors by the use of electron tunneling spectroscopy. Detailed analysis of a typical spectrum, obtained in a wide gate bias range and with both bias polarities, suggests the existence of electron traps both in the bulk of AlGaN and at the AlGaN/GaN interface. The energy levels of the electron traps have been determined to lie within a 0.5?eV band below the conduction band minimum of AlGaN, and there is strong evidence suggesting that these traps contribute to Frenkel-Poole conduction through the AlGaN barrier.

  14. Unbalanced edge modes and topological phase transition in gated...

    Office of Scientific and Technical Information (OSTI)

    Unbalanced edge modes and topological phase transition in gated trilayer graphene Prev Next Title: Unbalanced edge modes and topological phase transition in gated trilayer...

  15. Vehicle Technologies Office Merit Review 2015: Gate Driver Optimizatio...

    Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

    Gate Driver Optimization for WBG Applications Vehicle Technologies Office Merit Review 2015: Gate Driver Optimization for WBG Applications Presentation given by Oak Ridge National...

  16. PENN STATE DOE GRADUATE AUTOMOTIVE TECHNOLOGY EDUCATION (GATE...

    Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

    PENN STATE DOE GRADUATE AUTOMOTIVE TECHNOLOGY EDUCATION (GATE) PROGRAM FOR PENN STATE DOE GRADUATE AUTOMOTIVE TECHNOLOGY EDUCATION (GATE) PROGRAM FOR 2009 DOE Hydrogen Program and...

  17. University of Illinois at Urbana-Champaign's GATE Center for...

    Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

    Champaign's GATE Center for Advanced Automotive Bio-Fuel Combustion Engines University of Illinois at Urbana-Champaign's GATE Center for Advanced Automotive Bio-Fuel Combustion...

  18. Gate-tunable exchange coupling between cobalt clusters on graphene...

    Office of Scientific and Technical Information (OSTI)

    Accepted Manuscript: Gate-tunable exchange coupling between cobalt clusters on graphene Title: Gate-tunable exchange coupling between cobalt clusters on graphene Authors:...

  19. PIA - Savannah River Nuclear Solution (SRNS) MedGate Occupational...

    Energy Savers [EERE]

    MedGate Occupational Health and Safety Medical System (OHS) (Includes the Drug and Alcohol Testing System (Assistant)) PIA - Savannah River Nuclear Solution (SRNS) MedGate...

  20. Tuning the metal-insulator crossover and magnetism in SrRuO3 by ionic gating

    DOE Public Access Gateway for Energy & Science Beta (PAGES Beta)

    Yi, Hee Taek; Gao, Bin; Xie, Wei; Cheong, Sang -Wook; Podzorov, Vitaly

    2014-10-13

    Reversible control of charge transport and magnetic properties without degradation is a key for device applications of transition metal oxides. Chemical doping during the growth of transition metal oxides can result in large changes in physical properties, but in most of the cases irreversibility is an inevitable constraint. We report a reversible control of charge transport, metal-insulator crossover and magnetism in field-effect devices based on ionically gated archetypal oxide system - SrRuO3. In these thin-film devices, the metal-insulator crossover temperature and the onset of magnetoresistance can be continuously and reversibly tuned in the range 90–250 K and 70–100 K, respectively,more »by application of a small gate voltage. We infer that a reversible diffusion of oxygen ions in the oxide lattice dominates the response of these materials to the gate electric field. These findings provide critical insights into both the understanding of ionically gated oxides and the development of novel applications.« less

  1. Tuning the metal-insulator crossover and magnetism in SrRuO3 by ionic gating

    SciTech Connect (OSTI)

    Yi, Hee Taek; Gao, Bin; Xie, Wei; Cheong, Sang -Wook; Podzorov, Vitaly

    2014-10-13

    Reversible control of charge transport and magnetic properties without degradation is a key for device applications of transition metal oxides. Chemical doping during the growth of transition metal oxides can result in large changes in physical properties, but in most of the cases irreversibility is an inevitable constraint. We report a reversible control of charge transport, metal-insulator crossover and magnetism in field-effect devices based on ionically gated archetypal oxide system - SrRuO3. In these thin-film devices, the metal-insulator crossover temperature and the onset of magnetoresistance can be continuously and reversibly tuned in the range 90–250 K and 70–100 K, respectively, by application of a small gate voltage. We infer that a reversible diffusion of oxygen ions in the oxide lattice dominates the response of these materials to the gate electric field. These findings provide critical insights into both the understanding of ionically gated oxides and the development of novel applications.

  2. Ancilla-Assisted Discrimination of Quantum Gates

    E-Print Network [OSTI]

    Jianxin Chen; Mingsheng Ying

    2008-09-02

    The intrinsic idea of superdense coding is to find as many gates as possible such that they can be perfectly discriminated. In this paper, we consider a new scheme of discrimination of quantum gates, called ancilla-assisted discrimination, in which a set of quantum gates on a $d-$dimensional system are perfectly discriminated with assistance from an $r-$dimensional ancilla system. The main contribution of the present paper is two-fold: (1) The number of quantum gates that can be discriminated in this scheme is evaluated. We prove that any $rd+1$ quantum gates cannot be perfectly discriminated with assistance from the ancilla, and there exist $rd$ quantum gates which can be perfectly discriminated with assistance from the ancilla. (2) The dimensionality of the minimal ancilla system is estimated. We prove that there exists a constant positive number $c$ such that for any $k\\leq cr$ quantum gates, if they are $d$-assisted discriminable, then they are also $r$-assisted discriminable, and there are $c^{\\prime}r\\textrm{}(c^{\\prime}>c)$ different quantum gates which can be discriminated with a $d-$dimensional ancilla, but they cannot be discriminated if the ancilla is reduced to an $r-$dimensional system. Thus, the order $O(r)$ of the number of quantum gates that can be discriminated with assistance from an $r-$dimensional ancilla is optimal. The results reported in this paper represent a preliminary step toward understanding the role ancilla system plays in discrimination of quantum gates as well as the power and limit of superdense coding.

  3. Threshold voltage in pentacene field effect transistors with parylene dielectric

    E-Print Network [OSTI]

    Wang, Annie I. (Annie I-Jen), 1981-

    2004-01-01

    Organic field effect transistors (OFETs) offer a suitable building block for many flexible, large-area applications such as display backplanes, electronic textiles, and robotic skin. Besides the organic semiconductor itself, ...

  4. BN/Graphene/BN Transistors for RF Applications

    E-Print Network [OSTI]

    Taychatanapat, Thiti

    In this letter, we demonstrate the first BN/graphene/BN field-effect transistor for RF applications. This device structure can preserve the high mobility and the high carrier velocity of graphene, even when it is sandwiched ...

  5. An evaluation of indium antimonide quantum well transistor technology

    E-Print Network [OSTI]

    Liu, Jingwei, M. Eng. Massachusetts Institute of Technology

    2006-01-01

    Motivated by the super high electron mobility of Indium Antimonide (InSb), researchers have seen great potential to use this new material in high switching speed and low power transistors. In Dec, 2005, Intel and its ...

  6. Simulation-based design of a strained graphene field effect transistor incorporating the pseudo magnetic field effect

    SciTech Connect (OSTI)

    Souma, Satofumi, E-mail: ssouma@harbor.kobe-u.ac.jp; Ueyama, Masayuki; Ogawa, Matsuto [Department of Electrical and Electronic Engineering, Kobe University, 1-1 Rokkodai, Nada, Kobe 657-8501 (Japan)

    2014-05-26

    We present a numerical study on the performance of strained graphene-based field-effect transistors. A local strain less than 10% is applied over a central channel region of the graphene to induce the shift of the Dirac point in the channel region along the transverse momentum direction. The left and the right unstrained graphene regions are doped to be either n-type or p-type. By using the atomistic tight-binding model and a Green's function method, we predict that the gate voltage applied to the central strained graphene region can switch the drain current on and off with an on/off ratio of more than six orders of magnitude at room temperature. This is in spite of the absence of a bandgap in the strained channel region. Steeper subthreshold slopes below 60?mV/decade are also predicted at room temperature because of a mechanism similar to the band-to-band tunneling field-effect transistors.

  7. Any correspondence concerning this service should be sent to the repository administrator: staff-oatao@inp-toulouse.fr

    E-Print Network [OSTI]

    Mailhes, Corinne

    and near oxide traps in small gate area MOS transistors (gate area ,1 mm2 ) lead to RTS noise which implies in order to maximise the pixel photosensitive area. This leads to an increase of MOS transistor low fre. Thus, this technique leads to a decrease of the image sensor sensitivity. In this Letter, we propose

  8. Substrate dielectric effects on graphene field effect transistors

    SciTech Connect (OSTI)

    Hu, Zhaoying; Prasad Sinha, Dhiraj; Ung Lee, Ji, E-mail: jlee1@albany.edu; Liehr, Michael [College of Nanoscale Science and Engineering, The State University of New York at Albany, Albany, New York 12203 (United States)

    2014-05-21

    Graphene is emerging as a promising material for future electronics and optoelectronics applications due to its unique electronic structure. Understanding the graphene-dielectric interaction is of vital importance for the development of graphene field effect transistors (FETs) and other novel graphene devices. Here, we extend the exploration of substrate dielectrics from conventionally used thermally grown SiO{sub 2} and hexagonal boron nitride films to technologically relevant deposited dielectrics used in semiconductor industry. A systematic analysis of morphology and optical and electrical properties was performed to study the effects of different substrates (SiO{sub 2}, HfO{sub 2}, Al{sub 2}O{sub 3}, tetraethyl orthosilicate (TEOS)-oxide, and Si{sub 3}N{sub 4}) on the carrier transport of chemical vapor deposition-derived graphene FET devices. As baseline, we use graphene FETs fabricated on thermal SiO{sub 2} with a relatively high carrier mobility of 10?000 cm{sup 2}/(V s). Among the deposited dielectrics studied, silicon nitride showed the highest mobility, comparable to the properties of graphene fabricated on thermal SiO{sub 2}. We conclude that this result comes from lower long range scattering and short range scattering rates in the nitride compared those in the other deposited films. The carrier fluctuation caused by substrates, however, seems to be the main contributing factor for mobility degradation, as a universal mobility-disorder density product is observed for all the dielectrics examined. The extrinsic doping trend is further confirmed by Raman spectra. We also provide, for the first time, correlation between the intensity ratio of G peak and 2D peak in the Raman spectra to the carrier mobility of graphene for different substrates.

  9. Large scale electromechanical transistor with application in mass sensing

    SciTech Connect (OSTI)

    Jin, Leisheng; Li, Lijie

    2014-12-07

    Nanomechanical transistor (NMT) has evolved from the single electron transistor, a device that operates by shuttling electrons with a self-excited central conductor. The unfavoured aspects of the NMT are the complexity of the fabrication process and its signal processing unit, which could potentially be overcome by designing much larger devices. This paper reports a new design of large scale electromechanical transistor (LSEMT), still taking advantage of the principle of shuttling electrons. However, because of the large size, nonlinear electrostatic forces induced by the transistor itself are not sufficient to drive the mechanical member into vibration—an external force has to be used. In this paper, a LSEMT device is modelled, and its new application in mass sensing is postulated using two coupled mechanical cantilevers, with one of them being embedded in the transistor. The sensor is capable of detecting added mass using the eigenstate shifts method by reading the change of electrical current from the transistor, which has much higher sensitivity than conventional eigenfrequency shift approach used in classical cantilever based mass sensors. Numerical simulations are conducted to investigate the performance of the mass sensor.

  10. Range gating experiments through a scattering media

    SciTech Connect (OSTI)

    Payton, J.; Cverna, F.; Gallegos, R.; McDonald, T.; Numkena, D.; Obst, A.; Pena-Abeyta, C.; Yates, G.

    1998-12-31

    This paper discusses range-gated imaging experiments performed recently at Redstone Arsenal in Huntsville, Alabama. Range gating is an imaging technique that uses a pulsed laser and gated camera to image objects at specific ranges. The technique can be used for imaging through scattering media such as dense smoke or fog. Range gating uses the fact that light travels at 3 x 10{sup 8} m/s. Knowing the speed of light the authors can calculate the time it will take the laser light to travel a known distance, then gate open a Micro Channel Plate Image Intensifier (MCPII) at the time the reflected light returns from the target. In the Redstone experiment the gate width on the MCPII was set to equal the laser pulse width ({approximately} 8 ns) for the highest signal to noise ratio. The gate allows the light reflected form the target and a small portion of the light reflected from the smoke in the vicinity of the target to be imaged. They obtained good results in light and medium smoke but the laser they were used did not have sufficient intensity to penetrate the thickest smoke. They did not diverge the laser beam to cover the entire target in order to maintain a high flux that would achieve better penetration through the smoke. They were able to image an Armored Personnel Carrier (APC) through light and medium smoke but they were not able to image the APC through heavy smoke. The experiment and results are presented.

  11. Extremely scaled high-k/In?.??Ga?.??As gate stacks with low leakage and low interface trap densities

    SciTech Connect (OSTI)

    Chobpattana, Varistha; Mikheev, Evgeny; Zhang, Jack Y.; Mates, Thomas E.; Stemmer, Susanne

    2014-09-28

    Highly scaled gate dielectric stacks with low leakage and low interface trap densities are required for complementary metal-oxide-semiconductor technology with III-V semiconductor channels. Here, we show that a novel pre-deposition technique, consisting of alternating cycles of nitrogen plasma and tetrakis(dimethylamino)titanium, allows for HfO? and ZrO? gate stacks with extremely high accumulation capacitance densities of more than 5 ?F/cm? at 1 MHz, low leakage current, low frequency dispersion, and low midgap interface trap densities (10¹²cm?²eV?¹range). Using x-ray photoelectron spectroscopy, we show that the interface contains TiO? and small quantities of In?O?, but no detectable Ga- or As-oxides, or As-As bonding. The results allow for insights into the microscopic mechanisms that control leakage and frequency dispersion in high-k/III-V gate stacks.

  12. Prediction of the Thermal Annealing of Thick Oxide Metal-Oxide-Semiconductor Dosimeters Irradiated in a Harsh Radiation Environment

    E-Print Network [OSTI]

    Ravotti, F; Saigné, F; Dusseau, L; Sarrabayrouse, G

    2006-01-01

    Radiation-sensing MOSFET transistors produced by the laboratory LAAS-CNRS were exposed to a harsh hadron field that represents the real radiation environment expected at the CERN Large Hadron Collider Experiments. The long-term stability of the transistor's Ids-Vgs characteristic was investigated using the isochronal annealing technique. In this work, devices exposed to high intensity hadron levels show evidences of displacement damages in the Ids-Vgs annealing behavior. By comparing experimental and simulated results over fourteen months, the isochronal annealing method, originally devoted to oxide trapped charge, is shown to enable prediction of the recovery of silicon bulk defects.

  13. Atomic layer deposited zinc tin oxide channel for amorphous oxide thin film transistors

    E-Print Network [OSTI]

    methods, such as pulsed laser deposition,10 solution deposition,11 inkjet printing12 and combustion13 have

  14. Design and fabrication of InGaN/GaN heterojunction bipolar transistors for microwave power amplifiers

    E-Print Network [OSTI]

    Keogh, David Martin

    2006-01-01

    power, high efficiency microwave amplifiers. ” ProceedingsBipolar Transistors for Microwave Power Amplifiers by DavidBipolar Transistors For Microwave Power Amplifiers A

  15. Efficient Modulation of 1.55 m Radiation with Gated Graphene on a Silicon Micro-ring Resonator

    E-Print Network [OSTI]

    Natelson, Douglas

    with complementary metal-oxide-semiconductor technology. #12;(TOC) Keywords: graphene photonics, NIR modulatorEfficient Modulation of 1.55 µm Radiation with Gated Graphene on a Silicon Micro-ring Resonator-edge onset of interband absorption in graphene can be utilized to modulate near-infrared radiation

  16. Trapping in GaN-based metal-insulator-semiconductor transistors: Role of high drain bias and hot electrons

    SciTech Connect (OSTI)

    Meneghini, M. Bisi, D.; Meneghesso, G.; Zanoni, E.

    2014-04-07

    This paper describes an extensive analysis of the role of off-state and semi-on state bias in inducing the trapping in GaN-based power High Electron Mobility Transistors. The study is based on combined pulsed characterization and on-resistance transient measurements. We demonstrate that—by changing the quiescent bias point from the off-state to the semi-on state—it is possible to separately analyze two relevant trapping mechanisms: (i) the trapping of electrons in the gate-drain access region, activated by the exposure to high drain bias in the off-state; (ii) the trapping of hot-electrons within the AlGaN barrier or the gate insulator, which occurs when the devices are operated in the semi-on state. The dependence of these two mechanisms on the bias conditions and on temperature, and the properties (activation energy and cross section) of the related traps are described in the text.

  17. Analog Noise Reduction in Enzymatic Logic Gates

    E-Print Network [OSTI]

    Dmitriy Melnikov; Guinevere Strack; Marcos Pita; Vladimir Privman; Evgeny Katz

    2009-05-17

    In this work we demonstrate both experimentally and theoretically that the analog noise generation by a single enzymatic logic gate can be dramatically reduced to yield gate operation with virtually no input noise amplification. This is achieved by exploiting the enzyme's specificity when using a co-substrate that has a much lower affinity than the primary substrate. Under these conditions, we obtain a negligible increase in the noise output from the logic gate as compared to the input noise level. Experimental realizations of the AND logic gate with the enzyme horseradish peroxidase using hydrogen peroxide and two different co-substrates, 2,2'-azino-bis(3-ethylbenzthiazoline-6-sulphonic acid) (ABTS) and ferrocyanide, with vastly different rate constants confirmed our general theoretical conclusions.

  18. High level compilation for gate reconfigurable architectures

    E-Print Network [OSTI]

    Babb, Jonathan William

    2001-01-01

    A continuing exponential increase in the number of programmable elements is turning management of gate-reconfigurable architectures as "glue logic" into an intractable problem; it is past time to raise this abstraction ...

  19. Digital gate pulse generator for cycloconverter control

    DOE Patents [OSTI]

    Klein, Frederick F. (Monroeville, PA); Mutone, Gioacchino A. (Pleasant Hills, PA)

    1989-01-01

    The present invention provides a digital gate pulse generator which controls the output of a cycloconverter used for electrical power conversion applications by determining the timing and delivery of the firing pulses to the switching devices in the cycloconverter. Previous gate pulse generators have been built with largely analog or discrete digital circuitry which require many precision components and periodic adjustment. The gate pulse generator of the present invention utilizes digital techniques and a predetermined series of values to develop the necessary timing signals for firing the switching device. Each timing signal is compared with a reference signal to determine the exact firing time. The present invention is significantly more compact than previous gate pulse generators, responds quickly to changes in the output demand and requires only one precision component and no adjustments.

  20. Low temperature atomic layer deposited ZnO photo thin film transistors

    SciTech Connect (OSTI)

    Oruc, Feyza B.; Aygun, Levent E.; Donmez, Inci; Biyikli, Necmi; Okyay, Ali K.; Yu, Hyun Yong

    2015-01-01

    ZnO thin film transistors (TFTs) are fabricated on Si substrates using atomic layer deposition technique. The growth temperature of ZnO channel layers are selected as 80, 100, 120, 130, and 250?°C. Material characteristics of ZnO films are examined using x-ray photoelectron spectroscopy and x-ray diffraction methods. Stoichiometry analyses showed that the amount of both oxygen vacancies and interstitial zinc decrease with decreasing growth temperature. Electrical characteristics improve with decreasing growth temperature. Best results are obtained with ZnO channels deposited at 80?°C; I{sub on}/I{sub off} ratio is extracted as 7.8 × 10{sup 9} and subthreshold slope is extracted as 0.116 V/dec. Flexible ZnO TFT devices are also fabricated using films grown at 80?°C. I{sub D}–V{sub GS} characterization results showed that devices fabricated on different substrates (Si and polyethylene terephthalate) show similar electrical characteristics. Sub-bandgap photo sensing properties of ZnO based TFTs are investigated; it is shown that visible light absorption of ZnO based TFTs can be actively controlled by external gate bias.

  1. Graphene-Base Hot-Electron Transistor

    E-Print Network [OSTI]

    Zeng, Caifu

    2014-01-01

    B. H. ; Wang, K. L. "Vertical Graphene-Base Hot-Electronoperation in single-layer graphene ferroelectric memory",of Dirac Point Energy at the Graphene/Oxide Interface", Nano

  2. Gate fidelity fluctuations and quantum process invariants

    SciTech Connect (OSTI)

    Magesan, Easwar; Emerson, Joseph [Institute for Quantum Computing and Department of Applied Mathematics, University of Waterloo, Waterloo, Ontario N2L 3G1 (Canada); Blume-Kohout, Robin [Theoretical Division, Los Alamos National Laboratory, Los Alamos, New Mexico 87545 (United States)

    2011-07-15

    We characterize the quantum gate fidelity in a state-independent manner by giving an explicit expression for its variance. The method we provide can be extended to calculate all higher order moments of the gate fidelity. Using these results, we obtain a simple expression for the variance of a single-qubit system and deduce the asymptotic behavior for large-dimensional quantum systems. Applications of these results to quantum chaos and randomized benchmarking are discussed.

  3. GaTe semiconductor for radiation detection

    DOE Patents [OSTI]

    Payne, Stephen A. (Castro Valley, CA); Burger, Arnold (Nashville, TN); Mandal, Krishna C. (Ashland, MA)

    2009-06-23

    GaTe semiconductor is used as a room-temperature radiation detector. GaTe has useful properties for radiation detectors: ideal bandgap, favorable mobilities, low melting point (no evaporation), non-hygroscopic nature, and availability of high-purity starting materials. The detector can be used, e.g., for detection of illicit nuclear weapons and radiological dispersed devices at ports of entry, in cities, and off shore and for determination of medical isotopes present in a patient.

  4. Investigation of the tunneling emitter bipolar transistor as spin-injector into silicon

    E-Print Network [OSTI]

    Van Veenhuizen, Marc Julien

    2010-01-01

    In this thesis is discussed the tunneling emitter bipolar transistor as a possible spin-injector into silicon. The transistor has a metallic emitter which as a spin-injector will be a ferromagnet. Spin-polarized electrons ...

  5. Graphene-on-Insulator Transistors Made Using C on Ni Chemical-Vapor Deposition

    E-Print Network [OSTI]

    Keast, Craig L.

    Graphene transistors are made by transferring a thin graphene film grown on Ni onto an insulating SiO[subscript 2] substrate. The properties and integration of these graphene-on-insulator transistors are presented and ...

  6. Hydrogen passivation of electron trap in amorphous In-Ga-Zn-O thin-film transistors

    SciTech Connect (OSTI)

    Hanyu, Yuichiro, E-mail: y-hanyu@lucid.msl.titech.ac.jp; Domen, Kay [Materials and Structures Laboratory, Tokyo Institute of Technology, Yokohama (Japan)] [Materials and Structures Laboratory, Tokyo Institute of Technology, Yokohama (Japan); Nomura, Kenji [Frontier Research Center, Tokyo Institute of Technology, Yokohama (Japan)] [Frontier Research Center, Tokyo Institute of Technology, Yokohama (Japan); Hiramatsu, Hidenori; Kamiya, Toshio [Materials and Structures Laboratory, Tokyo Institute of Technology, Yokohama (Japan) [Materials and Structures Laboratory, Tokyo Institute of Technology, Yokohama (Japan); Materials Research Center for Element Strategy, Tokyo Institute of Technology, Yokohama (Japan); Kumomi, Hideya [Materials Research Center for Element Strategy, Tokyo Institute of Technology, Yokohama (Japan)] [Materials Research Center for Element Strategy, Tokyo Institute of Technology, Yokohama (Japan); Hosono, Hideo [Materials and Structures Laboratory, Tokyo Institute of Technology, Yokohama (Japan) [Materials and Structures Laboratory, Tokyo Institute of Technology, Yokohama (Japan); Frontier Research Center, Tokyo Institute of Technology, Yokohama (Japan); Materials Research Center for Element Strategy, Tokyo Institute of Technology, Yokohama (Japan)

    2013-11-11

    We report an experimental evidence that some hydrogens passivate electron traps in an amorphous oxide semiconductor, a-In-Ga-Zn-O (a-IGZO). The a-IGZO thin-film transistors (TFTs) annealed at 300?°C exhibit good operation characteristics; while those annealed at ?400?°C show deteriorated ones. Thermal desorption spectra (TDS) of H{sub 2}O indicate that this threshold annealing temperature corresponds to depletion of H{sub 2}O desorption from the a-IGZO layer. Hydrogen re-doping by wet oxygen annealing recovers the good TFT characteristic. The hydrogens responsible for this passivation have specific binding energies corresponding to the desorption temperatures of 300–430?°C. A plausible structural model is suggested.

  7. Reduction of leakage current in In{sub 0.53}Ga{sub 0.47}As channel metal-oxide-semiconductor field-effect-transistors using AlAs{sub 0.56}Sb{sub 0.44} confinement layers

    SciTech Connect (OSTI)

    Huang, Cheng-Ying Lee, Sanghoon; Cohen-Elias, Doron; Law, Jeremy J. M.; Carter, Andrew D.; Rodwell, Mark J. W.; Chobpattana, Varistha; Stemmer, Susanne; Gossard, Arthur C.; Materials Department, University of California, Santa Barbara, California 93106

    2013-11-11

    We compare the DC characteristics of planar In{sub 0.53}Ga{sub 0.47}As channel MOSFETs using AlAs{sub 0.56}Sb{sub 0.44} barriers to similar MOSFETs using In{sub 0.52}Al{sub 0.48}As barriers. AlAs{sub 0.56}Sb{sub 0.44}, with ?1.0?eV conduction-band offset to In{sub 0.53}Ga{sub 0.47}As, improves electron confinement within the channel. At gate lengths below 100?nm and V{sub DS}?=?0.5?V, the MOSFETs with AlAs{sub 0.56}Sb{sub 0.44} barriers show steeper subthreshold swing (SS) and reduced drain-source leakage current. We attribute the greater leakage observed with the In{sub 0.52}Al{sub 0.48}As barrier to thermionic emission from the N?+?In{sub 0.53}Ga{sub 0.47}As source over the In{sub 0.53}Ga{sub 0.47}As/In{sub 0.52}Al{sub 0.48}As heterointerface. A 56?nm gate length device with the AlAs{sub 0.56}Sb{sub 0.44} barrier exhibits 1.96 mS/?m peak transconductance and SS?=?134?mV/dec at V{sub DS}?=?0.5?V.

  8. Designing a Micro-Mechanical Transistor

    SciTech Connect (OSTI)

    Mainieri, R.

    1999-06-03

    This is the final report of a three-year, Laboratory-Directed Research and Development (LDRD) project at the Los Alamos National Laboratory (LANL). Micro-mechanical electronic systems are chips with moving parts. They are fabricated with the same techniques that are used to manufacture electronic chips, sharing their low cost. Micro-mechanical chips can also contain electronic components. By combining mechanical parts with electronic parts it becomes possible to process signal mechanically. To achieve designs comparable to those obtained with electronic components it is necessary to have a mechanical device that can change its behavior in response to a small input - a mechanical transistor. The work proposed will develop the design tools for these complex-shaped resonant structures using the geometrical ray technique. To overcome the limitations of geometrical ray chaos, the dynamics of the rays will be studied using the methods developed for the study of nonlinear dynamical systems. T his leads to numerical methods that execute well in parallel computer architectures, using a limited amount of memory and no inter-process communication.

  9. Range gated strip proximity sensor

    DOE Patents [OSTI]

    McEwan, Thomas E. (Livermore, CA)

    1996-01-01

    A range gated strip proximity sensor uses one set of sensor electronics and a distributed antenna or strip which extends along the perimeter to be sensed. A micro-power RF transmitter is coupled to the first end of the strip and transmits a sequence of RF pulses on the strip to produce a sensor field along the strip. A receiver is coupled to the second end of the strip, and generates a field reference signal in response to the sequence of pulse on the line combined with received electromagnetic energy from reflections in the field. The sensor signals comprise pulses of radio frequency signals having a duration of less than 10 nanoseconds, and a pulse repetition rate on the order of 1 to 10 MegaHertz or less. The duration of the radio frequency pulses is adjusted to control the range of the sensor. An RF detector feeds a filter capacitor in response to received pulses on the strip line to produce a field reference signal representing the average amplitude of the received pulses. When a received pulse is mixed with a received echo, the mixing causes a fluctuation in the amplitude of the field reference signal, providing a range-limited Doppler type signature of a field disturbance.

  10. Range gated strip proximity sensor

    DOE Patents [OSTI]

    McEwan, T.E.

    1996-12-03

    A range gated strip proximity sensor uses one set of sensor electronics and a distributed antenna or strip which extends along the perimeter to be sensed. A micro-power RF transmitter is coupled to the first end of the strip and transmits a sequence of RF pulses on the strip to produce a sensor field along the strip. A receiver is coupled to the second end of the strip, and generates a field reference signal in response to the sequence of pulse on the line combined with received electromagnetic energy from reflections in the field. The sensor signals comprise pulses of radio frequency signals having a duration of less than 10 nanoseconds, and a pulse repetition rate on the order of 1 to 10 MegaHertz or less. The duration of the radio frequency pulses is adjusted to control the range of the sensor. An RF detector feeds a filter capacitor in response to received pulses on the strip line to produce a field reference signal representing the average amplitude of the received pulses. When a received pulse is mixed with a received echo, the mixing causes a fluctuation in the amplitude of the field reference signal, providing a range-limited Doppler type signature of a field disturbance. 6 figs.

  11. Dual-Threshold Pass-Transistor Logic Design Lara D. Oliver,

    E-Print Network [OSTI]

    Chakrabarty, Krishnendu

    high speed on critical paths and high-threshold-voltage (Vt,H) transistors to manage leakage elsewhere,krish,massoud}@ee.duke.edu ABSTRACT This paper introduces pass-transistor logic design with dual- threshold voltages. A set of single-rail threshold voltages and signal restora- tion transistors with high threshold voltages. Simulation is used

  12. Mechanics of thin-film transistors and solar cells on flexible substrates

    E-Print Network [OSTI]

    Suo, Zhigang

    Mechanics of thin-film transistors and solar cells on flexible substrates Helena Gleskova a,*, I be minimized throughout the fab- rication process. Amorphous silicon thin-film transistors and solar cells rights reserved. Keywords: Amorphous silicon; Thin-film transistor; Solar cell; Flexible electronics 1

  13. Engineer Nanocrystal Floating Gate Memory Scaling

    E-Print Network [OSTI]

    Ren, Jingjian

    2012-01-01

    layer is inserted into the oxide layer as the charge storagefor charge storage. As oxide layer gets thinner with scalingtunnel through the thin oxide layer and get trapped in the

  14. Photo-modulated thin film transistor based on dynamic charge transfer within quantum-dots-InGaZnO interface

    SciTech Connect (OSTI)

    Liu, Xiang; Yang, Xiaoxia; Liu, Mingju; Tao, Zhi; Wei, Lei Li, Chi Zhang, Xiaobing; Wang, Baoping; Dai, Qing; Nathan, Arokia

    2014-03-17

    The temporal development of next-generation photo-induced transistor across semiconductor quantum dots and Zn-related oxide thin film is reported in this paper. Through the dynamic charge transfer in the interface between these two key components, the responsibility of photocurrent can be amplified for scales of times (?10{sup 4}?A/W 450?nm) by the electron injection from excited quantum dots to InGaZnO thin film. And this photo-transistor has a broader waveband (from ultraviolet to visible light) optical sensitivity compared with other Zn-related oxide photoelectric device. Moreover, persistent photoconductivity effect can be diminished in visible waveband which lead to a significant improvement in the device's relaxation time from visible illuminated to dark state due to the ultrafast quenching of quantum dots. With other inherent properties such as integrated circuit compatible, low off-state current and high external quantum efficiency resolution, it has a great potential in the photoelectric device application, such as photodetector, phototransistor, and sensor array.

  15. Investigation of channel width-dependent threshold voltage variation in a-InGaZnO thin-film transistors

    SciTech Connect (OSTI)

    Liu, Kuan-Hsien; Chou, Wu-Ching [Department of Electrophysics, National Chiao Tung University, Hsinchu, Taiwan (China); Chang, Ting-Chang, E-mail: tcchang@mail.phys.nsysu.edu.tw [Department of Physics, National Sun Yat-Sen University, Kaohsiung 804, Taiwan (China); Advanced Optoelectronics Technology Center, National Cheng Kung University, Taiwan (China); Wu, Ming-Siou; Hung, Yi-Syuan; Sze, Simon M. [Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan (China); Hung, Pei-Hua; Chu, Ann-Kuo [Department of Photonics, National Sun Yat-Sen University, Kaohsiung 804, Taiwan (China); Hsieh, Tien-Yu [Department of Physics, National Sun Yat-Sen University, Kaohsiung 804, Taiwan (China); Yeh, Bo-Liang [Advanced Display Technology Research Center, AU Optronics, No. 1, Li-Hsin Rd. 2, Hsinchu Science Park, Hsinchu 30078, Taiwan (China)

    2014-03-31

    This Letter investigates abnormal channel width-dependent threshold voltage variation in amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors. Unlike drain-induced source barrier lowering effect, threshold voltage increases with increasing drain voltage. Furthermore, the wider the channel, the larger the threshold voltage observed. Because of the surrounding oxide and other thermal insulating material and the low thermal conductivity of the IGZO layer, the self-heating effect will be pronounced in wider channel devices and those with a larger operating drain bias. To further clarify the physical mechanism, fast IV measurement is utilized to demonstrate the self-heating induced anomalous channel width-dependent threshold voltage variation.

  16. 1120 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 5, MAY 2006 Theory of Interface-Trap-Induced NBTI Degradation

    E-Print Network [OSTI]

    Alam, Muhammad A.

    mechanisms that generate traps at the Si-channel/gate-oxide interface of MOSFETs during transistor operation. The semiconductor/oxide interface is a rough surface where the highly ordered crystalline channel and the amor lead to poor device performance; therefore, the transistors are annealed in hydrogen ambient during

  17. Amorphous silicon thin film transistor as nonvolatile device. 

    E-Print Network [OSTI]

    Nominanda, Helinda

    2008-10-10

    have been measured. The gamma-ray irradiation damaged bulk films and interfaces and caused the shift of the transfer characteristics to the positive voltage direction. The field effect mobility, on/off current ratio, and interface state density... accumulation layer, and (2) the gate, the gate dielectric, and the channel are viewed as a capacitor,25 i.e., the gate voltage, Vg, controls the mobile charge in the channel. The current observed at the drain, Id, ( ) dtgeffSiNd VVVLWCI x ?= µ (1) where...

  18. Gates, Oregon: Energy Resources | Open Energy Information

    Open Energy Info (EERE)

    AFDC Printable Version Share this resource Send a link to EERE: Alternative Fuels Data Center Home Page to someone by E-mail Share EERE: Alternative Fuels Data Center Home Page on Facebook Tweet about EERE: Alternative Fuels Data Center Home Page on Twitter Bookmark EERE: Alternative Fuels Data Center Home Page on Google Bookmark EERE: Alternative Fuels Data Center Home Page on QA:QAsource History View New PagesSustainable UrbanKentucky: Energy ResourcesMaui Area (DOEMaui AreaGastonGatesGates,

  19. Theory of semiconductor magnetic bipolar transistors M. E. Flattea)

    E-Print Network [OSTI]

    Flatte, Michael E.

    - rating both semiconductors and ferromagnets, such as the spin-valve transistor,12 have demonstrated polarized before passing into the collector. The first is a dramatic spin-filtering effect on carriers passing from the emitter to the p base, the second is spin-selective conduction electron spin flipping

  20. Vibration-Assisted Electron Tunneling in C140 Transistors

    E-Print Network [OSTI]

    McEuen, Paul L.

    Vibration-Assisted Electron Tunneling in C140 Transistors A. N. Pasupathy, J. Park, C. Chang, A. V C140, a molecule with a mass-spring-mass geometry chosen as a model system to study electron-vibration coupling. We observe vibration-assisted tunneling at an energy corresponding to the stretching mode of C140

  1. High Performance Graphene Transistors on Silicon Professor Xu Jianbin

    E-Print Network [OSTI]

    Huang, Jianwei

    High Performance Graphene Transistors on Silicon Professor Xu Jianbin Graphene composed of one nanoelectronics. In particular, the mobility of Graphene, which is a measure of how easily electrons can start for use in post-silicon electronics. However, fabrication of the graphene-based electronic devices

  2. Performance Projections for Ballistic Graphene Nanoribbon Field-Effect Transistors

    E-Print Network [OSTI]

    field-effect- transistors (MOSFETs) in realistic IC applications, however, material properties. Lundstrom Fellow, IEEE This work was supported by the MARCO Focus Center on Materials, Structures, and Devices and the Semiconductor Research Corporation. G. Liang, N. Neophytou, and M. S. Lundstrom

  3. Human dopamine receptor nanovesicles for gate-potential modulators in high-performance field-effect transistor biosensors

    E-Print Network [OSTI]

    Park, Seon Joo

    The development of molecular detection that allows rapid responses with high sensitivity and selectivity remains challenging. Herein, we demonstrate the strategy of novel bio-nanotechnology to successfully fabricate ...

  4. 372 JOURNAL OF DISPLAY TECHNOLOGY, VOL. 2, NO. 4, DECEMBER 2006 A New Gate Induced Barrier Thin-Film Transistor

    E-Print Network [OSTI]

    Kumar, M. Jagadesh

    , Semnan 35195-363, Iran. Digital Object Identifier 10.1109/JDT.2006.884692 channel using excimer laser

  5. Si-CMOS-Like Integration of AlGaN/GaN Dielectric-Gated High-Electron-Mobility Transistors 

    E-Print Network [OSTI]

    Johnson, Derek Wade

    2014-07-31

    production is projected to consume ~100,000 wafers per year by 2015 (Yole Development, “Power GaN – 2012 Edition”), this manufacturing breakthrough represents potential savings of ~$17 million per year....

  6. ADAPTIVE LOG DOMAIN FILTERS USING FLOATING GATE TRANSISTORS Pamela A. Abshire, Eric Liu Wong, Yiming Zhai and Marc H. Cohen

    E-Print Network [OSTI]

    Maryland at College Park, University of

    , Yiming Zhai and Marc H. Cohen Electrical and Computer Engineering / Institute for Systems Research

  7. On the Query Complexity of Perfect Gate Discrimination

    E-Print Network [OSTI]

    D'Ariano, Giacomo Mauro

    On the Query Complexity of Perfect Gate Discrimination Giulio Chiribella1 , Giacomo Mauro D'Ariano2 both deterministic strategies. For unambiguous gate discrimination, where errors are not tolerated that there is no difference between perfect probabilistic and perfect determin- istic gate discrimination. Hence, evaluating

  8. Tamper Resilient Circuits: The Adversary at the Gates Aggelos Kiayias

    E-Print Network [OSTI]

    International Association for Cryptologic Research (IACR)

    Tamper Resilient Circuits: The Adversary at the Gates Aggelos Kiayias Yiannis Tselekounis Abstract We initiate the investigation of gate-tampering attacks against cryptographic circuits. Our model is motivated by the plausibility of tampering directly with circuit gates and by the increasing use of tamper

  9. Facile fabrication of high-performance InGaZnO thin film transistor using hydrogen ion irradiation at room temperature

    SciTech Connect (OSTI)

    Ahn, Byung Du [School of Electrical and Electronic Engineering, 50, Yonsei University, Seoul 120-749 (Korea, Republic of); Park, Jin-Seong [Division of Materials Science and Engineering, Hanyang University, Seoul 133-791 (Korea, Republic of); Chung, K. B., E-mail: kbchung@dongguk.edu [Division of Physics and Semiconductor Science, Dongguk University, Seoul 100-715 (Korea, Republic of)

    2014-10-20

    Device performance of InGaZnO (IGZO) thin film transistors (TFTs) are investigated as a function of hydrogen ion irradiation dose at room temperature. Field effect mobility is enhanced, and subthreshold gate swing is improved with the increase of hydrogen ion irradiation dose, and there is no thermal annealing. The electrical device performance is correlated with the electronic structure of IGZO films, such as chemical bonding states, features of the conduction band, and band edge states below the conduction band. The decrease of oxygen deficient bonding and the changes in electronic structure of the conduction band leads to the improvement of device performance in IGZO TFT with an increase of the hydrogen ion irradiation dose.

  10. 846 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 3, MARCH 2003 Simulation of Oxide Trapping Noise in

    E-Print Network [OSTI]

    Florida, University of

    846 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 3, MARCH 2003 Simulation of Oxide Trapping--Carrier trapping via tunneling into the gate oxide was implemented into a partial differential equation -based are calculated using the carrier tunneling rates between trap centers in the oxide and those at the interface

  11. A Dual Platform for Selective Analyte Enrichment and Ionization in Mass Spectrometry Using Aptamer-Conjugated Graphene Oxide

    E-Print Network [OSTI]

    Tan, Weihong

    -Conjugated Graphene Oxide Basri Gulbakan, Emir Yasun, M. Ibrahim Shukoor, Zhi Zhu, Mingxu You, Xiaohong Tan,, Hernan: This study demonstrates the use of aptamer-conju- gated graphene oxide as an affinity extraction a matrix and with greatly improved signal- to-noise ratios. Aptamer-conjugated graphene oxide has clear

  12. Cavity-QED-based quantum phase gate 

    E-Print Network [OSTI]

    Zubairy, M. Suhail; Kim, M.; Scully, Marlan O.

    2003-01-01

    appropriately detuned from the other mode of the cavit photon each in the two modes and the atom is initially gate in such a system and discuss potential applications DOI: 10.1103/PhysRevA.68.033820 PAC I. INTRODUCTION Quantum computing @1# employs...

  13. Yuanmingyuan East Gate of Peking University

    E-Print Network [OSTI]

    Gu, Jin

    and New Energy Technology 32 Institute of Education Schools & Departments A Foreign Student AffairsRoad) MingdeRoad (XinminRoad) (XuetangRoad) (Zhishan Road) (Tsinghua Road) (XichunRoad) Car Zhaolanyuan Shopping Area West Gate New Qinghuaxuetang #12;

  14. Fabrication and characterization of junctionless carbon nanotube field effect transistor for cholesterol detection

    SciTech Connect (OSTI)

    Barik, Md. Abdul, E-mail: abdulnpl@gmail.com; Dutta, Jiten Ch. [Department of Electronics and Communication Engineering, Tezpur University, Napaam, Tezpur, Assam 784028 (India)

    2014-08-04

    We have reported fabrication and characterization of polyaniline (PANI)/zinc oxide (ZnO) membrane-based junctionless carbon nanotube field effect transistor deposited on indium tin oxide glass plate for the detection of cholesterol (0.5–22.2?mM). Cholesterol oxidase (ChOx) has been immobilized on the PANI/ZnO membrane by physical adsorption technique. Electrical response has been recorded using digital multimeter (Agilent 3458A) in the presence of phosphate buffer saline of 50?mM, pH 7.0, and 0.9% NaCl contained in a glass pot. The results of response studies for cholesterol reveal linearity as 0.5–16.6?mM and improved sensitivity of 60?mV/decade in good agreement with Nernstian limit ?59.2?mV/decade. The life time of this sensor has been found up to 5 months and response time of 1?s. The limit of detection with regression coefficient (r) ? 0.998 and Michaelis-Menten constant (K{sub m}) were found to be ?0.25 and 1.4?mM, respectively, indicating high affinity of ChOx to cholesterol. The results obtained in this work show negligible interference with glucose and urea.

  15. Electron density and currents of AlN/GaN high electron mobility transistors with thin GaN/AlN buffer layer

    SciTech Connect (OSTI)

    Bairamis, A.; Zervos, Ch.; Georgakilas, A.; Adikimenakis, A.; Kostopoulos, A.; Kayambaki, M.; Tsagaraki, K.; Konstantinidis, G.

    2014-09-15

    AlN/GaN high electron mobility transistor (HEMT) structures with thin GaN/AlN buffer layer have been analyzed theoretically and experimentally, and the effects of the AlN barrier and GaN buffer layer thicknesses on two-dimensional electron gas (2DEG) density and transport properties have been evaluated. HEMT structures consisting of [300?nm GaN/ 200?nm AlN] buffer layer on sapphire were grown by plasma-assisted molecular beam epitaxy and exhibited a remarkable agreement with the theoretical calculations, suggesting a negligible influence of the crystalline defects that increase near the heteroepitaxial interface. The 2DEG density varied from 6.8?×?10{sup 12} to 2.1 × 10{sup 13} cm{sup ?2} as the AlN barrier thickness increased from 2.2 to 4.5?nm, while a 4.5?nm AlN barrier would result to 3.1?×?10{sup 13} cm{sup ?2} on a GaN buffer layer. The 3.0?nm AlN barrier structure exhibited the highest 2DEG mobility of 900?cm{sup 2}/Vs for a density of 1.3?×?10{sup 13} cm{sup ?2}. The results were also confirmed by the performance of 1??m gate-length transistors. The scaling of AlN barrier thickness from 1.5?nm to 4.5?nm could modify the drain-source saturation current, for zero gate-source voltage, from zero (normally off condition) to 0.63?A/mm. The maximum drain-source current was 1.1?A/mm for AlN barrier thickness of 3.0?nm and 3.7?nm, and the maximum extrinsic transconductance was 320 mS/mm for 3.0?nm AlN barrier.

  16. A Bio-Polymer Transistor: Electrical Amplification by Microtubules

    E-Print Network [OSTI]

    Avner Priel; Arnolt J. Ramos; Jack A. Tuszynski; Horacio F. Cantiello

    2006-06-09

    Microtubules (MTs) are important cytoskeletal structures, engaged in a number of specific cellular activities, including vesicular traffic, cell cyto-architecture and motility, cell division, and information processing within neuronal processes. MTs have also been implicated in higher neuronal functions, including memory, and the emergence of "consciousness". How MTs handle and process electrical information, however, is heretofore unknown. Here we show new electrodynamic properties of MTs. Isolated, taxol-stabilized microtubules behave as bio-molecular transistors capable of amplifying electrical information. Electrical amplification by MTs can lead to the enhancement of dynamic information, and processivity in neurons can be conceptualized as an "ionic-based" transistor, which may impact among other known functions, neuronal computational capabilities.

  17. Bottom-up graphene nanoribbon field-effect transistors

    SciTech Connect (OSTI)

    Bennett, Patrick B.; Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, California 94720 ; Pedramrazi, Zahra; Madani, Ali; Chen, Yen-Chia; Crommie, Michael F.; Materials Sciences Division, Lawrence Berkeley National Laboratories, Berkeley, California 94720 ; Oteyza, Dimas G. de; Centro de Física de Materiales CSIC Chen, Chen; Fischer, Felix R.; Materials Sciences Division, Lawrence Berkeley National Laboratories, Berkeley, California 94720 ; Bokor, Jeffrey; Materials Sciences Division, Lawrence Berkeley National Laboratories, Berkeley, California 94720

    2013-12-16

    Recently developed processes have enabled bottom-up chemical synthesis of graphene nanoribbons (GNRs) with precise atomic structure. These GNRs are ideal candidates for electronic devices because of their uniformity, extremely narrow width below 1?nm, atomically perfect edge structure, and desirable electronic properties. Here, we demonstrate nano-scale chemically synthesized GNR field-effect transistors, made possible by development of a reliable layer transfer process. We observe strong environmental sensitivity and unique transport behavior characteristic of sub-1?nm width GNRs.

  18. Transistor-based filter for inhibiting load noise from entering a power supply

    DOE Patents [OSTI]

    Taubman, Matthew S

    2013-07-02

    A transistor-based filter for inhibiting load noise from entering a power supply is disclosed. The filter includes a first transistor having an emitter coupled to a power supply, a collector coupled to a load, and a base. The filter also includes a first capacitor coupled between the base of the first transistor and a ground terminal. The filter further includes an impedance coupled between the base and a node between the collector and the load, or a second transistor and second capacitor. The impedance can be a resistor or an inductor.

  19. Method for voltage-gated protein fractionation

    DOE Patents [OSTI]

    Hatch, Anson (Tracy, CA); Singh, Anup K. (Danville, CA)

    2012-04-24

    We report unique findings on the voltage dependence of protein exclusion from the pores of nanoporous polymer exclusion membranes. The pores are small enough that proteins are excluded from passage with low applied electric fields, but increasing the field enables proteins to pass through. The requisite field necessary for a change in exclusion is protein-specific with a correlation to protein size. The field-dependence of exclusion is important to consider for preconcentration applications. The ability to selectively gate proteins at exclusion membranes is also a promising means for manipulating and characterizing proteins. We show that field-gated exclusion can be used to selectively remove proteins from a mixture, or to selectively trap protein at one exclusion membrane in a series.

  20. Cluster computing software for GATE simulations

    SciTech Connect (OSTI)

    Beenhouwer, Jan de; Staelens, Steven; Kruecker, Dirk; Ferrer, Ludovic; D'Asseler, Yves; Lemahieu, Ignace; Rannou, Fernando R.

    2007-06-15

    Geometry and tracking (GEANT4) is a Monte Carlo package designed for high energy physics experiments. It is used as the basis layer for Monte Carlo simulations of nuclear medicine acquisition systems in GEANT4 Application for Tomographic Emission (GATE). GATE allows the user to realistically model experiments using accurate physics models and time synchronization for detector movement through a script language contained in a macro file. The downside of this high accuracy is long computation time. This paper describes a platform independent computing approach for running GATE simulations on a cluster of computers in order to reduce the overall simulation time. Our software automatically creates fully resolved, nonparametrized macros accompanied with an on-the-fly generated cluster specific submit file used to launch the simulations. The scalability of GATE simulations on a cluster is investigated for two imaging modalities, positron emission tomography (PET) and single photon emission computed tomography (SPECT). Due to a higher sensitivity, PET simulations are characterized by relatively high data output rates that create rather large output files. SPECT simulations, on the other hand, have lower data output rates but require a long collimator setup time. Both of these characteristics hamper scalability as a function of the number of CPUs. The scalability of PET simulations is improved here by the development of a fast output merger. The scalability of SPECT simulations is improved by greatly reducing the collimator setup time. Accordingly, these two new developments result in higher scalability for both PET and SPECT simulations and reduce the computation time to more practical values.

  1. Scanning probe microscopy imaging before and after atomic layer oxide deposition on a compound semiconductor surface

    E-Print Network [OSTI]

    Kummel, Andrew C.

    Scanning probe microscopy imaging before and after atomic layer oxide deposition on a compound fabricated using trimethylaluminum (TMA) and water atomic layer deposition (ALD) for the Al2O3 gate oxide level (Fig 2) suggesting that an ordered monolayer layer might be a requirement for unpinning

  2. Transport quantum logic gates for trapped ions

    E-Print Network [OSTI]

    D. Leibfried; E. Knill; C. Ospelkaus; D. J. Wineland

    2007-08-28

    Many efforts are currently underway to build a device capable of large scale quantum information processing (QIP). Whereas QIP has been demonstrated for a few qubits in several systems, many technical difficulties must be overcome in order to construct a large-scale device. In one proposal for large-scale QIP, trapped ions are manipulated by precisely controlled light pulses and moved through and stored in multizone trap arrays. The technical overhead necessary to precisely control both the ion geometrical configurations and the laser interactions is demanding. Here we propose methods that significantly reduce the overhead on laser beam control for performing single and multiple qubit operations on trapped ions. We show how a universal set of operations can be implemented by controlled transport of ions through stationary laser beams. At the same time, each laser beam can be used to perform many operations in parallel, potentially reducing the total laser power necessary to carry out QIP tasks. The overall setup necessary for implementing transport gates is simpler than for gates executed on stationary ions. We also suggest a transport-based two-qubit gate scheme utilizing microfabricated permanent magnets that can be executed without laser light.

  3. Electrical characteristics of multilayer MoS{sub 2} transistors at real operating temperatures with different ambient conditions

    SciTech Connect (OSTI)

    Kwon, Hyuk-Jun; Grigoropoulos, Costas P.; Jang, Jaewon Subramanian, Vivek; Kim, Sunkook

    2014-10-13

    Atomically thin, two-dimensional (2D) materials with bandgaps have attracted increasing research interest due to their promising electronic properties. Here, we investigate carrier transport and the impact of the operating ambient conditions on back-gated multilayer MoS{sub 2} field-effect transistors with a thickness of ?50?nm at their realistic working temperatures and under different ambient conditions (in air and in a vacuum of ?10{sup ?5}?Torr). Increases in temperature cause increases in I{sub min} (likely due to thermionic emission at defects), and result in decreased I{sub on} at high V{sub G} (likely due to increased phonon scattering). Thus, the I{sub on}/I{sub min} ratio decreases as the temperature increases. Moreover, the ambient effects with working temperatures on field effect mobilities were investigated. The adsorbed oxygen and water created more defect sites or impurities in the MoS{sub 2} channel, which can lead another scattering of the carriers. In air, the adsorbed molecules and phonon scattering caused a reduction of the field effect mobility, significantly. These channel mobility drop-off rates in air and in a vacuum reached 0.12?cm{sup 2}/V s K and 0.07?cm{sup 2}/V s K, respectively; the rate of degradation is steeper in air than in a vacuum due to enhanced phonon mode by the adsorbed oxygen and water molecules.

  4. Combustion-process derived comparable performances of Zn-(In:Sn)-O thin-film transistors with a complete miscibility

    SciTech Connect (OSTI)

    Jiang, Qingjun; Lu, Jianguo Cheng, Jipeng; Sun, Rujie; Feng, Lisha; Dai, Wen; Yan, Weichao; Ye, Zhizhen; Li, Xifeng

    2014-09-29

    Amorphous zinc-indium-tin oxide (a-ZITO) thin-film transistors (TFTs) have been prepared using a low-temperature combustion process, with an emphasis on complete miscibility of In and Sn contents. The a-ZITO TFTs were comparatively studied in detail, especially for the working stability. The a-ZITO TFTs all exhibited acceptable and excellent behaviors from Sn-free TFTs to In-free TFTs. The obtained a-ZTO TFTs presented a field-effect mobility of 1.20?cm{sup 2} V{sup ?1} s{sup ?1}, an on/off current ratio of 4.89?×?10{sup 6}, and a long-term stability under positive bias stress, which are comparable with those of the a-ZIO TFTs. The In-free a-ZTO TFTs are very potential for electrical applications with a low cost.

  5. Theoretical analysis of initial adsorption of high-metal oxides on InxGa1-xAs,,0 0 1...-,,42... surfaces

    E-Print Network [OSTI]

    Kummel, Andrew C.

    are molecular beam deposition MBE and atomic layer deposition ALD . The importance of the struc- ture of the first oxide layer has been demonstrated for both MBE and ALD gate oxides deposition. For example, Hale et al. showed that the first layer of Ga2O deposition is critical in unpinning the oxide

  6. PENN STATE DOE GRADUATE AUTOMOTIVE TECHNOLOGY EDUCATION (GATE...

    Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

    of GATE fellows * Partners - none Milestones Goals and Objectives * Provide graduate curriculum focused on high-power in- vehicle energy storage for hybrid electric and fuel cell...

  7. Optical Determination of Gate--Tunable Bandgap in Bilayer Graphene

    E-Print Network [OSTI]

    Zhang, Yuanbo

    2010-01-01

    Tunable Bandgap in Bilayer Graphene Yuanbo Zhang* 1 , Tsung-gate-tunable bandgap in graphene bilayers with magnitude asbands. In two- dimensional graphene bilayers this bandgap

  8. Fast gates for ion traps by splitting laser pulses

    E-Print Network [OSTI]

    C. D. B. Bentley; A. R. R. Carvalho; D. Kielpinski; J. J. Hope

    2013-04-09

    We present a fast phase gate scheme that is experimentally achievable and has an operation time more than two orders of magnitude faster than current experimental schemes for low numbers of pulses. The gate time improves with the number of pulses following an inverse power law. Unlike implemented schemes which excite precise motional sidebands, thus limiting the gate timescale, our scheme excites multiple motional states using discrete ultra-fast pulses. We use beam-splitters to divide pulses into smaller components to overcome limitations due to the finite laser pulse repetition rate. This provides gate times faster than proposed theoretical schemes when we optimise a practical setup.

  9. Gating-by-tilt of mechanosensitive membrane channels

    E-Print Network [OSTI]

    Matthew S. Turner; Pierre Sens

    2003-11-25

    We propose an alternative mechanism for the gating of biological membrane channels in response to membrane tension that involves a change in the slope of the membrane near the channel. Under biological membrane tensions we show that the energy difference between the closed (tilted) and open (untilted) states can far exceed kBT and is comparable to what is available under simple ilational gating. Recent experiments demonstrate that membrane leaflet asymmetries (spontaneous curvature) can strong effect the gating of some channels. Such a phenomenon would be more easy to explain under gating-by-tilt, given its novel intrinsic sensitivity to such asymmetry.

  10. Penn State DOE Graduate Automotive Technology Education (Gate...

    Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

    Penn State DOE Graduate Automotive Technology Education (Gate) Program for In-Vehicle, High-Power Energy Storage Systems Penn State DOE Graduate Automotive Technology Education...

  11. PIA - Savannah River Nuclear Solution (SRNS) MedGate Occupational...

    Energy Savers [EERE]

    PIA - Savannah River Nuclear Solution (SRNS) MedGate Occupational Health and Safety Medical System (OHS) (Includes the Drug and Alcohol Testing System (Assistant)) PIA - Savannah...

  12. Spin on dopants for high-performance single-crystal silicon transistors on flexible plastic substrates

    E-Print Network [OSTI]

    Rogers, John A.

    Spin on dopants for high-performance single-crystal silicon transistors on flexible plastic February 2005; published online 23 March 2005 Free-standing micro/nanoelements of single-crystal silicon-temperature device substrates, such as plastic, for high-performance mechanically flexible thin-film transistors TFTs

  13. Semi-epitaxial magnetic tunnel transistor: Effect of electron energy and temperature

    E-Print Network [OSTI]

    Bayreuther, Günther

    ; published online 6 May 2005 A magnetic tunnel transistor with spin-valve metallic base and epitaxial collector leakage. © 2005 American Institute of Physics. DOI: 10.1063/1.1853892 I. INTRODUCTION The hot-electron spin-valve transistor was introduced by Monsma et al. in 1995.1 Since then, interest in hot

  14. Impact-ionization field-effect-transistor based biosensors for ultra-sensitive detection of biomolecules

    E-Print Network [OSTI]

    Impact-ionization field-effect-transistor based biosensors for ultra-sensitive detection online 21 May 2013) The phenomenon of impact-ionization is proposed to be leveraged for a novel biosensor field-effect-transistor (IFET) based biosensor, it is possible to obtain an increase in sensitivity

  15. Photovoltaic transistors based on a steady-state internal polarization effect in asymmetric semiconductor superlattices

    E-Print Network [OSTI]

    Luryi, Serge

    Photovoltaic transistors based on a steady-state internal polarization effect in asymmetric that a modified structure can generate a steady-state photovoltage. We then propose a new class of photovoltaic novelty is such a photovoltaic transistor (PVT) aspect. Our idea of the PVT arises from the well known

  16. SUB-MM-WAVE TECHNOLOGIES: SYSTEMS, ICS, THZ TRANSISTORS M. J. W. Rodwell

    E-Print Network [OSTI]

    Rodwell, Mark J. W.

    SUB-MM-WAVE TECHNOLOGIES: SYSTEMS, ICS, THZ TRANSISTORS M. J. W. Rodwell Department of Electrical Engineering University of California, Santa Barbara, CA 93105 Abstract mm-wave and sub-mm-wave outdoor, bipolar transistors, mm- waves, sub-mm-waves, THz. I. INTRODUCTION With progressive scaling of junction

  17. Selective Gas Sensing with a Single Pristine Graphene Transistor Sergey Rumyantsev,,

    E-Print Network [OSTI]

    Selective Gas Sensing with a Single Pristine Graphene Transistor Sergey Rumyantsev,, Guanxiong Liu. Petersburg, 194021 Russia § Nano-Device Laboratory, Department of Electrical Engineering, Bourns College allow one to achieve the selective gas sensing with a single pristine graphene transistor. Our method

  18. Effect of energetic electron irradiation on graphene and graphene field-effect transistors

    E-Print Network [OSTI]

    Chen, Yong P.

    in the semiconductor substrate supporting graphene. The electrons travel through the substrate and can reachEffect of energetic electron irradiation on graphene and graphene field-effect transistors Isaac transport properties of graphene and the operation of graphene field-effect transistors (GFET). Exposure

  19. Polymeric semiconductor/graphene hybrid field-effect transistors Jia Huang a,b,

    E-Print Network [OSTI]

    Polymeric semiconductor/graphene hybrid field-effect transistors Jia Huang a,b, , Daniel R. Hines semiconductor Graphene Thin film transistor Hybrid material a b s t r a c t Solution processed organic field semiconductors and graphene. Compared against OFETs with only pure organic semiconductors, our hybrid FETs

  20. Bending tests of carbon nanotube thin-film transistors on flexible Daniel Pham1

    E-Print Network [OSTI]

    Chen, Ray

    Bending tests of carbon nanotube thin-film transistors on flexible substrate Daniel Pham1 , Harish, San Marcos, TX 78666. ABSTRACT Bending tests of carbon nanotube thin-film transistors on flexible substrate have been characterized in this paper. The device channel consisting of dense, aligned, 99% pure

  1. Fractional-Order Signal Processing using a Polymer-Electrolyte Transistor Robert L. Ewing1

    E-Print Network [OSTI]

    Stevens, Ken

    in silicon processing. This paper focuses on examining the fractional dynamic response of the LSL polymer-electrolyteFractional-Order Signal Processing using a Polymer-Electrolyte Transistor Robert L. Ewing1 , Hoda S-order functions. This paper addresses the use of a polymer-electrolyte transistor (PET) for use in implementating

  2. Graphene Transistors Fabricated via Transfer-Printing In Device Active-Areas

    E-Print Network [OSTI]

    Graphene Transistors Fabricated via Transfer-Printing In Device Active-Areas on Large Wafer Xiaogan graphene islands from a graphite and then uses transfer printing to place the islands from the stamp from the printed graphene. The transistors show a hole and electron mobility of 3735 and 795 cm2/V

  3. Speed control system for an access gate

    DOE Patents [OSTI]

    Bzorgi, Fariborz M. (Knoxville, TN)

    2012-03-20

    An access control apparatus for an access gate. The access gate typically has a rotator that is configured to rotate around a rotator axis at a first variable speed in a forward direction. The access control apparatus may include a transmission that typically has an input element that is operatively connected to the rotator. The input element is generally configured to rotate at an input speed that is proportional to the first variable speed. The transmission typically also has an output element that has an output speed that is higher than the input speed. The input element and the output element may rotate around a common transmission axis. A retardation mechanism may be employed. The retardation mechanism is typically configured to rotate around a retardation mechanism axis. Generally the retardation mechanism is operatively connected to the output element of the transmission and is configured to retard motion of the access gate in the forward direction when the first variable speed is above a control-limit speed. In many embodiments the transmission axis and the retardation mechanism axis are substantially co-axial. Some embodiments include a freewheel/catch mechanism that has an input connection that is operatively connected to the rotator. The input connection may be configured to engage an output connection when the rotator is rotated at the first variable speed in a forward direction and configured for substantially unrestricted rotation when the rotator is rotated in a reverse direction opposite the forward direction. The input element of the transmission is typically operatively connected to the output connection of the freewheel/catch mechanism.

  4. Apparatus and method for recharging a string a avalanche transistors within a pulse generator

    DOE Patents [OSTI]

    Fulkerson, E. Stephen (Livermore, CA)

    2000-01-01

    An apparatus and method for recharging a string of avalanche transistors within a pulse generator is disclosed. A plurality of amplification stages are connected in series. Each stage includes an avalanche transistor and a capacitor. A trigger signal, causes the apparatus to generate a very high voltage pulse of a very brief duration which discharges the capacitors. Charge resistors inject current into the string of avalanche transistors at various points, recharging the capacitors. The method of the present invention includes the steps of supplying current to charge resistors from a power supply; using the charge resistors to charge capacitors connected to a set of serially connected avalanche transistors; triggering the avalanche transistors; generating a high-voltage pulse from the charge stored in the capacitors; and recharging the capacitors through the charge resistors.

  5. Optimizing local protocols implementing nonlocal quantum gates

    E-Print Network [OSTI]

    Scott M. Cohen

    2010-02-02

    We present a method of optimizing recently designed protocols for implementing an arbitrary nonlocal unitary gate acting on a bipartite system. These protocols use only local operations and classical communication with the assistance of entanglement, and are deterministic while also being "one-shot", in that they use only one copy of an entangled resource state. The optimization is in the sense of minimizing the amount of entanglement used, and it is often the case that less entanglement is needed than with an alternative protocol using two-way teleportation.

  6. Poly-Si?â??xGex Film Growth for Ni Germanosilicided Metal Gate

    E-Print Network [OSTI]

    Yu, Hongpeng

    Scaling down of the CMOS technology requires thinner gate dielectric to maintain high performance. However, due to the depletion of poly-Si gate, it is difficult to reduce the gate thickness further especially for sub-65 ...

  7. Enhanced shot noise in carbon nanotube field-effect transistors

    SciTech Connect (OSTI)

    Betti, A.; Fiori, G.; Iannaccone, G.

    2009-12-21

    We predict shot noise enhancement in defect-free carbon nanotube field-effect transistors through a numerical investigation based on the self-consistent solution of the Poisson and Schroedinger equations within the nonequilibrium Green's functions formalism, and on a Monte Carlo approach to reproduce injection statistics. Noise enhancement is due to the correlation between trapping of holes from the drain into quasibound states in the channel and thermionic injection of electrons from the source, and can lead to an appreciable Fano factor of 1.22 at room temperature.

  8. Modeling gated neutron images of THD capsules

    SciTech Connect (OSTI)

    Wilson, Douglas Carl; Grim, Gary P; Tregillis, Ian L; Wilke, Mark D; Morgan, George L; Loomis, Eric N; Wilde, Carl H; Oertel, John A; Fatherley, Valerie E; Clark, David D; Schmitt, Mark J; Merrill, Frank E; Wang, Tai - Sen F; Danly, Christopher R; Batha, Steven H; Patel, M; Sepke, S; Hatarik, R; Fittinghoff, D; Bower, D; Marinak, M; Munro, D; Moran, M; Hilko, R; Frank, M; Buckles, R

    2010-01-01

    Time gating a neutron detector 28m from a NIF implosion can produce images at different energies. The brighter image near 14 MeV reflects the size and symmetry of the capsule 'hot spot'. Scattered neutrons, {approx}9.5-13 MeV, reflect the size and symmetry of colder, denser fuel, but with only {approx}1-7% of the neutrons. The gated detector records both the scattered neutron image, and, to a good approximation, an attenuated copy of the primary image left by scintillator decay. By modeling the imaging system the energy band for the scattered neutron image (10-12 MeV) can be chosen, trading off the decayed primary image and the decrease of scattered image brightness with energy. Modeling light decay from EJ399, BC422, BCF99-55, Xylene, DPAC-30, and Liquid A leads to a preference from BCF99-55 for the first NIF detector, but DPAC 30 and Liquid A would be preferred if incorporated into a system. Measurement of the delayed light from the NIF scintillator using implosions at the Omega laser shows BCF99-55 to be a good choice for down-scattered imaging at 28m.

  9. University of Illinois at Urbana-Champaigns GATE Center for...

    Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

    Champaigns GATE Center for Advanced Automotive Bio-Fuel Combustion Engines University of Illinois at Urbana-Champaigns GATE Center for Advanced Automotive Bio-Fuel Combustion...

  10. US DOE Sponsored Graduate Automotive Technology Education (GATE) Program at Penn State Emphasizing

    E-Print Network [OSTI]

    Lee, Dongwon

    US DOE Sponsored Graduate Automotive Technology Education (GATE) Program at Penn State Emphasizing in the automotive industry and academia. Develop relationships between GATE students, faculty, employers

  11. Demonstration of Robust Quantum Gate Tomography via Randomized Benchmarking

    E-Print Network [OSTI]

    Blake R. Johnson; Marcus P. da Silva; Colm A. Ryan; Shelby Kimmel; Jerry M. Chow; Thomas A. Ohki

    2015-05-25

    Typical quantum gate tomography protocols struggle with a self-consistency problem: the gate operation cannot be reconstructed without knowledge of the initial state and final measurement, but such knowledge cannot be obtained without well-characterized gates. A recently proposed technique, known as randomized benchmarking tomography (RBT), sidesteps this self-consistency problem by designing experiments to be insensitive to preparation and measurement imperfections. We implement this proposal in a superconducting qubit system, using a number of experimental improvements including implementing each of the elements of the Clifford group in single `atomic' pulses and custom control hardware to enable large overhead protocols. We show a robust reconstruction of several single-qubit quantum gates, including a unitary outside the Clifford group. We demonstrate that RBT yields physical gate reconstructions that are consistent with fidelities obtained by randomized benchmarking.

  12. Parallel transport quantum logic gates with trapped ions

    E-Print Network [OSTI]

    de Clercq, Ludwig; Marinelli, Matteo; Nadlinger, David; Oswald, Robin; Negnevitsky, Vlad; Kienzler, Daniel; Keitch, Ben; Home, Jonathan P

    2015-01-01

    Quantum information processing will require combinations of gate operations and communication, with each applied in parallel to large numbers of quantum systems. These tasks are often performed sequentially, with gates implemented by pulsed fields and information transported either by moving the physical qubits or using photonic links. For trapped ions, an alternative approach is to implement quantum logic gates by transporting the ions through static laser beams, combining qubit operations with transport. This has significant advantages for scalability since the voltage waveforms required for transport can potentially be generated using micro-electronics integrated into the trap structure itself, while both optical and microwave control elements are significantly more bulky. Using a multi-zone ion trap, we demonstrate transport gates on a qubit encoded in the hyperfine structure of a beryllium ion. We show the ability to perform sequences of operations, and to perform parallel gates on two ions transported t...

  13. Graphene terahertz modulators by ionic liquid gating

    E-Print Network [OSTI]

    Wu, Yang; Qiu, Xuepeng; Liu, Jingbo; Deorani, Praveen; Banerjee, Karan; Son, Jaesung; Chen, Yuanfu; Chia, Elbert E M; Yang, Hyunsoo

    2015-01-01

    Graphene based THz modulators are promising due to the conical band structure and high carrier mobility of graphene. Here, we tune the Fermi level of graphene via electrical gating with the help of ionic liquid to control the THz transmittance. It is found that, in the THz range, both the absorbance and reflectance of the device increase proportionately to the available density of states due to intraband transitions. Compact, stable, and repeatable THz transmittance modulation up to 93% (or 99%) for a single (or stacked) device has been demonstrated in a broad frequency range from 0.1 to 2.5 THz, with an applied voltage of only 3 V at room temperature.

  14. Quantum-correlated photon pairs generated in a commercial 45nm complementary metal-oxide semiconductor microelectronics chip

    E-Print Network [OSTI]

    Gentry, Cale M; Wade, Mark W; Stevens, Martin J; Dyer, Shellee D; Zeng, Xiaoge; Pavanello, Fabio; Gerrits, Thomas; Nam, Sae Woo; Mirin, Richard P; Popovi?, Miloš A

    2015-01-01

    Correlated photon pairs are a fundamental building block of quantum photonic systems. While pair sources have previously been integrated on silicon chips built using customized photonics manufacturing processes, these often take advantage of only a small fraction of the established techniques for microelectronics fabrication and have yet to be integrated in a process which also supports electronics. Here we report the first demonstration of quantum-correlated photon pair generation in a device fabricated in an unmodified advanced (sub-100nm) complementary metal-oxide-semiconductor (CMOS) process, alongside millions of working transistors. The microring resonator photon pair source is formed in the transistor layer structure, with the resonator core formed by the silicon layer typically used for the transistor body. With ultra-low continuous-wave on-chip pump powers ranging from 5 $\\mu$W to 400 $\\mu$W, we demonstrate pair generation rates between 165 Hz and 332 kHz using >80% efficient WSi superconducting nano...

  15. Polarization of Bi{sub 2}Te{sub 3} thin film in a floating-gate capacitor structure

    SciTech Connect (OSTI)

    Yuan, Hui E-mail: qli6@gmu.edu; Li, Haitao; Zhu, Hao; Zhang, Kai; Baumgart, Helmut; Bonevich, John E.; Richter, Curt A.; Li, Qiliang E-mail: qli6@gmu.edu

    2014-12-08

    Metal-Oxide-Semiconductor (MOS) capacitors with Bi{sub 2}Te{sub 3} thin film sandwiched and embedded inside the oxide layer have been fabricated and studied. The capacitors exhibit ferroelectric-like hysteresis which is a result of the robust, reversible polarization of the Bi{sub 2}Te{sub 3} thin film while the gate voltage sweeps. The temperature-dependent capacitance measurement indicates that the activation energy is about 0.33?eV for separating the electron and hole pairs in the bulk of Bi{sub 2}Te{sub 3}, and driving them to either the top or bottom surface of the thin film. Because of the fast polarization speed, potentially excellent endurance, and the complementary metal–oxide–semiconductor compatibility, the Bi{sub 2}Te{sub 3} embedded MOS structures are very interesting for memory application.

  16. Gated Si nanowires for large thermoelectric power factors

    SciTech Connect (OSTI)

    Neophytou, Neophytos, E-mail: N.Neophytou@warwick.ac.uk [School of Engineering, University of Warwick, Coventry CV4 7AL (United Kingdom); Kosina, Hans [Institute for Microelectronics, Vienna University of Technology, Gusshausstrasse 27-29/E360, Vienna A-1040 (Austria)

    2014-08-18

    We investigate the effect of electrostatic gating on the thermoelectric power factor of p-type Si nanowires (NWs) of up to 20?nm in diameter in the [100], [110], and [111] crystallographic transport orientations. We use atomistic tight-binding simulations for the calculation of the NW electronic structure, coupled to linearized Boltzmann transport equation for the calculation of the thermoelectric coefficients. We show that gated NW structures can provide ?5× larger thermoelectric power factor compared to doped channels, attributed to their high hole phonon-limited mobility, as well as gating induced bandstructure modifications which further improve mobility. Despite the fact that gating shifts the charge carriers near the NW surface, surface roughness scattering is not strong enough to degrade the transport properties of the accumulated hole layer. The highest power factor is achieved for the [111] NW, followed by the [110], and finally by the [100] NW. As the NW diameter increases, the advantage of the gated channel is reduced. We show, however, that even at 20?nm diameters (the largest ones that we were able to simulate), a ?3× higher power factor for gated channels is observed. Our simulations suggest that the advantage of gating could still be present in NWs with diameters of up to ?40?nm.

  17. SiGe optoelectronic metal-oxide semiconductor field-effect transistor

    E-Print Network [OSTI]

    Miller, David A. B.

    - munication rockets up. Although still efficient at short distances, copper wires suffer excessive power dissipation and delay in global lines and cannot cope with the growing bandwidth demand [1]. As the chip problems faced by copper wires [3]. Compound semi- conductors have been the forerunner in optoelec- tronic

  18. Influence of an anomalous dimension effect on thermal instability in amorphous-InGaZnO thin-film transistors

    SciTech Connect (OSTI)

    Liu, Kuan-Hsien; Chou, Wu-Ching, E-mail: tcchang3708@gmail.com, E-mail: wuchingchou@mail.nctu.edu.tw [Department of Electrophysics, National Chiao Tung University, Hsin-chu 300, Taiwan (China); Chang, Ting-Chang, E-mail: tcchang3708@gmail.com, E-mail: wuchingchou@mail.nctu.edu.tw [Department of Physics, National Sun Yat-Sen University, Kaohsiung 804, Taiwan (China); Advanced Optoelectronics Technology Center, National Cheng Kung University, Taiwan (China); Chen, Hua-Mao; Tai, Ya-Hsiang [Department of Photonics and Institute of Electro-Optical Engineering, National Chiao Tung University, Hsin-chu 300, Taiwan (China); Tsai, Ming-Yen; Hung, Pei-Hua; Chu, Ann-Kuo [Department of Photonics, National Sun Yat-Sen University, Kaohsiung 804, Taiwan (China); Wu, Ming-Siou; Hung, Yi-Syuan [Department of Electronics Engineering, National Chiao Tung University, Hsin-Chu 300, Taiwan (China); Hsieh, Tien-Yu [Department of Physics, National Sun Yat-Sen University, Kaohsiung 804, Taiwan (China); Yeh, Bo-Liang [Advanced Display Technology Research Center, AU Optronics, No.1, Li-Hsin Rd. 2, Hsinchu Science Park, Hsin-Chu 30078, Taiwan (China)

    2014-10-21

    This paper investigates abnormal dimension-dependent thermal instability in amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors. Device dimension should theoretically have no effects on threshold voltage, except for in short channel devices. Unlike short channel drain-induced source barrier lowering effect, threshold voltage increases with increasing drain voltage. Furthermore, for devices with either a relatively large channel width or a short channel length, the output drain current decreases instead of saturating with an increase in drain voltage. Moreover, the wider the channel and the shorter the channel length, the larger the threshold voltage and output on-state current degradation that is observed. Because of the surrounding oxide and other thermal insulating material and the low thermal conductivity of the IGZO layer, the self-heating effect will be pronounced in wider/shorter channel length devices and those with a larger operating drain bias. To further clarify the physical mechanism, fast I{sub D}-V{sub G} and modulated peak/base pulse time I{sub D}-V{sub D} measurements are utilized to demonstrate the self-heating induced anomalous dimension-dependent threshold voltage variation and on-state current degradation.

  19. Partial Gating Optimization for Power Reduction During Test Application

    E-Print Network [OSTI]

    Tehranipoor, Mohammad

    and energy consumption self testing of portable devices is rendered impractical. For all these reasons. INTRODUCTION Power consumption during testing has become an impor- tant issue in modern day designs consumption is especially important in today's chips, where larger numbers of transistors are packed

  20. Smart Electromechanical Pumping of Electrons in a Nanopillars Transistor

    E-Print Network [OSTI]

    Yue-Min Wan; Heng-Tien Lin

    2007-07-24

    Analysis of room-temperature current-voltage (I-V) characteristics of a silicon box in a nanopillar transistor suggests that a weak electromechanical coupling of 0.17 is responsible for the stable tunnel of single-electron. The dynamics involves a few electrons and the numbers (N) specified are periodical at 3, 6, and 12. Quantized currents are observed at N = 7 and 13, indicating that the box is a man-made atom. At a large value of 0.5, instability however dominates the I-V by showing interference, channel closure and the change of tunnel direction. Overall, the interplay of even and odd electrons between different channels also shows that the box operates itself like a smart quantum pump.

  1. From transistor to trapped-ion computers for quantum chemistry

    E-Print Network [OSTI]

    M. -H. Yung; J. Casanova; A. Mezzacapo; J. McClean; L. Lamata; A. Aspuru-Guzik; E. Solano

    2013-07-16

    Over the last few decades, quantum chemistry has progressed through the development of computational methods based on modern digital computers. However, these methods can hardly fulfill the exponentially-growing resource requirements when applied to large quantum systems. As pointed out by Feynman, this restriction is intrinsic to all computational models based on classical physics. Recently, the rapid advancement of trapped-ion technologies has opened new possibilities for quantum control and quantum simulations. Here, we present an efficient toolkit that exploits both the internal and motional degrees of freedom of trapped ions for solving problems in quantum chemistry, including molecular electronic structure, molecular dynamics, and vibronic coupling. We focus on applications that go beyond the capacity of classical computers, but may be realizable on state-of-the-art trapped-ion systems. These results allow us to envision a new paradigm of quantum chemistry that shifts from the current transistor to a near-future trapped-ion-based technology.

  2. Variability-Aware Design of Double Gate FinFET-based Current Mirrors

    E-Print Network [OSTI]

    Mohanty, Saraju P.

    = front gate voltage, Vgb= back gate voltage. In the SG mode, the front and back gates are tied together and the back-gate voltage (Vgb) is set to 0 V. The low-power (LP)-mode applies a reverse-bias voltage of -0.2V

  3. Femto-Molar Sensitive Field Effect Transistor Biosensors Based on Silicon Nanowires and

    E-Print Network [OSTI]

    De Micheli, Giovanni

    Femto-Molar Sensitive Field Effect Transistor Biosensors Based on Silicon Nanowires and AntibodiesNW-FET biosensors can be realized by linking recognition groups to the surface of the nanowire [5], [6], [7

  4. Deeply-scaled GaN high electron mobility transistors for RF applications

    E-Print Network [OSTI]

    Lee, Dong Seup

    2014-01-01

    Due to the unique combination of large critical breakdown field and high electron velocity, GaN-based high electron mobility transistors (HEMTs) have great potential for next generation high power RF amplifiers. The ...

  5. The bias-stress effect in pentacene organic thin-film transistors

    E-Print Network [OSTI]

    Ryu, Kyungbum

    2010-01-01

    Organic thin-film transistors (OTFTs) are promising for flexible large-area electronics. However, the bias-stress effect (BSE) in OTFTs causes operational instability that limits the usefulness of the OTFT technology in a ...

  6. Millimeter-wave GaN high electron mobility transistors and their integration with silicon electronics

    E-Print Network [OSTI]

    Chung, Jinwook W. (Jinwook Will)

    2011-01-01

    In spite of the great progress in performance achieved during the last few years, GaN high electron mobility transistors (HEMTs) still have several important issues to be solved for millimeter-wave (30 ~ 300 GHz) applications. ...

  7. The High-Electron Mobility Transistor at 30: Impressive Accomplishments and Exciting Prospects

    E-Print Network [OSTI]

    del Alamo, Jesus A.

    2010 marked the 30th anniversary of the High-Electron Mobility Transistor (HEMT). The HEMT represented a triumph for the, at the time, relatively new concept of bandgap engineering and nascent molecular beam epitaxy ...

  8. Bias-Stress Effect in Pentacene Organic Thin-Film Transistors

    E-Print Network [OSTI]

    Ryu, Kevin K.

    The effects of bias stress in integrated pentacene organic transistors are studied and modeled for different stress conditions. It is found that the effects of bias stress can be expressed in terms of the shift in applied ...

  9. Layered CU-based electrode for high-dielectric constant oxide thin film-based devices

    DOE Patents [OSTI]

    Auciello, Orlando

    2010-05-11

    A layered device including a substrate; an adhering layer thereon. An electrical conducting layer such as copper is deposited on the adhering layer and then a barrier layer of an amorphous oxide of TiAl followed by a high dielectric layer are deposited to form one or more of an electrical device such as a capacitor or a transistor or MEMS and/or a magnetic device.

  10. Low Voltage, Low Power Organic Light Emitting Transistors for AMOLED Displays

    SciTech Connect (OSTI)

    McCarthy, M. A. [University of Florida, Gainesville; Liu, B. [University of Florida, Gainesville; Donoghue, E. P. [University of Florida, Gainesville; Kravchenko, Ivan I [ORNL; Kim, D. Y. [University of Florida, Gainesville; Reynolds, J. R. [University of Florida, Gainesville; So, Franky [University of Florida, Gainesville; Rinzler, A. G. [University of Florida, Gainesville

    2011-01-01

    Low voltage, low power dissipation, high aperture ratio organic light emitting transistors are demonstrated. The high level of performance is enabled by a carbon nanotube source electrode that permits integration of the drive transistor and the organic light emitting diode into an efficient single stacked device. Given the demonstrated performance, this technology could break the technical logjam holding back widespread deployment of active matrix organic light emitting displays at flat panel screen sizes.

  11. Device and circuit-level models for carbon nanotube and graphene nanoribbon transistors

    E-Print Network [OSTI]

    Tan, Michael Loong Peng

    2011-06-07

    industry. Circuit simulation time has been substantially reduced through algorithm improvement and hardware enhancement through high performance computing (HPC) platforms. Given its ‘industry standard’ status for computer aided design and analysis... performance computation with digital logic. When current Si transistor features cannot be scaled to smaller sizes to keep improving performance, alternative material based transistors come into focus. Carbon nanotubes are essentially a rolled-up sheet...

  12. Micro-mechanical logic for field produceable gate arrays

    E-Print Network [OSTI]

    Prakash, Manu

    2005-01-01

    A paradigm of micro-mechanical gates for field produceable logic is explored. A desktop manufacturing system is sought after which is capable of printing functional logic devices in the field. A logic scheme which induces ...

  13. Constructing two-qubit gates with minimal couplings

    E-Print Network [OSTI]

    Yuan, Haidong

    Couplings between quantum systems are frequently less robust and harder to implement than controls on individual systems; thus, constructing quantum gates with minimal interactions is an important problem in quantum ...

  14. Gate-Level Characterization: Foundations and Hardware Security Applications

    E-Print Network [OSTI]

    Potkonjak, Miodrag

    Security Keywords Gate-level characterization, thermal conditioning, hardware Trojan horse, manufacturing leakage energy, ever increasing sub- strate noise, profound and intrinsic manufacturing variabil- ity (MV rights management. However, GLC is challenging due to the existence of manufacturing variability (MV

  15. Quantum optical interface for gate-controlled spintronic devices

    E-Print Network [OSTI]

    Hans-Andreas Engel; Jacob M. Taylor; Mikhail D. Lukin; Atac Imamoglu

    2006-12-29

    We describe an opto-electronic structure in which charge and spin degrees of freedom in electrical gate-defined quantum dots can be coherently coupled to light. This is achieved via electron-electron interaction or via electron tunneling into a proximal self-assembled quantum dot. We illustrate potential applications of this approach by considering several quantum control techniques, including optical read-out of gate-controlled semiconductor quantum bits and controlled generation of entangled photon-spin pairs.

  16. Optimal Control Theory for Continuous Variable Quantum Gates

    E-Print Network [OSTI]

    Rebing Wu; Raj Chakrabarti; Herschel Rabitz

    2007-08-16

    We apply the methodology of optimal control theory to the problem of implementing quantum gates in continuous variable systems with quadratic Hamiltonians. We demonstrate that it is possible to define a fidelity measure for continuous variable (CV) gate optimization that is devoid of traps, such that the search for optimal control fields using local algorithms will not be hindered. The optimal control of several quantum computing gates, as well as that of algorithms composed of these primitives, is investigated using several typical physical models and compared for discrete and continuous quantum systems. Numerical simulations indicate that the optimization of generic CV quantum gates is inherently more expensive than that of generic discrete variable quantum gates, and that the exact-time controllability of CV systems plays an important role in determining the maximum achievable gate fidelity. The resulting optimal control fields typically display more complicated Fourier spectra that suggest a richer variety of possible control mechanisms. Moreover, the ability to control interactions between qunits is important for delimiting the total control fluence. The comparative ability of current experimental protocols to implement such time-dependent controls may help determine which physical incarnations of CV quantum information processing will be the easiest to implement with optimal fidelity.

  17. Filter design for hybrid spin gates

    E-Print Network [OSTI]

    Andreas Albrecht; Martin B. Plenio

    2015-04-14

    The impact of control sequences on the environmental coupling of a quantum system can be described in terms of a filter. Here we analyze how the coherent evolution of two interacting spins subject to periodic control pulses, at the example of a nitrogen vacancy center coupled to a nuclear spin, can be described in the filter framework in both the weak and the strong coupling limit. A universal functional dependence around the filter resonances then allows for tuning the coupling type and strength. Originally limited to small rotation angles, we show how the validity range of the filter description can be extended to the long time limit by time-sliced evolution sequences. Based on that insight, the construction of tunable, noise decoupled, conditional gates composed of alternating pulse sequences is proposed. In particular such an approach can lead to a significant improvement in fidelity as compared to a strictly periodic control sequence. Moreover we analyze the decoherence impact, the relation to the filter for classical noise known from dynamical decoupling sequences, and we outline how an alternating sequence can improve spin sensing protocols.

  18. Gated integrator with signal baseline subtraction

    DOE Patents [OSTI]

    Wang, X.

    1996-12-17

    An ultrafast, high precision gated integrator includes an opamp having differential inputs. A signal to be integrated is applied to one of the differential inputs through a first input network, and a signal indicative of the DC offset component of the signal to be integrated is applied to the other of the differential inputs through a second input network. A pair of electronic switches in the first and second input networks define an integrating period when they are closed. The first and second input networks are substantially symmetrically constructed of matched components so that error components introduced by the electronic switches appear symmetrically in both input circuits and, hence, are nullified by the common mode rejection of the integrating opamp. The signal indicative of the DC offset component is provided by a sample and hold circuit actuated as the integrating period begins. The symmetrical configuration of the integrating circuit improves accuracy and speed by balancing out common mode errors, by permitting the use of high speed switching elements and high speed opamps and by permitting the use of a small integrating time constant. The sample and hold circuit substantially eliminates the error caused by the input signal baseline offset during a single integrating window. 5 figs.

  19. Gated integrator with signal baseline subtraction

    DOE Patents [OSTI]

    Wang, Xucheng (Lisle, IL)

    1996-01-01

    An ultrafast, high precision gated integrator includes an opamp having differential inputs. A signal to be integrated is applied to one of the differential inputs through a first input network, and a signal indicative of the DC offset component of the signal to be integrated is applied to the other of the differential inputs through a second input network. A pair of electronic switches in the first and second input networks define an integrating period when they are closed. The first and second input networks are substantially symmetrically constructed of matched components so that error components introduced by the electronic switches appear symmetrically in both input circuits and, hence, are nullified by the common mode rejection of the integrating opamp. The signal indicative of the DC offset component is provided by a sample and hold circuit actuated as the integrating period begins. The symmetrical configuration of the integrating circuit improves accuracy and speed by balancing out common mode errors, by permitting the use of high speed switching elements and high speed opamps and by permitting the use of a small integrating time constant. The sample and hold circuit substantially eliminates the error caused by the input signal baseline offset during a single integrating window.

  20. Impulse radar with swept range gate

    DOE Patents [OSTI]

    McEwan, T.E.

    1998-09-08

    A radar range finder and hidden object locator is based on ultra-wide band radar with a high resolution swept range gate. The device generates an equivalent time amplitude scan with a typical range of 4 inches to 20 feet, and an analog range resolution as limited by a jitter of on the order of 0.01 inches. A differential sampling receiver is employed to effectively eliminate ringing and other aberrations induced in the receiver by the near proximity of the transmit antenna, so a background subtraction is not needed, simplifying the circuitry while improving performance. Techniques are used to reduce clutter in the receive signal, such as decoupling the receive and transmit cavities by placing a space between them, using conductive or radiative damping elements on the cavities, and using terminating plates on the sides of the openings. The antennas can be arranged in a side-by-side parallel spaced apart configuration or in a coplanar opposed configuration which significantly reduces main bang coupling. 25 figs.

  1. The gated community: residents' crime experience and perception of safety behind gates and fences in the urban area 

    E-Print Network [OSTI]

    Kim, Suk Kyung

    2006-10-30

    The primary purpose of the study is to explore the connections between residents' perception of safety and their crime experience, and the existence of gates and fences in multi-family housing communities in urban areas. ...

  2. Ge MOS Characteristics with CVD HfO2 Gate Dielectrics and TaN Gate Electrode W. P. Bai*, N. Lu*, J. Liu*, A. Ramirez**, D. L. Kwong*, D. Wristers**, A. Ritenour#

    E-Print Network [OSTI]

    Ge MOS Characteristics with CVD HfO2 Gate Dielectrics and TaN Gate Electrode W. P. Bai*, N. Lu*, J, we report for the first time Ge MOS characteristics with ultra thin rapid thermal CVD HfO2 gate dielectrics and TaN gate electrode. Using the newly developed pre- gate cleaning and NH3-based Ge surface

  3. A laser-programmable gate array 

    E-Print Network [OSTI]

    Gullette, James Benjamin

    1985-01-01

    process with double layer polysilicon, typicaHy used for capacitors, and single layer metal. The laser techniques used to program the devices were the interconnection of the over- lapping polysilicon layers and the cutting of metal and polysilicon links... Array The VLSI program at Texas A&M University was provided with a standard double-poly N-channel Metal Oxide Semiconductor (NMOS) process. It has been found that certain laser personalization techniques for creating and deleting con- nections...

  4. Liquid crystal terahertz phase shifters with functional indium-tin-oxide nanostructures for biasing and alignment

    SciTech Connect (OSTI)

    Yang, Chan-Shan [Department of Physics, National Tsing Hua University, Hsinchu 30013, Taiwan (China); Chemical Sciences Division, Lawrence Berkeley National Laboratory, Berkeley, California 94720 (United States); Tang, Tsung-Ta [Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan (China); Pan, Ru-Pin [Department of Electrophysics, National Chiao Tung University, Hsinchu 30078, Taiwan (China); Yu, Peichen [Department of Photonics and Institute of Electro-Optical Engineering, National Chiao Tung University, Hsinchu 30010, Taiwan (China); Pan, Ci-Ling, E-mail: clpan@phys.nthu.edu.tw [Department of Physics, National Tsing Hua University, Hsinchu 30013, Taiwan (China); Frontier Research Center on Fundamental and Applied Science of Matters, Hsinchu 30013, Taiwan (China)

    2014-04-07

    Indium Tin Oxide (ITO) nanowhiskers (NWhs) obliquely evaporated by electron-beam glancing-angle deposition can serve simultaneously as transparent electrodes and alignment layer for liquid crystal (LC) devices in the terahertz (THz) frequency range. To demonstrate, we constructed a THz LC phase shifter with ITO NWhs. Phase shift exceeding ?/2 at 1.0 THz was achieved in a ?517??m-thick cell. The phase shifter exhibits high transmittance (?78%). The driving voltage required for quarter-wave operation is as low as 5.66?V (rms), compatible with complementary metal-oxide-semiconductor (CMOS) and thin-film transistor (TFT) technologies.

  5. Ambipolar charge transport in microcrystalline silicon thin-film transistors

    SciTech Connect (OSTI)

    Knipp, Dietmar; Marinkovic, M.; Chan, Kah-Yoong; Gordijn, Aad; Stiebig, Helmut

    2011-01-15

    Hydrogenated microcrystalline silicon ({mu}c-Si:H) is a promising candidate for thin-film transistors (TFTs) in large-area electronics due to high electron and hole charge carrier mobilities. We report on ambipolar TFTs based on {mu}c-Si:H prepared by plasma-enhanced chemical vapor deposition at temperatures compatible with flexible substrates. Electrons and holes are directly injected into the {mu}c-Si:H channel via chromium drain and source contacts. The TFTs exhibit electron and hole charge carrier mobilities of 30-50 cm{sup 2}/V s and 10-15 cm{sup 2}/V s, respectively. In this work, the electrical characteristics of the ambipolar {mu}c-Si:H TFTs are described by a simple analytical model that takes the ambipolar charge transport into account. The analytical expressions are used to model the transfer curves, the potential and the net surface charge along the channel of the TFTs. The electrical model provides insights into the electronic transport of ambipolar {mu}c-Si:H TFTs.

  6. Oxidation catalyst

    DOE Patents [OSTI]

    Ceyer, Sylvia T. (Cambridge, MA); Lahr, David L. (Cambridge, MA)

    2010-11-09

    The present invention generally relates to catalyst systems and methods for oxidation of carbon monoxide. The invention involves catalyst compositions which may be advantageously altered by, for example, modification of the catalyst surface to enhance catalyst performance. Catalyst systems of the present invention may be capable of performing the oxidation of carbon monoxide at relatively lower temperatures (e.g., 200 K and below) and at relatively higher reaction rates than known catalysts. Additionally, catalyst systems disclosed herein may be substantially lower in cost than current commercial catalysts. Such catalyst systems may be useful in, for example, catalytic converters, fuel cells, sensors, and the like.

  7. Deterministic and cascadable conditional phase gate for photonic qubits

    SciTech Connect (OSTI)

    Chudzicki, Christopher; Chuang, Isaac; Shapiro, Jeffrey H.

    2014-12-04

    Previous analyses of conditional ?{sub NL}-phase gates for photonic qubits that treat crossphase modulation (XPM) in a causal, multimode, quantum field setting suggest that a large (?? rad) nonlinear phase shift is always accompanied by fidelity-degrading noise [J. H. Shapiro, Phys. Rev. A 73, 062305 (2006); J. Gea-Banacloche, Phys. Rev. A 81, 043823 (2010)]. Using an atomic V-system to model an XPM medium, we present a conditional phase gate that, for sufficiently small nonzero ?{sub NL}, has high fidelity. The gate is made cascadable by using a special measurement, principal mode projection, to exploit the quantum Zeno effect and preclude the accumulation of fidelity-degrading departures from the principal-mode Hilbert space when both control and target photons illuminate the gate. The nonlinearity of the V-system we study is too weak for this particular implementation to be practical. Nevertheless, the idea of cascading through principal mode projection is of potential use to overcome fidelity degrading noise for a wide variety of nonlinear optical primitive gates.

  8. Decoherence and gate performance of coupled solid state qubits

    E-Print Network [OSTI]

    Markus J. Storcz; Frank K. Wilhelm

    2002-12-16

    Solid state quantum bits are promising candidates for the realization of a {\\em scalable} quantum computer. However, they are usually strongly limited by decoherence due to the many extra degrees of freedom of a solid state system. We investigate a system of two solid state qubits that are coupled via $\\sigma_z^{(i)} \\otimes \\sigma_z^{(j)}$ type of coupling. This kind of setup is typical for {\\em pseudospin} solid-state quantum bits such as charge or flux systems. We evaluate decoherence properties and gate quality factors in the presence of a common and two uncorrelated baths coupling to $\\sigma_z$, respectively. We show that at low temperatures, uncorrelated baths do degrade the gate quality more severely. In particular, we show that in the case of a common bath, optimum gate performance of a CPHASE gate can be reached at very low temperatures, because our type of coupling commutes with the coupling to the decoherence, which makes this type of coupling attractive as compared to previously studied proposals with $\\sigma_y^{(i)} \\otimes \\sigma_y^{(j)}$ -coupling. Although less pronounced, this advantage also applies to the CNOT gate.

  9. Strained Sistrained Ge dual-channel heterostructures on relaxed Si0.5Ge0.5 for symmetric mobility p-type and n-type metal-oxide-semiconductor

    E-Print Network [OSTI]

    Strained SiÕstrained Ge dual-channel heterostructures on relaxed Si0.5Ge0.5 for symmetric mobility By growing heterostructures that combine a surface strained Si layer with a buried strained Ge layer on Si0.5Ge0.5 , we have fabricated metal-oxide-semiconductor field-effect transistors with mobility

  10. Effects of surface passivation on top-down ZnO nanowire transistors N.M.J. Ditshego

    E-Print Network [OSTI]

    2015 Keywords: Depletion mode Field effect transistor Nanowire Remote plasma atomic layer deposition approach [6,7], which uses standard photolithography; remote plasma atomic layer deposition and anisotropicO) nanowire field effect transistors (NWFETs) using conventional top-down method of remote plasma atomic layer

  11. An optical fusion gate for W-states

    E-Print Network [OSTI]

    Sahin Kaya Ozdemir; Eiji Matsunaga; Toshiyuki Tashima; Takashi Yamamoto; Masato Koashi; Nobuyuki Imoto

    2011-03-11

    We introduce a simple optical gate to fuse arbitrary size polarization entangled W-states to prepare larger W-states. The gate requires a polarizing beam splitter (PBS), a half wave plate (HWP) and two photon detectors. We study numerically and analytically the necessary resource consumption for preparing larger W-states by fusing smaller ones with the proposed fusion gate. We show analytically that resource requirement scales at most sub-exponentially with the increasing size of the state to be prepared. We numerically determine the resource cost for fusion without recycling where W-states of arbitrary size can be optimally prepared. Moreover, we introduce another strategy which is based on recycling and outperforms the optimal strategy for non-recycling case.

  12. Fabrication of a gated gallium arsenide heterostructure resonant tunneling diode 

    E-Print Network [OSTI]

    Kinard, William Brian

    1989-01-01

    , . ' 'CONTACT PAD' PLANAR I ZED POLYAM I DE RECTIFYI CONTACT N DBHS Pig. 2. f'utavvay vieiv of a gated gallium arsenide heterostructure resonant tunneling diode 1018 graded from 10 18 io" 10? (lightly doped) units=cm 8 ?graded from 10 to 18...FABRICATION OF A GATED GALLIL". tl ARSEXIDE HETEROSTRL CTL RF. RESONANT TF'XXELI'XG DIODE A Thesis bt ttrILLIAAI BRIA'. s KI'iARD Subnut ted to the Office of Graduate Studies of Texas AE;M Eniverstty tn partial fulfillment of the requirements...

  13. Self-aligned submicron gate length gallium arsenide MESFET 

    E-Print Network [OSTI]

    Huang, Hsien-Ching

    1987-01-01

    38 21. Proximity cap annealing . 22. Temperature profile of post implant anneal 46 47 23. 24. 25. 26. 27. 28. 29. 30. "Pits" or holes in GaAs post implant anneal without sacrificial cap Silicon monoxide source (bafile box) used.... 16(b)). The bottom resist layer is then further etched in the oxygen plasma to produce undercutting for the desire gate structure. The amount of undercut is determined by the desired length of the gate and is the width of the remaining resist...

  14. Isolated-attosecond-pulse generation with infrared double optical gating

    SciTech Connect (OSTI)

    Lan Pengfei; Takahashi, Eiji J.; Midorikawa, Katsumi [Extreme Photonics Research Group, RIKEN Advanced Science Institute, 2-1 Hirosawa, Wako, Saitama 351-0198 (Japan)

    2011-06-15

    We propose and theoretically demonstrate an infrared two-color polarization gating scheme for generating an intense isolated attosecond pulse (IAP) in the multicycle regime. Our simulations show that an IAP can be produced using a multicycle two-color driving pulse with a duration up to 60 fs. Moreover, the carrier-envelope phase (CEP) of the driving laser is not required to be stabilized, although the IAP intensity changes with the CEP slip. Such a gating scheme significantly relaxes the requirements for driving lasers and opens the door to easily create intense IAPs with a high-power conventional multicycle laser pulse.

  15. Quantum entanglement and controlled logical gates using coupled SQUID flux qubits

    E-Print Network [OSTI]

    Zhou, Zhongyuan; Han, Siyuan; Chu, Shih-I

    2005-06-01

    We present an approach to realize universal two-bit quantum gates using two SQUID flux qubits. In this approach the basic unit consists of two inductively coupled SQUIDs with realistic device parameters. Quantum logical gates are implemented...

  16. High performance transistors via aligned polyfluorene-sorted carbon nanotubes

    SciTech Connect (OSTI)

    Brady, Gerald J.; Joo, Yongho; Singha Roy, Susmit; Gopalan, Padma; Arnold, Michael S.

    2014-02-24

    We evaluate the performance of exceptionally electronic-type sorted, semiconducting, aligned single-walled carbon nanotubes (s-SWCNTs) in field effect transistors (FETs). High on-conductance and high on/off conductance modulation are simultaneously achieved at channel lengths which are both shorter and longer than individual s-SWCNTs. The s-SWCNTs are isolated from heterogeneous mixtures using a polyfluorene-derivative as a selective agent and aligned on substrates via dose-controlled, floating evaporative self-assembly at densities of ?50 s-SWCNTs ?m{sup ?1}. At a channel length of 9??m the s-SWCNTs percolate to span the FET channel, and the on/off ratio and charge transport mobility are 2.2?×?10{sup 7} and 46?cm{sup 2}?V{sup ?1}?s{sup ?1}, respectively. At a channel length of 400?nm, a large fraction of the s-SWCNTs directly span the channel, and the on-conductance per width is 61??S??m{sup ?1} and the on/off ratio is 4?×?10{sup 5}. These results are considerably better than previous solution-processed FETs, which have suffered from poor on/off ratio due to spurious metallic nanotubes that bridge the channel. 4071 individual and small bundles of s-SWCNTs are tested in 400?nm channel length FETs, and all show semiconducting behavior, demonstrating the high fidelity of polyfluorenes as selective agents and the promise of assembling s-SWCNTs from solution to create high performance semiconductor electronic devices.

  17. The civic forum in ancient Israel : the form, function, and symbolism of city gates

    E-Print Network [OSTI]

    Frese, Daniel Allan

    2012-01-01

    from the massive amounts of wood ash and burnt ceiling beamsand the presence of wood ash in some gate passages,

  18. Chemical Wave Logic Gates Oliver Steinbock, Petteri Kettunen, and Kenneth Showalter*

    E-Print Network [OSTI]

    Showalter, Kenneth

    Chemical Wave Logic Gates Oliver Steinbock, Petteri Kettunen, and Kenneth Showalter* Department Form: August 6, 1996X Logic gates based on chemical wave propagation in geometrically constrained. Computational studies of the serial coupling of elements to form multicomponent gates and general chemical wave

  19. PHYSICAL REVIEW B 90, 144504 (2014) Compressed sensing quantum process tomography for superconducting quantum gates

    E-Print Network [OSTI]

    Martinis, John M.

    2014-01-01

    for superconducting quantum gates Andrey V. Rodionov,1 Andrzej Veitia,1 R. Barends,2 J. Kelly,2 Daniel Sank,2 J quantum gates based on superconducting Xmon and phase qubits. Using experimental data for a two and Monte Carlo process certification have been demonstrated experimentally for superconducting qubit gates

  20. PHYSICAL REVIEW A 87, 052306 (2013) Protected gates for superconducting qubits

    E-Print Network [OSTI]

    Preskill, John

    2013-01-01

    PHYSICAL REVIEW A 87, 052306 (2013) Protected gates for superconducting qubits Peter Brooks, Alexei the accuracy of quantum phase gates acting on "0- qubits" in superconducting circuits, where the gates superconducting circuits for this purpose. Specifically, several authors [3­5] have proposed designs

  1. Case Studies on Clock Gating and Local Routign for VLSI Clock Mesh 

    E-Print Network [OSTI]

    Ramakrishnan, Sundararajan

    2010-10-12

    . This thesis deals with the introduction of 'reconfigurability' by using control structures like transmission gates between sub-clock meshes, thus enabling clock gating in clock mesh. By using the optimum value of size for PMOS and NMOS of transmission gate...

  2. Learning Methods for Lung Tumor Markerless Gating in Image-Guided Radiotherapy

    E-Print Network [OSTI]

    Dy, Jennifer G.

    Learning Methods for Lung Tumor Markerless Gating in Image-Guided Radiotherapy Ying Cui Dept. For gated lung cancer radiotherapy, it is difficult to generate ac- curate gating signals due to the large techniques, we apply them on five sequences of fluoroscopic images from five lung cancer patients against

  3. High-performance chemical-bath deposited CdS thin-film transistors with ZrO2 gate dielectric

    E-Print Network [OSTI]

    Dondapati, Hareesh; Ha, Duc; Jenrette, Erin; Xiao, Bo; Pradhan, A. K

    2014-01-01

    2014) High-performance chemical-bath deposited CdS thin-filmWe demonstrate high performance chemical bath deposited CdSgeneration, inexpensive chemical-based low temperature

  4. An overview of the gate and panel industry 

    E-Print Network [OSTI]

    Fisher, C. West

    2000-01-01

    acquiring raw materials, its pre-fabrication, welding, touch-up, and delivery of the product. My first major responsibility for Texas Gate and Panel was to expand its sales territory. It soon became obvious that a thorough knowledge of my competitors...

  5. FLOATING GATE COMPARATOR WITH AUTOMATIC OFFSET MANIPULATION FUNCTIONALITY

    E-Print Network [OSTI]

    Maryland at College Park, University of

    a desired offset. We exploit the nega- tive feedback functionality of pFET hot-electron injection to achieve to this circuit node, so charge on this gate remains trapped for a very long time. In our comparator, the circuit offset is stored in this high-retention charge form, and altered by means of injection and tunneling

  6. Quantum Logic Gates in Superconducting Qubits John M. Martinis

    E-Print Network [OSTI]

    Martinis, John M.

    Quantum Logic Gates in Superconducting Qubits John M. Martinis Department of Physics University on surface codes may allow errors in the 10-2 range [2]. Much research in superconducting qubits has been di for superconducting qubits, since they typically use fixed coupling elements set by fabrication. TRANSITION LOGIC

  7. Gating and regulation of connexin 43 (Cx43) hemichannels

    E-Print Network [OSTI]

    Newman, Eric A.

    Gating and regulation of connexin 43 (Cx43) hemichannels Jorge E. Contreras* , Juan C. Sa Connexin 43 (Cx43) nonjunctional or ``unapposed'' hemichannels can open under physiological or pathological conditions. We char- acterize hemichannels comprised of Cx43 or Cx43-EGFP (Cx43 with enhanced GFP fused

  8. Clustering of cyclic-nucleotide-gated channels in olfactory cilia

    E-Print Network [OSTI]

    French, Donald A.

    Cincinnati, OH 45267-0667, USA 513-558-6099 513-558-2727 FAX steve@syrano.acb.uc.edu Running title: CNG of olfactory signal transduction, including a high density of cyclic-nucleotide-gated (CNG) channels. CNG the locations of CNG channels along the length may be important in determining the sensitivity of odor detection

  9. Three-qubit phase gate based on cavity quantum electrodynamics 

    E-Print Network [OSTI]

    Chang, Jun-Tao; Zubairy, M. Suhail

    2008-01-01

    We describe a three-qubit quantum phase gate which is implemented by passing a four-level atom in a cascade configuration initially in its ground state through a three-mode optical cavity. The three qubits are represented by the photons in the three...

  10. Optical gating of perylene bisimide fluorescence using dithienylcyclopentene photochromic switches

    SciTech Connect (OSTI)

    Pärs, Martti; Köhler, Jürgen, E-mail: juergen.koehler@uni-bayreuth.de [Experimental Physics IV, University of Bayreuth, 95440 Bayreuth (Germany)] [Experimental Physics IV, University of Bayreuth, 95440 Bayreuth (Germany); Gräf, Katja; Bauer, Peter; Thelakkat, Mukundan [Applied Functional Polymers, University of Bayreuth, 95440 Bayreuth (Germany)] [Applied Functional Polymers, University of Bayreuth, 95440 Bayreuth (Germany)

    2013-11-25

    The emission of millions of fluorescence photons from a chromophore is controlled by the absorption of a few tens of photons in a photochromic molecule. The parameters that determine the efficiency of this process are investigated, providing insights for the development of an all-optical gate.

  11. Temperature-controlled molecular depolarization gates in nuclear magnetic resonance

    SciTech Connect (OSTI)

    Schroder, Leif; Schroder, Leif; Chavez, Lana; Meldrum, Tyler; Smith, Monica; Lowery, Thomas J.; E. Wemmer, David; Pines, Alexander

    2008-02-27

    Down the drain: Cryptophane cages in combination with selective radiofrequency spin labeling can be used as molecular 'transpletor' units for transferring depletion of spin polarization from a hyperpolarized 'source' spin ensemble to a 'drain' ensemble. The flow of nuclei through the gate is adjustable by the ambient temperature, thereby enabling controlled consumption of hyperpolarization.

  12. Compact floating-gate true random number generator

    E-Print Network [OSTI]

    Maryland at College Park, University of

    Compact floating-gate true random number generator P. Xu, Y.L. Wong, T.K. Horiuchi and P.A. Abshire A compact true random number generator (RNG) integrated circuit with adjustable probability is presented. Introduction: Random number generation is indispensable in crypto- graphy, scientific computing and stochastic

  13. TECH FORUM: [VERIFIED RTL TO GATES] Efficient RC power grid

    E-Print Network [OSTI]

    Najm, Farid N.

    TECH FORUM: [VERIFIED RTL TO GATES] Efficient RC power grid verification using node elimination proposes a novel approach to systematically reduce the power grid and accurately compute an upper bound on the voltage drops at power grid nodes that are retained. Furthermore, acriterion for the safety of nodes

  14. A Gate Level Sensor Network for Integrated Circuits Temperature Monitoring

    E-Print Network [OSTI]

    Potkonjak, Miodrag

    A Gate Level Sensor Network for Integrated Circuits Temperature Monitoring Alireza Vahdatpour, Saro and temporal) temperature monitoring allows several run-time optimizations. Protecting shared processors from, miodrag}@cs.ucla.edu Abstract-- We present the first sensor network architecture to monitor integrated

  15. Gating of high-mobility InAs metamorphic heterostructures

    SciTech Connect (OSTI)

    Shabani, J.; McFadden, A. P.; Shojaei, B.; Palmstrøm, C. J.

    2014-12-29

    We investigate the performance of gate-defined devices fabricated on high mobility InAs metamorphic heterostructures. We find that heterostructures capped with In{sub 0.75}Ga{sub 0.25}As often show signs of parallel conduction due to proximity of their surface Fermi level to the conduction band minimum. Here, we introduce a technique that can be used to estimate the density of this surface charge that involves cool-downs from room temperature under gate bias. We have been able to remove the parallel conduction under high positive bias, but achieving full depletion has proven difficult. We find that by using In{sub 0.75}Al{sub 0.25}As as the barrier without an In{sub 0.75}Ga{sub 0.25}As capping, a drastic reduction in parallel conduction can be achieved. Our studies show that this does not change the transport properties of the quantum well significantly. We achieved full depletion in InAlAs capped heterostructures with non-hysteretic gating response suitable for fabrication of gate-defined mesoscopic devices.

  16. Trapped-ion quantum logic gates based on oscillating magnetic fields

    E-Print Network [OSTI]

    C. Ospelkaus; C. E. Langer; J. M. Amini; K. R. Brown; D. Leibfried; D. J. Wineland

    2008-05-14

    Oscillating magnetic fields and field gradients can be used to implement single-qubit rotations and entangling multi-qubit quantum gates for trapped-ion quantum information processing (QIP). With fields generated by currents in microfabricated surface-electrode traps, it should be possible to achieve gate speeds that are comparable to those of optically induced gates for realistic distances between the ion crystal and the electrode surface. Magnetic-field-mediated gates have the potential to significantly reduce the overhead in laser beam control and motional state initialization compared to current QIP experiments with trapped ions and will eliminate spontaneous scattering, a fundamental source of decoherence in laser-mediated gates.

  17. Ambient induced degradation and chemically activated recovery in copper phthalocyanine thin film transistors

    E-Print Network [OSTI]

    Kummel, Andrew C.

    Ambient induced degradation and chemically activated recovery in copper phthalocyanine thin film 2009 The electrical degradation aging of copper phthalocyanine CuPc organic thin film transistors OTFTs of Physics. DOI: 10.1063/1.3159885 I. INTRODUCTION The recent demand for low cost, versatile electronic de

  18. Bendable single crystal silicon thin film transistors formed by printing on plastic substrates

    E-Print Network [OSTI]

    Rogers, John A.

    Bendable single crystal silicon thin film transistors formed by printing on plastic substrates E on plastic substrates using an efficient dry transfer printing technique. In these devices, free standing-Si is then transferred, to a specific location and with a controlled orientation, onto a thin plastic sheet

  19. Self-Assembled Metallic Nanowire-Based Vertical Organic Field-Effect Transistor

    E-Print Network [OSTI]

    Tessler, Nir

    -effect transistors (VOFETs). In the VOFET architecture, the nanowires' microstructure facilitates current modulation there is a wide selection of such substrates, insulators, semi- conductors, and conductors, solution, as with the case of standard light-emitting diodes (LEDs) and solar cells. But the functionality of nonoptical

  20. Nanometer-scale InGaAs Field-Effect Transistors for THz and CMOS technologies

    E-Print Network [OSTI]

    del Alamo, Jesus A.

    Integrated circuits based on InGaAs Field Effect Transistors are currently in wide use in the RF front-ends of smart phones and other mobile platforms, wireless LANs, high data rate fiber-optic links and many defense and ...

  1. Fully Printed, High Performance Carbon Nanotube Thin-Film Transistors on Flexible Substrates

    E-Print Network [OSTI]

    Javey, Ali

    range of large-area electronic applications based on carbon nanotube networks. KEYWORDS: Flexible using SWNT TFTs has been shown.1,5,7,8 In order to enable the use of flexible electronics for largeFully Printed, High Performance Carbon Nanotube Thin-Film Transistors on Flexible Substrates Pak

  2. IEEE TRANSACTIONS ON ELECTRON DEVICES 1 Bipolar Charge-Plasma Transistor

    E-Print Network [OSTI]

    Kumar, M. Jagadesh

    on undoped silicon-on-7 insulator (SOI) to form the emitter, base, and collector regions of a8 lateral n-p with that of a conventionally10 doped lateral bipolar junction transistor (BJT) with identical11 dimensions. Our simulation 54 with a significantly larger current gain, as compared with a 55 conventional bipolar junction

  3. Current gain in bipolar transistors with a field plate over the base surface

    E-Print Network [OSTI]

    Anantharam, Venkat

    the base surface and extending from the collector- base junction edge, on the current gain of vertical n-p. Abstract: Vertical n-p-n and lateral p-n-p transistor structures of an integrated circuit are studied using carriers into the base contact. This simulation study has also been adopted for the study of lateral p-n-p

  4. Forward delay in scaled Alo.481n,.,,As/ln,,,Ga,4,As heterojunction bipolar transistors

    E-Print Network [OSTI]

    Levi, Anthony F. J.

    simulations of the intrinsic forward delay as a function of base thickness in abrupt junction n-p-n Ab,4s band diagram of an Ab.4sIno.52As/Ino.53Ga0.47AS n-p-n heterojunction bipolar transistor (HBT) under

  5. High Carrier Mobility in Single Ultrathin Colloidal Lead Selenide Nanowire Field Effect Transistors

    E-Print Network [OSTI]

    Yu, Dong

    transistors incorporating single colloidal PbSe nanowires with diameters of 6-15 nm, coated with ammonium, enabling photovoltaic cell production through roll-by-roll technology, similar to a printing press surface, we coat the colloidal NWs with a thin layer of SiO2, which also protects the NWs from being

  6. Reducing Power and Delay in Memory Cells Using Virtual Source Transistors

    E-Print Network [OSTI]

    Delgado-Frias, José G.

    Reducing Power and Delay in Memory Cells Using Virtual Source Transistors Katie Blomster and José G a memory cell is switching its stored value; however, they do lead to significant power consumption in this paper seeks to decrease both delay and power consumption through the design of seven novel SRAM cells

  7. Transistor Sizing of Energy-DelayEfficient Circuits Paul I. Penzes, Mika Nystrom, Alain J. Martin

    E-Print Network [OSTI]

    Transistor Sizing of Energy-Delay­Efficient Circuits Paul I. P´enzes, Mika Nystr¨om, Alain J optimized for energy-delay efficiency, i.e., for optimal ¢¤£¦¥ where ¢ is the energy consumption-off between energy and delay. We propose a set of analytical formulas that closely ap- proximate the optimal

  8. AN ADAPTIVE MIXED SCHEME FOR ENERGY-TRANSPORT SIMULATIONS OF FIELD-EFFECT TRANSISTORS

    E-Print Network [OSTI]

    Pietra, Paola

    AN ADAPTIVE MIXED SCHEME FOR ENERGY-TRANSPORT SIMULATIONS OF FIELD-EFFECT TRANSISTORS #3; STEFAN HOLST, ANSGAR J  UNGEL y AND PAOLA PIETRA z Abstract. Energy-transport models are used in semiconductor simulations to account for ther- mal e#11;ects. The model consists of the continuity equations for the mass

  9. Light Quasiparticles Dominate Electronic Transport in Molecular Crystal Field-Effect Transistors

    E-Print Network [OSTI]

    Light Quasiparticles Dominate Electronic Transport in Molecular Crystal Field-Effect Transistors Z 1 Department of Physics, University of California, San Diego, La Jolla, California 92093, USA 2, Lawrence Berkeley National Laboratory, Berkeley, California 94720, USA (Received 1 March 2007; published 6

  10. High-Performance Solution-Processed Amorphous-Oxide-Semiconductor TFTs with Organic Polymeric Gate Dielectrics

    E-Print Network [OSTI]

    Pecunia, Vincenzo; Banger, Kulbinder K.; Sirringhaus, Henning

    2015-01-13

    are shown in Table 1: CYTOP™, an amorphous fluoropolymer of the PTFE family; poly(?-methylstyrene) (P?MS), a hydrophobic polymer with a phenyl functionality; poly(styrene-co-acrylonitrile) (SAN), a copolymer with nitrile functionality; poly(bisphenol A...

  11. Zirconium-doped tantalum oxide high-k gate dielectric films 

    E-Print Network [OSTI]

    Tewg, Jun-Yen

    2005-02-17

    ) is unacceptable for many practical reasons. By replacing the SiO2 layer with a high dielectric constant material (high-k), many of the problems can be solved. In this study, a novel high-k dielectric thin film, i.e., TaOx doped with Zr, was deposited and studied...

  12. Gate-Tunable Graphene Quantum Dot and Dirac Oscillator

    E-Print Network [OSTI]

    Abdelhadi Belouad; Ahmed Jellal; Youness Zahidi

    2015-05-29

    We obtain the solution of the Dirac equation in (2+1) dimensions in the presence of a constant magnetic field normal to the plane together with a two-dimensional Dirac-oscillator potential coupling. We study the energy spectrum of graphene quantum dot (QD) defined by electrostatic gates. We give discussions of our results based on different physical settings, whether the cyclotron frequency is similar or larger/smaller compared to the oscillator frequency. This defines an effective magnetic field that produces the effective quantized Landau levels. We study analytically such field in gate-tunable graphene QD and show that our structure allow us to control the valley degeneracy. Finally, we compare our results with already published work and also discuss the possible applications of such QD.

  13. Gate-Tunable Graphene Quantum Dot and Dirac Oscillator

    E-Print Network [OSTI]

    Belouad, Abdelhadi; Zahidi, Youness

    2015-01-01

    We obtain the solution of the Dirac equation in (2+1) dimensions in the presence of a constant magnetic field normal to the plane together with a two-dimensional Dirac-oscillator potential coupling. We study the energy spectrum of graphene quantum dot (QD) defined by electrostatic gates. We give discussions of our results based on different physical settings, whether the cyclotron frequency is similar or larger/smaller compared to the oscillator frequency. This defines an effective magnetic field that produces the effective quantized Landau levels. We study analytically such field in gate-tunable graphene QD and show that our structure allow us to control the valley degeneracy. Finally, we compare our results with already published work and also discuss the possible applications of such QD.

  14. High Fidelity Quantum Gates in the Presence of Dispersion

    E-Print Network [OSTI]

    Botan Khani; Seth T. Merkel; Felix Motzoi; Jay M. Gambetta; Frank K. Wilhelm

    2011-11-07

    We numerically demonstrate the control of motional degrees of freedom of an ensemble of neutral atoms in an optical lattice with a shallow trapping potential. Taking into account the range of quasimomenta across different Brillouin zones results in an ensemble whose members effectively have inhomogeneous control fields as well as spectrally distinct control Hamiltonians. We present an ensemble-averaged optimal control technique that yields high fidelity control pulses, irrespective of quasimomentum, with average fidelities above 98%. The resulting controls show a broadband spectrum with gate times in the order of several free oscillations to optimize gates with up to 13.2% dispersion in the energies from the band structure. This can be seen as a model system for the prospects of robust quantum control. This result explores the limits of discretizing a continuous ensemble for control theory.

  15. Quantum gate using qubit states separated by terahertz

    SciTech Connect (OSTI)

    Toyoda, Kenji; Urabe, Shinji [Graduate School of Engineering Science, Osaka University, 1-3 Machikaneyama, Toyonaka, Osaka 560-8531 (Japan); JST-CREST, 4-1-8 Honmachi, Kawaguchi, Saitama 331-0012 (Japan); Haze, Shinsuke [Graduate School of Engineering Science, Osaka University, 1-3 Machikaneyama, Toyonaka, Osaka 560-8531 (Japan); Yamazaki, Rekishu [JST-CREST, 4-1-8 Honmachi, Kawaguchi, Saitama 331-0012 (Japan)

    2010-03-15

    A two-qubit quantum gate is realized using electronically excited states in a single ion with an energy separation on the order of a terahertz times the Planck constant as a qubit. Two phase-locked lasers are used to excite a stimulated Raman transition between two metastable states D{sub 3/2} and D{sub 5/2} separated by 1.82 THz in a single trapped {sup 40}Ca{sup +} ion to construct a qubit, which is used as the target bit for the Cirac-Zoller two-qubit controlled NOT gate. Quantum dynamics conditioned on a motional qubit is clearly observed as a fringe reversal in Ramsey interferometry.

  16. Synthesis of Reversible Functions Beyond Gate Count and Quantum Cost

    E-Print Network [OSTI]

    Robert Wille; Mehdi Saeedi; Rolf Drechsler

    2010-04-26

    Many synthesis approaches for reversible and quantum logic have been proposed so far. However, most of them generate circuits with respect to simple metrics, i.e. gate count or quantum cost. On the other hand, to physically realize reversible and quantum hardware, additional constraints exist. In this paper, we describe cost metrics beyond gate count and quantum cost that should be considered while synthesizing reversible and quantum logic for the respective target technologies. We show that the evaluation of a synthesis approach may differ if additional costs are applied. In addition, a new cost metric, namely Nearest Neighbor Cost (NNC) which is imposed by realistic physical quantum architectures, is considered in detail. We discuss how existing synthesis flows can be extended to generate optimal circuits with respect to NNC while still keeping the quantum cost small.

  17. Apparatus for sensing patterns of electrical field variations across a surface

    DOE Patents [OSTI]

    Warren, William L. (Arlington, VA); Devine, Roderick A. B. (Paris, FR)

    2001-01-01

    An array of nonvolatile field effect transistors used to sense electric potential variations. The transistors owe their nonvolatility to the movement of protons within the oxide layer that occurs only in response to an externally applied electric potential between the gate on one side of the oxide and the source/drain on the other side. The position of the protons within the oxide layer either creates or destroys a conducting channel in the adjacent source/channel/drain layer below it, the current in the channel being measured as the state of the nonvolatile memory. The protons can also be moved by potentials created by other instrumentalities, such as charges on fingerprints or styluses above the gates, pressure on a piezoelectric layer above the gates, light shining upon a photoconductive layer above the gates. The invention allows sensing of fingerprints, handwriting, and optical images, which are converted into digitized images thereof in a nonvolatile format.

  18. Physical limits of the ballistic and nonballistic spin-field-effect transistor: Spin dynamics in remote-doped structures 

    E-Print Network [OSTI]

    Sherman, EY; Sinova, Jairo.

    2005-01-01

    spin-field-effect transistor in the diffusive regime possible. We demonstrate that the spin relaxation through the randomness of spin-orbit coupling imposes important physical limitations on the operational properties of these devices....

  19. Correlating stress generation and sheet resistance in InAlN/GaN nanoribbon high electron mobility transistors

    E-Print Network [OSTI]

    Azize, Mohamed

    We report the nanoscale characterization of the mechanical stress in InAlN/GaN nanoribbon-structured high electron mobility transistors (HEMTs) through the combined use of convergent beam electron diffraction (CBED) and ...

  20. Advanced technologies for improving high frequency performance of AlGaN/GaN high electron mobility transistors

    E-Print Network [OSTI]

    Chung, Jinwook W. (Jinwook Will)

    2008-01-01

    In this thesis, we have used a combination of physical analysis, numerical simulation and experimental work to identify and overcome some of the main challenges in AlGaN/GaN high electron mobility transistors (HEMTs) for ...

  1. High image quality sub 100 picosecond gated framing camera development

    SciTech Connect (OSTI)

    Price, R.H.; Wiedwald, J.D.

    1983-11-17

    A major challenge for laser fusion is the study of the symmetry and hydrodynamic stability of imploding fuel capsules. Framed x-radiographs of 10-100 ps duration, excellent image quality, minimum geometrical distortion (< 1%), dynamic range greater than 1000, and more than 200 x 200 pixels are required for this application. Recent progress on a gated proximity focused intensifier which meets these requirements is presented.

  2. GATE: Energy Efficient Vehicles for Sustainable Mobility | Department of

    Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

    AFDC Printable Version Share this resource Send a link to EERE: Alternative Fuels Data Center Home Page to someone by E-mail Share EERE: Alternative Fuels Data Center Home Page on Facebook Tweet about EERE: Alternative Fuels Data Center Home Page on Twitter Bookmark EERE: Alternative Fuels Data Center Home Page on Google Bookmark EERE: Alternative Fuels Data Center Home Page on Delicious Rank EERE:FinancingPetroleum12,Executive Compensation References: FAR 31.205-6Applications |Energy GATE:

  3. Single qubit gates in frequency-crowded transmon systems

    E-Print Network [OSTI]

    R. Schutjens; F. Abu Dagga; D. J. Egger; F. K. Wilhelm

    2013-06-10

    Recent experimental work on superconducting transmon qubits in 3D cavities show that their coherence times are increased by an order of magnitude compared to their 2D cavity counterparts. However to take advantage of these coherence times while scaling up the number of qubits it is advantageous to address individual qubits which are all coupled to the same 3D cavity fields. The challenge in controlling this system comes from spectral crowding, where leakage transition of qubits are close to computational transitions in other. Here it is shown that fast pulses are possible which address single qubits using two quadrature control of the pulse envelope while the DRAG method alone only gives marginal improvements over the conventional Gaussian pulse shape. On the other hand, a first order result using the Magnus expansion gives a fast analytical pulse shape which gives a high fidelity gate for a specific gate time, up to a phase factor on the second qubit. Further numerical analysis corroborates these results and yields to even faster gates, showing that leakage state anharmonicity does not provide a fundamental quantum speed limit.

  4. Growth and properties of crystalline barium oxide on the GaAs(100) substrate

    SciTech Connect (OSTI)

    Yasir, M.; Dahl, J.; Lång, J.; Tuominen, M.; Punkkinen, M. P. J.; Laukkanen, P., E-mail: pekka.laukkanen@utu.fi; Kokko, K. [Department of Physics and Astronomy, University of Turku, FI-20014 Turku (Finland)] [Department of Physics and Astronomy, University of Turku, FI-20014 Turku (Finland); Kuzmin, M. [Department of Physics and Astronomy, University of Turku, FI-20014 Turku (Finland) [Department of Physics and Astronomy, University of Turku, FI-20014 Turku (Finland); Ioffe Physical-Technical Institute, Russian Academy of Sciences, St. Petersburg 194021 (Russian Federation); Korpijärvi, V.-M.; Polojärvi, V.; Guina, M. [Optoelectronics Research Centre, Tampere University of Technology, FI-33101 Tampere (Finland)] [Optoelectronics Research Centre, Tampere University of Technology, FI-33101 Tampere (Finland)

    2013-11-04

    Growing a crystalline oxide film on III-V semiconductor renders possible approaches to improve operation of electronics and optoelectronics heterostructures such as oxide/semiconductor junctions for transistors and window layers for solar cells. We demonstrate the growth of crystalline barium oxide (BaO) on GaAs(100) at low temperatures, even down to room temperature. Photoluminescence (PL) measurements reveal that the amount of interface defects is reduced for BaO/GaAs, compared to Al{sub 2}O{sub 3}/GaAs, suggesting that BaO is a useful buffer layer to passivate the surface of the III-V device material. PL and photoemission data show that the produced junction tolerates the post heating around 600?°C.

  5. Enhancement of thermal stability and water resistance in yttrium-doped GeO{sub 2}/Ge gate stack

    SciTech Connect (OSTI)

    Lu, Cimang, E-mail: cimang@adam.t.u-tokyo.ac.jp; Hyun Lee, Choong; Zhang, Wenfeng; Nishimura, Tomonori; Nagashio, Kosuke; Toriumi, Akira [Department of Materials Engineering, The University of Tokyo, 7-3-1 Hongo, Tokyo 113-8656 (Japan); JST, CREST, 7-3-1 Hongo, Tokyo 113-8656 (Japan)

    2014-03-03

    We have systematically investigated the material and electrical properties of yttrium-doped GeO{sub 2} (Y-GeO{sub 2}) on Germanium (Ge). A significant improvement of both thermal stability and water resistance were demonstrated by Y-GeO{sub 2}/Ge stack, compared to that of pure GeO{sub 2}/Ge stack. The excellent electrical properties of Y-GeO{sub 2}/Ge stacks with low D{sub it} were presented as well as enhancement of dielectric constant in Y-GeO{sub 2} layer, which is beneficial for further equivalent oxide thickness scaling of Ge gate stack. The improvement of thermal stability and water resistance are discussed both in terms of the Gibbs free energy lowering and network modification of Y-GeO{sub 2}.

  6. Use of a hard mask for formation of gate and dielectric via nanofilament field emission devices

    DOE Patents [OSTI]

    Morse, Jeffrey D. (Martinez, CA); Contolini, Robert J. (Lake Oswego, OR)

    2001-01-01

    A process for fabricating a nanofilament field emission device in which a via in a dielectric layer is self-aligned to gate metal via structure located on top of the dielectric layer. By the use of a hard mask layer located on top of the gate metal layer, inert to the etch chemistry for the gate metal layer, and in which a via is formed by the pattern from etched nuclear tracks in a trackable material, a via is formed by the hard mask will eliminate any erosion of the gate metal layer during the dielectric via etch. Also, the hard mask layer will protect the gate metal layer while the gate structure is etched back from the edge of the dielectric via, if such is desired. This method provides more tolerance for the electroplating of a nanofilament in the dielectric via and sharpening of the nanofilament.

  7. Static ferroelectric memory transistor having improved data retention

    DOE Patents [OSTI]

    Evans, Jr., Joseph T. (13609 Verbena Pl., N.E., Albuquerque, NM 87112); Warren, William L. (7716 Wm. Moyers Ave., NE., Albuquerque, NM 87112); Tuttle, Bruce A. (12808 Lillian Pl., NE., Albuquerque, NM 87112)

    1996-01-01

    An improved ferroelectric FET structure in which the ferroelectric layer is doped to reduce retention loss. A ferroelectric FET according to the present invention includes a semiconductor layer having first and second contacts thereon, the first and second contacts being separated from one another. The ferroelectric FET also includes a bottom electrode and a ferroelectric layer which is sandwiched between the semiconductor layer and the bottom electrode. The ferroelectric layer is constructed from a perovskite structure of the chemical composition ABO.sub.3 wherein the B site comprises first and second elements and a dopant element that has an oxidation state greater than +4 in sufficient concentration to impede shifts in the resistance measured between the first and second contacts with time. The ferroelectric FET structure preferably comprises Pb in the A-site. The first and second elements are preferably Zr and Ti, respectively. The preferred B-site dopants are Niobium, Tantalum, and Tungsten at concentrations between 1% and 8%.

  8. Nanoporous carbon tunable resistor/transistor and methods of production thereof

    DOE Patents [OSTI]

    Biener, Juergen; Baumann, Theodore F; Dasgupta, Subho; Hahn, Horst

    2014-04-22

    In one embodiment, a tunable resistor/transistor includes a porous material that is electrically coupled between a source electrode and a drain electrode, wherein the porous material acts as an active channel, an electrolyte solution saturating the active channel, the electrolyte solution being adapted for altering an electrical resistance of the active channel based on an applied electrochemical potential, wherein the active channel comprises nanoporous carbon arranged in a three-dimensional structure. In another embodiment, a method for forming the tunable resistor/transistor includes forming a source electrode, forming a drain electrode, and forming a monolithic nanoporous carbon material that acts as an active channel and selectively couples the source electrode to the drain electrode electrically. In any embodiment, the electrolyte solution saturating the nanoporous carbon active channel is adapted for altering an electrical resistance of the nanoporous carbon active channel based on an applied electrochemical potential.

  9. A Quantum Optomechanical Transistor Based on a Cavity-Optomechanical System

    E-Print Network [OSTI]

    Jin-Jin Li; Wei-He; Ka-Di Zhu

    2015-08-22

    We theoretically propose a scheme to realize an all-optically controlled quantum optomechanical transistor based on a cavity-optomechanical system, where the cavity photons interfere with the input signal photons while the pump field controls the transmission spectrum of the signal laser. Theoretical analysis shows such a quantum optomechanical transistor can be switched on or off by turning on or off the pump laser, which corresponds to amplification or attenuation of the signal laser, respectively. The results further demonstrate that the output signal gain is enhanced abruptly with increasing the input pump power. The scheme proposed here will pave the way towards many important applications such as all-optical logic circuits and quantum repeaters.

  10. Universal Gates via Fusion and Measurement Operations on SU$(2)_4$ Anyons

    E-Print Network [OSTI]

    Claire Levaillant; Bela Bauer; Michael Freedman; Zhenghan Wang; Parsa Bonderson

    2015-07-01

    We examine a class of operations for topological quantum computation based on fusing and measuring topological charges for systems with SU$(2)_4$ or $k=4$ Jones-Kauffman anyons. We show that such operations augment the braiding operations, which, by themselves, are not computationally universal. This augmentation results in a computationally universal gate set through the generation of an exact, topologically protected irrational phase gate and an approximate, topologically protected controlled-$Z$ gate.

  11. A simple trapped-ion architecture for high-fidelity Toffoli gates

    E-Print Network [OSTI]

    Massimo Borrelli; Laura Mazzola; Mauro Paternostro; Sabrina Maniscalco

    2010-12-08

    We discuss a simple architecture for a quantum Toffoli gate implemented using three trapped ions. The gate, which in principle can be implemented with a single laser-induced operation, is effective under rather general conditions and is strikingly robust (within any experimentally realistic range of values) against dephasing, heating and random fluctuations of the Hamiltonian parameters. We provide a full characterization of the unitary and noise-affected gate using three-qubit quantum process tomography.

  12. III-V Multigate Non-Planar Channel Transistor Simulations and Technologies

    E-Print Network [OSTI]

    Shih, Kun-Huan

    2012-01-01

    MOG Metal-oxide-graphene MESFET Metal-semiconductor field-Multilayer graphene MOSFET Metal-oxide-semiconductor field-contact the semiconductor (or zero bandgap graphene semi-

  13. Application of the FETMOS transistor as a quasi-analog storage element 

    E-Print Network [OSTI]

    Sweeney, John Hillabrant

    1989-01-01

    Cell. . . . . First Order Model of FETMOS Transistor Capacitances. . . . . Experimental Setup for Charge Accumulation Experiments . . Read Current vs Prog. Pulses for Pulse Height Variation (FETMOS A) . . Threshold Voltage vs Prog. Pulses for Pulse... Height Variation (FETMOS A) . . . . . . 17 . 21 . 21 3. 3a Read Current vs Prog. Pulses for Pulse Height Variation (FETMOS B). . 22 3, 3b 3. 4 3 . 5 3. 6a 3. 6b 3. 7a 3. 7b Threshold Voltage vs Pmg. Pulses for Pulse Height Variation (FETMOS...

  14. Thin film transistors on plastic substrates with reflective coatings for radiation protection

    DOE Patents [OSTI]

    Wolfe, Jesse D.; Theiss, Steven D.; Carey, Paul G.; Smith, Patrick M.; Wickboldt, Paul

    2003-11-04

    Fabrication of silicon thin film transistors (TFT) on low-temperature plastic substrates using a reflective coating so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The TFT can be used in large area low cost electronics, such as flat panel displays and portable electronics such as video cameras, personal digital assistants, and cell phones.

  15. Thin film transistors on plastic substrates with reflective coatings for radiation protection

    DOE Patents [OSTI]

    Wolfe, Jesse D. (Fairfield, CA); Theiss, Steven D. (Woodbury, MN); Carey, Paul G. (Mountain View, CA); Smith, Patrick M. (San Ramon, CA); Wickbold, Paul (Walnut Creek, CA)

    2006-09-26

    Fabrication of silicon thin film transistors (TFT) on low-temperature plastic substrates using a reflective coating so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The TFT can be used in large area low cost electronics, such as flat panel displays and portable electronics such as video cameras, personal digital assistants, and cell phones.

  16. Modulation and amplification of radiative far field heat transfer : towards a simple radiative thermal transistor

    E-Print Network [OSTI]

    Joulain, Karl; Drevillon, Jeremie; Ben-Abdallah, Philippe

    2015-01-01

    We show in this article that phase change materials (PCM) exhibiting a phase transition between a dielectric state and a metallic state are good candidates to perform modulation as well as amplification of radiative thermal flux. We propose a simple situation in plane parallel geometry where a so-called radiative thermal transistor could be achieved. In this configuration, we put a PCM between two blackbodies at different temperatures. We show that the transistor effect can be achieved easily when this material has its critical temperature between the two blackbody temperatures. We also see, that the more the material is reflective in the metallic state, the more switching effect is realized whereas the more PCM transition is stiff in temperature, the more thermal amplification is high. We finally take the example of VO2 that exhibits an insulator-metallic transition at 68{\\textdegree}C. We show that a demonstrator of a radiative transistor could easily be achieved in view of the heat flux levels predicted. F...

  17. Electronic system for data acquisition to study radiation effects on operating MOSFET transistors

    SciTech Connect (OSTI)

    Alves de Oliveira, Juliano; Assis de Melo, Marco Antônio; Guazzelli da Silveira, Marcilei A.; Medina, Nilberto H.

    2014-11-11

    In this work we present the development of an acquisition system for characterizing transistors under X-ray radiation. The system is able to carry out the acquisition and to storage characteristic transistor curves. To test the acquisition system we have submitted polarized P channel MOS transistors under continuous 10-keV X-ray doses up to 1500 krad. The characterization system can operate in the saturation region or in the linear region in order to observe the behavior of the currents or voltages involved during the irradiation process. Initial tests consisted of placing the device under test (DUT) in front of the X-ray beam direction, while its drain current was constantly monitored through the prototype generated in this work, the data are stored continuously and system behavior was monitored during the test. In order to observe the behavior of the DUT during the radiation tests, we used an acquisition system that consists of an ultra-low consumption16-bit Texas Instruments MSP430 microprocessor. Preliminary results indicate linear behavior of the voltage as a function of the exposure time and fast recovery. These features may be favorable to use this device as a radiation dosimeter to monitor low rate X-ray.

  18. Use of high-level design information for enabling automation of fine-grained power gating

    E-Print Network [OSTI]

    Agarwal, Abhinav

    2014-01-01

    Leakage power reduction through power gating requires considerable design and verification effort. Conventionally, extensive analysis is required for dividing a heterogeneous design into power domains and generating control ...

  19. How to Successfully Implement a Knowledge Management System for the Mechanical Engineering Department at Gating Incorporated

    E-Print Network [OSTI]

    Mudd, John

    2009-05-15

    , utilizing some of the strategies, for the implementation of a Knowledge Management System for the Mechanical Engineering Department at Gating Incorporated....

  20. A Surprising Clarification of the Mechanism of Ion-channel Voltage-Gating

    E-Print Network [OSTI]

    Ashok Palaniappan

    2011-04-20

    An intense controversy has surrounded the mechanism of voltage-gating in ion channels. We interpreted the two leading models of voltage-gating with respect to the thermodynamic energetics of membrane insertion of the voltage-sensing 'module' from a comprehensive set of potassium channels. KvAP is an archaeal voltage-gated potassium channel whose x-ray structure was the basis for determining the general mechanism of voltage-gating. The free energy of membrane insertion of the KvAP voltage sensor was revealed to be a single outlier. This was due to its unusual sequence that facilitated large gating movements in its native lipid membrane. This degree of free energy was the least typical of the other voltage sensors, including the Shaker potassium channel. We inferred that the two leading models of voltage-gating referred to alternative mechanisms of voltage-gating: each is applicable to an independent set of ion channels. The large motion of the voltage-sensor during gating proposed by the KvAP-paddle model of gating is unlikely to be mirrored by the majority of ion channels whose voltage sensors are not located at the membrane-cytoplasm interface in the channel closed state.

  1. Sandia Energy - ECIS and i-GATE: Innovation Hub Connects Clean...

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    support system to accelerate the commercialization of innovative technologies related to green transportation and clean energy. There are now eight i-GATE clients developing fuel...

  2. Low Power 8T SRAM Using 32nm Independent Gate FinFET Young Bok Kim

    E-Print Network [OSTI]

    Ayers, Joseph

    by the process, but also it can be controlled by the back gate voltage (VGb). This is similar to the body effect

  3. Implementing a neutral-atom controlled-phase gate with a single Rydberg pulse

    E-Print Network [OSTI]

    Rui Han; Hui Khoon Ng; Berthold-Georg Englert

    2014-09-04

    One can implement fast two-qubit entangling gates by exploiting the Rydberg blockade. Although various theoretical schemes have been proposed, experimenters have not yet been able to demonstrate two-atom gates of high fidelity due to experimental constraints. We propose a novel scheme, which only uses a single Rydberg pulse, for the construction of neutral-atom controlled-phase gates. In contrast to the existing schemes, our scheme is simpler to implement and requires neither individual addressing of atoms nor adiabatic procedures. With realistically estimated experimental parameters, a gate fidelity higher than 0.99 is achievable.

  4. Bill Gates and Deputy Secretary Poneman Discuss the Energy Technology Landscape

    Office of Energy Efficiency and Renewable Energy (EERE)

    Bill Gates and Deputy Secretary of Energy Daniel Poneman discuss the future of energy technology during the twenty-second Plenary Meeting of the Nuclear Suppliers Group.

  5. Local implementations of non-local quantum gates in linear entangled channel

    E-Print Network [OSTI]

    Debashis Saha; Sanket Nandan; Prasanta K. Panigrahi

    2014-08-03

    In this paper, we demonstrate n-party controlled unitary gate implementations locally on arbitrary remote state through linear entangled channel where control parties share entanglement with the adjacent control parties and only one of them shares entanglement with the target party. In such a network, we describe the protocol of simultaneous implementation of controlled-Hermitian gate starting from three party scenario. We also explicate the implementation of three party controlled-Unitary gate, a generalized form of To?oli gate and subsequently generalize the protocol for n-party using minimal cost.

  6. Photo-oxidation catalysts

    DOE Patents [OSTI]

    Pitts, J. Roland (Lakewood, CO); Liu, Ping (Irvine, CA); Smith, R. Davis (Golden, CO)

    2009-07-14

    Photo-oxidation catalysts and methods for cleaning a metal-based catalyst are disclosed. An exemplary catalyst system implementing a photo-oxidation catalyst may comprise a metal-based catalyst, and a photo-oxidation catalyst for cleaning the metal-based catalyst in the presence of light. The exposure to light enables the photo-oxidation catalyst to substantially oxidize absorbed contaminants and reduce accumulation of the contaminants on the metal-based catalyst. Applications are also disclosed.

  7. Nonadiabatic molecular orientation by polarization-gated ultrashort laser pulses

    SciTech Connect (OSTI)

    Chen Cheng; Wu Jian; Zeng Heping [State Key Laboratory of Precision Spectroscopy, East China Normal University, Shanghai 200062 (China)

    2010-09-15

    We show that the nonadiabatic orientation of diatomic polar molecules can be controlled by polarization-gated ultrashort laser pulses. By finely adjusting the time interval between two circularly polarized pulses of different wavelengths but the same helicity, the orientation direction of the molecules can be twirled. A cloverlike potential is created by using two circularly polarized laser pulses of different wavelengths and opposite helicity, leading to multidirectional molecular orientation along the potential wells, which can be well revealed by a high-order statistics metric of <>.

  8. Gates County, North Carolina: Energy Resources | Open Energy Information

    Open Energy Info (EERE)

    AFDC Printable Version Share this resource Send a link to EERE: Alternative Fuels Data Center Home Page to someone by E-mail Share EERE: Alternative Fuels Data Center Home Page on Facebook Tweet about EERE: Alternative Fuels Data Center Home Page on Twitter Bookmark EERE: Alternative Fuels Data Center Home Page on Google Bookmark EERE: Alternative Fuels Data Center Home Page on QA:QAsource History View New PagesSustainable UrbanKentucky: Energy ResourcesMaui Area (DOEMaui AreaGastonGates County,

  9. Gates Mills, Ohio: Energy Resources | Open Energy Information

    Open Energy Info (EERE)

    AFDC Printable Version Share this resource Send a link to EERE: Alternative Fuels Data Center Home Page to someone by E-mail Share EERE: Alternative Fuels Data Center Home Page on Facebook Tweet about EERE: Alternative Fuels Data Center Home Page on Twitter Bookmark EERE: Alternative Fuels Data Center Home Page on Google Bookmark EERE: Alternative Fuels Data Center Home Page on QA:QAsource History View New PagesSustainable UrbanKentucky: Energy ResourcesMaui Area (DOEMaui AreaGastonGates

  10. Gate Hours & Services | Stanford Synchrotron Radiation Lightsource

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    AFDC Printable Version Share this resource Send a link to EERE: Alternative Fuels Data Center Home Page to someone by E-mail Share EERE: Alternative Fuels Data Center Home Page on Facebook Tweet about EERE: Alternative Fuels Data Center Home Page on Twitter Bookmark EERE: Alternative Fuels Data Center Homesum_a_epg0_fpd_mmcf_m.xls" ,"Available from WebQuantity ofkandz-cm11 Outreach Home Room NewsInformation Current HABFESOpportunities Nuclearlong version)shortGate Hours & Services

  11. Phase Discrimination through Oxidant Selection for Iron Oxide...

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Phase Discrimination through Oxidant Selection for Iron Oxide Ultrathin Films Home > Research > ANSER Research Highlights > Phase Discrimination through Oxidant Selection for Iron...

  12. Cerium Oxide Coating for Oxidation Reduction

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Award In order to produce power more efficiently and cleanly, the next generation of power plant boilers, turbines, solid oxide fuel cells (SOFCs) and other essential equipment...

  13. SU-E-J-45: Design and Study of An In-House Respiratory Gating Phantom Platform for Gated Radiotherapy

    SciTech Connect (OSTI)

    Senthilkumar, S

    2014-06-01

    Purpose: The main purpose of this work was to develop an in-house low cost respiratory motion phantom platform for testing the accuracy of the gated radiotherapy system and analyze the dosimetric difference during gated radiotherapy. Methods: An in-house respiratory motion platform(RMP) was designed and constructed for testing the targeting accuracy of respiratory tracking system. The RMP consist of acrylic Chest Wall Platform, 2 DC motors, 4 IR sensors, speed controller circuit, 2 LED and 2 moving rods inside the RMP. The velocity of the movement can be varied from 0 to 30 cycles per minute. The platform mounted to a base using precision linear bearings. The base and platform are made of clear, 15mm thick polycarbonate plastic and the linear ball bearings are oriented to restrict the platform to a movement of approximately 50mm up and down with very little friction. Results: The targeting accuracy of the respiratory tracking system was evaluated using phantom with and without respiratory movement with varied amplitude. We have found the 5% dose difference to the PTV during the movement in comparison with stable PTV. The RMP can perform sinusoidal motion in 1D with fixed peak to peak motion of 5 to 50mm and cycle interval from 2 to 6 seconds. The RMP was designed to be able to simulate the gross anatomical anterior posterior motion attributable to respiration-induced motion of the thoracic region. Conclusion: The unique RMP simulates breathing providing the means to create a comprehensive program for commissioning, training, quality assurance and dose verification of gated radiotherapy treatments. Create the anterior/posterior movement of a target over a 5 to 50 mm distance to replicate tumor movement. The targeting error of the respiratory tracking system is less than 1.0 mm which shows suitable for clinical treatment with highly performance.

  14. Integration of reduced graphene oxide into organic field-effect transistors as conducting electrodes and as a metal modification layer

    E-Print Network [OSTI]

    a patterned sample into a HRG colloidal suspension. The solvent for this HRG suspen- sion is a mixture of DMF-area, and flexible electronic applications. The perfor- mance and stability of OFETs critically depends

  15. Performance analysis of boron nitride embedded armchair graphene nanoribbon metal–oxide–semiconductor field effect transistor with Stone Wales defects

    SciTech Connect (OSTI)

    Chanana, Anuja; Sengupta, Amretashis; Mahapatra, Santanu

    2014-01-21

    We study the performance of a hybrid Graphene-Boron Nitride armchair nanoribbon (a-GNR-BN) n-MOSFET at its ballistic transport limit. We consider three geometric configurations 3p, 3p + 1, and 3p + 2 of a-GNR-BN with BN atoms embedded on either side (2, 4, and 6 BN) on the GNR. Material properties like band gap, effective mass, and density of states of these H-passivated structures are evaluated using the Density Functional Theory. Using these material parameters, self-consistent Poisson-Schrodinger simulations are carried out under the Non Equilibrium Green's Function formalism to calculate the ballistic n-MOSFET device characteristics. For a hybrid nanoribbon of width ?5?nm, the simulated ON current is found to be in the range of 265??A–280??A with an ON/OFF ratio 7.1 × 10{sup 6}–7.4 × 10{sup 6} for a V{sub DD}?=?0.68?V corresponding to 10?nm technology node. We further study the impact of randomly distributed Stone Wales (SW) defects in these hybrid structures and only 2.5% degradation of ON current is observed for SW defect density of 3.18%.

  16. Investigation of hole mobility in gate-all-around Si nanowire p-MOSFETs with high-k/metal-gate: Effects of hydrogen thermal annealing and nanowire shape

    E-Print Network [OSTI]

    Hashemi, Pouya

    A detailed study of hole mobility is presented for gate-all-around Si nanowire p-MOSFETs with conformal high-?/MG and various high-temperature hydrogen annealing processes. Hole mobility enhancement relative to planar SOI ...

  17. Sodium channel activation mechanisms. Insights from deuterium oxide substitution

    SciTech Connect (OSTI)

    Alicata, D.A.; Rayner, M.D.; Starkus, J.G. )

    1990-04-01

    Schauf and Bullock, using Myxicola giant axons, demonstrated that solvent substitution with deuterium oxide (D2O) significantly affects both sodium channel activation and inactivation kinetics without corresponding changes in gating current or tail current rates. They concluded that (a) no significant component of gating current derives from the final channel opening step, and (b) channels must deactivate (during tail currents) by a different pathway from that used in channel opening. By contrast, Oxford found in squid axons that when a depolarizing pulse is interrupted by a brief (approximately 100 microseconds) return to holding potential, subsequent reactivation (secondary activation) is very rapid and shows almost monoexponential kinetics. Increasing the interpulse interval resulted in secondary activation rate returning towards control, sigmoid (primary activation) kinetics. He concluded that channels open and close (deactivate) via the same pathway. We have repeated both sets of observations in crayfish axons, confirming the results obtained in both previous studies, despite the apparently contradictory conclusions reached by these authors. On the other hand, we find that secondary activation after a brief interpulse interval (50 microseconds) is insensitive to D2O, although reactivation after longer interpulse intervals (approximately 400 microseconds) returns towards a D2O sensitivity similar to that of primary activation. We conclude that D2O-sensitive primary activation and D2O-insensitive tail current deactivation involve separate pathways. However, D2O-insensitive secondary activation involves reversal of the D2O-insensitive deactivation step. These conclusions are consistent with parallel gate models, provided that one gating particle has a substantially reduced effective valence.

  18. Workshop on gate valve pressure locking and thermal binding

    SciTech Connect (OSTI)

    Brown, E.J.

    1995-07-01

    The purpose of the Workshop on Gate Valve Pressure Locking and Thermal Binding was to discuss pressure locking and thermal binding issues that could lead to inoperable gate valves in both boiling water and pressurized water reactors. The goal was to foster exchange of information to develop the technical bases to understand the phenomena, identify the components that are susceptible, discuss actual events, discuss the safety significance, and illustrate known corrective actions that can prevent or limit the occurrence of pressure locking or thermal binding. The presentations were structured to cover U.S. Nuclear Regulatory Commission staff evaluation of operating experience and planned regulatory activity; industry discussions of specific events, including foreign experience, and efforts to determine causes and alleviate the affects; and valve vendor experience and recommended corrective action. The discussions indicated that identifying valves susceptible to pressure locking and thermal binding was a complex process involving knowledge of components, systems, and plant operations. The corrective action options are varied and straightforward.

  19. Low-frequency 1/f noise in MoS{sub 2} transistors: Relative contributions of the channel and contacts

    SciTech Connect (OSTI)

    Renteria, J.; Jiang, C.; Samnakay, R.; Rumyantsev, S. L.; Goli, P.; Balandin, A. A.; Shur, M. S.

    2014-04-14

    We report on the results of the low-frequency (1/f, where f is frequency) noise measurements in MoS{sub 2} field-effect transistors revealing the relative contributions of the MoS{sub 2} channel and Ti/Au contacts to the overall noise level. The investigation of the 1/f noise was performed for both as fabricated and aged transistors. It was established that the McWhorter model of the carrier number fluctuations describes well the 1/f noise in MoS{sub 2} transistors, in contrast to what is observed in graphene devices. The trap densities extracted from the 1/f noise data for MoS{sub 2} transistors, are 2?×?10{sup 19}?eV{sup ?1}cm{sup ?3} and 2.5?×?10{sup 20}?eV{sup ?1}cm{sup ?3} for the as fabricated and aged devices, respectively. It was found that the increase in the noise level of the aged MoS{sub 2} transistors is due to the channel rather than the contact degradation. The obtained results are important for the proposed electronic applications of MoS{sub 2} and other van der Waals materials.

  20. Constructing Quantum Logic Gates Using q-Deformed Harmonic Oscillator Algebras

    E-Print Network [OSTI]

    Azmi Ali Altintas; Fatih Ozaydin; Can Yesilyurt; Sinan Bugu; Metin Arik

    2015-04-23

    We study two-level q-deformed angular momentum states and us- ing q-deformed harmonic oscillators, we provide a framework for con- structing qubits and quantum gates. We also present the construction of some basic quantum gates including CNOT, SWAP, Toffoli and Fredkin.

  1. Z-Gate Operation on a Superconducting Flux Qubit via Its Readout SQUID

    E-Print Network [OSTI]

    Jin, X.?Y.

    Detuning a superconducting qubit from its rotating frame is one means to implement a Z-gate operation. In this work, we implement a Z gate by pulsing a current through the qubit’s readout dc SQUID. While the dc SQUID acts ...

  2. Gating Currents from Kv7 Channels Carrying Neuronal Hyperexcitability Mutations in the Voltage-Sensing Domain

    E-Print Network [OSTI]

    Bezanilla, Francisco

    unable to provide a detailed assessment of the structural rearrangements underlying channel gating.2 channels both functionally and structurally, were used for these experiments. The data obtained showed activation of gating-pore currents at depolarized potentials. These results reveal that distinct molecular

  3. THE SMALL SIGNAL AMPLIFICATION OF THE GATED DIODE OPERATED IN BREAKDOWN REGIME

    E-Print Network [OSTI]

    capacitance of approximately 4pF. Figure 1 - Cross section of the gated diode. The device was fabricated impedance given by the pn junction avalanche regime. The cross section of the utilized device is presented and the area of the gate gives a capacitance of approximately 4pF. 2. DC Measurements In order to set the bias

  4. [ ]February 2014 The original 1957 Gates pile driving formula is an empirically derived dynamic formula

    E-Print Network [OSTI]

    Harms, Kyle E.

    [ ]February 2014 PROBLEM The original 1957 Gates pile driving formula is an empirically derived dynamic formula that is used to predict pile capacity in the field during pile installation.The original Gates formula tends to over-predict pile capacity for low driving resistances and under-predict pile

  5. Fig. 1. Schematic of gating operation driven by centrifugal force. (a) shows top view of the

    E-Print Network [OSTI]

    Banerjee, Debjyoti

    R1 R2 (a) Pm (b) Fig. 1. Schematic of gating operation driven by centrifugal force. (a) shows top-expanding opening. Liquid pressure at the meniscus is Pm. DESIGN ANALYSES OF CAPILLARY BURST VALVES IN CENTRIFUGAL, Capillary Gating, Centrifugal force, FlumeCAD I. Introduction There is a wide interest in micron

  6. Quantum Process Tomography of a Universal Entangling Gate Implemented with Josephson Phase Qubits

    E-Print Network [OSTI]

    Martinis, John M.

    . Experiments using superconducting qubits have validated the truth table for particular implementations of e the performance of a universal entangling gate between two superconducting quantum bits. Process tomography . The SQiSW is a "natural" two-qubit gate as it directly results from capacitive coupling of superconducting

  7. Logic gates at the surface code threshold: Superconducting qubits poised for fault-tolerant quantum computing

    E-Print Network [OSTI]

    Martinis, John M.

    Logic gates at the surface code threshold: Superconducting qubits poised for fault-tolerant quantum circuits, and is compatible with microfabrication. For superconducting qubits the surface code7 99%. Here, we demonstrate a universal set of logic gates in a superconducting multi-qubit processor

  8. Microfluidic logic gates and timers{ Michael W. Toepke, Vinay V. Abhyankar and David J. Beebe*

    E-Print Network [OSTI]

    Beebe, David J.

    Microfluidic logic gates and timers{ Michael W. Toepke, Vinay V. Abhyankar and David J. Beebe to create a number of microfluidic analogs to electronic circuit components. Three classes of components are demonstrated: (1) OR/AND, NOR/NAND, and XNOR digital microfluidic logic gates; (2) programmable, autonomous

  9. Gated frequency-resolved optical imaging with an optical parametric amplifier

    DOE Patents [OSTI]

    Cameron, Stewart M. (Albuquerque, NM); Bliss, David E. (Tijeras, NM); Kimmel, Mark W. (Edgewood, NM); Neal, Daniel R. (Tijeras, NM)

    1999-01-01

    A system for detecting objects in a turbid media utilizes an optical parametric amplifier as an amplifying gate for received light from the media. An optical gating pulse from a second parametric amplifier permits the system to respond to and amplify only ballistic photons from the object in the media.

  10. Gated frequency-resolved optical imaging with an optical parametric amplifier

    DOE Patents [OSTI]

    Cameron, S.M.; Bliss, D.E.; Kimmel, M.W.; Neal, D.R.

    1999-08-10

    A system for detecting objects in a turbid media utilizes an optical parametric amplifier as an amplifying gate for received light from the media. An optical gating pulse from a second parametric amplifier permits the system to respond to and amplify only ballistic photons from the object in the media. 13 figs.

  11. STANDARD OPERATING PROCEDURE FOR TUBE "A1-GateOx" furnace in TRL.

    E-Print Network [OSTI]

    Reif, Rafael

    STANDARD OPERATING PROCEDURE FOR TUBE "A1-GateOx" furnace in TRL. INTRODUCTION Tube "A1-Gate. Three Eurotherm temperature controllers provide a 20 inch long, flat profile in the Center Zone the special heat resistant gloves to handle those parts PROCEDURE. 1) "ENGAGE" the machine in CORAL for TRL

  12. Integrated Results for Dual Low Voltage IC Based High and Low Side Gate Drive

    E-Print Network [OSTI]

    , electronicballast I. INTRODUCTION High and low side gate drivers are required in most switching power converters Zane Colorado Power Electronics Center (CoPEC) Department of Electrical and Computer Engineering, UCB design for high and low side gate drive is presented based on use of two identical low voltage ICs

  13. Fig. 1: (a) Tuning fork resonator with two electromechanical transistors on the outer tips of the nano-resonator, i.e. boxed region on the left.

    E-Print Network [OSTI]

    Ludwig-Maximilians-Universität, München

    Fig. 1: (a) Tuning fork resonator with two electromechanical transistors on the outer tips of the transistor: evaporated gold contacts on single crytalline silicon (purple) with spring constants k+/- . Nano-Electromechanical as a phase sensitive bi-polar current switch. Index Terms -- Nanotechnology, nano-electromechanical systems

  14. High Mobility WSe2 p-and n-Type Field-Effect Transistors Contacted by Highly Doped Graphene for Low-Resistance Contacts

    E-Print Network [OSTI]

    Tománek, David

    -resistance ohmic contacts to a wide range of quasi-2D semiconductors. KEYWORDS: MoS2, WSe2, field-effect transistor channel effects.2 In addition, pristine surfaces of two- dimensional (2D) TMDs are free of dangling bondsHigh Mobility WSe2 p- and n-Type Field-Effect Transistors Contacted by Highly Doped Graphene

  15. Piezoelectric Field Effect Transistor and Nanoforce Sensor Based on a Single

    E-Print Network [OSTI]

    Wang, Zhong L.

    across two Ohmic contacts, in which the source to drain current is controlled by the bending of the NW. An almost linear relationship between the bending force and the conductance was found at small bending In this paper, we report an alternative design of a NW FET without using the gate electrode. With connection

  16. Molecular and quantum dot floating gate non-volatile memories

    E-Print Network [OSTI]

    Abdu, Hassen

    2008-01-01

    Conventional Flash memory devices face a scaling issue that will impede memory scaling beyond the 50nm node: a reliability issue involving the tunneling oxide thickness and charge retention. A possible solution is to replace ...

  17. Room-temperature Si single-electron memory fabricated by nanoimprint lithography

    E-Print Network [OSTI]

    , Haixiong Ge, Christopher Keimel, and Stephen Y. Chou NanoStructure Laboratory, Department of Electrical using nanoimprint lithography NIL . The devices consist of a narrow channel metal­ oxide­semiconductor field-effect transistor and a sub-10-nm storage dot, which is located between the channel and the gate

  18. Glitch Power Minimization by Gate Freezing L. Benini3 G. De Micheli A. Maciiz E. Maciiz M. Poncinoz R. Scarsiz

    E-Print Network [OSTI]

    De Micheli, Giovanni

    Glitch Power Minimization by Gate Freezing L. Benini3 G. De Micheli A. Maciiz E. Maciiz M freezing idea we present in this paper. Di erently from gate freezing, the techniques above are applied before placement and routing. We have applied the gate freezing procedure to the Iscas'85 benchmarks 2

  19. Quantum-correlated photon pairs generated in a commercial 45nm complementary metal-oxide semiconductor microelectronics chip

    E-Print Network [OSTI]

    Cale M. Gentry; Jeffrey M. Shainline; Mark T. Wade; Martin J. Stevens; Shellee D. Dyer; Xiaoge Zeng; Fabio Pavanello; Thomas Gerrits; Sae Woo Nam; Richard P. Mirin; Miloš A. Popovi?

    2015-07-24

    Correlated photon pairs are a fundamental building block of quantum photonic systems. While pair sources have previously been integrated on silicon chips built using customized photonics manufacturing processes, these often take advantage of only a small fraction of the established techniques for microelectronics fabrication and have yet to be integrated in a process which also supports electronics. Here we report the first demonstration of quantum-correlated photon pair generation in a device fabricated in an unmodified advanced (sub-100nm) complementary metal-oxide-semiconductor (CMOS) process, alongside millions of working transistors. The microring resonator photon pair source is formed in the transistor layer structure, with the resonator core formed by the silicon layer typically used for the transistor body. With ultra-low continuous-wave on-chip pump powers ranging from 5 $\\mu$W to 400 $\\mu$W, we demonstrate pair generation rates between 165 Hz and 332 kHz using >80% efficient WSi superconducting nanowire single photon detectors. Coincidences-to-accidentals ratios consistently exceeding 40 were measured with a maximum of 55. In the process of characterizing this source we also accurately predict pair generation rates from the results of classical four-wave mixing measurements. This proof-of-principle device demonstrates the potential of commercial CMOS microelectronics as an advanced quantum photonics platform with capability of large volume, pristine process control, and where state-of-the-art high-speed digital circuits could interact with quantum photonic circuits.

  20. A Graphene Quantum Dot with a Single Electron Transistor as Integrated Charge Sensor

    E-Print Network [OSTI]

    Ling-Jun Wang; Gang Cao; Tao Tu; Hai-Ou Li; Cheng Zhou; Xiao-Jie Hao; Zhan Su; Guang-Can Guo; Guo-Ping Guo; Hong-Wen Jiang

    2010-08-28

    We have developed an etching process to fabricate a quantum dot and a nearby single electron transistor as a charge detector in a single layer graphene. The high charge sensitivity of the detector is used to probe Coulomb diamonds as well as excited spectrum in the dot, even in the regime where the current through the quantum dot is too small to be measured by conventional transport means. The graphene based quantum dot and integrated charge sensor serve as an essential building block to form a solid-state qubit in a nuclear-spin-free quantum world.

  1. Coulomb Oscillations of Indium-doped ZnO Nanowire Transistors in a Magnetic Field

    E-Print Network [OSTI]

    Xiulai Xu; Andrew C. Irvine; Yang Yang; Xitian Zhang; David A. Williams

    2010-11-05

    We report on the observation of Coulomb oscillations from localized quantum dots superimposed on the normal hopping current in ZnO nanowire transistors. The Coulomb oscillations can be resolved up to 20 K. Positive anisotropic magnetoresistance has been observed due to the Lorentz force on the carrier motion. Magnetic field-induced tunneling barrier transparency results in an increase of oscillation amplitude with increasing magnetic field. The energy shift as a function of magnetic field indicates electron wavefunction modification in the quantum dots.

  2. Negative differential resistance in GaN tunneling hot electron transistors

    SciTech Connect (OSTI)

    Yang, Zhichao; Nath, Digbijoy; Rajan, Siddharth

    2014-11-17

    Room temperature negative differential resistance is demonstrated in a unipolar GaN-based tunneling hot electron transistor. Such a device employs tunnel-injected electrons to vary the electron energy and change the fraction of reflected electrons, and shows repeatable negative differential resistance with a peak to valley current ratio of 7.2. The device was stable when biased in the negative resistance regime and tunable by changing collector bias. Good repeatability and double-sweep characteristics at room temperature show the potential of such device for high frequency oscillators based on quasi-ballistic transport.

  3. Total dose and dose rate models for bipolar transistors in circuit simulation.

    SciTech Connect (OSTI)

    Campbell, Phillip Montgomery; Wix, Steven D.

    2013-05-01

    The objective of this work is to develop a model for total dose effects in bipolar junction transistors for use in circuit simulation. The components of the model are an electrical model of device performance that includes the effects of trapped charge on device behavior, and a model that calculates the trapped charge densities in a specific device structure as a function of radiation dose and dose rate. Simulations based on this model are found to agree well with measurements on a number of devices for which data are available.

  4. Impact of graphene polycrystallinity on the performance of graphene field-effect transistors

    SciTech Connect (OSTI)

    Jiménez, David; Chaves, Ferney [Departament d'Enginyeria Electrònica, Escola d'Enginyeria, Universitat Autònoma de Barcelona, 08193-Bellaterra (Spain); Cummings, Aron W.; Van Tuan, Dinh [ICN2, Institut Català de Nanociencia i Nanotecnologia, Campus UAB, 08193 Bellaterra (Barcelona) (Spain); Kotakoski, Jani [Faculty of Physics, University of Vienna, Boltzmanngasse 5, 1090 Wien (Austria); Department of Physics, University of Helsinki, P.O. Box 43, 00014 University of Helsinki (Finland); Roche, Stephan [ICN2, Institut Català de Nanociencia i Nanotecnologia, Campus UAB, 08193 Bellaterra (Barcelona) (Spain); ICREA, Institució Catalana de Recerca i Estudis Avançats, 08070 Barcelona (Spain)

    2014-01-27

    We have used a multi-scale physics-based model to predict how the grain size and different grain boundary morphologies of polycrystalline graphene will impact the performance metrics of graphene field-effect transistors. We show that polycrystallinity has a negative impact on the transconductance, which translates to a severe degradation of the maximum and cutoff frequencies. On the other hand, polycrystallinity has a positive impact on current saturation, and a negligible effect on the intrinsic gain. These results reveal the complex role played by graphene grain boundaries and can be used to guide the further development and optimization of graphene-based electronic devices.

  5. Ballistic electron transport calculation of strained germanium-tin fin field-effect transistors

    SciTech Connect (OSTI)

    Lan, H.-S.; Liu, C. W.

    2014-05-12

    The dependence of ballistic electron current on Sn content, sidewall orientations, fin width, and uniaxial stress is theoretically studied for the GeSn fin field-effect transistors. Alloying Sn increases the direct ? valley occupancy and enhances the injection velocity at virtual source node. (112{sup ¯}) sidewall gives the highest current enhancement due to the rapidly increasing ? valley occupancy. The non-parabolicity of the ? valley affects the occupancy significantly. However, uniaxial tensile stress and the shrinkage of fin width reduce the ? valley occupancy, and the currents are enhanced by increasing occupancy of specific indirect L valleys with high injection velocity.

  6. All-electric and all-semiconductor spin field effect transistors

    E-Print Network [OSTI]

    Chuang, Pojen; Ho, Sheng-Chin; Smith, L. W.; Sfigakis, F.; Pepper, M.; Chen, Chin-Hung; Fan, Ju-Chun; Griffiths, J. P.; Farrer, I.; Beere, H. E.; Jones, G. A. C.; Ritchie, D. A.; Chen, T.-M.

    2014-12-22

    and results in two spin-polarized 1D subbands shifted in wavevector as shown in Fig. 1c. In the case where the Fermi energy EF is tuned below the crossing point between two spin-polarized subbands, the left- and right-moving 1D electrons are both fully spin... transport in In0.75Ga0.25As quantum wires. Appl. Phys. Lett. 92, 152108 (2008). 31. Sugahara, S. & Nitta, J. Spin-Transistor Electronics: An Overview and Outlook. Proceedings of the IEEE 98, 2124-2154 (2010). Acknowledgements We thank C.-W. Chang, C...

  7. Solvent-induced changes in PEDOT:PSS films for organic electrochemical transistors

    SciTech Connect (OSTI)

    Zhang, Shiming; Kumar, Prajwal; Nouas, Amel Sarah; Fontaine, Laurie; Tang, Hao; Cicoira, Fabio

    2015-01-01

    Organic electrochemical transistors based on the conducting polymer poly(3,4-ethylenedioxythiophene) doped with poly(styrenesulfonate) (PEDOT:PSS) are of interest for several bioelectronic applications. In this letter, we investigate the changes induced by immersion of PEDOT:PSS films, processed by spin coating from different mixtures, in water and other solvents of different polarities. We found that the film thickness decreases upon immersion in polar solvents, while the electrical conductivity remains unchanged. The decrease in film thickness is minimized via the addition of a cross-linking agent to the mixture used for the spin coating of the films.

  8. Methane oxidation rates by AMS

    E-Print Network [OSTI]

    Pack, M; Heintz, M; ReeburGh, WS; Trumbore, SE; Valentine, DL; Xu, X

    2009-01-01

    second case. Number of cases Methane oxidation rates by AMSIn the marine environment methane (CH 4 ) oxidation consumes

  9. Low Power, Red, Green and Blue Carbon Nanotube Enabled Vertical Organic Light Emitting Transistors for Active Matrix OLED Displays

    SciTech Connect (OSTI)

    McCarthy, M. A. [University of Florida, Gainesville; Liu, B. [University of Florida, Gainesville; Donoghue, E. P. [University of Florida, Gainesville; Kravchenko, Ivan I [ORNL; Kim, D. Y. [University of Florida, Gainesville; So, Franky [University of Florida, Gainesville; Rinzler, A. G. [University of Florida, Gainesville

    2011-01-01

    Organic semiconductors are potential alternatives to polycrystalline silicon as the semiconductor used in the backplane of active matrix organic light emitting diode displays. Demonstrated here is a light-emitting transistor with an organic channel, operating with low power dissipation at low voltage, and high aperture ratio, in three colors: red, green and blue. The single-wall carbon nanotube network source electrode is responsible for the high level of performance demonstrated. A major benefit enabled by this architecture is the integration of the drive transistor, storage capacitor and light emitter into a single device. Performance comparable to commercialized polycrystalline-silicon TFT driven OLEDs is demonstrated.

  10. Procedures for realizing an approximate universal NOT gate

    E-Print Network [OSTI]

    Jeongho Bang; Seung-Woo Lee; Hyunseok Jeong; Jinhyoung Lee

    2012-12-19

    We consider procedures to realize an approximate universal NOT gate in terms of average fidelity and fidelity deviation. The average fidelity indicates the optimality of operation on average, while the fidelity deviation does the universality of operation. We show that one-qubit operations have a sharp trade-off relation between average fidelity and fidelity deviation, and two-qubit operations show a looser trade-off relation. The genuine universality holds for operations of more than two qubits, and those of even more qubits are beneficial to compensating imperfection of control. In addition, we take into account operational noises which contaminate quantum operation in realistic circumstances. We show that the operation recovers from the contamination by a feedback procedure of differential evolution. Our feedback scheme is also applicable to finding an optimal and universal operation of NOT.

  11. Gas-controlled dynamic vacuum insulation with gas gate

    DOE Patents [OSTI]

    Benson, David K. (Golden, CO); Potter, Thomas F. (Denver, CO)

    1994-06-07

    Disclosed is a dynamic vacuum insulation comprising sidewalls enclosing an evacuated chamber and gas control means for releasing hydrogen gas into a chamber to increase gas molecule conduction of heat across the chamber and retrieving hydrogen gas from the chamber. The gas control means includes a metal hydride that absorbs and retains hydrogen gas at cooler temperatures and releases hydrogen gas at hotter temperatures; a hydride heating means for selectively heating the metal hydride to temperatures high enough to release hydrogen gas from the metal hydride; and gate means positioned between the metal hydride and the chamber for selectively allowing hydrogen to flow or not to flow between said metal hydride and said chamber.

  12. Gas-controlled dynamic vacuum insulation with gas gate

    DOE Patents [OSTI]

    Benson, D.K.; Potter, T.F.

    1994-06-07

    Disclosed is a dynamic vacuum insulation comprising sidewalls enclosing an evacuated chamber and gas control means for releasing hydrogen gas into a chamber to increase gas molecule conduction of heat across the chamber and retrieving hydrogen gas from the chamber. The gas control means includes a metal hydride that absorbs and retains hydrogen gas at cooler temperatures and releases hydrogen gas at hotter temperatures; a hydride heating means for selectively heating the metal hydride to temperatures high enough to release hydrogen gas from the metal hydride; and gate means positioned between the metal hydride and the chamber for selectively allowing hydrogen to flow or not to flow between said metal hydride and said chamber. 25 figs.

  13. Partial oxidation catalyst

    DOE Patents [OSTI]

    Krumpelt, Michael (Naperville, IL); Ahmed, Shabbir (Bolingbrook, IL); Kumar, Romesh (Naperville, IL); Doshi, Rajiv (Downers Grove, IL)

    2000-01-01

    A two-part catalyst comprising a dehydrogenation portion and an oxide-ion conducting portion. The dehydrogenation portion is a group VIII metal and the oxide-ion conducting portion is selected from a ceramic oxide crystallizing in the fluorite or perovskite structure. There is also disclosed a method of forming a hydrogen rich gas from a source of hydrocarbon fuel in which the hydrocarbon fuel contacts a two-part catalyst comprising a dehydrogenation portion and an oxide-ion conducting portion at a temperature not less than about 400.degree. C. for a time sufficient to generate the hydrogen rich gas while maintaining CO content less than about 5 volume percent. There is also disclosed a method of forming partially oxidized hydrocarbons from ethanes in which ethane gas contacts a two-part catalyst comprising a dehydrogenation portion and an oxide-ion conducting portion for a time and at a temperature sufficient to form an oxide.

  14. ZIRCONIUM OXIDE NANOSTRUCTURES PREPARED BY ANODIC OXIDATION

    SciTech Connect (OSTI)

    Dang, Y. Y.; Bhuiyan, M.S.; Paranthaman, M. P.

    2008-01-01

    Zirconium oxide is an advanced ceramic material highly useful for structural and electrical applications because of its high strength, fracture toughness, chemical and thermal stability, and biocompatibility. If highly-ordered porous zirconium oxide membranes can be successfully formed, this will expand its real-world applications, such as further enhancing solid-oxide fuel cell technology. Recent studies have achieved various morphologies of porous zirconium oxide via anodization, but they have yet to create a porous layer where nanoholes are formed in a highly ordered array. In this study, electrochemical methods were used for zirconium oxide synthesis due to its advantages over other coating techniques, and because the thickness and morphology of the ceramic fi lms can be easily tuned by the electrochemical parameters, such as electrolyte solutions and processing conditions, such as pH, voltage, and duration. The effects of additional steps such as pre-annealing and post-annealing were also examined. Results demonstrate the formation of anodic porous zirconium oxide with diverse morphologies, such as sponge-like layers, porous arrays with nanoholes ranging from 40 to 75 nm, and nanotube layers. X-ray powder diffraction analysis indicates a cubic crystallographic structure in the zirconium oxide. It was noted that increased voltage improved the ability of the membrane to stay adhered to the zirconium substrate, whereas lower voltages caused a propensity for the oxide fi lm to fl ake off. Further studies are needed to defi ne the parameters windows that create these morphologies and to investigate other important characteristics such as ionic conductivity.

  15. Optimized controlled Z gates for two superconducting qubits coupled through a resonator

    E-Print Network [OSTI]

    D. J. Egger; F. K. Wilhelm

    2013-06-28

    Superconducting qubits are a promising candidate for building a quantum computer. A continued challenge for fast yet accurate gates to minimize the effects of decoherence. Here we apply numerical methods to design fast entangling gates, specifically the controlled Z, in an architecture where two qubits are coupled via a resonator. We find that the gates can be sped up by a factor of two and reach any target fidelity. We also discuss how systematic errors arising from experimental conditions affect the pulses and how to remedy them, providing a strategy for the experimental implementation of our results. We discuss the shape of the pulses, their spectrum and symmetry.

  16. Adiabatic two-photon quantum gate operations using a long-range photonic bus

    E-Print Network [OSTI]

    Anthony P. Hope; Thach G. Nguyen; Arnan Mitchell; Andrew D. Greentree

    2014-12-01

    Adiabatic techniques have much potential to realise practical and robust optical waveguide devices. Traditionally photonic elements are limited to coupling schemes that rely on proximity to nearest neighbour elements. We combine adiabatic passage with a continuum based long-range optical bus to break free from such topological restraints and thereby outline a new approach to photonic quantum gate design. We explicitly show designs for adiabatic quantum gates that produce a Hadamard, 50:50 and 1/3:2/3 beam splitter, and non-deterministic CNOT gate based on planar thin, shallow ridge waveguides. Our calculations are performed under conditions of one and two-photon inputs.

  17. Design of a spin-wave majority gate employing mode selection

    SciTech Connect (OSTI)

    Klingler, S. Pirro, P.; Brächer, T.; Leven, B.; Hillebrands, B.; Chumak, A. V.

    2014-10-13

    The design of a microstructured, fully functional spin-wave majority gate is presented and studied using micromagnetic simulations. This all-magnon logic gate consists of three-input waveguides, a spin-wave combiner, and an output waveguide. In order to ensure the functionality of the device, the output waveguide is designed to perform spin-wave mode selection. We demonstrate that the gate evaluates the majority of the input signals coded into the spin-wave phase. Moreover, the all-magnon data processing device is used to perform logic AND-, OR-, NAND-, and NOR- operations.

  18. High-performance MoS{sub 2} transistors with low-resistance molybdenum contacts

    SciTech Connect (OSTI)

    Kang, Jiahao; Liu, Wei; Banerjee, Kaustav, E-mail: kaustav@ece.ucsb.edu [Department of Electrical and Computer Engineering, University of California, Santa Barbara, California 93106 (United States)

    2014-03-03

    In this Letter, molybdenum (Mo) is introduced and evaluated as an alternative contact metal to atomically-thin molybdenum disulphide (MoS{sub 2}), and high-performance field-effect transistors are experimentally demonstrated. In order to understand the physical nature of the interface and highlight the role of the various factors contributing to the Mo-MoS{sub 2} contacts, density functional theory (DFT) simulations are employed, which reveal that Mo can form high quality contact interface with monolayer MoS{sub 2} with zero tunnel barrier and zero Schottky barrier under source/drain contact, as well as an ultra-low Schottky barrier (0.1?eV) at source/drain-channel junction due to strong Fermi level pinning. In agreement with the DFT simulations, high mobility, high ON-current, and low contact resistance are experimentally demonstrated on both monolayer and multilayer MoS{sub 2} transistors using Mo contacts. The results obtained not only reveal the advantages of using Mo as a contact metal for MoS{sub 2} but also highlight the fact that the properties of contacts with 2-dimensional materials cannot be intuitively predicted by solely considering work function values and Schottky theory.

  19. A Water-Soluble Polythiophene for Organic Field-Effect Transistors

    SciTech Connect (OSTI)

    Shao, Ming; He, Youjun; Hong, Kunlun; Rouleau, Christopher M; Geohegan, David B; Xiao, Kai

    2013-01-01

    Synthesis of a non-ionic, water-soluble poly(thiophene) (PT) derivative, poly(3-(2-(2-methoxyethoxy) ethoxy)ethoxy) methylthiophene) (P3TEGT) with a hydrophilic tri-ethylene glycol side group, is reported and thin films of the polymer suitable for organic field-effect transistors (OFETs) are characterized by combining analysis techniques that include UV-Vis absorption and fluorescence spectroscopy, x-ray diffraction, and atomic force microscopy. After thermal annealing, P3TEGT films exhibit a well-organized nanofibrillar lamellar nanostructure that originates from the strong - stacking of the thiophene backbones. P-type organic field-effect transistors (OFETs) with hole mobilities of 10-5 cm2V-1s-1 were fabricated from this water-soluble poly(thiophene) derivative, demonstrating the possibility that environmentally-friendly solvents may be promising alternatives for the low-cost, green solution-based organic electronic device manufacturing of OFETs, organic photovoltaics (OPVs), and biosensors.

  20. Integrated digital inverters based on two-dimensional anisotropic ReS? field-effect transistors

    DOE Public Access Gateway for Energy & Science Beta (PAGES Beta)

    Liu, Erfu; Fu, Yajun; Wang, Yaojia; Feng, Yanqing; Liu, Huimei; Wan, Xiangang; Zhou, Wei; Wang, Baigeng; Shao, Lubin; Ho, Ching -Hwa; et al

    2015-05-07

    Semiconducting two-dimensional transition metal dichalcogenides are emerging as top candidates for post-silicon electronics. While most of them exhibit isotropic behaviour, lowering the lattice symmetry could induce anisotropic properties, which are both scientifically interesting and potentially useful. Here we present atomically thin rhenium disulfide (ReS?) flakes with unique distorted 1T structure, which exhibit in-plane anisotropic properties. We fabricated monolayer and few-layer ReS? field-effect transistors, which exhibit competitive performance with large current on/off ratios (~10?) and low subthreshold swings (100 mV per decade). The observed anisotropic ratio along two principle axes reaches 3.1, which is the highest among all known two-dimensional semiconductingmore »materials. Furthermore, we successfully demonstrated an integrated digital inverter with good performance by utilizing two ReS? anisotropic field-effect transistors, suggesting the promising implementation of large-scale two-dimensional logic circuits. Our results underscore the unique properties of two-dimensional semiconducting materials with low crystal symmetry for future electronic applications.« less

  1. A versatile LabVIEW and field-programmable gate array-based scanning probe microscope for in operando electronic device characterization

    SciTech Connect (OSTI)

    Berger, Andrew J. Page, Michael R.; Young, Justin R.; Bhallamudi, Vidya P.; Johnston-Halperin, Ezekiel; Pelekhov, Denis V.; Hammel, P. Chris; Jacob, Jan; Lewis, Jim; Wenzel, Lothar

    2014-12-15

    Understanding the complex properties of electronic and spintronic devices at the micro- and nano-scale is a topic of intense current interest as it becomes increasingly important for scientific progress and technological applications. In operando characterization of such devices by scanning probe techniques is particularly well-suited for the microscopic study of these properties. We have developed a scanning probe microscope (SPM) which is capable of both standard force imaging (atomic, magnetic, electrostatic) and simultaneous electrical transport measurements. We utilize flexible and inexpensive FPGA (field-programmable gate array) hardware and a custom software framework developed in National Instrument's LabVIEW environment to perform the various aspects of microscope operation and device measurement. The FPGA-based approach enables sensitive, real-time cantilever frequency-shift detection. Using this system, we demonstrate electrostatic force microscopy of an electrically biased graphene field-effect transistor device. The combination of SPM and electrical transport also enables imaging of the transport response to a localized perturbation provided by the scanned cantilever tip. Facilitated by the broad presence of LabVIEW in the experimental sciences and the openness of our software solution, our system permits a wide variety of combined scanning and transport measurements by providing standardized interfaces and flexible access to all aspects of a measurement (input and output signals, and processed data). Our system also enables precise control of timing (synchronization of scanning and transport operations) and implementation of sophisticated feedback protocols, and thus should be broadly interesting and useful to practitioners in the field.

  2. Oxidation Resistant Graphite Studies

    SciTech Connect (OSTI)

    W. Windes; R. Smith

    2014-07-01

    The Very High Temperature Reactor (VHTR) Graphite Research and Development Program is investigating doped nuclear graphite grades exhibiting oxidation resistance. During a oxygen ingress accident the oxidation rates of the high temperature graphite core region would be extremely high resulting in significant structural damage to the core. Reducing the oxidation rate of the graphite core material would reduce the structural effects and keep the core integrity intact during any air-ingress accident. Oxidation testing of graphite doped with oxidation resistant material is being conducted to determine the extent of oxidation rate reduction. Nuclear grade graphite doped with varying levels of Boron-Carbide (B4C) was oxidized in air at nominal 740°C at 10/90% (air/He) and 100% air. The oxidation rates of the boronated and unboronated graphite grade were compared. With increasing boron-carbide content (up to 6 vol%) the oxidation rate was observed to have a 20 fold reduction from unboronated graphite. Visual inspection and uniformity of oxidation across the surface of the specimens were conducted. Future work to determine the remaining mechanical strength as well as graphite grades with SiC doped material are discussed.

  3. Benchmarking the performance of ultrathin body InAs-on-insulator transistors as a function of body thickness

    E-Print Network [OSTI]

    Javey, Ali

    are primarily dominated by Shockley Read Hall recombination/generation and trap-assisted tunneling. The OFF-effect transistors (FETs) to enable low-power and high- speed electronics.1­6 In this regard, the use of ultrathin InAs XOI n-FETs have been experimentally reported with the effective electron mobility of ln ¼ 1000

  4. 1376 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 7, JULY 2005 Lateral High-Speed Bipolar Transistors

    E-Print Network [OSTI]

    Ng, Wai Tung

    Transistors on SOI for RF SoC Applications I-Shan Michael Sun, Student Member, IEEE, Wai Tung Ng, Senior, or current drive capability. Furthermore, with no additional mask, both common­emitter and common­collector.-S. M. Sun and W. T. Ng are with the Edward S. Rogers, Sr. Department of Electrical and Computer

  5. Mesoscopic Photon Heat Transistor Teemu Ojanen1,2,* and Antti-Pekka Jauho3,4

    E-Print Network [OSTI]

    von Oppen, Felix

    coupled via an intermediate electric circuit. The reservoirs are assumed to behave as linear dissipative, mediated by electromagnetic fluctuations, can be controlled with an intermediate quantum circuit--leading to the device concept of a mesoscopic photon heat transistor (MPHT). Our theoretical analysis is based

  6. 44 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 11, NO. 1, JANUARY 2012 Self-Aligned Carbon Nanotube Thin-Film Transistors

    E-Print Network [OSTI]

    Chen, Ray

    and cost-effective method to produce electronics. It is an attractive process for flexible electronics due as the channel material for several state-of-the-art flexible electronics [1], [2]. However, the carrier mobility Thin-Film Transistors on Flexible Substrates With Novel Source­Drain Contact and Multilayer Metal

  7. PUBLISHED ONLINE: 25 OCTOBER 2009 | DOI: 10.1038/NPHYS1433 Superconductivity in a single-C60 transistor

    E-Print Network [OSTI]

    Loss, Daniel

    -up quantum-dot (QD) structures have recently been experimentally realized using semiconducting nanowires16 Balestro Single-molecule transistors are currently attracting enormous attention as possible quantum, stable devices showing Institut Néel, CNRS-Université Joseph Fourier-Grenoble INP, BP 166, F-38042

  8. SnO2 functionalized AlGaN/GaN high electron mobility transistor for hydrogen sensing applications

    E-Print Network [OSTI]

    Florida, University of

    for spacecraft and other long-term sensing applications. However, hydrogen is a dangerous gas for storage for monitoring leakage of hydrogen storage equipment and fuel tanks for spacecraft and hydrogen fuel cellSnO2 functionalized AlGaN/GaN high electron mobility transistor for hydrogen sensing applications

  9. METAL OXIDE NANOPARTICLES

    SciTech Connect (OSTI)

    FERNANDEZ-GARCIA,M.; RODGRIGUEZ, J.A.

    2007-10-01

    This chapter covers the fundamental science, synthesis, characterization, physicochemical properties and applications of oxide nanomaterials. Explains fundamental aspects that determine the growth and behavior of these systems, briefly examines synthetic procedures using bottom-up and top-down fabrication technologies, discusses the sophisticated experimental techniques and state of the art theory results used to characterize the physico-chemical properties of oxide solids and describe the current knowledge concerning key oxide materials with important technological applications.

  10. Barium oxide, calcium oxide, magnesia, and alkali oxide free glass

    DOE Patents [OSTI]

    Lu, Peizhen Kathy; Mahapatra, Manoj Kumar

    2013-09-24

    A glass composition consisting essentially of about 10-45 mole percent of SrO; about 35-75 mole percent SiO.sub.2; one or more compounds from the group of compounds consisting of La.sub.2O.sub.3, Al.sub.2O.sub.3, B.sub.2O.sub.3, and Ni; the La.sub.2O.sub.3 less than about 20 mole percent; the Al.sub.2O.sub.3 less than about 25 mole percent; the B.sub.2O.sub.3 less than about 15 mole percent; and the Ni less than about 5 mole percent. Preferably, the glass is substantially free of barium oxide, calcium oxide, magnesia, and alkali oxide. Preferably, the glass is used as a seal in a solid oxide fuel/electrolyzer cell (SOFC) stack. The SOFC stack comprises a plurality of SOFCs connected by one or more interconnect and manifold materials and sealed by the glass. Preferably, each SOFC comprises an anode, a cathode, and a solid electrolyte.

  11. Multi-images deconvolution improves signal-to-noise ratio on gated stimulated emission depletion microscopy

    SciTech Connect (OSTI)

    Castello, Marco; Diaspro, Alberto; Vicidomini, Giuseppe

    2014-12-08

    Time-gated detection, namely, only collecting the fluorescence photons after a time-delay from the excitation events, reduces complexity, cost, and illumination intensity of a stimulated emission depletion (STED) microscope. In the gated continuous-wave- (CW-) STED implementation, the spatial resolution improves with increased time-delay, but the signal-to-noise ratio (SNR) reduces. Thus, in sub-optimal conditions, such as a low photon-budget regime, the SNR reduction can cancel-out the expected gain in resolution. Here, we propose a method which does not discard photons, but instead collects all the photons in different time-gates and recombines them through a multi-image deconvolution. Our results, obtained on simulated and experimental data, show that the SNR of the restored image improves relative to the gated image, thereby improving the effective resolution.

  12. Shot noise in an electron waveguide square root of NOT gate

    E-Print Network [OSTI]

    Linda E. Reichl; Michael G. Snyder

    2006-01-17

    We present a calculation of the shot noise in a ballistic electron waveguide square root of NOT gate. A general expression for the shot noise in the leads connected to these types of gates is shown. We then parameterize an S-matrix which qualitatively describes the action of a square root of NOT gate previously found through numerical methods for GaAs/Al_xGa_{1-x}As based waveguides systems. Using this S-matrix, the shot noise in a single output lead and across two output leads is calculated. We find that the measurement of the shot noise across two output leads allows for the determination of the fidelity of the gate itself.

  13. Retrofit of Tehran City Gate Station C.G.S. No. 2 by Using Turboexpander 

    E-Print Network [OSTI]

    Seresht, R. T.; Ja, H. K.

    2010-01-01

    air components. 6. Liquefaction gases (like Helium). 7. Separating condensable components of natural gas. 8. Power generation from geothermal energy. Retrofit of Tehran City Gate Station C.G.S. No.2 by Using Turboexpander Yasun Farayand Company...

  14. Vehicle Technologies Office Merit Review 2015: GATE: Energy Efficient Vehicles for Sustainable Mobility

    Office of Energy Efficiency and Renewable Energy (EERE)

    Presentation given by The Ohio State University at 2015 DOE Hydrogen and Fuel Cells Program and Vehicle Technologies Office Annual Merit Review and Peer Evaluation Meeting about GATE: energy...

  15. Improving Quantum Gate Fidelities by Using a Qubit to Measure Microwave Pulse Distortions

    E-Print Network [OSTI]

    Gustavsson, Simon

    We present a new method for determining pulse imperfections and improving the single-gate fidelity in a superconducting qubit. By applying consecutive positive and negative ? pulses, we amplify the qubit evolution due to ...

  16. Vehicle Technologies Office Merit Review 2015: GATE Center for Electric Drive Transportation

    Broader source: Energy.gov [DOE]

    Presentation given by Regents University of Michigan at 2015 DOE Hydrogen and Fuel Cells Program and Vehicle Technologies Office Annual Merit Review and Peer Evaluation Meeting about GATE Center...

  17. Vehicle Technologies Office Merit Review 2015: GATE Center of Excellence in Sustainable Vehicle Systems

    Broader source: Energy.gov [DOE]

    Presentation given by Clemson University at 2015 DOE Hydrogen and Fuel Cells Program and Vehicle Technologies Office Annual Merit Review and Peer Evaluation Meeting about GATE center of excellence...

  18. Vehicle Technologies Office Merit Review 2014: DOE GATE Center of Excellence in Sustainable Vehicle Systems

    Broader source: Energy.gov [DOE]

    Presentation given by Clemson University at 2014 DOE Hydrogen and Fuel Cells Program and Vehicle Technologies Office Annual Merit Review and Peer Evaluation Meeting about DOE GATE Center of...

  19. Vehicle Technologies Office Merit Review 2014: GATE: Energy Efficient Vehicles for Sustainable Mobility

    Broader source: Energy.gov [DOE]

    Presentation given by Ohio State University at 2014 DOE Hydrogen and Fuel Cells Program and Vehicle Technologies Office Annual Merit Review and Peer Evaluation Meeting about GATE: energy efficient...

  20. CNT-based gas ionizers with integrated MEMS gate for portable mass spectrometry applications

    E-Print Network [OSTI]

    Velasquez-Garcia, Luis Fernando

    We report the fabrication and experimental characterization of a novel low-cost carbon nanotube (CNT)-based electron impact ionizer (EII) with integrated gate for portable mass spectrometry applications. The device achieves ...