National Library of Energy BETA

Sample records for transistor gate oxide

  1. Looking at Transistor Gate Oxide Formation in Real Time

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Looking at Transistor Gate Oxide Formation in Real Time Print The oxide gate layer is critical to every transistor, and present-day layer thicknesses are in the 10-20 range (1-2...

  2. Looking at Transistor Gate Oxide Formation in Real Time

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Looking at Transistor Gate Oxide Formation in Real Time Print The oxide gate layer is ... Now, for the first time, a group of researchers has obtained real-time oxidation results ...

  3. Looking at Transistor Gate Oxide Formation in Real Time

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Looking at Transistor Gate Oxide Formation in Real Time Looking at Transistor Gate Oxide Formation in Real Time Print Wednesday, 25 June 2008 00:00 The oxide gate layer is critical to every transistor, and present-day layer thicknesses are in the 10-20 Å range (1-2 nm). However, little information exists on the oxidation process at this thickness. Available results are either for thicker layers grown under high-pressure conditions or for only the first couple of monolayers studied under

  4. Looking at Transistor Gate Oxide Formation in Real Time

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Looking at Transistor Gate Oxide Formation in Real Time Print The oxide gate layer is critical to every transistor, and present-day layer thicknesses are in the 10-20 Å range (1-2 nm). However, little information exists on the oxidation process at this thickness. Available results are either for thicker layers grown under high-pressure conditions or for only the first couple of monolayers studied under high-vacuum conditions. Now, for the first time, a group of researchers has obtained

  5. Looking at Transistor Gate Oxide Formation in Real Time

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Looking at Transistor Gate Oxide Formation in Real Time Print The oxide gate layer is critical to every transistor, and present-day layer thicknesses are in the 10-20 Å range (1-2 nm). However, little information exists on the oxidation process at this thickness. Available results are either for thicker layers grown under high-pressure conditions or for only the first couple of monolayers studied under high-vacuum conditions. Now, for the first time, a group of researchers has obtained

  6. Looking at Transistor Gate Oxide Formation in Real Time

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Looking at Transistor Gate Oxide Formation in Real Time Print The oxide gate layer is critical to every transistor, and present-day layer thicknesses are in the 10-20 Å range (1-2 nm). However, little information exists on the oxidation process at this thickness. Available results are either for thicker layers grown under high-pressure conditions or for only the first couple of monolayers studied under high-vacuum conditions. Now, for the first time, a group of researchers has obtained

  7. Looking at Transistor Gate Oxide Formation in Real Time

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Looking at Transistor Gate Oxide Formation in Real Time Print The oxide gate layer is critical to every transistor, and present-day layer thicknesses are in the 10-20 Å range (1-2 nm). However, little information exists on the oxidation process at this thickness. Available results are either for thicker layers grown under high-pressure conditions or for only the first couple of monolayers studied under high-vacuum conditions. Now, for the first time, a group of researchers has obtained

  8. Looking at Transistor Gate Oxide Formation in Real Time

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Looking at Transistor Gate Oxide Formation in Real Time Print The oxide gate layer is critical to every transistor, and present-day layer thicknesses are in the 10-20 Å range (1-2 nm). However, little information exists on the oxidation process at this thickness. Available results are either for thicker layers grown under high-pressure conditions or for only the first couple of monolayers studied under high-vacuum conditions. Now, for the first time, a group of researchers has obtained

  9. Looking at Transistor Gate Oxide Formation in Real Time

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Looking at Transistor Gate Oxide Formation in Real Time Print The oxide gate layer is critical to every transistor, and present-day layer thicknesses are in the 10-20 Å range (1-2 nm). However, little information exists on the oxidation process at this thickness. Available results are either for thicker layers grown under high-pressure conditions or for only the first couple of monolayers studied under high-vacuum conditions. Now, for the first time, a group of researchers has obtained

  10. Looking at Transistor Gate Oxide Formation in Real Time

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Looking at Transistor Gate Oxide Formation in Real Time Print The oxide gate layer is critical to every transistor, and present-day layer thicknesses are in the 10-20 Å range (1-2 nm). However, little information exists on the oxidation process at this thickness. Available results are either for thicker layers grown under high-pressure conditions or for only the first couple of monolayers studied under high-vacuum conditions. Now, for the first time, a group of researchers has obtained

  11. Looking at Transistor Gate Oxide Formation in Real Time

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    transistors (about 4,000 per person) are produced worldwide as part of the integrated circuits that drive information technology. Each of these transistors contains an...

  12. Looking at Transistor Gate Oxide Formation in Real Time

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    on the oxidation process at this thickness. Available results are either for thicker layers grown under high-pressure conditions or for only the first couple of monolayers...

  13. Protonic/electronic hybrid oxide transistor gated by chitosan and its full-swing low voltage inverter applications

    SciTech Connect (OSTI)

    Chao, Jin Yu; Zhu, Li Qiang Xiao, Hui; Yuan, Zhi Guo

    2015-12-21

    Modulation of charge carrier density in condensed materials based on ionic/electronic interaction has attracted much attention. Here, protonic/electronic hybrid indium-zinc-oxide (IZO) transistors gated by chitosan based electrolyte were obtained. The chitosan-based electrolyte illustrates a high proton conductivity and an extremely strong proton gating behavior. The transistor illustrates good electrical performances at a low operating voltage of ∼1.0 V such as on/off ratio of ∼3 × 10{sup 7}, subthreshold swing of ∼65 mV/dec, threshold voltage of ∼0.3 V, and mobility of ∼7 cm{sup 2}/V s. Good positive gate bias stress stabilities are obtained. Furthermore, a low voltage driven resistor-loaded inverter was built by using an IZO transistor in series with a load resistor, exhibiting a linear relationship between the voltage gain and the supplied voltage. The inverter is also used for decreasing noises of input signals. The protonic/electronic hybrid IZO transistors have potential applications in biochemical sensors and portable electronics.

  14. Solution processed lanthanum aluminate gate dielectrics for use in metal oxide-based thin film transistors

    SciTech Connect (OSTI)

    Esro, M.; Adamopoulos, G.; Mazzocco, R.; Kolosov, O.; Krier, A.; Vourlias, G.; Milne, W. I.

    2015-05-18

    We report on ZnO-based thin-film transistors (TFTs) employing lanthanum aluminate gate dielectrics (La{sub x}Al{sub 1−x}O{sub y}) grown by spray pyrolysis in ambient atmosphere at 440 °C. The structural, electronic, optical, morphological, and electrical properties of the La{sub x}Al{sub 1−x}O{sub y} films and devices as a function of the lanthanum to aluminium atomic ratio were investigated using a wide range of characterization techniques such as UV-visible absorption spectroscopy, impedance spectroscopy, spectroscopic ellipsometry, atomic force microscopy, x-ray diffraction, and field-effect measurements. As-deposited LaAlO{sub y} dielectrics exhibit a wide band gap (∼6.18 eV), high dielectric constant (k ∼ 16), low roughness (∼1.9 nm), and very low leakage currents (<3 nA/cm{sup 2}). TFTs employing solution processed LaAlO{sub y} gate dielectrics and ZnO semiconducting channels exhibit excellent electron transport characteristics with hysteresis-free operation, low operation voltages (∼10 V), high on/off current modulation ratio of >10{sup 6}, subthreshold swing of ∼650 mV dec{sup −1}, and electron mobility of ∼12 cm{sup 2} V{sup −1} s{sup −1}.

  15. Recovery from ultraviolet-induced threshold voltage shift in indium gallium zinc oxide thin film transistors by positive gate bias

    SciTech Connect (OSTI)

    Liu, P.; Chen, T. P.; Li, X. D.; Wong, J. I.; Liu, Z.; Liu, Y.; Leong, K. C.

    2013-11-11

    The effect of short-duration ultraviolet (UV) exposure on the threshold voltage (V{sub th}) of amorphous indium gallium zinc oxide thin film transistors (TFTs) and its recovery characteristics were investigated. The V{sub th} exhibited a significant negative shift after UV exposure. The V{sub th} instability caused by UV illumination is attributed to the positive charge trapping in the dielectric layer and/or at the channel/dielectric interface. The illuminated devices showed a slow recovery in threshold voltage without external bias. However, an instant recovery can be achieved by the application of positive gate pulses, which is due to the elimination of the positive trapped charges as a result of the presence of a large amount of field-induced electrons in the interface region.

  16. Advanced insulated gate bipolar transistor gate drive

    DOE Patents [OSTI]

    Short, James Evans; West, Shawn Michael; Fabean, Robert J.

    2009-08-04

    A gate drive for an insulated gate bipolar transistor (IGBT) includes a control and protection module coupled to a collector terminal of the IGBT, an optical communications module coupled to the control and protection module, a power supply module coupled to the control and protection module and an output power stage module with inputs coupled to the power supply module and the control and protection module, and outputs coupled to a gate terminal and an emitter terminal of the IGBT. The optical communications module is configured to send control signals to the control and protection module. The power supply module is configured to distribute inputted power to the control and protection module. The control and protection module outputs on/off, soft turn-off and/or soft turn-on signals to the output power stage module, which, in turn, supplies a current based on the signal(s) from the control and protection module for charging or discharging an input capacitance of the IGBT.

  17. Effect of top gate bias on photocurrent and negative bias illumination stress instability in dual gate amorphous indium-gallium-zinc oxide thin-film transistor

    SciTech Connect (OSTI)

    Lee, Eunji; Chowdhury, Md Delwar Hossain; Park, Min Sang; Jang, Jin

    2015-12-07

    We have studied the effect of top gate bias (V{sub TG}) on the generation of photocurrent and the decay of photocurrent for back channel etched inverted staggered dual gate structure amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film-transistors. Upon 5 min of exposure of 365 nm wavelength and 0.7 mW/cm{sup 2} intensity light with negative bottom gate bias, the maximum photocurrent increases from 3.29 to 322 pA with increasing the V{sub TG} from −15 to +15 V. By changing V{sub TG} from negative to positive, the Fermi level (E{sub F}) shifts toward conduction band edge (E{sub C}), which substantially controls the conversion of neutral vacancy to charged one (V{sub O} → V{sub O}{sup +}/V{sub O}{sup 2+} + e{sup −}/2e{sup −}), peroxide (O{sub 2}{sup 2−}) formation or conversion of ionized interstitial (O{sub i}{sup 2−}) to neutral interstitial (O{sub i}), thus electron concentration at conduction band. With increasing the exposure time, more carriers are generated, and thus, maximum photocurrent increases until being saturated. After negative bias illumination stress, the transfer curve shows −2.7 V shift at V{sub TG} = −15 V, which gradually decreases to −0.42 V shift at V{sub TG} = +15 V. It clearly reveals that the position of electron quasi-Fermi level controls the formation of donor defects (V{sub O}{sup +}/V{sub O}{sup 2+}/O{sub 2}{sup 2−}/O{sub i}) and/or hole trapping in the a-IGZO /interfaces.

  18. High mobility field effect transistor based on BaSnO{sub 3} with Al{sub 2}O{sub 3} gate oxide

    SciTech Connect (OSTI)

    Park, Chulkwon; Kim, Useong; Ju, Chan Jong; Park, Ji Sung; Kim, Young Mo; Char, Kookrin

    2014-11-17

    We fabricated an n-type accumulation-mode field effect transistor based on BaSnO{sub 3} transparent perovskite semiconductor, taking advantage of its high mobility and oxygen stability. We used the conventional metal-insulator-semiconductor structures: (In,Sn){sub 2}O{sub 3} as the source, drain, and gate electrodes, Al{sub 2}O{sub 3} as the gate insulator, and La-doped BaSnO{sub 3} as the semiconducting channel. The Al{sub 2}O{sub 3} gate oxide was deposited by atomic layer deposition technique. At room temperature, we achieved the field effect mobility value of 17.8?cm{sup 2}/Vs and the I{sub on}/I{sub off} ratio value higher than 10{sup 5} for V{sub DS}?=?1?V. These values are higher than those previously reported on other perovskite oxides, in spite of the large density of threading dislocations in the BaSnO{sub 3} on SrTiO{sub 3} substrates. However, a relatively large subthreshold swing value was found, which we attribute to the large density of charge traps in the Al{sub 2}O{sub 3} as well as the threading dislocations.

  19. Effect of proton irradiation dose on InAlN/GaN metal-oxide semiconductor high electron mobility transistors with Al2O3 gate oxide

    DOE Public Access Gateway for Energy & Science Beta (PAGES Beta)

    Ahn, Shihyun; Kim, Byung -Jae; Lin, Yi -Hsuan; Ren, Fan; Pearton, Stephen J.; Yang, Gwangseok; Kim, Jihyun; Kravchenko, Ivan I.

    2016-07-26

    The effects of proton irradiation on the dc performance of InAlN/GaN metal-oxide-semiconductor high electron mobility transistors (MOSHEMTs) with Al2O3 as the gate oxide were investigated. The InAlN/GaN MOSHEMTs were irradiated with doses ranging from 1×1013 to 1×1015cm–2 at a fixed energy of 5MeV. There was minimal damage induced in the two dimensional electron gas at the lowest irradiation dose with no measurable increase in sheet resistance, whereas a 9.7% increase of the sheet resistance was observed at the highest irradiation dose. By sharp contrast, all irradiation doses created more severe degradation in the Ohmic metal contacts, with increases of specificmore » contact resistance from 54% to 114% over the range of doses investigated. These resulted in source-drain current–voltage decreases ranging from 96 to 242 mA/mm over this dose range. The trap density determined from temperature dependent drain current subthreshold swing measurements increased from 1.6 × 1013 cm–2 V–1 for the reference MOSHEMTs to 6.7 × 1013 cm–2 V–1 for devices irradiated with the highest dose. In conclusion, the carrier removal rate was 1287 ± 64 cm–1, higher than the authors previously observed in AlGaN/GaN MOSHEMTs for the same proton energy and consistent with the lower average bond energy of the InAlN.« less

  20. Electron-electron scattering-induced channel hot electron injection in nanoscale n-channel metal-oxide-semiconductor field-effect-transistors with high-k/metal gate stacks

    SciTech Connect (OSTI)

    Tsai, Jyun-Yu; Liu, Kuan-Ju; Lu, Ying-Hsin; Liu, Xi-Wen; Chang, Ting-Chang; Chen, Ching-En; Ho, Szu-Han; Tseng, Tseung-Yuen; Cheng, Osbert; Huang, Cheng-Tung; Lu, Ching-Sen

    2014-10-06

    This work investigates electron-electron scattering (EES)-induced channel hot electron (CHE) injection in nanoscale n-channel metal-oxide-semiconductor field-effect-transistors (n-MOSFETs) with high-k/metal gate stacks. Many groups have proposed new models (i.e., single-particle and multiple-particle process) to well explain the hot carrier degradation in nanoscale devices and all mechanisms focused on Si-H bond dissociation at the Si/SiO{sub 2} interface. However, for high-k dielectric devices, experiment results show that the channel hot carrier trapping in the pre-existing high-k bulk defects is the main degradation mechanism. Therefore, we propose a model of EES-induced CHE injection to illustrate the trapping-dominant mechanism in nanoscale n-MOSFETs with high-k/metal gate stacks.

  1. Proton conducting sodium alginate electrolyte laterally coupled low-voltage oxide-based transistors

    SciTech Connect (OSTI)

    Liu, Yang Hui; Wan, Qing; Qiang Zhu, Li; Shi, Yi

    2014-03-31

    Solution-processed sodium alginate electrolyte film shows a high proton conductivity of ?5.5??10{sup ?3} S/cm and a high lateral electric-double-layer (EDL) capacitance of ?2.0??F/cm{sup 2} at room temperature with a relative humidity of 57%. Low-voltage in-plane-gate indium-zinc-oxide-based EDL transistors laterally gated by sodium alginate electrolytes are fabricated on glass substrates. The field-effect mobility, current ON/OFF ratio, and subthreshold swing of such EDL transistors are estimated to be 4.2 cm{sup 2} V{sup ?1} s{sup ?1}, 2.8??10{sup 6}, and 130?mV/decade, respectively. At last, a low-voltage driven resistor-load inverter is also demonstrated. Such in-plane-gate EDL transistors have potential applications in portable electronics and low-cost biosensors.

  2. Organic field-effect transistor nonvolatile memories utilizing sputtered C nanoparticles as nano-floating-gate

    SciTech Connect (OSTI)

    Liu, Jie; Liu, Chang-Hai; She, Xiao-Jian; Sun, Qi-Jun; Gao, Xu; Wang, Sui-Dong

    2014-10-20

    High-performance organic field-effect transistor nonvolatile memories have been achieved using sputtered C nanoparticles as the nano-floating-gate. The sputtered C nano-floating-gate is prepared with low-cost material and simple process, forming uniform and discrete charge trapping sites covered by a smooth and complete polystyrene layer. The devices show large memory window, excellent retention capability, and programming/reading/erasing/reading endurance. The sputtered C nano-floating-gate can effectively trap both holes and electrons, and it is demonstrated to be suitable for not only p-type but also n-type organic field-effect transistor nonvolatile memories.

  3. Coherent molecular transistor: Control through variation of the gate wave function

    SciTech Connect (OSTI)

    Ernzerhof, Matthias

    2014-03-21

    In quantum interference transistors (QUITs), the current through the device is controlled by variation of the gate component of the wave function that interferes with the wave function component joining the source and the sink. Initially, mesoscopic QUITs have been studied and more recently, QUITs at the molecular scale have been proposed and implemented. Typically, in these devices the gate lead is subjected to externally adjustable physical parameters that permit interference control through modifications of the gate wave function. Here, we present an alternative model of a molecular QUIT in which the gate wave function is directly considered as a variable and the transistor operation is discussed in terms of this variable. This implies that we specify the gate current as well as the phase of the gate wave function component and calculate the resulting current through the source-sink channel. Thus, we extend on prior works that focus on the phase of the gate wave function component as a control parameter while having zero or certain discrete values of the current. We address a large class of systems, including finite graphene flakes, and obtain analytic solutions for how the gate wave function controls the transistor.

  4. A hydrogel capsule as gate dielectric in flexible organic field-effect transistors

    SciTech Connect (OSTI)

    Dumitru, L. M.; Manoli, K.; Magliulo, M.; Torsi, L.; Ligonzo, T.; Palazzo, G.

    2015-01-01

    A jellified alginate based capsule serves as biocompatible and biodegradable electrolyte system to gate an organic field-effect transistor fabricated on a flexible substrate. Such a system allows operating thiophene based polymer transistors below 0.5 V through an electrical double layer formed across an ion-permeable polymeric electrolyte. Moreover, biological macro-molecules such as glucose-oxidase and streptavidin can enter into the gating capsules that serve also as delivery system. An enzymatic bio-reaction is shown to take place in the capsule and preliminary results on the measurement of the electronic responses promise for low-cost, low-power, flexible electronic bio-sensing applications using capsule-gated organic field-effect transistors.

  5. Dirac point and transconductance of top-gated graphene field-effect transistors operating at elevated temperature

    SciTech Connect (OSTI)

    Hopf, T.; Vassilevski, K. V., E-mail: k.vasilevskiy@ncl.ac.uk; Escobedo-Cousin, E.; King, P. J.; Wright, N. G.; O'Neill, A. G.; Horsfall, A. B.; Goss, J. P. [School of Electrical and Electronic Engineering, Newcastle University, Newcastle upon Tyne NE1 7RU (United Kingdom); Wells, G. H.; Hunt, M. R. C. [Department of Physics, Durham University, Durham DH1 3LE (United Kingdom)

    2014-10-21

    Top-gated graphene field-effect transistors (GFETs) have been fabricated using bilayer epitaxial graphene grown on the Si-face of 4H-SiC substrates by thermal decomposition of silicon carbide in high vacuum. Graphene films were characterized by Raman spectroscopy, Atomic Force Microscopy, Scanning Tunnelling Microscopy, and Hall measurements to estimate graphene thickness, morphology, and charge transport properties. A 27?nm thick Al?O? gate dielectric was grown by atomic layer deposition with an e-beam evaporated Al seed layer. Electrical characterization of the GFETs has been performed at operating temperatures up to 100?C limited by deterioration of the gate dielectric performance at higher temperatures. Devices displayed stable operation with the gate oxide dielectric strength exceeding 4.5 MV/cm at 100?C. Significant shifting of the charge neutrality point and an increase of the peak transconductance were observed in the GFETs as the operating temperature was elevated from room temperature to 100?C.

  6. Bottom-gate coplanar graphene transistors with enhanced graphene adhesion on atomic layer deposition Al{sub 2}O{sub 3}

    SciTech Connect (OSTI)

    Park, Dong-Wook; Mikael, Solomon; Chang, Tzu-Hsuan; Ma, Zhenqiang; Gong, Shaoqin

    2015-03-09

    A graphene transistor with a bottom-gate coplanar structure and an atomic layer deposition (ALD) aluminum oxide (Al{sub 2}O{sub 3}) gate dielectric is demonstrated. Wetting properties of ALD Al{sub 2}O{sub 3} under different deposition conditions are investigated by measuring the surface contact angle. It is observed that the relatively hydrophobic surface is suitable for adhesion between graphene and ALD Al{sub 2}O{sub 3}. To achieve hydrophobic surface of ALD Al{sub 2}O{sub 3}, a methyl group (CH{sub 3})-terminated deposition method has been developed and compared with a hydroxyl group (OH)-terminated deposition. Based on this approach, bottom-gate coplanar graphene field-effect transistors are fabricated and characterized. A post-thermal annealing process improves the performance of the transistors by enhancing the contacts between the source/drain metal and graphene. The fabricated transistor shows an I{sub on}/I{sub off} ratio, maximum transconductance, and field-effect mobility of 4.04, 20.1??S at V{sub D}?=?0.1?V, and 249.5?cm{sup 2}/Vs, respectively.

  7. Top-gate organic depletion and inversion transistors with doped channel and injection contact

    SciTech Connect (OSTI)

    Liu, Xuhai; Kasemann, Daniel Leo, Karl

    2015-03-09

    Organic field-effect transistors constitute a vibrant research field and open application perspectives in flexible electronics. For a commercial breakthrough, however, significant performance improvements are still needed, e.g., stable and high charge carrier mobility and on-off ratio, tunable threshold voltage, as well as integrability criteria such as n- and p-channel operation and top-gate architecture. Here, we show pentacene-based top-gate organic transistors operated in depletion and inversion regimes, realized by doping source and drain contacts as well as a thin layer of the transistor channel. By varying the doping concentration and the thickness of the doped channel, we control the position of the threshold voltage without degrading on-off ratio or mobility. Capacitance-voltage measurements show that an inversion channel can indeed be formed, e.g., an n-doped channel can be inverted to a p-type inversion channel with highly p-doped contacts. The Cytop polymer dielectric minimizes hysteresis, and the transistors can be biased for prolonged cycles without a shift of threshold voltage, indicating excellent operation stability.

  8. Gate controlled electronic transport in monolayer MoS{sub 2} field effect transistor

    SciTech Connect (OSTI)

    Zhou, Y. F.; Wang, B.; Yu, Y. J.; Wei, Y. D. E-mail: jianwang@hku.hk; Xian, H. M.; Wang, J. E-mail: jianwang@hku.hk

    2015-03-14

    The electronic spin and valley transport properties of a monolayer MoS{sub 2} are investigated using the non-equilibrium Green's function formalism combined with density functional theory. Due to the presence of strong Rashba spin orbit interaction (RSOI), the electronic valence bands of monolayer MoS{sub 2} are split into spin up and spin down Zeeman-like texture near the two inequivalent vertices K and K′ of the first Brillouin zone. When the gate voltage is applied in the scattering region, an additional strong RSOI is induced which generates an effective magnetic field. As a result, electron spin precession occurs along the effective magnetic field, which is controlled by the gate voltage. This, in turn, causes the oscillation of conductance as a function of the magnitude of the gate voltage and the length of the gate region. This current modulation due to the spin precession shows the essential feature of the long sought Datta-Das field effect transistor (FET). From our results, the oscillation periods for the gate voltage and gate length are found to be approximately 2.2 V and 20.03a{sub B} (a{sub B} is Bohr radius), respectively. These observations can be understood by a simple spin precessing model and indicate that the electron behaviors in monolayer MoS{sub 2} FET are both spin and valley related and can easily be controlled by the gate.

  9. High-performance carbon-nanotube-based complementary field-effect-transistors and integrated circuits with yttrium oxide

    SciTech Connect (OSTI)

    Liang, Shibo; Zhang, Zhiyong Si, Jia; Zhong, Donglai; Peng, Lian-Mao

    2014-08-11

    High-performance p-type carbon nanotube (CNT) transistors utilizing yttrium oxide as gate dielectric are presented by optimizing oxidization and annealing processes. Complementary metal-oxide-semiconductor (CMOS) field-effect-transistors (FETs) are then fabricated on CNTs, and the p- and n-type devices exhibit symmetrical high performances, especially with low threshold voltage near to zero. The corresponding CMOS CNT inverter is demonstrated to operate at an ultra-low supply voltage down to 0.2?V, while displaying sufficient voltage gain, high noise margin, and low power consumption. Yttrium oxide is proven to be a competitive gate dielectric for constructing high-performance CNT CMOS FETs and integrated circuits.

  10. Effect of proton irradiation energy on AlGaN/GaN metal-oxide semiconductor high electron mobility transistors

    DOE Public Access Gateway for Energy & Science Beta (PAGES Beta)

    Ahn, S.; Dong, C.; Zhu, W.; Kim, B. -j.; Hwang, Ya-Hsi; Ren, F.; Pearton, S. J.; Yang, Gwangseok; Kim, J.; Patrick, Erin; et al

    2015-08-18

    The effects of proton irradiation energy on dc characteristics of AlGaN/GaN metal-oxide semiconductor high electron mobility transistors (MOSHEMTs) using Al2O3 as the gate dielectric were studied. Al2O3/AlGaN/GaN MOSHEMTs were irradiated with a fixed proton dose of 5 × 1015 cm-2 at different energies of 5, 10, or 15 MeV. More degradation of the device dc characteristics was observed for lower irradiation energy due to the larger amount of nonionizing energy loss in the active region of the MOSHEMTs under these conditions. The reductions in saturation current were 95.3%, 68.3%, and 59.8% and reductions in maximum transconductance were 88%, 54.4%, andmore » 40.7% after 5, 10, and 15 MeV proton irradiation, respectively. Both forward and reverse gate leakage current were reduced more than one order of magnitude after irradiation. The carrier removal rates for the irradiation energies employed in this study were in the range of 127–289 cm-1. These are similar to the values reported for conventional metal-gate high-electron mobility transistors under the same conditions and show that the gate dielectric does not affect the response to proton irradiation for these energies.« less

  11. Direct probing of electron and hole trapping into nano-floating-gate in organic field-effect transistor nonvolatile memories

    SciTech Connect (OSTI)

    Cui, Ze-Qun; Wang, Shun; Chen, Jian-Mei; Gao, Xu; Dong, Bin E-mail: chilf@suda.edu.cn Chi, Li-Feng E-mail: chilf@suda.edu.cn Wang, Sui-Dong E-mail: chilf@suda.edu.cn

    2015-03-23

    Electron and hole trapping into the nano-floating-gate of a pentacene-based organic field-effect transistor nonvolatile memory is directly probed by Kelvin probe force microscopy. The probing is straightforward and non-destructive. The measured surface potential change can quantitatively profile the charge trapping, and the surface characterization results are in good accord with the corresponding device behavior. Both electrons and holes can be trapped into the nano-floating-gate, with a preference of electron trapping than hole trapping. The trapped charge quantity has an approximately linear relation with the programming/erasing gate bias, indicating that the charge trapping in the device is a field-controlled process.

  12. Physics of gate leakage current in N-polar InAlN/GaN heterojunction field effect transistors

    SciTech Connect (OSTI)

    Goswami, Arunesh; Trew, Robert J.; Bilbro, Griff L.

    2014-10-28

    A physics based model of the gate leakage current in N-polar InAlN/GaN heterojunction field effect transistors is demonstrated. The model is based on the space charge limited current flow dominated by the effects of deep traps in the InAlN surface layer. The model predicts accurately the gate-leakage measurement data of the N-polar InAlN/GaN device with InAlN cap layer. In the pinch-off state, the gate leakage current conduction through the surface of the device in the drain access region dominates the current flow through the two dimensional electron gas channel. One deep trap level and two levels of shallow traps are extracted by fitting the model results with measurement data.

  13. Looking at Transistor Gate Oxide Formation in Real Time

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Hamburg (Germany); Overseas Advanced Education and Research Program from the Ministry of Education, Culture, Sports, Science, and Technology of Japan; Creative Research...

  14. Looking at Transistor Gate Oxide Formation in Real Time

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    University, Japan); B.S. Mun (Hanyang University, Korea, and ALS); M. Rossi, and Z. Hussain (ALS); P.N. Ross Jr. (Berkeley Lab); C.S. Fadley (University of California at...

  15. Looking at Transistor Gate Oxide Formation in Real Time

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Advanced Education and Research Program from the Ministry of Education, Culture, Sports, Science, and Technology of Japan; Creative Research Initiatives of MOSTKOSEF...

  16. Light-induced hysteresis and recovery behaviors in photochemically activated solution-processed metal-oxide thin-film transistors

    SciTech Connect (OSTI)

    Jo, Jeong-Wan; Park, Sung Kyu E-mail: skpark@cau.ac.kr; Kim, Yong-Hoon E-mail: skpark@cau.ac.kr

    2014-07-28

    In this report, photo-induced hysteresis, threshold voltage (V{sub T}) shift, and recovery behaviors in photochemically activated solution-processed indium-gallium-zinc oxide (IGZO) thin-film transistors (TFTs) are investigated. It was observed that a white light illumination caused negative V{sub T} shift along with creation of clockwise hysteresis in electrical characteristics which can be attributed to photo-generated doubly ionized oxygen vacancies at the semiconductor/gate dielectric interface. More importantly, the photochemically activated IGZO TFTs showed much reduced overall V{sub T} shift compared to thermally annealed TFTs. Reduced number of donor-like interface states creation under light illumination and more facile neutralization of ionized oxygen vacancies by electron capture under positive gate potential are claimed to be the origin of the less V{sub T} shift in photochemically activated TFTs.

  17. Palladium nanoparticle decorated silicon nanowire field-effect transistor with side-gates for hydrogen gas detection

    SciTech Connect (OSTI)

    Ahn, Jae-Hyuk; Yun, Jeonghoon; Park, Inkyu; KI for the NanoCentury, KAIST, Daejeon 305-701; Mobile Sensor and IT Convergence Center, KAIST, Daejeon 305-701 ; Choi, Yang-Kyu

    2014-01-06

    A silicon nanowire field-effect transistor (SiNW FET) with local side-gates and Pd surface decoration is demonstrated for hydrogen (H{sub 2}) detection. The SiNW FETs are fabricated by top-down method and functionalized with palladium nanoparticles (PdNPs) through electron beam evaporation for H{sub 2} detection. The drain current of the PdNP-decorated device reversibly responds to H{sub 2} at different concentrations. The local side-gates allow individual addressing of each sensor and enhance the sensitivity by adjusting the working region to the subthreshold regime. A control experiment using a non-functionalized device verifies that the hydrogen-sensitivity is originated from the PdNPs functionalized on the SiNW surface.

  18. Thin Film Transistors On Plastic Substrates

    DOE Patents [OSTI]

    Carey, Paul G.; Smith, Patrick M.; Sigmon, Thomas W.; Aceves, Randy C.

    2004-01-20

    A process for formation of thin film transistors (TFTs) on plastic substrates replaces standard thin film transistor fabrication techniques, and uses sufficiently lower processing temperatures so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The silicon based thin film transistor produced by the process includes a low temperature substrate incapable of withstanding sustained processing temperatures greater than about 250.degree. C., an insulating layer on the substrate, a layer of silicon on the insulating layer having sections of doped silicon, undoped silicon, and poly-silicon, a gate dielectric layer on the layer of silicon, a layer of gate metal on the dielectric layer, a layer of oxide on sections of the layer of silicon and the layer of gate metal, and metal contacts on sections of the layer of silicon and layer of gate metal defining source, gate, and drain contacts, and interconnects.

  19. Gate-modulated conductance of few-layer WSe{sub 2} field-effect transistors in the subgap regime: Schottky barrier transistor and subgap impurity states

    SciTech Connect (OSTI)

    Wang, Junjie; Feng, Simin; Rhodes, Daniel; Balicas, Luis; Nguyen, Minh An T.; Watanabe, K.; Taniguchi, T.; Mallouk, Thomas E.; Terrones, Mauricio; Zhu, J.

    2015-04-13

    Two key subjects stand out in the pursuit of semiconductor research: material quality and contact technology. The fledging field of atomically thin transition metal dichalcogenides (TMDCs) faces a number of challenges in both efforts. This work attempts to establish a connection between the two by examining the gate-dependent conductance of few-layer (1-5L) WSe{sub 2} field effect devices. Measurements and modeling of the subgap regime reveal Schottky barrier transistor behavior. We show that transmission through the contact barrier is dominated by thermionic field emission (TFE) at room temperature, despite the lack of intentional doping. The TFE process arises due to a large number of subgap impurity states, the presence of which also leads to high mobility edge carrier densities. The density of states of such impurity states is self-consistently determined to be approximately 1–2 × 10{sup 13}/cm{sup 2}/eV in our devices. We demonstrate that substrate is unlikely to be a major source of the impurity states and suspect that lattice defects within the material itself are primarily responsible. Our experiments provide key information to advance the quality and understanding of TMDC materials and electrical devices.

  20. Charging dynamics of a floating gate transistor with site-controlled quantum dots

    SciTech Connect (OSTI)

    Maier, P. Hartmann, F.; Emmerling, M.; Schneider, C.; Hfling, S.; Kamp, M.; Worschech, L.

    2014-08-04

    A quantum dot memory based on a GaAs/AlGaAs quantum wire with site-controlled InAs quantum dots was realized by means of molecular beam epitaxy and etching techniques. By sampling of different gate voltage sweeps for the determination of charging and discharging thresholds, it was found that discharging takes place at short time scales of ?s, whereas several seconds of waiting times within a distinct negative gate voltage range were needed to charge the quantum dots. Such quantum dot structures have thus the potential to implement logic functions comprising charge and time dependent ingredients such as counting of signals or learning rules.

  1. High performance TiN gate contact on AlGaN/GaN transistor using a mechanically strain induced P-doping

    SciTech Connect (OSTI)

    Soltani, A. Rousseau, M.; Gerbedoen, J.-C.; Bourzgui, N.; Mattalah, M.; Bonanno, P. L.; Ougazzaden, A.; Telia, A.; Patriarche, G.; BenMoussa, A.

    2014-06-09

    High performance titanium nitride sub-100 nm rectifying contact, deposited by sputtering on AlGaN/GaN high electron mobility transistors, shows a reverse leakage current as low as 38 pA/mm at V{sub GS} = −40 V and a Schottky barrier height of 0.95 eV. Based on structural characterization and 3D simulations, it is found that the polarization gradient induced by the gate metallization forms a P-type pseudo-doping region under the gate between the tensile surface and the compressively strained bulk AlGaN barrier layer. The strain induced by the gate metallization can compensate for the piezoelectric component. As a result, the gate contact can operate at temperatures as high as 700 °C and can withstand a large reverse bias of up to −100 V, which is interesting for high-performance transistors dedicated to power applications.

  2. Current collapse imaging of Schottky gate AlGaN/GaN high electron mobility transistors by electric field-induced optical second-harmonic generation measurement

    SciTech Connect (OSTI)

    Katsuno, Takashi Ishikawa, Tsuyoshi; Ueda, Hiroyuki; Uesugi, Tsutomu; Manaka, Takaaki; Iwamoto, Mitsumasa

    2014-06-23

    Two-dimensional current collapse imaging of a Schottky gate AlGaN/GaN high electron mobility transistor device was achieved by optical electric field-induced second-harmonic generation (EFISHG) measurements. EFISHG measurements can detect the electric field produced by carriers trapped in the on-state of the device, which leads to current collapse. Immediately after (e.g., 1, 100, or 800 μs) the completion of drain-stress voltage (200 V) in the off-state, the second-harmonic (SH) signals appeared within 2 μm from the gate edge on the drain electrode. The SH signal intensity became weak with time, which suggests that the trapped carriers are emitted from the trap sites. The SH signal location supports the well-known virtual gate model for current collapse.

  3. L{sub g}?=?100?nm In{sub 0.7}Ga{sub 0.3}As quantum well metal-oxide semiconductor field-effect transistors with atomic layer deposited beryllium oxide as interfacial layer

    SciTech Connect (OSTI)

    Koh, D., E-mail: dh.koh@utexas.edu, E-mail: Taewoo.Kim@sematech.org [Department of Electrical and Computer Engineering, Microelectronics Research Center, The University of Texas at Austin, Austin, Texas 78758 (United States); SEMATECH, Inc., Albany, New York 12203 (United States); Kwon, H. M. [Department of Electronics Engineering, Chungnam National University, Daejeon 305-764 (Korea, Republic of); Kim, T.-W., E-mail: dh.koh@utexas.edu, E-mail: Taewoo.Kim@sematech.org; Veksler, D.; Gilmer, D.; Kirsch, P. D. [SEMATECH, Inc., Albany, New York 12203 (United States); Kim, D.-H. [SEMATECH, Inc., Albany, New York 12203 (United States); GLOBALFOUNDRIES, Malta, New York 12020 (United States); Hudnall, Todd W. [Department of Chemistry and Biochemistry, Texas State University, San Marcos, Texas, 78666 (United States); Bielawski, Christopher W. [Department of Chemistry and Biochemistry, The University of Texas at Austin, Austin, Texas 78712 (United States); Maszara, W. [GLOBALFOUNDRIES, Santa Clara, California 95054 (United States); Banerjee, S. K. [Department of Electrical and Computer Engineering, Microelectronics Research Center, The University of Texas at Austin, Austin, Texas 78758 (United States)

    2014-04-21

    In this study, we have fabricated nanometer-scale channel length quantum-well (QW) metal-oxide-semiconductor field effect transistors (MOSFETs) incorporating beryllium oxide (BeO) as an interfacial layer. BeO has high thermal stability, excellent electrical insulating characteristics, and a large band-gap, which make it an attractive candidate for use as a gate dielectric in making MOSFETs. BeO can also act as a good diffusion barrier to oxygen owing to its small atomic bonding length. In this work, we have fabricated In{sub 0.53}Ga{sub 0.47}As MOS capacitors with BeO and Al{sub 2}O{sub 3} and compared their electrical characteristics. As interface passivation layer, BeO/HfO{sub 2} bilayer gate stack presented effective oxide thickness less 1 nm. Furthermore, we have demonstrated In{sub 0.7}Ga{sub 0.3}As QW MOSFETs with a BeO/HfO{sub 2} dielectric, showing a sub-threshold slope of 100?mV/dec, and a transconductance (g{sub m,max}) of 1.1 mS/?m, while displaying low values of gate leakage current. These results highlight the potential of atomic layer deposited BeO for use as a gate dielectric or interface passivation layer for IIIV MOSFETs at the 7?nm technology node and/or beyond.

  4. Radiation-hardened transistor and integrated circuit

    DOE Patents [OSTI]

    Ma, Kwok K.

    2007-11-20

    A composite transistor is disclosed for use in radiation hardening a CMOS IC formed on an SOI or bulk semiconductor substrate. The composite transistor has a circuit transistor and a blocking transistor connected in series with a common gate connection. A body terminal of the blocking transistor is connected only to a source terminal thereof, and to no other connection point. The blocking transistor acts to prevent a single-event transient (SET) occurring in the circuit transistor from being coupled outside the composite transistor. Similarly, when a SET occurs in the blocking transistor, the circuit transistor prevents the SET from being coupled outside the composite transistor. N-type and P-type composite transistors can be used for each and every transistor in the CMOS IC to radiation harden the IC, and can be used to form inverters and transmission gates which are the building blocks of CMOS ICs.

  5. Negative differential transconductance in silicon quantum well metal-oxide-semiconductor field effect/bipolar hybrid transistors

    SciTech Connect (OSTI)

    Naquin, Clint; Lee, Mark; Edwards, Hal; Mathur, Guru; Chatterjee, Tathagata; Maggio, Ken

    2014-11-24

    Introducing explicit quantum transport into Si transistors in a manner amenable to industrial fabrication has proven challenging. Hybrid field-effect/bipolar Si transistors fabricated on an industrial 45 nm process line are shown to demonstrate explicit quantum transport signatures. These transistors incorporate a lateral ion implantation-defined quantum well (QW) whose potential depth is controlled by a gate voltage (V{sub G}). Quantum transport in the form of negative differential transconductance (NDTC) is observed to temperatures >200 K. The NDTC is tied to a non-monotonic dependence of bipolar current gain on V{sub G} that reduces drain-source current through the QW. These devices establish the feasibility of exploiting quantum transport to transform the performance horizons of Si devices fabricated in an industrially scalable manner.

  6. Understanding the Structure of High-K Gate Oxides - Oral Presentation

    SciTech Connect (OSTI)

    Miranda, Andre

    2015-08-25

    Hafnium Oxide (HfO2) amorphous thin films are being used as gate oxides in transistors because of their high dielectric constant (κ) over Silicon Dioxide. The present study looks to find the atomic structure of HfO2 thin films which hasn’t been done with the technique of this study. In this study, two HfO2 samples were studied. One sample was made with thermal atomic layer deposition (ALD) on top of a Chromium and Gold layer on a silicon wafer. The second sample was made with plasma ALD on top of a Chromium and Gold layer on a Silicon wafer. Both films were deposited at a thickness of 50nm. To obtain atomic structure information, Grazing Incidence X-ray diffraction (GIXRD) was carried out on the HfO2 samples. Because of this, absorption, footprint, polarization, and dead time corrections were applied to the scattering intensity data collected. The scattering curves displayed a difference in structure between the ALD processes. The plasma ALD sample showed the broad peak characteristic of an amorphous structure whereas the thermal ALD sample showed an amorphous structure with characteristics of crystalline materials. This appears to suggest that the thermal process results in a mostly amorphous material with crystallites within. Further, the scattering intensity data was used to calculate a pair distribution function (PDF) to show more atomic structure. The PDF showed atom distances in the plasma ALD sample had structure up to 10 Å, while the thermal ALD sample showed the same structure below 10 Å. This structure that shows up below 10 Å matches the bond distances of HfO2 published in literature. The PDF for the thermal ALD sample also showed peaks up to 20 Å, suggesting repeating atomic spacing outside the HfO2 molecule in the sample. This appears to suggest that there is some crystalline structure within the thermal ALD sample.

  7. Effect of tunnel injection through the Schottky gate on the static and noise behavior of GaInAs/AlInAs high electron mobility transistor

    SciTech Connect (OSTI)

    Moro-Melgar, Diego; Mateos, Javier Gonzlez, Toms Vasallo, Beatriz G.

    2014-12-21

    By using a Monte Carlo simulator, the influence of the tunnel injection through the Schottky contact at the gate electrode of a GaInAs/AlInAs High Electron Mobility Transistor (HEMT) has been studied in terms of the static and noise performance. The method used to characterize the quantum tunnel current has been the Wentzel-Kramers-Brillouin (WKB) approach. The possibility of taking into account the influence of the image charge effect in the potential barrier height has been included as well. Regarding the static behavior, tunnel injection leads to a decrease in the drain current I{sub D} due to an enhancement of the potential barrier controlling the carrier transport through the channel. However, the pinch-off is degraded due to the tunneling current. Regarding the noise behavior, since the fluctuations in the potential barrier height caused by the tunnel-injected electrons are strongly coupled with the drain current fluctuations, a significant increase in the drain-current noise takes place, even when the tunnel effect is hardly noticeable in the static I-V characteristics, fact that must be taken into account when designing scaled HEMT for low-noise applications. In addition, tunnel injection leads to the appearance of full shot noise in the gate current.

  8. Transfer-free graphene synthesis on sapphire by catalyst metal agglomeration technique and demonstration of top-gate field-effect transistors

    SciTech Connect (OSTI)

    Miyoshi, Makoto Arima, Yukinori; Kubo, Toshiharu; Egawa, Takashi; Mizuno, Masaya; Soga, Tetsuo

    2015-08-17

    Transfer-free graphene synthesis was performed on sapphire substrates by using the catalyst metal agglomeration technique, and the graphene film quality was compared to that synthesized on sputtered SiO{sub 2}/Si substrates. Raman scattering measurements indicated that the graphene film on sapphire has better structural qualities than that on sputtered SiO{sub 2}/Si substrates. The cross-sectional transmission microscopic study also revealed that the film flatness was drastically improved by using sapphire substrates instead of sputtered SiO{sub 2}/Si substrates. These quality improvements seemed to be due the chemical and thermal stabilities of sapphire. Top-gate field-effect transistors were fabricated using the graphene films on sapphire, and it was confirmed that their drain current can be modulated with applied gate voltages. The maximum field-effect mobilities were estimated to be 720 cm{sup 2}/V s for electrons and 880 cm{sup 2}/V s for holes, respectively.

  9. Silicon on insulator self-aligned transistors

    DOE Patents [OSTI]

    McCarthy, Anthony M.

    2003-11-18

    A method for fabricating thin-film single-crystal silicon-on-insulator (SOI) self-aligned transistors. Standard processing of silicon substrates is used to fabricate the transistors. Physical spaces, between the source and gate, and the drain and gate, introduced by etching the polysilicon gate material, are used to provide connecting implants (bridges) which allow the transistor to perform normally. After completion of the silicon substrate processing, the silicon wafer is bonded to an insulator (glass) substrate, and the silicon substrate is removed leaving the transistors on the insulator (glass) substrate. Transistors fabricated by this method may be utilized, for example, in flat panel displays, etc.

  10. Impact of total ionizing dose irradiation on electrical property of ferroelectric-gate field-effect transistor

    SciTech Connect (OSTI)

    Yan, S. A.; Tang, M. H. Xiao, Y. G.; Zhang, W. L.; Ding, H.; Chen, J. W.; Zhou, Y. C.; Xiong, Y.; Li, Z.; Zhao, W.; Guo, H. X.

    2014-05-28

    P-type channel metal-ferroelectric-insulator-silicon field-effect transistors (FETs) with a 300?nm thick SrBi{sub 2}Ta{sub 2}O{sub 9} ferroelectric film and a 10?nm thick HfTaO layer on silicon substrate were fabricated and characterized. The prepared FeFETs were then subjected to {sup 60}Co gamma irradiation in steps of three dose levels. Irradiation-induced degradation on electrical characteristics of the fabricated FeFETs was observed after 1 week annealing at room temperature. The possible irradiation-induced degradation mechanisms were discussed and simulated. All the irradiation experiment results indicated that the stability and reliability of the fabricated FeFETs for nonvolatile memory applications will become uncontrollable under strong irradiation dose and/or long irradiation time.

  11. Ferroelectric switching of poly(vinylidene difluoride-trifluoroethylene) in metal-ferroelectric-semiconductor non-volatile memories with an amorphous oxide semiconductor

    SciTech Connect (OSTI)

    Gelinck, G. H.; Breemen, A. J. J. M. van; Cobb, B.

    2015-03-02

    Ferroelectric polarization switching of poly(vinylidene difluoride-trifluoroethylene) is investigated in different thin-film device structures, ranging from simple capacitors to dual-gate thin-film transistors (TFT). Indium gallium zinc oxide, a high mobility amorphous oxide material, is used as semiconductor. We find that the ferroelectric can be polarized in both directions in the metal-ferroelectric-semiconductor (MFS) structure and in the dual-gate TFT under certain biasing conditions, but not in the single-gate thin-film transistors. These results disprove the common belief that MFS structures serve as a good model system for ferroelectric polarization switching in thin-film transistors.

  12. Experimental study on vertical scaling of InAs-on-insulator metal-oxide-semiconductor field-effect transistors

    SciTech Connect (OSTI)

    Kim, SangHyeon E-mail: sh-kim@kist.re.kr; Yokoyama, Masafumi; Nakane, Ryosho; Takenaka, Mitsuru; Takagi, Shinichi; Ichikawa, Osamu; Osada, Takenori; Hata, Masahiko

    2014-06-30

    We have investigated effects of the vertical scaling on electrical properties in extremely thin-body InAs-on-insulator (-OI) metal-oxide-semiconductor field-effect transistors (MOSFETs). It is found that the body thickness (T{sub body}) scaling provides better short channel effect (SCE) control, whereas the T{sub body} scaling also causes the reduction of the mobility limited by channel thickness fluctuation (δT{sub body}) scattering (μ{sub fluctuation}). Also, in order to achieve better SCEs control, the thickness of InAs channel layer (T{sub channel}) scaling is more favorable than the thickness of MOS interface buffer layer (T{sub buffer}) scaling from a viewpoint of a balance between SCEs control and μ{sub fluctuation} reduction. These results indicate necessity of quantum well channel structure in InAs-OI MOSFETs and these should be considered in future transistor design.

  13. Superconducting transistor

    DOE Patents [OSTI]

    Gray, Kenneth E.

    1979-01-01

    A superconducting transistor is formed by disposing three thin films of superconducting material in a planar parallel arrangement and insulating the films from each other by layers of insulating oxides to form two tunnel junctions. One junction is biased above twice the superconducting energy gap and the other is biased at less than twice the superconducting energy gap. Injection of quasiparticles into the center film by one junction provides a current gain in the second junction.

  14. Ionizing radiation induced leakage current on ultra-thin gate oxides

    SciTech Connect (OSTI)

    Scarpa, A.; Paccagnella, A.; Montera, F.; Ghibaudo, G.; Pananakakis, G.; Fuochi, P.G.

    1997-12-01

    MOS capacitors with a 4.4 nm thick gate oxide have been exposed to {gamma} radiation from a Co{sup 60} source. As a result, the authors have measured a stable leakage current at fields lower than those required for Fowler-Nordheim tunneling. This Radiation Induced Leakage Current (RILC) is similar to the usual Stress Induced Leakage Currents (SILC) observed after electrical stresses of MOS devices. They have verified that these two currents share the same dependence on the oxide field, and the RILC contribution can be normalized to an equivalent injected charge for Constant Current Stresses. They have also considered the dependence of the RILC from the cumulative radiation dose, and from the applied bias during irradiation, suggesting a correlation between RILC and the distribution of trapped holes and neutral levels in the oxide layer.

  15. Transistor-based particle detection systems and methods

    DOE Patents [OSTI]

    Jain, Ankit; Nair, Pradeep R.; Alam, Muhammad Ashraful

    2015-06-09

    Transistor-based particle detection systems and methods may be configured to detect charged and non-charged particles. Such systems may include a supporting structure contacting a gate of a transistor and separating the gate from a dielectric of the transistor, and the transistor may have a near pull-in bias and a sub-threshold region bias to facilitate particle detection. The transistor may be configured to change current flow through the transistor in response to a change in stiffness of the gate caused by securing of a particle to the gate, and the transistor-based particle detection system may configured to detect the non-charged particle at least from the change in current flow.

  16. Detection of saliva-range glucose concentrations using organic thin-film transistors

    SciTech Connect (OSTI)

    Elkington, D.; Belcher, W. J.; Dastoor, P. C.; Zhou, X. J.

    2014-07-28

    We describe the development of a glucose sensor through direct incorporation of an enzyme (glucose oxidase) into the gate of an organic thin film transistor (OTFT). We show that glucose diffusion is the key determinant of the device response time and present a mechanism of glucose sensing in these devices that involves protonic doping of the transistor channel via enzymatic oxidation of glucose. The integrated OTFT sensor is sensitive across 4 decades of glucose concentration; a range that encompasses both the blood and salivary glucose concentration levels. As such, this work acts as a proof-of-concept for low-cost printed biosensors for salivary glucose.

  17. Enhanced stability against bias-stress of metal-oxide thin film transistors deposited at elevated temperatures

    SciTech Connect (OSTI)

    Fakhri, M.; Goerrn, P.; Riedl, T. [Institute of Electronic Devices, University of Wuppertal, Rainer-Gruenter-St. 21, 42119 Wuppertal (Germany); Weimann, T.; Hinze, P. [Physikalisch-Technische Bundesanstalt Braunschweig, Bundesallee 100, 38116 Braunschweig (Germany)

    2011-09-19

    Transparent zinc-tin-oxide (ZTO) thin film transistors (TFTs) have been prepared by DC magnetron sputtering. Compared to reference devices with a channel deposited at room temperature and subsequently annealing at 400 deg. C, a substantially enhanced stability against bias stress is evidenced for devices with in-situ substrate heating during deposition (400 deg. C). A reduced density of sub-gap defect states in TFT channels prepared with in-situ substrate heating is found. Concomitantly, a reduced sensitivity to the adsorption of ambient gases is evidenced for the in-situ heated devices. This finding is of particular importance for an application as driver electronics for organic light emitting diode displays.

  18. Method for double-sided processing of thin film transistors

    DOE Patents [OSTI]

    Yuan, Hao-Chih; Wang, Guogong; Eriksson, Mark A.; Evans, Paul G.; Lagally, Max G.; Ma, Zhenqiang

    2008-04-08

    This invention provides methods for fabricating thin film electronic devices with both front- and backside processing capabilities. Using these methods, high temperature processing steps may be carried out during both frontside and backside processing. The methods are well-suited for fabricating back-gate and double-gate field effect transistors, double-sided bipolar transistors and 3D integrated circuits.

  19. Polarization induced doped transistor

    DOE Patents [OSTI]

    Xing, Huili; Jena, Debdeep; Nomoto, Kazuki; Song, Bo; Zhu, Mingda; Hu, Zongyang

    2016-06-07

    A nitride-based field effect transistor (FET) comprises a compositionally graded and polarization induced doped p-layer underlying at least one gate contact and a compositionally graded and doped n-channel underlying a source contact. The n-channel is converted from the p-layer to the n-channel by ion implantation, a buffer underlies the doped p-layer and the n-channel, and a drain underlies the buffer.

  20. Rapid low-temperature processing of metal-oxide thin film transistors with combined far ultraviolet and thermal annealing

    SciTech Connect (OSTI)

    Leppniemi, J. Ojanper, K.; Kololuoma, T.; Huttunen, O.-H.; Majumdar, H.; Alastalo, A.; Dahl, J.; Tuominen, M.; Laukkanen, P.

    2014-09-15

    We propose a combined far ultraviolet (FUV) and thermal annealing method of metal-nitrate-based precursor solutions that allows efficient conversion of the precursor to metal-oxide semiconductor (indium zinc oxide, IZO, and indium oxide, In{sub 2}O{sub 3}) both at low-temperature and in short processing time. The combined annealing method enables a reduction of more than 100?C in annealing temperature when compared to thermally annealed reference thin-film transistor (TFT) devices of similar performance. Amorphous IZO films annealed at 250?C with FUV for 5?min yield enhancement-mode TFTs with saturation mobility of ?1?cm{sup 2}/(Vs). Amorphous In{sub 2}O{sub 3} films annealed for 15?min with FUV at temperatures of 180?C and 200?C yield TFTs with low-hysteresis and saturation mobility of 3.2?cm{sup 2}/(Vs) and 7.5?cm{sup 2}/(Vs), respectively. The precursor condensation process is clarified with x-ray photoelectron spectroscopy measurements. Introducing the FUV irradiation at 160?nm expedites the condensation process via in situ hydroxyl radical generation that results in the rapid formation of a continuous metal-oxygen-metal structure in the film. The results of this paper are relevant in order to upscale printed electronics fabrication to production-scale roll-to-roll environments.

  1. Comparison of gate dielectric plasma damage from plasma-enhanced atomic layer deposited and magnetron sputtered TiN metal gates

    SciTech Connect (OSTI)

    Brennan, Christopher J.; Neumann, Christopher M.; Vitale, Steven A.

    2015-07-28

    Fully depleted silicon-on-insulator transistors were fabricated using two different metal gate deposition mechanisms to compare plasma damage effects on gate oxide quality. Devices fabricated with both plasma-enhanced atomic-layer-deposited (PE-ALD) TiN gates and magnetron plasma sputtered TiN gates showed very good electrostatics and short-channel characteristics. However, the gate oxide quality was markedly better for PE-ALD TiN. A significant reduction in interface state density was inferred from capacitance-voltage measurements as well as a 1200× reduction in gate leakage current. A high-power magnetron plasma source produces a much higher energetic ion and vacuum ultra-violet (VUV) photon flux to the wafer compared to a low-power inductively coupled PE-ALD source. The ion and VUV photons produce defect states in the bulk of the gate oxide as well as at the oxide-silicon interface, causing higher leakage and potential reliability degradation.

  2. Low-temperature formation of high-quality gate oxide by ultraviolet irradiation on spin-on-glass

    SciTech Connect (OSTI)

    Usuda, R.; Uchida, K.; Nozaki, S.

    2015-11-02

    Although a UV cure was found to effectively convert a perhydropolysilazane (PHPS) spin-on-glass film into a dense SiO{sub x} film at low temperature, the electrical characteristics were never reported in order to recommend the use of PHPS as a gate-oxide material that can be formed at low temperature. We have formed a high-quality gate oxide by UV irradiation on the PHPS film, and obtained an interface midgap trap density of 3.4 × 10{sup 11 }cm{sup −2} eV{sup −1} by the UV wet oxidation and UV post-metallization annealing (PMA), at a temperature as low as 160 °C. In contrast to the UV irradiation using short-wavelength UV light, which is well known to enhance oxidation by the production of the excited states of oxygen, the UV irradiation was carried out using longer-wavelength UV light from a metal halide lamp. The UV irradiation during the wet oxidation of the PHPS film generates electron-hole pairs. The electrons ionize the H{sub 2}O molecules and facilitate dissociation of the molecules into H and OH{sup −}. The OH{sup −} ions are highly reactive with Si and improve the stoichiometry of the oxide. The UV irradiation during the PMA excites the electrons from the accumulation layer, and the built-in electric field makes the electron injection into the oxide much easier. The electrons injected into the oxide recombine with the trapped holes, which have caused a large negative flat band voltage shift after the UV wet oxidation, and also ionize the H{sub 2}O molecules. The ionization results in the electron stimulated dissociation of H{sub 2}O molecules and the decreased interface trap density.

  3. The impact of carbon sp{sup 2} fraction of reduced graphene oxide on the performance of reduced graphene oxide contacted organic transistors

    SciTech Connect (OSTI)

    Kang, Narae; Khondaker, Saiful I.

    2014-12-01

    One of the major bottlenecks in fabricating high performance organic field effect transistors (OFETs) is a large interfacial contact barrier between metal electrodes and organic semiconductors (OSCs) which makes the charge injection inefficient. Recently, reduced graphene oxide (RGO) has been suggested as an alternative electrode material for OFETs. RGO has tunable electronic properties and its conductivity can be varied by several orders of magnitude by varying the carbon sp{sup 2} fraction. However, whether the sp{sup 2} fraction of RGO in the electrode affects the performance of the fabricated OFETs is yet to be investigated. In this study, we demonstrate that the performance of OFETs with pentacene as OSC and RGO as electrode can be continuously improved by increasing the carbon sp{sup 2} fraction of RGO. When compared to control palladium electrodes, the mobility of the OFETs shows an improvement of ∼200% for 61% sp{sup 2} fraction RGO, which further improves to ∼500% for 80% RGO electrode. Similar improvements were also observed in current on-off ratio, on-current, and transconductance. Our study suggests that, in addition to π-π interaction at RGO/pentacene interface, the tunable electronic properties of RGO electrode have a significant role in OFETs performance.

  4. Comprehensive study and design of scaled metal/high-k/Ge gate stacks with ultrathin aluminum oxide interlayers

    SciTech Connect (OSTI)

    Asahara, Ryohei; Hideshima, Iori; Oka, Hiroshi; Minoura, Yuya; Hosoi, Takuji Shimura, Takayoshi; Watanabe, Heiji; Ogawa, Shingo; Yoshigoe, Akitaka; Teraoka, Yuden

    2015-06-08

    Advanced metal/high-k/Ge gate stacks with a sub-nm equivalent oxide thickness (EOT) and improved interface properties were demonstrated by controlling interface reactions using ultrathin aluminum oxide (AlO{sub x}) interlayers. A step-by-step in situ procedure by deposition of AlO{sub x} and hafnium oxide (HfO{sub x}) layers on Ge and subsequent plasma oxidation was conducted to fabricate Pt/HfO{sub 2}/AlO{sub x}/GeO{sub x}/Ge stacked structures. Comprehensive study by means of physical and electrical characterizations revealed distinct impacts of AlO{sub x} interlayers, plasma oxidation, and metal electrodes serving as capping layers on EOT scaling, improved interface quality, and thermal stability of the stacks. Aggressive EOT scaling down to 0.56 nm and very low interface state density of 2.4 × 10{sup 11 }cm{sup −2}eV{sup −1} with a sub-nm EOT and sufficient thermal stability were achieved by systematic process optimization.

  5. Transistors using crystalline silicon devices on glass

    DOE Patents [OSTI]

    McCarthy, Anthony M.

    1995-01-01

    A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed.

  6. Method of making self-aligned lightly-doped-drain structure for MOS transistors

    DOE Patents [OSTI]

    Weiner, Kurt H.; Carey, Paul G.

    2001-01-01

    A process for fabricating lightly-doped-drains (LDD) for short-channel metal oxide semiconductor (MOS) transistors. The process utilizes a pulsed laser process to incorporate the dopants, thus eliminating the prior oxide deposition and etching steps. During the process, the silicon in the source/drain region is melted by the laser energy. Impurities from the gas phase diffuse into the molten silicon to appropriately dope the source/drain regions. By controlling the energy of the laser, a lightly-doped-drain can be formed in one processing step. This is accomplished by first using a single high energy laser pulse to melt the silicon to a significant depth and thus the amount of dopants incorporated into the silicon is small. Furthermore, the dopants incorporated during this step diffuse to the edge of the MOS transistor gate structure. Next, many low energy laser pulses are used to heavily dope the source/drain silicon only in a very shallow region. Because of two-dimensional heat transfer at the MOS transistor gate edge, the low energy pulses are inset from the region initially doped by the high energy pulse. By computer control of the laser energy, the single high energy laser pulse and the subsequent low energy laser pulses are carried out in a single operational step to produce a self-aligned lightly-doped-drain-structure.

  7. Radiation induced leakage current and stress induced leakage current in ultra-thin gate oxides

    SciTech Connect (OSTI)

    Ceschia, M.; Paccagnella, A.; Cester, A.; Scarpa, A.; Ghidini, G.

    1998-12-01

    Low-field leakage current has been measured in thin oxides after exposure to ionizing radiation. This Radiation Induced Leakage Current (RILC) can be described as an inelastic tunneling process mediated by neutral traps in the oxide, with an energy loss of about 1 eV. The neutral trap distribution is influenced by the oxide field applied during irradiation, thus indicating that the precursors of the neutral defects are charged, likely being defects associated to trapped holes. The maximum leakage current is found under zero-field condition during irradiation, and it rapidly decreases as the field is enhanced, due to a displacement of the defect distribution across the oxide towards the cathodic interface. The RILC kinetics are linear with the cumulative dose, in contrast with the power law found on electrically stressed devices.

  8. Effects of low-temperature (120 °C) annealing on the carrier concentration and trap density in amorphous indium gallium zinc oxide thin film transistors

    SciTech Connect (OSTI)

    Kim, Jae-sung; Piao, Mingxing; Jang, Ho-Kyun; Kim, Gyu-Tae; Oh, Byung Su; Joo, Min-Kyu; Ahn, Seung-Eon

    2014-12-28

    We report an investigation of the effects of low-temperature annealing on the electrical properties of amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs). X-ray photoelectron spectroscopy was used to characterize the charge carrier concentration, which is related to the density of oxygen vacancies. The field-effect mobility was found to decrease as a function of the charge carrier concentration, owing to the presence of band-tail states. By employing the transmission line method, we show that the contact resistance did not significantly contribute to the changes in device performance after annealing. In addition, using low-frequency noise analyses, we found that the trap density decreased by a factor of 10 following annealing at 120 °C. The switching operation and on/off ratio of the a-IGZO TFTs improved considerably after low-temperature annealing.

  9. Photoemission spectroscopy study of the lanthanum lutetium oxide/silicon interface

    SciTech Connect (OSTI)

    Nichau, A.; Schnee, M.; Schubert, J.; Bernardy, P.; Hollaender, B.; Buca, D.; Mantl, S.; Besmehn, A.; Breuer, U.; Rubio-Zuazo, J.; Castro, G. R.; Muecklich, A.; Borany, J. von

    2013-04-21

    Rare earth oxides are promising candidates for future integration into nano-electronics. A key property of these oxides is their ability to form silicates in order to replace the interfacial layer in Si-based complementary metal-oxide field effect transistors. In this work a detailed study of lanthanum lutetium oxide based gate stacks is presented. Special attention is given to the silicate formation at temperatures typical for CMOS processing. The experimental analysis is based on hard x-ray photoemission spectroscopy complemented by standard laboratory experiments as Rutherford backscattering spectrometry and high-resolution transmission electron microscopy. Homogenously distributed La silicate and Lu silicate at the Si interface are proven to form already during gate oxide deposition. During the thermal treatment Si atoms diffuse through the oxide layer towards the TiN metal gate. This mechanism is identified to be promoted via Lu-O bonds, whereby the diffusion of La was found to be less important.

  10. Charge noise analysis of metal oxide semiconductor dual-gate Si/SiGe quantum point contacts

    SciTech Connect (OSTI)

    Kamioka, J.; Oda, S.; Kodera, T.; Takeda, K.; Obata, T.; Tarucha, S.

    2014-05-28

    The frequency dependence of conductance noise through a gate-defined quantum point contact fabricated on a Si/SiGe modulation doped wafer is characterized. The 1/f{sup 2} noise, which is characteristic of random telegraph noise, is reduced by application of a negative bias on the global top gate to reduce the local gate voltage. Direct leakage from the large global gate voltage also causes random telegraph noise, and therefore, there is a suitable point to operate quantum dot measurement.

  11. Thin-film transistors based on p-type Cu{sub 2}O thin films produced at room temperature

    SciTech Connect (OSTI)

    Fortunato, Elvira; Figueiredo, Vitor; Barquinha, Pedro; Elamurugu, Elangovan; Goncalves, Goncalo; Martins, Rodrigo; Park, Sang-Hee Ko; Hwang, Chi-Sun

    2010-05-10

    Copper oxide (Cu{sub 2}O) thin films were used to produce bottom gate p-type transparent thin-film transistors (TFTs). Cu{sub 2}O was deposited by reactive rf magnetron sputtering at room temperature and the films exhibit a polycrystalline structure with a strongest orientation along (111) plane. The TFTs exhibit improved electrical performance such as a field-effect mobility of 3.9 cm{sup 2}/V s and an on/off ratio of 2x10{sup 2}.

  12. Ultrathin body GaSb-on-insulator p-channel metal-oxide-semiconductor field-effect transistors on Si fabricated by direct wafer bonding

    SciTech Connect (OSTI)

    Yokoyama, Masafumi Takenaka, Mitsuru; Takagi, Shinichi; Yokoyama, Haruki

    2015-02-16

    We have realized ultrathin body GaSb-on-insulator (GaSb-OI) on Si wafers by direct wafer bonding technology using atomic-layer deposition (ALD) Al{sub 2}O{sub 3} and have demonstrated GaSb-OI p-channel metal-oxide-semiconductor field-effect transistors (p-MOSFETs) on Si. A 23-nm-thick GaSb-OI p-MOSFET exhibits the peak effective mobility of ∼76 cm{sup 2}/V s. We have found that the effective hole mobility of the thin-body GaSb-OI p-MOSFETs decreases with a decrease in the GaSb-OI thickness or with an increase in Al{sub 2}O{sub 3} ALD temperature. The InAs passivation of GaSb-OI MOS interfaces can enhance the peak effective mobility up to 159 cm{sup 2}/V s for GaSb-OI p-MOSFETs with the 20-nm-thick GaSb layer.

  13. Physical understanding of electron mobility in asymmetrically strained InGaAs-on-insulator metal-oxide-semiconductor field-effect transistors fabricated by lateral strain relaxation

    SciTech Connect (OSTI)

    Kim, SangHyeon E-mail: sh-kim@kist.re.kr; Yokoyama, Masafumi; Ikku, Yuki; Nakane, Ryosho; Takenaka, Mitsuru; Takagi, Shinichi; Ichikawa, Osamu; Osada, Takenori; Hata, Masahiko

    2014-03-17

    In this paper, we fabricated asymmetrically tensile-strained In{sub 0.53}Ga{sub 0.47}As-on-insulator (-OI) metal-oxide-semiconductor field-effect transistors (MOSFETs) using a lateral strain relaxation technique. A stripe-like line structure, fabricated in biaxially strained In{sub 0.53}Ga{sub 0.47}As-OI can lead to the lateral strain relaxation and asymmetric strain configuration in In{sub 0.53}Ga{sub 0.47}As-OI with the channel width of 100 nm. We have found that the effective mobility (μ{sub eff}) enhancement in In{sub 0.53}Ga{sub 0.47}As-OI MOSFETs with uniaxial-like asymmetric strain becomes smaller than that in In{sub 0.53}Ga{sub 0.47}As-OI MOSFETs with biaxial strain. We have clarified from a systematic analysis between the strain values and the μ{sub eff} characteristics that this mobility behavior can be understood by the change of the energy level of the conduction band minimum due to the lateral strain relaxation.

  14. Transistors using crystalline silicon devices on glass

    DOE Patents [OSTI]

    McCarthy, A.M.

    1995-05-09

    A method is disclosed for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed. 13 figs.

  15. All diamond self-aligned thin film transistor

    DOE Patents [OSTI]

    Gerbi, Jennifer

    2008-07-01

    A substantially all diamond transistor with an electrically insulating substrate, an electrically conductive diamond layer on the substrate, and a source and a drain contact on the electrically conductive diamond layer. An electrically insulating diamond layer is in contact with the electrically conductive diamond layer, and a gate contact is on the electrically insulating diamond layer. The diamond layers may be homoepitaxial, polycrystalline, nanocrystalline or ultrananocrystalline in various combinations.A method of making a substantially all diamond self-aligned gate transistor is disclosed in which seeding and patterning can be avoided or minimized, if desired.

  16. Method for fabricating transistors using crystalline silicon devices on glass

    DOE Patents [OSTI]

    McCarthy, Anthony M.

    1997-01-01

    A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed.

  17. Femtosecond all-optical parallel logic gates based on tunable saturable to reverse saturable absorption in graphene-oxide thin films

    SciTech Connect (OSTI)

    Roy, Sukhdev Yadav, Chandresh

    2013-12-09

    A detailed theoretical analysis of ultrafast transition from saturable absorption (SA) to reverse saturable absorption (RSA) has been presented in graphene-oxide thin films with femtosecond laser pulses at 800 nm. Increase in pulse intensity leads to switching from SA to RSA with increased contrast due to two-photon absorption induced excited-state absorption. Theoretical results are in good agreement with reported experimental results. Interestingly, it is also shown that increase in concentration results in RSA to SA transition. The switching has been optimized to design parallel all-optical femtosecond NOT, AND, OR, XOR, and the universal NAND and NOR logic gates.

  18. A Heteroepitaxial Perovskite Metal-Base Transistor

    SciTech Connect (OSTI)

    Yajima, T.; Hikita, Y.; Hwang, H.Y.; ,

    2011-08-11

    'More than Moore' captures a concept for overcoming limitations in silicon electronics by incorporating new functionalities in the constituent materials. Perovskite oxides are candidates because of their vast array of physical properties in a common structure. They also enable new electronic devices based on strongly-correlated electrons. The field effect transistor and its derivatives have been the principal oxide devices investigated thus far, but another option is available in a different geometry: if the current is perpendicular to the interface, the strong internal electric fields generated at back-to-back heterojunctions can be used for oxide electronics, analogous to bipolar transistors. Here we demonstrate a perovskite heteroepitaxial metal-base transistor operating at room temperature, enabled by interface dipole engineering. Analysis of many devices quantifies the evolution from hot-electron to permeable-base behaviour. This device provides a platform for incorporating the exotic ground states of perovskite oxides, as well as novel electronic phases at their interfaces.

  19. Room-temperature amorphous alloy field-effect transistor exhibiting particle and wave electronic transport

    SciTech Connect (OSTI)

    Fukuhara, M.; Kawarada, H.

    2015-02-28

    The realization of room-temperature macroscopic field effect transistors (FETs) will lead to new epoch-making possibilities for electronic applications. The I{sub d}-V{sub g} characteristics of the millimeter-sized aluminum-oxide amorphous alloy (Ni{sub 0.36}Nb{sub 0.24}Zr{sub 0.40}){sub 90}H{sub 10} FETs were measured at a gate-drain bias voltage of 060??V in nonmagnetic conditions and under a magnetic fields at room temperature. Application of dc voltages to the gate electrode resulted in the transistor exhibiting one-electron Coulomb oscillation with a period of 0.28?mV, Fabry-Perot interference with a period of 2.35??V under nonmagnetic conditions, and a Fano effect with a period of 0.26?mV for Vg and 0.2?T under a magnetic field. The realization of a low-energy controllable device made from millimeter-sized Ni-Nb-Zr-H amorphous alloy throws new light on cluster electronics.

  20. Inversion-mode GaAs wave-shaped field-effect transistor on GaAs (100) substrate

    SciTech Connect (OSTI)

    Zhang, Jingyun; Si, Mengwei; Wu, Heng; Ye, Peide D.; Lou, Xiabing; Gordon, Roy G.; Shao, Jiayi; Manfra, Michael J.

    2015-02-16

    Inversion-mode GaAs wave-shaped metal-oxide-semiconductor field-effect transistors (WaveFETs) are demonstrated using atomic-layer epitaxy of La{sub 2}O{sub 3} as gate dielectric on (111)A nano-facets formed on a GaAs (100) substrate. The wave-shaped nano-facets, which are desirable for the device on-state and off-state performance, are realized by lithographic patterning and anisotropic wet etching with optimized geometry. A well-behaved 1 μm gate length GaAs WaveFET shows a maximum drain current of 64 mA/mm, a subthreshold swing of 135 mV/dec, and an I{sub ON}/I{sub OFF} ratio of greater than 10{sup 7}.

  1. STABILIZED TRANSISTOR AMPLIFIER

    DOE Patents [OSTI]

    Noe, J.B.

    1963-05-01

    A temperature stabilized transistor amplifier having a pair of transistors coupled in cascade relation that are capable of providing amplification through a temperature range of - 100 un. Concent 85% F to 400 un. Concent 85% F described. The stabilization of the amplifier is attained by coupling a feedback signal taken from the emitter of second transistor at a junction between two serially arranged biasing resistances in the circuit of the emitter of the second transistor to the base of the first transistor. Thus, a change in the emitter current of the second transistor is automatically corrected by the feedback adjustment of the base-emitter potential of the first transistor and by a corresponding change in the base-emitter potential of the second transistor. (AEC)

  2. Gate Access

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Gate Access Gate Access Print When you first arrive at the ALS, gate clearance will have been arranged for you by the User Office. Berkeley Lab employees and visiting researchers (participating guests) may arrange for gate clearance for their visitors through the Lab's Site Access Office . Please notify the Site Office by submitting a Visitor Pass Request before 3:00 p.m. on the day before the expected visit. Include the name(s) of any visitors, the time you expect them, and your name and

  3. Sample size requirements for estimating effective dose from computed tomography using solid-state metal-oxide-semiconductor field-effect transistor dosimetry

    SciTech Connect (OSTI)

    Trattner, Sigal; Cheng, Bin; Pieniazek, Radoslaw L.; Hoffmann, Udo; Douglas, Pamela S.; Einstein, Andrew J.

    2014-04-15

    Purpose: Effective dose (ED) is a widely used metric for comparing ionizing radiation burden between different imaging modalities, scanners, and scan protocols. In computed tomography (CT), ED can be estimated by performing scans on an anthropomorphic phantom in which metal-oxide-semiconductor field-effect transistor (MOSFET) solid-state dosimeters have been placed to enable organ dose measurements. Here a statistical framework is established to determine the sample size (number of scans) needed for estimating ED to a desired precision and confidence, for a particular scanner and scan protocol, subject to practical limitations. Methods: The statistical scheme involves solving equations which minimize the sample size required for estimating ED to desired precision and confidence. It is subject to a constrained variation of the estimated ED and solved using the Lagrange multiplier method. The scheme incorporates measurement variation introduced both by MOSFET calibration, and by variation in MOSFET readings between repeated CT scans. Sample size requirements are illustrated on cardiac, chest, and abdomenpelvis CT scans performed on a 320-row scanner and chest CT performed on a 16-row scanner. Results: Sample sizes for estimating ED vary considerably between scanners and protocols. Sample size increases as the required precision or confidence is higher and also as the anticipated ED is lower. For example, for a helical chest protocol, for 95% confidence and 5% precision for the ED, 30 measurements are required on the 320-row scanner and 11 on the 16-row scanner when the anticipated ED is 4 mSv; these sample sizes are 5 and 2, respectively, when the anticipated ED is 10 mSv. Conclusions: Applying the suggested scheme, it was found that even at modest sample sizes, it is feasible to estimate ED with high precision and a high degree of confidence. As CT technology develops enabling ED to be lowered, more MOSFET measurements are needed to estimate ED with the same

  4. CNEEC - Electrolyte Gating by David Goldhaber-Gordon

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Electrolyte Gating

  5. C-H surface diamond field effect transistors for high temperature (400 °C) and high voltage (500 V) operation

    SciTech Connect (OSTI)

    Kawarada, H.; Tsuboi, H.; Naruo, T.; Yamada, T.; Xu, D.; Daicho, A.; Saito, T.; Hiraiwa, A.

    2014-07-07

    By forming a highly stable Al{sub 2}O{sub 3} gate oxide on a C-H bonded channel of diamond, high-temperature, and high-voltage metal-oxide-semiconductor field-effect transistor (MOSFET) has been realized. From room temperature to 400 °C (673 K), the variation of maximum drain-current is within 30% at a given gate bias. The maximum breakdown voltage (V{sub B}) of the MOSFET without a field plate is 600 V at a gate-drain distance (L{sub GD}) of 7 μm. We fabricated some MOSFETs for which V{sub B}/L{sub GD} > 100 V/μm. These values are comparable to those of lateral SiC or GaN FETs. The Al{sub 2}O{sub 3} was deposited on the C-H surface by atomic layer deposition (ALD) at 450 °C using H{sub 2}O as an oxidant. The ALD at relatively high temperature results in stable p-type conduction and FET operation at 400 °C in vacuum. The drain current density and transconductance normalized by the gate width are almost constant from room temperature to 400 °C in vacuum and are about 10 times higher than those of boron-doped diamond FETs.

  6. Amorphorized tantalum-nickel binary films for metal gate applications

    SciTech Connect (OSTI)

    Ouyang, Jiaomin; Wongpiya, Ranida; Clemens, Bruce M.; Deal, Michael D.; Nishi, Yoshio

    2015-04-13

    Amorphous metal gates have the potential to eliminate the work function variation due to grain orientation for poly-crystalline metal gate materials, which is a leading contributor to threshold voltage variation for small transistors. Structural and electrical properties of TaNi alloys using co-sputtering with different compositions and multilayer structures with different thicknesses are investigated in this work. It is found that TaNi films are amorphous for a wide range of compositions as deposited, and the films stay amorphous after annealing at 400?C in RTA for 1?min and up to at least 700?C depending on the composition. The amorphous films eventually crystallize into Ni, Ta, and TaNi{sub 3} phases at high enough temperature. For multilayer Ta/Ni structures, samples with individual layer thickness of 0.12?nm and 1.2?nm are amorphous as deposited due to intermixing during deposition, and stay amorphous until annealed at 500?C. The resistivity of the films as-deposited are around 200 ??cm. The work function of the alloy is fixed at close to the Ta work function of 4.6?eV for a wide range of compositions. This is attributed to the segregation of Ta at the metal-oxide interface, which is confirmed by XPS depth profile. Overall, the excellent thermal stability and low resistivity makes this alloy system a promising candidate for eliminating work function variation for gate last applications, as compared to crystalline Ta or TiN gates.

  7. The role of the substrate on the dispersion in accumulation in III-V compound semiconductor based metal-oxide-semiconductor gate stacks

    SciTech Connect (OSTI)

    Krylov, Igor; Ritter, Dan; Eizenberg, Moshe

    2015-09-07

    Dispersion in accumulation is a widely observed phenomenon in metal-oxide-semiconductor gate stacks based on III-V compound semiconductors. The physical origin of this phenomenon is attributed to border traps located in the dielectric material adjacent to the semiconductor. Here, we study the role of the semiconductor substrate on the electrical quality of the first layers at atomic layer deposited (ALD) dielectrics. For this purpose, either Al{sub 2}O{sub 3} or HfO{sub 2} dielectrics with variable thicknesses were deposited simultaneously on two technology important semiconductors—InGaAs and InP. Significantly larger dispersion was observed in InP based gate stacks compared to those based on InGaAs. The observed difference is attributed to a higher border trap density in dielectrics deposited on InP compared to those deposited on InGaAs. We therefore conclude that the substrate plays an important role in the determination of the electrical quality of the first dielectric monolayers deposited by ALD. An additional observation is that larger dispersion was obtained in HfO{sub 2} based capacitors compared to Al{sub 2}O{sub 3} based capacitors, deposited on the same semiconductor. This phenomenon is attributed to the lower conduction band offset rather than to a higher border trap density.

  8. Stage Gate Management Guide

    Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

    Stage Gate Management in the Biomass Program February 2005 Revision 2 2 TABLE OF CONTENTS OVERVIEW............................................................................................................................. 4 STAGE GATE MANAGEMENT .................................................................................................... 4 STAGE GATE PROCESS AND LONG RANGE STRATEGIC PROGRAM PLANNING ........................ 5 GATE REVIEWS

  9. Visible-light-induced instability in amorphous metal-oxide based TFTs for transparent electronics

    SciTech Connect (OSTI)

    Ha, Tae-Jun

    2014-10-15

    We investigate the origin of visible-light-induced instability in amorphous metal-oxide based thin film transistors (oxide-TFTs) for transparent electronics by exploring the shift in threshold voltage (V{sub th}). A large hysteresis window in amorphous indium-gallium-zinc-oxide (a-IGZO) TFTs possessing large optical band-gap (≈3 eV) was observed in a visible-light illuminated condition whereas no hysteresis window was shown in a dark measuring condition. We also report the instability caused by photo irradiation and prolonged gate bias stress in oxide-TFTs. Larger V{sub th} shift was observed after photo-induced stress combined with a negative gate bias than the sum of that after only illumination stress and only negative gate bias stress. Such results can be explained by trapped charges at the interface of semiconductor/dielectric and/or in the gate dielectric which play a role in a screen effect on the electric field applied by gate voltage, for which we propose that the localized-states-assisted transitions by visible-light absorption can be responsible.

  10. Probing Organic Transistors with Infrared Beams

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Probing Organic Transistors with Infrared Beams Probing Organic Transistors with Infrared Beams Print Wednesday, 26 July 2006 00:00 Silicon-based transistors are well-understood,...

  11. Transparently wrap-gated semiconductor nanowire arrays for studies of gate-controlled photoluminescence

    SciTech Connect (OSTI)

    Nylund, Gustav; Storm, Kristian; Torstensson, Henrik; Wallentin, Jesper; Borgstrm, Magnus T.; Hessman, Dan; Samuelson, Lars

    2013-12-04

    We present a technique to measure gate-controlled photoluminescence (PL) on arrays of semiconductor nanowire (NW) capacitors using a transparent film of Indium-Tin-Oxide (ITO) wrapping around the nanowires as the gate electrode. By tuning the wrap-gate voltage, it is possible to increase the PL peak intensity of an array of undoped InP NWs by more than an order of magnitude. The fine structure of the PL spectrum reveals three subpeaks whose relative peak intensities change with gate voltage. We interpret this as gate-controlled state-filling of luminescing quantum dot segments formed by zincblende stacking faults in the mainly wurtzite NW crystal structure.

  12. Method for formation of thin film transistors on plastic substrates

    DOE Patents [OSTI]

    Carey, P.G.; Smith, P.M.; Sigmon, T.W.; Aceves, R.C.

    1998-10-06

    A process for formation of thin film transistors (TFTs) on plastic substrates replaces standard thin film transistor fabrication techniques, and uses sufficiently lower processing temperatures so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The process relies on techniques for depositing semiconductors, dielectrics, and metals at low temperatures; crystallizing and doping semiconductor layers in the TFT with a pulsed energy source; and creating top-gate self-aligned as well as back-gate TFT structures. The process enables the fabrication of amorphous and polycrystalline channel silicon TFTs at temperatures sufficiently low to prevent damage to plastic substrates. The process has use in large area low cost electronics, such as flat panel displays and portable electronics. 5 figs.

  13. Method for formation of thin film transistors on plastic substrates

    DOE Patents [OSTI]

    Carey, Paul G.; Smith, Patrick M.; Sigmon, Thomas W.; Aceves, Randy C.

    1998-10-06

    A process for formation of thin film transistors (TFTs) on plastic substrates replaces standard thin film transistor fabrication techniques, and uses sufficiently lower processing temperatures so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The process relies on techniques for depositing semiconductors, dielectrics, and metals at low temperatures; crystallizing and doping semiconductor layers in the TFT with a pulsed energy source; and creating top-gate self-aligned as well as back-gate TFT structures. The process enables the fabrication of amorphous and polycrystalline channel silicon TFTs at temperatures sufficiently low to prevent damage to plastic substrates. The process has use in large area low cost electronics, such as flat panel displays and portable electronics.

  14. Method for fabricating transistors using crystalline silicon devices on glass

    DOE Patents [OSTI]

    McCarthy, A.M.

    1997-09-02

    A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed. 13 figs.

  15. Transistor-based interface circuitry

    DOE Patents [OSTI]

    Taubman, Matthew S.

    2004-02-24

    Among the embodiments of the present invention is an apparatus that includes a transistor, a servo device, and a current source. The servo device is operable to provide a common base mode of operation of the transistor by maintaining an approximately constant voltage level at the transistor base. The current source is operable to provide a bias current to the transistor. A first device provides an input signal to an electrical node positioned between the emitter of the transistor and the current source. A second device receives an output signal from the collector of the transistor.

  16. Transistor-based interface circuitry

    DOE Patents [OSTI]

    Taubman, Matthew S.

    2007-02-13

    Among the embodiments of the present invention is an apparatus that includes a transistor, a servo device, and a current source. The servo device is operable to provide a common base mode of operation of the transistor by maintaining an approximately constant voltage level at the transistor base. The current source is operable to provide a bias current to the transistor. A first device provides an input signal to an electrical node positioned between the emitter of the transistor and the current source. A second device receives an output signal from the collector of the transistor.

  17. Carbon nanotube network thin-film transistors on flexible/stretchable substrates

    DOE Patents [OSTI]

    Takei, Kuniharu; Takahashi, Toshitake; Javey, Ali

    2016-03-29

    This disclosure provides systems, methods, and apparatus for flexible thin-film transistors. In one aspect, a device includes a polymer substrate, a gate electrode disposed on the polymer substrate, a dielectric layer disposed on the gate electrode and on exposed portions of the polymer substrate, a carbon nanotube network disposed on the dielectric layer, and a source electrode and a drain electrode disposed on the carbon nanotube network.

  18. Controlling the interface charge density in GaN-based metal-oxide-semiconductor heterostructures by plasma oxidation of metal layers

    SciTech Connect (OSTI)

    Hahn, Herwig Kalisch, Holger; Vescan, Andrei; Pécz, Béla; Kovács, András; Heuken, Michael

    2015-06-07

    In recent years, investigating and engineering the oxide-semiconductor interface in GaN-based devices has come into focus. This has been driven by a large effort to increase the gate robustness and to obtain enhancement mode transistors. Since it has been shown that deep interface states act as fixed interface charge in the typical transistor operating regime, it appears desirable to intentionally incorporate negative interface charge, and thus, to allow for a positive shift in threshold voltage of transistors to realise enhancement mode behaviour. A rather new approach to obtain such negative charge is the plasma-oxidation of thin metal layers. In this study, we present transmission electron microscopy and energy dispersive X-ray spectroscopy analysis as well as electrical data for Al-, Ti-, and Zr-based thin oxide films on a GaN-based heterostructure. It is shown that the plasma-oxidised layers have a polycrystalline morphology. An interfacial amorphous oxide layer is only detectable in the case of Zr. In addition, all films exhibit net negative charge with varying densities. The Zr layer is providing a negative interface charge density of more than 1 × 10{sup 13 }cm{sup –2} allowing to considerably shift the threshold voltage to more positive values.

  19. VOLTAGE-CONTROLLED TRANSISTOR OSCILLATOR

    DOE Patents [OSTI]

    Scheele, P.F.

    1958-09-16

    This patent relates to transistor oscillators and in particular to those transistor oscillators whose frequencies vary according to controlling voltages. A principal feature of the disclosed transistor oscillator circuit resides in the temperature compensation of the frequency modulating stage by the use of a resistorthermistor network. The resistor-thermistor network components are selected to have the network resistance, which is in series with the modulator transistor emitter circuit, vary with temperature to compensate for variation in the parameters of the transistor due to temperature change.

  20. High gain, low noise, fully complementary logic inverter based on bi-layer WSe{sub 2} field effect transistors

    SciTech Connect (OSTI)

    Das, Saptarshi; Roelofs, Andreas; Dubey, Madan

    2014-08-25

    In this article, first, we show that by contact work function engineering, electrostatic doping and proper scaling of both the oxide thickness and the flake thickness, high performance p- and n-type WSe{sub 2} field effect transistors (FETs) can be realized. We report record high drive current of 98??A/?m for the electron conduction and 110 ?A/?m for the hole conduction in Schottky barrier WSe{sub 2} FETs. Then, we combine high performance WSe{sub 2} PFET with WSe{sub 2} NFET in double gated transistor geometry to demonstrate a fully complementary logic inverter. We also show that by adjusting the threshold voltages for the NFET and the PFET, the gain and the noise margin of the inverter can be significantly enhanced. The maximum gain of our chemical doping free WSe{sub 2} inverter was found to be ?25 and the noise margin was close to its ideal value of ?2.5?V for a supply voltage of V{sub DD}?=?5.0?V.

  1. Ripple gate drive circuit for fast operation of series connected IGBTs

    DOE Patents [OSTI]

    Rockot, Joseph H.; Murray, Thomas W.; Bass, Kevin C.

    2005-09-20

    A ripple gate drive circuit includes a plurality of transistors having their power terminals connected in series across an electrical potential. A plurality of control circuits, each associated with one of the transistors, is provided. Each control circuit is responsive to a control signal and an optical signal received from at least one other control circuit for controlling the conduction of electrical current through the power terminals of the associated transistor. The control circuits are responsive to a first state of the control circuit for causing each transistor in series to turn on sequentially and responsive to a second state of the control signal for causing each transistor in series to turn off sequentially.

  2. Antiferromagnetic Spin Wave Field-Effect Transistor

    DOE Public Access Gateway for Energy & Science Beta (PAGES Beta)

    Cheng, Ran; Daniels, Matthew W.; Zhu, Jian-Gang; Xiao, Di

    2016-04-06

    In a collinear antiferromagnet with easy-axis anisotropy, symmetry dictates that the spin wave modes must be doubly degenerate. Theses two modes, distinguished by their opposite polarization and available only in antiferromagnets, give rise to a novel degree of freedom to encode and process information. We show that the spin wave polarization can be manipulated by an electric field induced Dzyaloshinskii-Moriya interaction and magnetic anisotropy. We propose a prototype spin wave field effect transistor which realizes a gate-tunable magnonic analog of the Faraday effect, and demonstrate its application in THz signal modulation. In conclusion, our findings open up the exciting possibilitymore » of digital data processing utilizing antiferromagnetic spin waves and enable the direct projection of optical computing concepts onto the mesoscopic scale.« less

  3. Design of step composition gradient thin film transistor channel layers grown by atomic layer deposition

    SciTech Connect (OSTI)

    Ahn, Cheol Hyoun; Hee Kim, So; Gu Yun, Myeong; Koun Cho, Hyung

    2014-12-01

    In this study, we proposed the artificially designed channel structure in oxide thin-film transistors (TFTs) called a “step-composition gradient channel.” We demonstrated Al step-composition gradient Al-Zn-O (AZO) channel structures consisting of three AZO layers with different Al contents. The effects of stacking sequence in the step-composition gradient channel on performance and electrical stability of bottom-gate TFT devices were investigated with two channels of inverse stacking order (ascending/descending step-composition). The TFT with ascending step-composition channel structure (5 → 10 → 14 at. % Al composition) showed relatively negative threshold voltage (−3.7 V) and good instability characteristics with a reduced threshold voltage shift (Δ 1.4 V), which was related to the alignment of the conduction band off-set within the channel layer depending on the Al contents. Finally, the reduced Al composition in the initial layer of ascending step-composition channel resulted in the best field effect mobility of 4.5 cm{sup 2}/V s. We presented a unique active layer of the “step-composition gradient channel” in the oxide TFTs and explained the mechanism of adequate channel design.

  4. TRANSISTOR HIGH VOLTAGE POWER SUPPLY

    DOE Patents [OSTI]

    Driver, G.E.

    1958-07-15

    High voltage, direct current power supplies are described for use with battery powered nuclear detection equipment. The particular advantages of the power supply described, are increased efficiency and reduced size and welght brought about by the use of transistors in the circuit. An important feature resides tn the employment of a pair of transistors in an alternatefiring oscillator circuit having a coupling transformer and other circuit components which are used for interconnecting the various electrodes of the transistors.

  5. Low interface defect density of atomic layer deposition BeO with self-cleaning reaction for InGaAs metal oxide semiconductor field effect transistors

    SciTech Connect (OSTI)

    Shin, H. S.; SEMATECH, 2706 Montopolis Dr., Austin, Texas 78741; The University of Texas, Austin, Texas 78758 ; Yum, J. H.; The University of Texas, Austin, Texas 78758 ; Johnson, D. W.; Texas A and M University College Station, Texas 77843 ; Harris, H. R.; Hudnall, Todd W.; Oh, J.; Kirsch, P.; Wang, W.-E.; Bielawski, C. W.; Banerjee, S. K.; Lee, J. C.; Lee, H. D.

    2013-11-25

    In this paper, we discuss atomic configuration of atomic layer deposition (ALD) beryllium oxide (BeO) using the quantum chemistry to understand the theoretical origin. BeO has shorter bond length, higher reaction enthalpy, and larger bandgap energy compared with those of ALD aluminum oxide. It is shown that the excellent material properties of ALD BeO can reduce interface defect density due to the self-cleaning reaction and this contributes to the improvement of device performance of InGaAs MOSFETs. The low interface defect density and low leakage current of InGaAs MOSFET were demonstrated using X-ray photoelectron spectroscopy and the corresponding electrical results.

  6. REGENERATIVE TRANSISTOR AMPLIFIER

    DOE Patents [OSTI]

    Kabell, L.J.

    1958-11-25

    Electrical circults for use in computers and the like are described. particularly a regenerative bistable transistor amplifler which is iurned on by a clock signal when an information signal permits and is turned off by the clock signal. The amplifier porforms the above function with reduced power requirements for the clock signal and circuit operation. The power requirements are reduced in one way by employing transformer coupling which increases the collector circuit efficiency by eliminating the loss of power in the collector load resistor.

  7. Gated strip proportional detector

    DOE Patents [OSTI]

    Morris, C.L.; Idzorek, G.C.; Atencio, L.G.

    1985-02-19

    A gated strip proportional detector includes a gas tight chamber which encloses a solid ground plane, a wire anode plane, a wire gating plane, and a multiconductor cathode plane. The anode plane amplifies the amount of charge deposited in the chamber by a factor of up to 10/sup 6/. The gating plane allows only charge within a narrow strip to reach the cathode. The cathode plane collects the charge allowed to pass through the gating plane on a set of conductors perpendicular to the open-gated region. By scanning the open-gated region across the chamber and reading out the charge collected on the cathode conductors after a suitable integration time for each location of the gate, a two-dimensional image of the intensity of the ionizing radiation incident on the detector can be made.

  8. Gated strip proportional detector

    DOE Patents [OSTI]

    Morris, Christopher L.; Idzorek, George C.; Atencio, Leroy G.

    1987-01-01

    A gated strip proportional detector includes a gas tight chamber which encloses a solid ground plane, a wire anode plane, a wire gating plane, and a multiconductor cathode plane. The anode plane amplifies the amount of charge deposited in the chamber by a factor of up to 10.sup.6. The gating plane allows only charge within a narrow strip to reach the cathode. The cathode plane collects the charge allowed to pass through the gating plane on a set of conductors perpendicular to the open-gated region. By scanning the open-gated region across the chamber and reading out the charge collected on the cathode conductors after a suitable integration time for each location of the gate, a two-dimensional image of the intensity of the ionizing radiation incident on the detector can be made.

  9. Single atom impurity in a single molecular transistor

    SciTech Connect (OSTI)

    Ray, S. J.

    2014-10-21

    The influence of an impurity atom on the electrostatic behaviour of a Single Molecular Transistor was investigated through Ab-initio calculations in a double-gated geometry. The charge stability diagram carries unique signature of the position of the impurity atom in such devices which together with the charging energy of the molecule could be utilised as an electronic fingerprint for the detection of such impurity states in a nano-electronic device. The two gated geometry allows additional control over the electrostatics as can be seen from the total energy surfaces (for a specific charge state), which is sensitive to the positions of the impurity. These devices which are operational at room temperature can provide significant advantages over the conventional silicon based single dopant devices functional at low temperature. The present approach could be a very powerful tool for the detection and control of individual impurity atoms in a single molecular device and for applications in future molecular electronics.

  10. The fundamental downscaling limit of field effect transistors

    SciTech Connect (OSTI)

    Mamaluy, Denis Gao, Xujiao

    2015-05-11

    We predict that within next 15 years a fundamental down-scaling limit for CMOS technology and other Field-Effect Transistors (FETs) will be reached. Specifically, we show that at room temperatures all FETs, irrespective of their channel material, will start experiencing unacceptable level of thermally induced errors around 5-nm gate lengths. These findings were confirmed by performing quantum mechanical transport simulations for a variety of 6-, 5-, and 4-nm gate length Si devices, optimized to satisfy high-performance logic specifications by ITRS. Different channel materials and wafer/channel orientations have also been studied; it is found that altering channel-source-drain materials achieves only insignificant increase in switching energy, which overall cannot sufficiently delay the approaching downscaling limit. Alternative possibilities are discussed to continue the increase of logic element densities for room temperature operation below the said limit.

  11. Range gated imaging experiments using gated intensifiers

    SciTech Connect (OSTI)

    McDonald, T.E. Jr.; Yates, G.J.; Cverna, F.H.; Gallegos, R.A.; Jaramillo, S.A.; Numkena, D.M.; Payton, J.; Pena-Abeyta, C.R.

    1999-03-01

    A variety of range gated imaging experiments using high-speed gated/shuttered proximity focused microchannel plate image intensifiers (MCPII) are reported. Range gated imaging experiments were conducted in water for detection of submerged mines in controlled turbidity tank test and in sea water for the Naval Coastal Sea Command/US Marine Corps. Field experiments have been conducted consisting of kilometer range imaging of resolution targets and military vehicles in atmosphere at Eglin Air Force Base for the US Air Force, and similar imaging experiments, but in smoke environment, at Redstone Arsenal for the US Army Aviation and Missile Command (AMCOM). Wavelength of the illuminating laser was 532 nm with pulse width ranging from 6 to 12 ns and comparable gate widths. These tests have shown depth resolution in the tens of centimeters range from time phasing reflected LADAR images with MCPII shutter opening.

  12. Pulse Thermal Processing for Low Thermal Budget Integration of IGZO Thin Film Transistors

    SciTech Connect (OSTI)

    Noh, Joo Hyon; Joshi, Pooran C.; Kuruganti, Teja; Rack, Philip D.

    2014-11-26

    Pulse thermal processing (PTP) has been explored for low thermal budget integration of indium gallium zinc oxide (IGZO) thin film transistors (TFTs). The IGZO TFTs are exposed to a broadband (0.2-1.4 m) arc lamp radiation spectrum with 100 pulses of 1 msec pulse width. The impact of radiant exposure power on the TFT performance was analyzed in terms of the switching characteristics and bias stress reliability characteristics, respectively. The PTP treated IGZO TFTs with power density of 3.95 kW/cm2 and 0.1 sec total irradiation time showed comparable switching properties, at significantly lower thermal budget, to furnace annealed IGZO TFT. The typical field effect mobility FE, threshold voltage VT, and sub-threshold gate swing S.S were calculated to be 7.8 cm2/ V s, 8.1 V, and 0.22 V/ decade, respectively. The observed performance shows promise for low thermal budget TFT integration on flexible substrates exploiting the large-area, scalable PTP technology.

  13. Pulse Thermal Processing for Low Thermal Budget Integration of IGZO Thin Film Transistors

    DOE Public Access Gateway for Energy & Science Beta (PAGES Beta)

    Noh, Joo Hyon; Joshi, Pooran C.; Kuruganti, Teja; Rack, Philip D.

    2014-11-26

    Pulse thermal processing (PTP) has been explored for low thermal budget integration of indium gallium zinc oxide (IGZO) thin film transistors (TFTs). The IGZO TFTs are exposed to a broadband (0.2-1.4 m) arc lamp radiation spectrum with 100 pulses of 1 msec pulse width. The impact of radiant exposure power on the TFT performance was analyzed in terms of the switching characteristics and bias stress reliability characteristics, respectively. The PTP treated IGZO TFTs with power density of 3.95 kW/cm2 and 0.1 sec total irradiation time showed comparable switching properties, at significantly lower thermal budget, to furnace annealed IGZO TFT. Themore » typical field effect mobility FE, threshold voltage VT, and sub-threshold gate swing S.S were calculated to be 7.8 cm2/ V s, 8.1 V, and 0.22 V/ decade, respectively. The observed performance shows promise for low thermal budget TFT integration on flexible substrates exploiting the large-area, scalable PTP technology.« less

  14. Impacts of SiN passivation on the degradation modes of AlGaN/GaN high electron mobility transistors under reverse-bias stress

    SciTech Connect (OSTI)

    Chen, Wei-Wei; Ma, Xiao-Hua E-mail: yhao@xidian.edu.cn; Hou, Bin; Zhu, Jie-Jie; Chen, Yong-He; Zheng, Xue-Feng; Zhang, Jin-Cheng; Hao, Yue E-mail: yhao@xidian.edu.cn

    2014-10-27

    Impacts of SiN passivation on the degradation modes of AlGaN/GaN high electron mobility transistors are investigated. The gate leakage current decreases significantly upon removing the SiN layer and no clear critical voltage for the sudden degradation of the gate leakage current can be observed in the reverse-bias step-stress experiments. Gate-lag measurements reveal the decrease of the fast-state surface traps and the increase of slow-state traps after the passivation layer removal. It is postulated that consistent surface charging relieves the electric field peak on the gate edge, thus the inverse piezoelectric effect is shielded.

  15. Gating of Permanent Molds for ALuminum Casting (Technical Report...

    Office of Scientific and Technical Information (OSTI)

    problems caused by improper gating are entrained aluminum oxide films and entrapped gas. ... Publication Date: 2004-03-30 OSTI Identifier: 822451 DOE Contract Number: FC36-01ID13983 ...

  16. Sliding-gate valve

    DOE Patents [OSTI]

    Usnick, George B.; Ward, Gene T.; Blair, Henry O.; Roberts, James W.; Warner, Terry N.

    1979-01-01

    This invention is a novel valve of the slidable-gate type. The valve is designed especially for long-term use with highly abrasive slurries. The sealing surfaces of the gate are shielded by the valve seats when the valve is fully open or closed, and the gate-to-seat clearance is swept with an inflowing purge gas while the gate is in transit. A preferred form of the valve includes an annular valve body containing an annular seat assembly defining a flow channel. The seat assembly comprises a first seat ring which is slidably and sealably mounted in the body, and a second seat ring which is tightly fitted in the body. These rings cooperatively define an annular gap which, together with passages in the valve body, forms a guideway extending normal to the channel. A plate-type gate is mounted for reciprocation in the guideway between positions where a portion of the plate closes the channel and where a circular aperture in the gate is in register with the channel. The valve casing includes opposed chambers which extend outwardly from the body along the axis of the guideway to accommodate the end portions of the gate. The chambers are sealed from atmosphere; when the gate is in transit, purge gas is admitted to the chambers and flows inwardly through the gate-to-seat-ring, clearance, minimizing buildup of process solids therein. A shaft reciprocated by an external actuator extends into one of the sealed chambers through a shaft seal and is coupled to an end of the gate. Means are provided for adjusting the clearance between the first seat ring and the gate while the valve is in service.

  17. Optical NAND gate

    DOE Patents [OSTI]

    Skogen, Erik J.; Raring, James; Tauke-Pedretti, Anna

    2011-08-09

    An optical NAND gate is formed from two pair of optical waveguide devices on a substrate, with each pair of the optical waveguide devices consisting of an electroabsorption modulator and a photodetector. One pair of the optical waveguide devices is electrically connected in parallel to operate as an optical AND gate; and the other pair of the optical waveguide devices is connected in series to operate as an optical NOT gate (i.e. an optical inverter). The optical NAND gate utilizes two digital optical inputs and a continuous light input to provide a NAND function output. The optical NAND gate can be formed from III-V compound semiconductor layers which are epitaxially deposited on a III-V compound semiconductor substrate, and operates at a wavelength in the range of 0.8-2.0 .mu.m.

  18. Reduction of skin effect losses in double-level-T-gate structure

    SciTech Connect (OSTI)

    Mikulics, M. Hardtdegen, H.; Arango, Y. C.; Adam, R.; Fox, A.; Grützmacher, D.; Gregušová, D.; Novák, J.; Stanček, S.; Kordoš, P.; Sofer, Z.; Juul, L.; Marso, M.

    2014-12-08

    We developed a T-gate technology based on selective wet etching yielding 200 nm wide T-gate structures used for fabrication of High Electron Mobility Transistors (HEMT). Major advantages of our process are the use of only standard photolithographic process and the ability to generate T-gate stacks. A HEMT fabricated on AlGaN/GaN/sapphire with gate length L{sub g} = 200 nm and double-stacked T-gates exhibits 60 GHz cutoff frequency showing ten-fold improvement compared to 6 GHz for the same device with 2 μm gate length. HEMTs with a double-level-T-gate (DLTG) structure exhibit up to 35% improvement of f{sub max} value compared to a single T-gate device. This indicates a significant reduction of skin effect losses in DLTG structure compared to its standard T-gate counterpart. These results agree with the theoretical predictions.

  19. Probing Organic Transistors with Infrared Beams

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Probing Organic Transistors with Infrared Beams Probing Organic Transistors with Infrared Beams Print Wednesday, 26 July 2006 00:00 Silicon-based transistors are well-understood, basic components of contemporary electronic technology. In contrast, there is growing need for the development of electronic devices based on organic polymer materials. Organic field-effect transistors (FETs) are ideal for special applications that require large areas, light weight, and structural flexibility. They also

  20. Nonlinear photoresponse of field effect transistors terahertz detectors at high irradiation intensities

    SciTech Connect (OSTI)

    But, D. B.; Drexler, C.; Ganichev, S. D.; Sakhno, M. V.; Sizov, F. F.; Dyakonova, N.; Drachenko, O.; Gutin, A.; Knap, W.

    2014-04-28

    Terahertz power dependence of the photoresponse of field effect transistors, operating at frequencies from 0.1 to 3 THz for incident radiation power density up to 100?kW/cm{sup 2} was studied for Si metaloxidesemiconductor field-effect transistors and InGaAs high electron mobility transistors. The photoresponse increased linearly with increasing radiation intensity up to the kW/cm{sup 2} range. Nonlinearity followed by saturation of the photoresponse was observed for all investigated field effect transistors for intensities above several kW/cm{sup 2}. The observed photoresponse nonlinearity is explained by nonlinearity and saturation of the transistor channel current. A theoretical model of terahertz field effect transistor photoresponse at high intensity was developed. The model explains quantitative experimental data both in linear and nonlinear regions. Our results show that dynamic range of field effect transistors is very high and can extend over more than six orders of magnitudes of power densities (from ?0.5 mW/cm{sup 2} to ?5?kW/cm{sup 2})

  1. Optical NOR gate

    DOE Patents [OSTI]

    Skogen, Erik J.; Tauke-Pedretti, Anna

    2011-09-06

    An optical NOR gate is formed from two pair of optical waveguide devices on a substrate, with each pair of the optical waveguide devices consisting of an electroabsorption modulator electrically connected in series with a waveguide photodetector. The optical NOR gate utilizes two digital optical inputs and a continuous light input to provide a NOR function digital optical output. The optical NOR gate can be formed from III-V compound semiconductor layers which are epitaxially deposited on a III-V compound semiconductor substrate, and operates at a wavelength in the range of 0.8-2.0 .mu.m.

  2. Optical XOR gate

    DOE Patents [OSTI]

    Vawter, G. Allen

    2013-11-12

    An optical XOR gate is formed as a photonic integrated circuit (PIC) from two sets of optical waveguide devices on a substrate, with each set of the optical waveguide devices including an electroabsorption modulator electrically connected in series with a waveguide photodetector. The optical XOR gate utilizes two digital optical inputs to generate an XOR function digital optical output. The optical XOR gate can be formed from III-V compound semiconductor layers which are epitaxially deposited on a III-V compound semiconductor substrate, and operates at a wavelength in the range of 0.8-2.0 .mu.m.

  3. Silicon-on-insulator field effect transistor with improved body ties for rad-hard applications

    DOE Patents [OSTI]

    Schwank, James R.; Shaneyfelt, Marty R.; Draper, Bruce L.; Dodd, Paul E.

    2001-01-01

    A silicon-on-insulator (SOI) field-effect transistor (FET) and a method for making the same are disclosed. The SOI FET is characterized by a source which extends only partially (e.g. about half-way) through the active layer wherein the transistor is formed. Additionally, a minimal-area body tie contact is provided with a short-circuit electrical connection to the source for reducing floating body effects. The body tie contact improves the electrical characteristics of the transistor and also provides an improved single-event-upset (SEU) radiation hardness of the device for terrestrial and space applications. The SOI FET also provides an improvement in total-dose radiation hardness as compared to conventional SOI transistors fabricated without a specially prepared hardened buried oxide layer. Complementary n-channel and p-channel SOI FETs can be fabricated according to the present invention to form integrated circuits (ICs) for commercial and military applications.

  4. Negative differential transconductance in electrolyte-gated ruthenate

    SciTech Connect (OSTI)

    Hassan, Muhammad Umair; Dhoot, Anoop Singh; Wimbush, Stuart C.

    2015-01-19

    We report on a study of electric field-induced doping of the highly conductive ruthenate SrRuO{sub 3} using an ionic liquid as the gate dielectric in a field-effect transistor configuration. Two distinct carrier transport regimes are identified for increasing positive gate voltage in thin (10 nm) films grown heteroepitaxially on SrTiO{sub 3} substrates. For V{sub g} = 2 V and lower, the sample shows an increased conductivity of up to 13%, as might be expected for electron doping of a metal. At higher V{sub g} = 2.5 V, we observe a large decrease in electrical conductivity of >20% (at 4.2 K) due to the prevalence of strongly blocked conduction pathways.

  5. Oxide

    SciTech Connect (OSTI)

    2014-07-15

    Oxide is a modular framework for feature extraction and analysis of executable files. Oxide is useful in a variety of reverse engineering and categorization tasks relating to executable content.

  6. Reliability of AlGaN/GaN high electron mobility transistors on low dislocation density bulk GaN substrate: Implications of surface step edges

    SciTech Connect (OSTI)

    Killat, N. E-mail: Martin.Kuball@bristol.ac.uk; Montes Bajo, M.; Kuball, M. E-mail: Martin.Kuball@bristol.ac.uk; Paskova, T.; Materials Science and Engineering Department, North Carolina State University, Raleigh, North Carolina 27695 ; Evans, K. R.; Leach, J.; Electrical and Computer Engineering Department, Virginia Commonwealth University, Richmond, Virginia 23284 ; Li, X.; Özgür, Ü.; Morkoç, H.; Chabak, K. D.; Crespo, A.; Gillespie, J. K.; Fitch, R.; Kossler, M.; Walker, D. E.; Trejo, M.; Via, G. D.; Blevins, J. D.

    2013-11-04

    To enable gaining insight into degradation mechanisms of AlGaN/GaN high electron mobility transistors, devices grown on a low-dislocation-density bulk-GaN substrate were studied. Gate leakage current and electroluminescence (EL) monitoring revealed a progressive appearance of EL spots during off-state stress which signify the generation of gate current leakage paths. Atomic force microscopy evidenced the formation of semiconductor surface pits at the failure location, which corresponds to the interaction region of the gate contact edge and the edges of surface steps.

  7. Formation of low resistivity titanium silicide gates in semiconductor integrated circuits

    DOE Patents [OSTI]

    Ishida, Emi

    1999-08-10

    A method of forming a titanium silicide (69) includes the steps of forming a transistor having a source region (58), a drain region (60) and a gate structure (56) and forming a titanium layer (66) over the transistor. A first anneal is performed with a laser anneal at an energy level that causes the titanium layer (66) to react with the gate structure (56) to form a high resistivity titanium silicide phase (68) having substantially small grain sizes. The unreacted portions of the titanium layer (66) are removed and a second anneal is performed, thereby causing the high resistivity titanium silicide phase (68) to convert to a low resistivity titanium silicide phase (69). The small grain sizes obtained by the first anneal allow low resistivity titanium silicide phase (69) to be achieved at device geometries less than about 0.25 micron.

  8. Semianalytical quantum model for graphene field-effect transistors

    SciTech Connect (OSTI)

    Pugnaghi, Claudio; Grassi, Roberto Gnudi, Antonio; Di Lecce, Valerio; Gnani, Elena; Reggiani, Susanna; Baccarani, Giorgio

    2014-09-21

    We develop a semianalytical model for monolayer graphene field-effect transistors in the ballistic limit. Two types of devices are considered: in the first device, the source and drain regions are doped by charge transfer with Schottky contacts, while, in the second device, the source and drain regions are doped electrostatically by a back gate. The model captures two important effects that influence the operation of both devices: (i) the finite density of states in the source and drain regions, which limits the number of states available for transport and can be responsible for negative output differential resistance effects, and (ii) quantum tunneling across the potential steps at the source-channel and drain-channel interfaces. By comparison with a self-consistent non-equilibrium Green's function solver, we show that our model provides very accurate results for both types of devices, in the bias region of quasi-saturation as well as in that of negative differential resistance.

  9. A spin filter transistor made of topological Weyl semimetal

    SciTech Connect (OSTI)

    Shi, Zhangsheng; Wang, Maoji; Wu, Jiansheng

    2015-09-07

    Topological boundary states (TBSs) in Weyl semimetal (WSM) thin film can induce tunneling. Such TBSs are spin polarized inducing spin-polarized current, which can be used to build a spin-filter transistor (SFT) in spintronics. The WSM thin film can be viewed as a series of decoupled quantum anomalous Hall insulator (QAHI) wires connected in parallel, so compared with the proposed SFT made of QAHI nanowire, this SFT has a broader working energy region and easier to be manipulated. And within a narrow region outside this energy domain, the 2D WSM is with very low conductance, so it makes a good on/off switch device with controllable chemical potential induced by liquid ion gate. We also construct a loop device made of 2D WSM with inserted controllable flux to control the polarized current.

  10. Probing Organic Transistors with Infrared Beams

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Probing Organic Transistors with Infrared Beams Print Silicon-based transistors are well-understood, basic components of contemporary electronic technology. In contrast, there is growing need for the development of electronic devices based on organic polymer materials. Organic field-effect transistors (FETs) are ideal for special applications that require large areas, light weight, and structural flexibility. They also have the advantage of being easy to mass-produce at very low cost. However,

  11. Single-transistor-clocked flip-flop

    DOE Patents [OSTI]

    Zhao, Peiyi; Darwish, Tarek; Bayoumi, Magdy

    2005-08-30

    The invention provides a low power, high performance flip-flop. The flip-flop uses only one clocked transistor. The single clocked transistor is shared by the first and second branches of the device. A pulse generator produces a clock pulse to trigger the flip-flop. In one preferred embodiment the device can be made as a static explicit pulsed flip-flop which employs only two clocked transistors.

  12. Probing Organic Transistors with Infrared Beams

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Probing Organic Transistors with Infrared Beams Print Silicon-based transistors are well-understood, basic components of contemporary electronic technology. In contrast, there is growing need for the development of electronic devices based on organic polymer materials. Organic field-effect transistors (FETs) are ideal for special applications that require large areas, light weight, and structural flexibility. They also have the advantage of being easy to mass-produce at very low cost. However,

  13. Probing Organic Transistors with Infrared Beams

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Probing Organic Transistors with Infrared Beams Print Silicon-based transistors are well-understood, basic components of contemporary electronic technology. In contrast, there is growing need for the development of electronic devices based on organic polymer materials. Organic field-effect transistors (FETs) are ideal for special applications that require large areas, light weight, and structural flexibility. They also have the advantage of being easy to mass-produce at very low cost. However,

  14. Complementary junction heterostructure field-effect transistor

    DOE Patents [OSTI]

    Baca, Albert G.; Drummond, Timothy J.; Robertson, Perry J.; Zipperian, Thomas E.

    1995-01-01

    A complimentary pair of compound semiconductor junction heterostructure field-effect transistors and a method for their manufacture are disclosed. The p-channel junction heterostructure field-effect transistor uses a strained layer to split the degeneracy of the valence band for a greatly improved hole mobility and speed. The n-channel device is formed by a compatible process after removing the strained layer. In this manner, both types of transistors may be independently optimized. Ion implantation is used to form the transistor active and isolation regions for both types of complimentary devices. The invention has uses for the development of low power, high-speed digital integrated circuits.

  15. Complementary junction heterostructure field-effect transistor

    DOE Patents [OSTI]

    Baca, A.G.; Drummond, T.J.; Robertson, P.J.; Zipperian, T.E.

    1995-12-26

    A complimentary pair of compound semiconductor junction heterostructure field-effect transistors and a method for their manufacture are disclosed. The p-channel junction heterostructure field-effect transistor uses a strained layer to split the degeneracy of the valence band for a greatly improved hole mobility and speed. The n-channel device is formed by a compatible process after removing the strained layer. In this manner, both types of transistors may be independently optimized. Ion implantation is used to form the transistor active and isolation regions for both types of complimentary devices. The invention has uses for the development of low power, high-speed digital integrated circuits. 10 figs.

  16. Probing Organic Transistors with Infrared Beams

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    materials. Organic field-effect transistors (FETs) are ideal for special applications that require large areas, light ... The prospect of electronic devices incorporating lightweight...

  17. Probing Organic Transistors with Infrared Beams

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    there is growing need for the development of electronic devices based on organic polymer materials. Organic field-effect transistors (FETs) are ideal for special applications...

  18. Universal power transistor base drive control unit

    DOE Patents [OSTI]

    Gale, Allan R.; Gritter, David J.

    1988-01-01

    A saturation condition regulator system for a power transistor which achieves the regulation objectives of a Baker clamp but without dumping excess base drive current into the transistor output circuit. The base drive current of the transistor is sensed and used through an active feedback circuit to produce an error signal which modulates the base drive current through a linearly operating FET. The collector base voltage of the power transistor is independently monitored to develop a second error signal which is also used to regulate base drive current. The current-sensitive circuit operates as a limiter. In addition, a fail-safe timing circuit is disclosed which automatically resets to a turn OFF condition in the event the transistor does not turn ON within a predetermined time after the input signal transition.

  19. Universal power transistor base drive control unit

    DOE Patents [OSTI]

    Gale, A.R.; Gritter, D.J.

    1988-06-07

    A saturation condition regulator system for a power transistor is disclosed which achieves the regulation objectives of a Baker clamp but without dumping excess base drive current into the transistor output circuit. The base drive current of the transistor is sensed and used through an active feedback circuit to produce an error signal which modulates the base drive current through a linearly operating FET. The collector base voltage of the power transistor is independently monitored to develop a second error signal which is also used to regulate base drive current. The current-sensitive circuit operates as a limiter. In addition, a fail-safe timing circuit is disclosed which automatically resets to a turn OFF condition in the event the transistor does not turn ON within a predetermined time after the input signal transition. 2 figs.

  20. Investigation of defect-induced abnormal body current in fin field-effect-transistors

    SciTech Connect (OSTI)

    Liu, Kuan-Ju; Tsai, Jyun-Yu; Lu, Ying-Hsin; Liu, Xi-Wen; Chang, Ting-Chang; Chen, Ching-En; Yang, Ren-Ya; Cheng, Osbert; Huang, Cheng-Tung

    2015-08-24

    This letter investigates the mechanism of abnormal body current at the linear region in n-channel high-k/metal gate stack fin field effect transistors. Unlike body current, which is generated by impact ionization at high drain voltages, abnormal body current was found to increase with decreasing drain voltages. Notably, the unusual body leakage only occurs in three-dimensional structure devices. Based on measurements under different operation conditions, the abnormal body current can be attributed to fin surface defect-induced leakage current, and the mechanism is electron tunneling to the fin via the defects, resulting in holes left at the body terminal.

  1. High-voltage field effect transistors with wide-bandgap β-Ga{sub 2}O{sub 3} nanomembranes

    SciTech Connect (OSTI)

    Hwang, Wan Sik E-mail: djena@nd.edu; Verma, Amit; Protasenko, Vladimir; Rouvimov, Sergei; Xing, Huili; Seabaugh, Alan; Jena, Debdeep E-mail: djena@nd.edu; Peelaers, Hartwin; Van de Walle, Chris; Haensch, Wilfried; Galazka, Zbigniew; Albrecht, Martin; Fornari, Roberto

    2014-05-19

    Nanoscale semiconductor materials have been extensively investigated as the channel materials of transistors for energy-efficient low-power logic switches to enable scaling to smaller dimensions. On the opposite end of transistor applications is power electronics for which transistors capable of switching very high voltages are necessary. Miniaturization of energy-efficient power switches can enable the integration with various electronic systems and lead to substantial boosts in energy efficiency. Nanotechnology is yet to have an impact in this arena. In this work, it is demonstrated that nanomembranes of the wide-bandgap semiconductor gallium oxide can be used as channels of transistors capable of switching high voltages, and at the same time can be integrated on any platform. The findings mark a step towards using lessons learnt in nanomaterials and nanotechnology to address a challenge that yet remains untouched by the field.

  2. Silicon field-effect transistors as radiation detectors for the Sub-THz range

    SciTech Connect (OSTI)

    But, D. B. Golenkov, O. G.; Sakhno, N. V.; Sizov, F. F.; Korinets, S. V.; Gumenjuk-Sichevska, J. V.; Reva, V. P.; Bunchuk, S. G.

    2012-05-15

    The nonresonance response of silicon metal-oxide-semiconductor field-effect transistors (Si-MOSFETs) with a long channel (1-20 {mu}m) to radiation in the frequency range 43-135 GHz is studied. The transistors are fabricated by the standard CMOS technology with 1-{mu}m design rules. The volt-watt sensitivity and the noise equivalent power (NEP) for such detectors are estimated with the calculated effective area of the detecting element taken into account. It is shown that such transistors can operate at room temperature as broadband direct detectors of sub-THz radiation. In the 4-5 mm range of wavelengths, the volt-watt sensitivity can be as high as tens of kV/W and the NEP can amount to 10{sup -11} - 10{sup -12}W/{radical}Hz . The parameters of detectors under study can be improved by the optimization of planar antennas.

  3. Giant amplification of tunnel magnetoresistance in a molecular junction: Molecular spin-valve transistor

    SciTech Connect (OSTI)

    Dhungana, Kamal B.; Pati, Ranjit

    2014-04-21

    Amplification of tunnel magnetoresistance by gate field in a molecular junction is the most important requirement for the development of a molecular spin valve transistor. Herein, we predict a giant amplification of tunnel magnetoresistance in a single molecular spin valve junction, which consists of Ru-bis-terpyridine molecule as a spacer between two ferromagnetic nickel contacts. Based on the first-principles quantum transport approach, we show that a modest change in the gate field that is experimentally accessible can lead to a substantial amplification (320%) of tunnel magnetoresistance. The origin of such large amplification is attributed to the spin dependent modification of orbitals at the molecule-lead interface and the resultant Stark effect induced shift in channel position with respect to the Fermi energy.

  4. In situ electrical characterization of palladium-based single electron transistors made by electromigration technique

    SciTech Connect (OSTI)

    Arzubiaga, L.; Llopis, R.; Golmar, F.; Casanova, F.; Hueso, L. E.

    2014-11-15

    We report the fabrication of single electron transistors (SETs) by feedback-controlled electromigration of palladium and palladium-nickel alloy nanowires. We have optimized a gradual electromigration process for obtaining devices consisting of three terminals (source, drain and gate electrodes), which are capacitively coupled to a metallic cluster of nanometric dimensions. This metal nanocluster forms into the inter-electrode channel during the electromigration process and constitutes the active element of each device, acting as a quantum dot that rules the electron flow between source and drain electrodes. The charge transport of the as-fabricated devices shows Coulomb blockade characteristics and the source to drain conductance can be modulated by electrostatic gating. We have thus achieved the fabrication and in situ measurement of palladium-based SETs inside a liquid helium cryostat chamber.

  5. Compact gate valve

    DOE Patents [OSTI]

    Bobo, Gerald E.

    1977-01-01

    This invention relates to a double-disc gate valve which is compact, comparatively simple to construct, and capable of maintaining high closing pressures on the valve discs with low frictional forces. The valve casing includes axially aligned ports. Mounted in the casing is a sealed chamber which is pivotable transversely of the axis of the ports. The chamber contains the levers for moving the valve discs axially, and an actuator for the levers. When an external drive means pivots the chamber to a position where the discs are between the ports and axially aligned therewith, the actuator for the levers is energized to move the discs into sealing engagement with the ports.

  6. ONE SHAKE GATE FORMER

    DOE Patents [OSTI]

    Kalibjian, R.; Perez-Mendez, V.

    1957-08-20

    An improved circuit for forming square pulses having substantially short and precise durations is described. The gate forming circuit incorporates a secondary emission R. F. pentode adapted to receive input trigger pulses amd having a positive feedback loop comnected from the dynode to the control grid to maintain conduction in response to trigger pulses. A short circuited pulse delay line is employed to precisely control the conducting time of the tube and a circuit for squelching spurious oscillations is provided in the feedback loop.

  7. Penn State DOE GATE Program

    SciTech Connect (OSTI)

    Anstrom, Joel

    2012-08-31

    The Graduate Automotive Technology Education (GATE) Program at The Pennsylvania State University (Penn State) was established in October 1998 pursuant to an award from the U.S. Department of Energy (U.S. DOE). The focus area of the Penn State GATE Program is advanced energy storage systems for electric and hybrid vehicles.

  8. Method for producing silicon thin-film transistors with enhanced forward current drive

    DOE Patents [OSTI]

    Weiner, Kurt H.

    1998-01-01

    A method for fabricating amorphous silicon thin film transistors (TFTs) with a polycrystalline silicon surface channel region for enhanced forward current drive. The method is particularly adapted for producing top-gate silicon TFTs which have the advantages of both amorphous and polycrystalline silicon TFTs, but without problem of leakage current of polycrystalline silicon TFTs. This is accomplished by selectively crystallizing a selected region of the amorphous silicon, using a pulsed excimer laser, to create a thin polycrystalline silicon layer at the silicon/gate-insulator surface. The thus created polysilicon layer has an increased mobility compared to the amorphous silicon during forward device operation so that increased drive currents are achieved. In reverse operation the polysilicon layer is relatively thin compared to the amorphous silicon, so that the transistor exhibits the low leakage currents inherent to amorphous silicon. A device made by this method can be used, for example, as a pixel switch in an active-matrix liquid crystal display to improve display refresh rates.

  9. Method for producing silicon thin-film transistors with enhanced forward current drive

    DOE Patents [OSTI]

    Weiner, K.H.

    1998-06-30

    A method is disclosed for fabricating amorphous silicon thin film transistors (TFTs) with a polycrystalline silicon surface channel region for enhanced forward current drive. The method is particularly adapted for producing top-gate silicon TFTs which have the advantages of both amorphous and polycrystalline silicon TFTs, but without problem of leakage current of polycrystalline silicon TFTs. This is accomplished by selectively crystallizing a selected region of the amorphous silicon, using a pulsed excimer laser, to create a thin polycrystalline silicon layer at the silicon/gate-insulator surface. The thus created polysilicon layer has an increased mobility compared to the amorphous silicon during forward device operation so that increased drive currents are achieved. In reverse operation the polysilicon layer is relatively thin compared to the amorphous silicon, so that the transistor exhibits the low leakage currents inherent to amorphous silicon. A device made by this method can be used, for example, as a pixel switch in an active-matrix liquid crystal display to improve display refresh rates. 1 fig.

  10. Method of fabrication of display pixels driven by silicon thin film transistors

    DOE Patents [OSTI]

    Carey, Paul G.; Smith, Patrick M.

    1999-01-01

    Display pixels driven by silicon thin film transistors are fabricated on plastic substrates for use in active matrix displays, such as flat panel displays. The process for forming the pixels involves a prior method for forming individual silicon thin film transistors on low-temperature plastic substrates. Low-temperature substrates are generally considered as being incapable of withstanding sustained processing temperatures greater than about 200.degree. C. The pixel formation process results in a complete pixel and active matrix pixel array. A pixel (or picture element) in an active matrix display consists of a silicon thin film transistor (TFT) and a large electrode, which may control a liquid crystal light valve, an emissive material (such as a light emitting diode or LED), or some other light emitting or attenuating material. The pixels can be connected in arrays wherein rows of pixels contain common gate electrodes and columns of pixels contain common drain electrodes. The source electrode of each pixel TFT is connected to its pixel electrode, and is electrically isolated from every other circuit element in the pixel array.

  11. Thermal Transistor for Energy Smart Buildings

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Thermal Transistor for Energy Smart Buildings Thermal Transistor for Energy Smart Buildings Assumptions & Limitations: * Current LANL prototype: ~50 cm 2 active area. Assume it can be scaled to sq.ft size relevant for applications * Switching requires ~200 Volts but only draws a few µA. The associated drive electronics comprises only off-the- shelf components. Thermally adaptive devices and systems may be a game changer in energy efficiency, buildings and beyond: * Thermally agile walls can

  12. Gate Hours & Services | Stanford Synchrotron Radiation Lightsource

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    personnel contactdirectory (SLAC phone directory) assistance, and directions and maps. ... Satellite view | Aerial view detail Gate 17 Sector 30 Gate 247 proximity access for ...

  13. Low temperature thin film transistors with hollow cathode plasma-assisted atomic layer deposition based GaN channels

    SciTech Connect (OSTI)

    Bolat, S. E-mail: aokyay@ee.bilkent.edu.tr; Tekcan, B.; Ozgit-Akgun, C.; Biyikli, N.; Okyay, A. K. E-mail: aokyay@ee.bilkent.edu.tr

    2014-06-16

    We report GaN thin film transistors (TFT) with a thermal budget below 250?C. GaN thin films are grown at 200?C by hollow cathode plasma-assisted atomic layer deposition (HCPA-ALD). HCPA-ALD-based GaN thin films are found to have a polycrystalline wurtzite structure with an average crystallite size of 9.3?nm. TFTs with bottom gate configuration are fabricated with HCPA-ALD grown GaN channel layers. Fabricated TFTs exhibit n-type field effect characteristics. N-channel GaN TFTs demonstrated on-to-off ratios (I{sub ON}/I{sub OFF}) of 10{sup 3} and sub-threshold swing of 3.3?V/decade. The entire TFT device fabrication process temperature is below 250?C, which is the lowest process temperature reported for GaN based transistors, so far.

  14. Single molecule transistor based nanopore for the detection of nicotine

    SciTech Connect (OSTI)

    Ray, S. J.

    2014-12-28

    A nanopore based detection methodology was proposed and investigated for the detection of Nicotine. This technique uses a Single Molecular Transistor working as a nanopore operational in the Coulomb Blockade regime. When the Nicotine molecule is pulled through the nanopore area surrounded by the Source(S), Drain (D), and Gate electrodes, the charge stability diagram can detect the presence of the molecule and is unique for a specific molecular structure. Due to the weak coupling between the different electrodes which is set by the nanopore size, the molecular energy states stay almost unaffected by the electrostatic environment that can be realised from the charge stability diagram. Identification of different orientation and position of the Nicotine molecule within the nanopore area can be made from specific regions of overlap between different charge states on the stability diagram that could be used as an electronic fingerprint for detection. This method could be advantageous and useful to detect the presence of Nicotine in smoke which is usually performed using chemical chromatography techniques.

  15. Graphene nanopore field effect transistors

    SciTech Connect (OSTI)

    Qiu, Wanzhi; Skafidas, Efstratios

    2014-07-14

    Graphene holds great promise for replacing conventional Si material in field effect transistors (FETs) due to its high carrier mobility. Previously proposed graphene FETs either suffer from low ON-state current resulting from constrained channel width or require complex fabrication processes for edge-defecting or doping. Here, we propose an alternative graphene FET structure created on intrinsic metallic armchair-edged graphene nanoribbons with uniform width, where the channel region is made semiconducting by drilling a pore in the interior, and the two ends of the nanoribbon act naturally as connecting electrodes. The proposed GNP-FETs have high ON-state currents due to seamless atomic interface between the channel and electrodes and are able to be created with arbitrarily wide ribbons. In addition, the performance of GNP-FETs can be tuned by varying pore size and ribbon width. As a result, their performance and fabrication process are more predictable and controllable in comparison to schemes based on edge-defects and doping. Using first-principle transport calculations, we show that GNP-FETs can achieve competitive leakage current of ∼70 pA, subthreshold swing of ∼60 mV/decade, and significantly improved On/Off current ratios on the order of 10{sup 5} as compared with other forms of graphene FETs.

  16. Gate Solar | Open Energy Information

    Open Energy Info (EERE)

    Spain Sector: Solar Product: JV set up for the promotion, exploitation and sale of photovoltaic solar power plants. References: Gate Solar1 This article is a stub. You can help...

  17. High Accuracy Transistor Compact Model Calibrations

    SciTech Connect (OSTI)

    Hembree, Charles E.; Mar, Alan; Robertson, Perry J.

    2015-09-01

    Typically, transistors are modeled by the application of calibrated nominal and range models. These models consists of differing parameter values that describe the location and the upper and lower limits of a distribution of some transistor characteristic such as current capacity. Correspond- ingly, when using this approach, high degrees of accuracy of the transistor models are not expected since the set of models is a surrogate for a statistical description of the devices. The use of these types of models describes expected performances considering the extremes of process or transistor deviations. In contrast, circuits that have very stringent accuracy requirements require modeling techniques with higher accuracy. Since these accurate models have low error in transistor descriptions, these models can be used to describe part to part variations as well as an accurate description of a single circuit instance. Thus, models that meet these stipulations also enable the calculation of quantifi- cation of margins with respect to a functional threshold and uncertainties in these margins. Given this need, new model high accuracy calibration techniques for bipolar junction transis- tors have been developed and are described in this report.

  18. Antiferromagnetic Spin Wave Field-Effect Transistor (Journal...

    Office of Scientific and Technical Information (OSTI)

    Antiferromagnetic Spin Wave Field-Effect Transistor Citation Details ... Type: Accepted Manuscript Journal Name: Scientific Reports Additional Journal Information: ...

  19. Latest design of gate valves

    SciTech Connect (OSTI)

    Kurzhofer, U.; Stolte, J.; Weyand, M.

    1996-12-01

    Babcock Sempell, one of the most important valve manufacturers in Europe, has delivered valves for the nuclear power industry since the beginning of the peaceful application of nuclear power in the 1960s. The latest innovation by Babcock Sempell is a gate valve that meets all recent technical requirements of the nuclear power technology. At the moment in the United States, Germany, Sweden, and many other countries, motor-operated gate and globe valves are judged very critically. Besides the absolute control of the so-called {open_quotes}trip failure,{close_quotes} the integrity of all valve parts submitted to operational forces must be maintained. In case of failure of the limit and torque switches, all valve designs have been tested with respect to the quality of guidance of the gate. The guidances (i.e., guides) shall avoid a tilting of the gate during the closing procedure. The gate valve newly designed by Babcock Sempell fulfills all these characteristic criteria. In addition, the valve has cobalt-free seat hardfacing, the suitability of which has been proven by friction tests as well as full-scale blowdown tests at the GAP of Siemens in Karlstein, West Germany. Babcock Sempell was to deliver more than 30 gate valves of this type for 5 Swedish nuclear power stations by autumn 1995. In the presentation, the author will report on the testing performed, qualifications, and sizing criteria which led to the new technical design.

  20. Stretchable transistors with buckled carbon nanotube films as conducting channels

    DOE Patents [OSTI]

    Arnold, Michael S; Xu, Feng

    2015-03-24

    Thin-film transistors comprising buckled films comprising carbon nanotubes as the conductive channel are provided. Also provided are methods of fabricating the transistors. The transistors, which are highly stretchable and bendable, exhibit stable performance even when operated under high tensile strains.

  1. Self-protecting transistor oscillator for treating animal tissues

    DOE Patents [OSTI]

    Doss, James D.

    1980-01-01

    A transistor oscillator circuit wherein the load current applied to animal tissue treatment electrodes is fed back to the transistor. Removal of load is sensed to automatically remove feedback and stop oscillations. A thermistor on one treatment electrode senses temperature, and by means of a control circuit controls oscillator transistor current.

  2. Air-gap gating of MgZnO/ZnO heterostructures

    SciTech Connect (OSTI)

    Tambo, T.; Falson, J. Kozuka, Y.; Maryenko, D.; Tsukazaki, A.; Kawasaki, M.

    2014-08-28

    The adaptation of air-gap dielectric based field-effect transistor technology to controlling the MgZnO/ZnO heterointerface confined two-dimensional electron system (2DES) is reported. We find it possible to tune the charge density of the 2DES via a gate electrode spatially separated from the heterostructure surface by a distance of 5??m. Under static gating, the observation of the quantum Hall effect suggests that the charge carrier density remains homogeneous, with the 2DES in the 3?mm square sample the sole conductor. The availability of this technology enables the exploration of the charge carrier density degree of freedom in the pristine sample limit.

  3. Gate-tunable gigantic lattice deformation in VO{sub 2}

    SciTech Connect (OSTI)

    Okuyama, D. E-mail: nakano@imr.tohoku.ac.jp Hatano, T.; Nakano, M. E-mail: nakano@imr.tohoku.ac.jp; Takeshita, S.; Ohsumi, H.; Tardif, S.; Shibuya, K.; Yumoto, H.; Koyama, T.; Ohashi, H.; Takata, M.; Kawasaki, M.; Tokura, Y.; Iwasa, Y. E-mail: nakano@imr.tohoku.ac.jp; Arima, T.

    2014-01-13

    We examined the impact of electric field on crystal lattice of vanadium dioxide (VO{sub 2}) in a field-effect transistor geometry by in-situ synchrotron x-ray diffraction measurements. Whereas the c-axis lattice parameter of VO{sub 2} decreases through the thermally induced insulator-to-metal phase transition, the gate-induced metallization was found to result in a significant increase of the c-axis length by almost 1% from that of the thermally stabilized insulating state. We also found that this gate-induced gigantic lattice deformation occurs even at the thermally stabilized metallic state, enabling dynamic control of c-axis lattice parameter by more than 1% at room temperature.

  4. Magnetic field effect on the terahertz emission from nanometer InGaAs/AlInAs high electron mobility transistors

    SciTech Connect (OSTI)

    Dyakonova, N.; Teppe, F.; Lusakowski, J.; Knap, W.; Levinshtein, M.; Dmitriev, A.P.; Shur, M.S.; Bollaert, S.; Cappy, A.

    2005-06-01

    The influence of the magnetic field on the excitation of plasma waves in InGaAs/AlInAs lattice matched high electron mobility transistors is reported. The threshold source-drain voltage of the excitation of the terahertz emission shifts to higher values under a magnetic field increasing from 0 to 6 T. We show that the main change of the emission threshold in relatively low magnetic fields (smaller than approximately 4 T) is due to the magnetoresistance of the ungated parts of the channel. In higher magnetic fields, the effect of the magnetic field on the gated region of the device becomes important.

  5. High-Performance Organic Field-Effect Transistors with Dielectric and Active Layers Printed Sequentially by Ultrasonic Spraying

    SciTech Connect (OSTI)

    Shao, Ming [ORNL; Sanjib, Das [University of Tennessee, Knoxville (UTK); Chen, Jihua [ORNL; Keum, Jong Kahk [ORNL; Ivanov, Ilia N [ORNL; Gu, Gong [University of Tennessee, Knoxville (UTK); Geohegan, David B [ORNL; Xiao, Kai [ORNL

    2013-01-01

    High-performance, flexible organic field-effect transistors (OFETs) are reported with PVP dielectric and TIPS-PEN active layers sequentially deposited by ultrasonic spray-coating on plastic substrate. OFETs fabricated in ambient air with a bottom-gate/top-contact geometry are shown to achieve on/off ratios of >104 and mobilities as high as 0.35 cm2/Vs. These rival the characteristics of the best solution-processible small molecule FETs fabricated by other fabrication methods such as drop casting and ink-jet printing.

  6. Ultra-low noise high electron mobility transistors for high-impedance and low-frequency deep cryogenic readout electronics

    SciTech Connect (OSTI)

    Dong, Q.; Liang, Y. X.; Ferry, D.; Cavanna, A.; Gennser, U.; Couraud, L.; Jin, Y.

    2014-07-07

    We report on the results obtained from specially designed high electron mobility transistors at 4.2?K: the gate leakage current can be limited lower than 1 aA, and the equivalent input noise-voltage and noise-current at 1?Hz can reach 6.3 nV/Hz{sup 1?2} and 20 aA/Hz{sup 1?2}, respectively. These results open the way to realize high performance low-frequency readout electronics under very low-temperature conditions.

  7. Comparative investigation of InGaP/GaAs pseudomorphic field-effect transistors with triple doped-channel profiles

    SciTech Connect (OSTI)

    Tsai, Jung-Hui; Guo, Der-Feng; Lour, Wen-Shiung

    2011-09-15

    In this article, the comparison of DC performance on InGaP/GaAs pseudomorphic field-effect transistors with tripe doped-channel profiles is demonstrated. As compared to the uniform and high-medium-low doped-channel devices, the low-medium-high doped-channel device exhibits the broadest gate voltage swing and the best device linearity because more twodimensional electron gases are formed in the heaviest doped channel to enhance the magnitude of negative threshold voltage. Experimentally, the transconductance within 50% of its maximum value for gate voltage swing is 4.62 V in the low-medium-high doped-channel device, which is greater than 3.58 (3.30) V in the uniform (high-medium-low) doped-channel device.

  8. Wide-bandgap high-mobility ZnO thin-film transistors produced at room temperature

    SciTech Connect (OSTI)

    Fortunato, Elvira M.C.; Barquinha, Pedro M.C.; Pimentel, Ana C.M.B.G.; Goncalves, Alexandra M.F.; Marques, Antonio J.S.; Martins, Rodrigo F.P.; Pereira, Luis M.N.

    2004-09-27

    We report high-performance ZnO thin-film transistor (ZnO-TFT) fabricated by rf magnetron sputtering at room temperature with a bottom gate configuration. The ZnO-TFT operates in the enhancement mode with a threshold voltage of 19 V, a saturation mobility of 27 cm{sup 2}/V s, a gate voltage swing of 1.39 V/decade and an on/off ratio of 3x10{sup 5}. The ZnO-TFT presents an average optical transmission (including the glass substrate) of 80% in the visible part of the spectrum. The combination of transparency, high mobility, and room-temperature processing makes the ZnO-TFT a very promising low-cost optoelectronic device for the next generation of invisible and flexible electronics.

  9. Structural and electrical characterization of CoTiN metal gates

    SciTech Connect (OSTI)

    Wongpiya, Ranida; Ouyang, Jiaomin; Chung, Chia-Jung; Duong, Duc T.; Clemens, Bruce; Deal, Michael; Nishi, Yoshio

    2015-02-21

    As the gate size continues to decrease in nanoscale transistors, having metal gates with amorphous or near amorphous structures can potentially reduce grain-induced work function variation. Furthermore, amorphous materials are known to have superior diffusion barrier properties, which can help prevent work function change due to the diffusion of metals in contact with the gate. In this work we show that with the addition of cobalt, thin films of polycrystalline TiN become more amorphous with a smaller grain size. Co{sub x}(TiN){sub 1-x} films, where x?=?6080%, appear to consist of nanocrystals embedded in an amorphous matrix, and are thermally stable with no significant crystallization up to an annealing temperature of at least 600?C. Reducing the nitrogen gas flow ratio during sputter deposition from 9% to 2.5% further decreases the films' crystallinity, which is apparent by more sparse and even smaller nanocrystals. In addition to being partially amorphous, these CoTiN films also exhibit good thermal stability, low resistivity, low roughness, and have the potential for atomic layer deposition compatibility. Even though these materials are not completely amorphous, their small crystal size and amorphous matrix can potentially reduce work function variation and improve their diffusion barrier property. These properties make CoTiN a good candidate as a gate material for future nanoelectronic devices and technology.

  10. Gallium nitride junction field-effect transistor

    DOE Patents [OSTI]

    Zolper, J.C.; Shul, R.J.

    1999-02-02

    An ion implanted gallium-nitride (GaN) junction field-effect transistor (JFET) and method of making the same are disclosed. Also disclosed are various ion implants, both n- and p-type, together with or without phosphorus co-implantation, in selected III-V semiconductor materials. 19 figs.

  11. Gallium nitride junction field-effect transistor

    DOE Patents [OSTI]

    Zolper, John C.; Shul, Randy J.

    1999-01-01

    An all-ion implanted gallium-nitride (GaN) junction field-effect transistor (JFET) and method of making the same. Also disclosed are various ion implants, both n- and p-type, together with or without phosphorous co-implantation, in selected III-V semiconductor materials.

  12. Radiation Tolerance of 65nm CMOS Transistors

    SciTech Connect (OSTI)

    Krohn, M.; Bentele, B.; Christian, D. C.; Cumalat, J. P.; Deptuch, G.; Fahim, F.; Hoff, J.; Shenai, A.; Wagner, S. R.

    2015-12-11

    We report on the effects of ionizing radiation on 65 nm CMOS transistors held at approximately -20C during irradiation. The pattern of damage observed after a total dose of 1 Grad is similar to damage reported in room temperature exposures, but we observe less damage than was observed at room temperature.

  13. Radiation Tolerance of 65nm CMOS Transistors

    DOE Public Access Gateway for Energy & Science Beta (PAGES Beta)

    Krohn, M.; Bentele, B.; Christian, D. C.; Cumalat, J. P.; Deptuch, G.; Fahim, F.; Hoff, J.; Shenai, A.; Wagner, S. R.

    2015-12-11

    We report on the effects of ionizing radiation on 65 nm CMOS transistors held at approximately -20°C during irradiation. The pattern of damage observed after a total dose of 1 Grad is similar to damage reported in room temperature exposures, but we observe less damage than was observed at room temperature.

  14. Stage-Gate Innovation Management Guidelines

    Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

    Program Stage-Gate Innovation Management Guidelines Managing risk through structured project decision-making February 2007 Version 1.3 Table of Contents Overview of ITP Stage-Gate Innovation Management........................................................ 1 Background............................................................................................................................................. 1 Process

  15. Radial gate evaluation: Olympus Dam, Colorado

    SciTech Connect (OSTI)

    1997-06-01

    The report presents a structural analysis of the radial gates of Olympus Dam in eastern Colorado. Five 20-foot wide by 17-foot high radial gates are used to control flow through the spillway at Olympus Dam. The spillway gates were designed in 1947. The gate arm assemblies consist of two separate wide flange beams, with a single brace between the arms. The arms pivot about a 4.0-inch diameter pin and bronze graphite-insert bushing. The pin is cantilevered from the pier anchor girder. The radial gates are supported by a pin bearing on a pier anchor birder bolted to the end of the concrete pier. The gates are operated by two-part wire rope 15,000-pound capacity hoise. Stoplog slots upstream of the radial gates are provided in the concrete piers. Selected drawings of the gates and hoists are located in appendix A.

  16. Manipulation of transport hysteresis on graphene field effect transistors with Ga ion irradiation

    SciTech Connect (OSTI)

    Wang, Quan, E-mail: wangq@mail.ujs.edu.cn [School of Mechanical Engineering, Jiangsu University, Zhenjiang 212013 (China); State Key Laboratory of Transducer Technology, Chinese Academy of Sciences, Shanghai 200050 (China); Liu, Shuai; Ren, Naifei [School of Mechanical Engineering, Jiangsu University, Zhenjiang 212013 (China)

    2014-09-29

    We have studied the effect of Ga ion irradiation on the controllable hysteretic behavior of graphene field effect transistors fabricated on Si/SO{sub 2} substrates. The various densities of defects in graphene were monitored by Raman spectrum. It was found that the Dirac point shifted to the positive gate voltage constantly, while the hysteretic behavior was enhanced first and then weakened, with the dose of ion irradiation increasing. By contrasting the trap charges density induced by dopant and the total density of effective trap charges, it demonstrated that adsorbate doping was not the decisive factor that induced the hysteretic behavior. The tunneling between the defect sites induced by ion irradiation was also an important cause for the hysteresis.

  17. Random telegraph signals by alkanethiol-protected Au nanoparticles in chemically assembled single-electron transistors

    SciTech Connect (OSTI)

    Kano, Shinya; Azuma, Yasuo; Tanaka, Daisuke; Sakamoto, Masanori; Teranishi, Toshiharu; Smith, Luke W.; Smith, Charles G.; Majima, Yutaka

    2013-12-14

    We have studied random telegraph signals (RTSs) in a chemically assembled single-electron transistor (SET) at temperatures as low as 300 mK. The RTSs in the chemically assembled SET were investigated by measuring the sourcedrain current, using a histogram of the RTS dwell time, and calculating the power spectrum density of the drain currenttime characteristics. It was found that the dwell time of the RTS was dependent on the drain voltage of the SET, but was independent of the gate voltage. Considering the spatial structure of the chemically assembled SET, the origin of the RTS is attributed to the trapped charges on an alkanethiol-protected Au nanoparticle positioned near the SET. These results are important as they will help to realize stable chemically assembled SETs in practical applications.

  18. Microscopic origin of low frequency noise in MoS{sub 2} field-effect transistors

    SciTech Connect (OSTI)

    Ghatak, Subhamoy; Jain, Manish; Ghosh, Arindam; Mukherjee, Sumanta; Sarma, D. D.

    2014-09-01

    We report measurement of low frequency 1/f noise in molybdenum di-sulphide (MoS{sub 2}) field-effect transistors in multiple device configurations including MoS{sub 2} on silicon dioxide as well as MoS{sub 2}-hexagonal boron nitride (hBN) heterostructures. All as-fabricated devices show similar magnitude of noise with number fluctuation as the dominant mechanism at high temperatures and density, although the calculated density of traps is two orders of magnitude higher than that at the SiO{sub 2} interface. Measurements on the heterostructure devices with vacuum annealing and dual gated configuration reveals that along with the channel, metal-MoS{sub 2} contacts also play a significant role in determining noise magnitude in these devices.

  19. Field-effect transistor having a superlattice channel and high carrier velocities at high applied fields

    DOE Patents [OSTI]

    Chaffin, R.J.; Dawson, L.R.; Fritz, I.J.; Osbourn, G.C.; Zipperian, T.E.

    1987-06-08

    A field effect transistor comprises a semiconductor having a source, a drain, a channel and a gate in operational relationship. The semiconductor is a strained layer superlattice comprising alternating quantum well and barrier layers, the quantum well layers and barrier layers being selected from the group of layer pairs consisting of InGaAs/AlGaAs, InAs/InAlGaAs, and InAs/InAlAsP. The layer thicknesses of the quantum well and barrier layers are sufficiently thin that the alternating layers constitute a superlattice which has a superlattice conduction band energy level structure in k-vector space. The layer thicknesses of the quantum well layers are selected to provide a superlattice L/sub 2D/-valley which has a shape which is substantially more two-dimensional than that of said bulk L-valley. 2 figs.

  20. Examination of hot-carrier stress induced degradation on fin field-effect transistor

    SciTech Connect (OSTI)

    Yang, Yi-Lin Yen, Tzu-Sung; Ku, Chao-Chen; Wu, Tai-Hsuan; Wang, Tzuo-Li; Li, Chien-Yi; Wu, Bing-Tze; Zhang, Wenqi; Hong, Jia-Jian; Wong, Jie-Chen; Yeh, Wen-Kuan; Lin, Shih-Hung

    2014-02-24

    Degradation in fin field-effect transistor devices was investigated in detail under various hot-carrier stress conditions. The threshold voltage (V{sub TH}) shift, substrate current (I{sub B}), and subthreshold swing were extracted to determine the degradation of a device. The power-law time exponent of the V{sub TH} shift was largest at V{sub G}?=?0.3 V{sub D}, indicating that the V{sub TH} shift was dominated by interface state generation. Although the strongest impact ionization occurred at V{sub G}?=?V{sub D}, the V{sub TH} shift was mainly caused by electron trapping resulting from a large gate leakage current.

  1. Graduate Automotive Technology Education (GATE) Initiative Awards |

    Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

    Department of Energy Graduate Automotive Technology Education (GATE) Initiative Awards Graduate Automotive Technology Education (GATE) Initiative Awards September 8, 2011 - 11:46am Addthis Graduate Automotive Technology Education (GATE) Initiative Awards DOE's Graduate Automotive Technology Education (GATE) initiative will award $6.4 million over the course of five years to support seven Centers of Excellence at American colleges, universities, and university-affiliated research

  2. Dynamic gating window for compensation of baseline shift in respiratory-gated radiation therapy

    SciTech Connect (OSTI)

    Pepin, Eric W.; Wu Huanmei; Shirato, Hiroki

    2011-04-15

    Purpose: To analyze and evaluate the necessity and use of dynamic gating techniques for compensation of baseline shift during respiratory-gated radiation therapy of lung tumors. Methods: Motion tracking data from 30 lung tumors over 592 treatment fractions were analyzed for baseline shift. The finite state model (FSM) was used to identify the end-of-exhale (EOE) breathing phase throughout each treatment fraction. Using duty cycle as an evaluation metric, several methods of end-of-exhale dynamic gating were compared: An a posteriori ideal gating window, a predictive trend-line-based gating window, and a predictive weighted point-based gating window. These methods were evaluated for each of several gating window types: Superior/inferior (SI) gating, anterior/posterior beam, lateral beam, and 3D gating. Results: In the absence of dynamic gating techniques, SI gating gave a 39.6% duty cycle. The ideal SI gating window yielded a 41.5% duty cycle. The weight-based method of dynamic SI gating yielded a duty cycle of 36.2%. The trend-line-based method yielded a duty cycle of 34.0%. Conclusions: Dynamic gating was not broadly beneficial due to a breakdown of the FSM's ability to identify the EOE phase. When the EOE phase was well defined, dynamic gating showed an improvement over static-window gating.

  3. Impact of La{sub 2}O{sub 3} interfacial layers on InGaAs metal-oxide-semiconductor interface properties in Al{sub 2}O{sub 3}/La{sub 2}O{sub 3}/InGaAs gate stacks deposited by atomic-layer-deposition

    SciTech Connect (OSTI)

    Chang, C.-Y. Takenaka, M.; Takagi, S.; Ichikawa, O.; Osada, T.; Hata, M.; Yamada, H.

    2015-08-28

    We examine the electrical properties of atomic layer deposition (ALD) La{sub 2}O{sub 3}/InGaAs and Al{sub 2}O{sub 3}/La{sub 2}O{sub 3}/InGaAs metal-oxide-semiconductor (MOS) capacitors. It is found that the thick ALD La{sub 2}O{sub 3}/InGaAs interface provides low interface state density (D{sub it}) with the minimum value of ∼3 × 10{sup 11} cm{sup −2} eV{sup −1}, which is attributable to the excellent La{sub 2}O{sub 3} passivation effect for InGaAs surfaces. It is observed, on the other hand, that there are a large amount of slow traps and border traps in La{sub 2}O{sub 3}. In order to simultaneously satisfy low D{sub it} and small hysteresis, the effectiveness of Al{sub 2}O{sub 3}/La{sub 2}O{sub 3}/InGaAs gate stacks with ultrathin La{sub 2}O{sub 3} interfacial layers is in addition evaluated. The reduction of the La{sub 2}O{sub 3} thickness to 0.4 nm in Al{sub 2}O{sub 3}/La{sub 2}O{sub 3}/InGaAs gate stacks leads to the decrease in hysteresis. On the other hand, D{sub it} of the Al{sub 2}O{sub 3}/La{sub 2}O{sub 3}/InGaAs interfaces becomes higher than that of the La{sub 2}O{sub 3}/InGaAs ones, attributable to the diffusion of Al{sub 2}O{sub 3} through La{sub 2}O{sub 3} into InGaAs and resulting modification of the La{sub 2}O{sub 3}/InGaAs interface structure. As a result of the effective passivation effect of La{sub 2}O{sub 3} on InGaAs, however, the Al{sub 2}O{sub 3}/10 cycle (0.4 nm) La{sub 2}O{sub 3}/InGaAs gate stacks can realize still lower D{sub it} with maintaining small hysteresis and low leakage current than the conventional Al{sub 2}O{sub 3}/InGaAs MOS interfaces.

  4. Double-disc gate valve

    DOE Patents [OSTI]

    Wheatley, Seth J.

    1979-01-01

    This invention relates to an improvement in a conventional double-disc gate valve having a vertically movable gate assembly including a wedge, spreaders slidably engaged therewtih, a valve disc carried by the spreaders. When the gate assembly is lowered to a selected point in the valve casing, the valve discs are moved transversely outward to close inlet and outlet ports in the casing. The valve includes hold-down means for guiding the disc-and-spreader assemblies as they are moved transversely outward and inward. If such valves are operated at relatively high differential pressures, they sometimes jam during opening. Such jamming has been a problem for many years in gate valves used in gaseous diffusion plants for the separtion of uranium isotopes. The invention is based on the finding that the above-mentioned jamming results when the outlet disc tilts about its horizontal axis in a certain way during opening of the valve. In accordance with the invention, tilting of the outlet disc is maintained at a tolerable value by providing the disc with a rigid downwardly extending member and by providing the casing with a stop for limiting inward arcuate movement of the member to a preselected value during opening of the valve.

  5. Position sensitivity of graphene field effect transistors to X-rays

    SciTech Connect (OSTI)

    Cazalas, Edward Moore, Michael E.; Jovanovic, Igor; Sarker, Biddut K.; Childres, Isaac; Chen, Yong P.

    2015-06-01

    Device architectures that incorporate graphene to realize detection of electromagnetic radiation typically utilize the direct absorbance of radiation by graphene. This limits their effective area to the size of the graphene and their applicability to lower-energy, less penetrating forms of radiation. In contrast, graphene-based transistor architectures that utilize the field effect as the detection mechanism can be sensitive to interactions of radiation not only with graphene but also with the surrounding substrate. Here, we report the study of the position sensitivity and response of a graphene-based field effect transistor (GFET) to penetrating, well-collimated radiation (micro-beam X-rays), producing ionization in the substrate primarily away from graphene. It is found that responsivity and response speed are strongly dependent on the X-ray beam distance from graphene and the gate voltage applied to the GFET. To develop an understanding of the spatially dependent response, a model is developed that incorporates the volumetric charge generation, transport, and recombination. The model is in good agreement with the observed spatial response characteristics of the GFET and predicts a greater response potential of the GFET to radiation interacting near its surface. The study undertaken provides the necessary insight into the volumetric nature of the GFET response, essential for development of GFET-based detectors for more penetrating forms of ionizing radiation.

  6. GaSb molecular beam epitaxial growth on p-InP(001) and passivation with in situ deposited Al{sub 2}O{sub 3} gate oxide

    SciTech Connect (OSTI)

    Merckling, C.; Brammertz, G.; Hoffmann, T. Y.; Caymax, M.; Dekoster, J.; Sun, X.; Alian, A.; Heyns, M.; Afanas'ev, V. V.

    2011-04-01

    The integration of high carrier mobility materials into future CMOS generations is presently being studied in order to increase drive current capability and to decrease power consumption in future generation CMOS devices. If III-V materials are the candidates of choice for n-type channel devices, antimonide-based semiconductors present high hole mobility and could be used for p-type channel devices. In this work we first demonstrate the heteroepitaxy of fully relaxed GaSb epilayers on InP(001) substrates. In a second part, the properties of the Al{sub 2}O{sub 3}/GaSb interface have been studied by in situ deposition of an Al{sub 2}O{sub 3} high-{kappa} gate dielectric. The interface is abrupt without any substantial interfacial layer, and is characterized by high conduction and valence band offsets. Finally, MOS capacitors show well-behaved C-V with relatively low D{sub it} along the bandgap, these results point out an efficient electrical passivation of the Al{sub 2}O{sub 3}/GaSb interface.

  7. Npn double heterostructure bipolar transistor with ingaasn base region

    DOE Patents [OSTI]

    Chang, Ping-Chih; Baca, Albert G.; Li, Nein-Yi; Hou, Hong Q.; Ashby, Carol I. H.

    2004-07-20

    An NPN double heterostructure bipolar transistor (DHBT) is disclosed with a base region comprising a layer of p-type-doped indium gallium arsenide nitride (InGaAsN) sandwiched between n-type-doped collector and emitter regions. The use of InGaAsN for the base region lowers the transistor turn-on voltage, V.sub.on, thereby reducing power dissipation within the device. The NPN transistor, which has applications for forming low-power electronic circuitry, is formed on a gallium arsenide (GaAs) substrate and can be fabricated at commercial GaAs foundries. Methods for fabricating the NPN transistor are also disclosed.

  8. Exploring graphene field effect transistor devices to improve...

    Office of Scientific and Technical Information (OSTI)

    Exploring graphene field effect transistor devices to improve spectral resolution of semiconductor radiation detectors Citation Details In-Document Search Title: Exploring graphene ...

  9. Separation of interlayer resistance in multilayer MoS{sub 2} field-effect transistors

    SciTech Connect (OSTI)

    Na, Junhong; Jeong Kim, Yun; Kim, Gyu-Tae; Shin, Minju; Joo, Min-Kyu; Huh, Junghwan; Jong Choi, Hyung; Hyung Shim, Joon

    2014-06-09

    We extracted the interlayer resistance between two layers in multilayer molybdenum disulfide (MoS{sub 2}) field-effect transistors by confirming that contact resistances (R{sub contact}) measured using the four-probe measurements were similar, within ∼30%, to source/drain series resistances (R{sub sd}) measured using the two-probe measurements. R{sub contact} values obtained from gated four-probe measurements exhibited gate voltage dependency. In the two-probe measurements, the Y-function method was applied to obtain the R{sub sd} values. By comparing those two R{sub contact} (∼9.5 kΩ) and R{sub sd} (∼12.3 kΩ) values in strong accumulation regime, we found the rationality that those two values had nearly the same properties, i.e., the Schottky barrier resistances and interlayer resistances. The R{sub sd} values of devices with two-probe source/drain electrodes exhibited thickness dependency due to interlayer resistance changes. The interlayer resistance between two layers was also obtained as ∼2.0 Ω mm.

  10. Design, fabrication, and analysis of p-channel arsenide/antimonide hetero-junction tunnel transistors

    SciTech Connect (OSTI)

    Rajamohanan, Bijesh Mohata, Dheeraj; Hollander, Matthew; Datta, Suman; Zhu, Yan; Hudait, Mantu; Jiang, Zhengping; Klimeck, Gerhard

    2014-01-28

    In this paper, we demonstrate InAs/GaSb hetero-junction (hetJ) and GaSb homo-junction (homJ) p-channel tunneling field effect transistors (pTFET) employing a low temperature atomic layer deposited high-κ gate dielectric. HetJ pTFET exhibited drive current of 35 μA/μm in comparison to homJ pTFET, which exhibited drive current of 0.3 μA/μm at V{sub DS} = −0.5 V under DC biasing conditions. Additionally, with pulsing of 1 μs gate voltage, hetJ pTFET exhibited enhanced drive current of 85 μA/μm at V{sub DS} = −0.5 V, which is the highest reported in the category of III-V pTFET. Detailed device characterization was performed through analysis of the capacitance-voltage characteristics, pulsed current-voltage characteristics, and x-ray diffraction studies.

  11. Can p-channel tunnel field-effect transistors perform as good as n-channel?

    SciTech Connect (OSTI)

    Verhulst, A. S. Pourghaderi, M. A.; Collaert, N.; Thean, A. V.-Y.; Verreck, D.; Van de Put, M.; Groeseneken, G.; Sore, B.

    2014-07-28

    We show that bulk semiconductor materials do not allow perfectly complementary p- and n-channel tunnel field-effect transistors (TFETs), due to the presence of a heavy-hole band. When tunneling in p-TFETs is oriented towards the gate-dielectric, field-induced quantum confinement results in a highest-energy subband which is heavy-hole like. In direct-bandgap IIIV materials, the most promising TFET materials, phonon-assisted tunneling to this subband degrades the subthreshold swing and leads to at least 10 smaller on-current than the desired ballistic on-current. This is demonstrated with quantum-mechanical predictions for p-TFETs with tunneling orthogonal to the gate, made out of InP, In{sub 0.53}Ga{sub 0.47}As, InAs, and a modified version of In{sub 0.53}Ga{sub 0.47}As with an artificially increased conduction-band density-of-states. We further show that even if the phonon-assisted current would be negligible, the build-up of a heavy-hole-based inversion layer prevents efficient ballistic tunneling, especially at low supply voltages. For p-TFET, a strongly confined n-i-p or n-p-i-p configuration is therefore recommended, as well as a tensily strained line-tunneling configuration.

  12. Doping suppression and mobility enhancement of graphene transistors fabricated using an adhesion promoting dry transfer process

    SciTech Connect (OSTI)

    Cheol Shin, Woo; Hun Mun, Jeong; Yong Kim, Taek; Choi, Sung-Yool; Jin Cho, Byung E-mail: tskim1@kaist.ac.kr; Yoon, Taeshik; Kim, Taek-Soo E-mail: tskim1@kaist.ac.kr

    2013-12-09

    We present the facile dry transfer of graphene synthesized via chemical vapor deposition on copper film to a functional device substrate. High quality uniform dry transfer of graphene to oxidized silicon substrate was achieved by exploiting the beneficial features of a poly(4-vinylphenol) adhesive layer involving a strong adhesion energy to graphene and negligible influence on the electronic and structural properties of graphene. The graphene field effect transistors (FETs) fabricated using the dry transfer process exhibit excellent electrical performance in terms of high FET mobility and low intrinsic doping level, which proves the feasibility of our approach in graphene-based nanoelectronics.

  13. Gating of the proton-gated ion channel from Gloeobacter violaceus...

    Office of Scientific and Technical Information (OSTI)

    Title: Gating of the proton-gated ion channel from Gloeobacter violaceus at pH 4 as revealed by X-ray crystallography Authors: Gonzalez-Gutierrez, Giovanni ; Cuello, Luis G. ; ...

  14. Low temperature carrier transport study of monolayer MoS{sub 2} field effect transistors prepared by chemical vapor deposition under an atmospheric pressure

    SciTech Connect (OSTI)

    Liu, Xinke E-mail: wujing026@gmail.com; He, Jiazhu; Tang, Dan; Lu, Youming; Zhu, Deliang; Liu, Wenjun; Cao, Peijiang; Han, Sun; Liu, Qiang; Wen, Jiao; Yu, Wenjie; Liu, Wenjun; Wu, Jing E-mail: wujing026@gmail.com; He, Zhubing; Ang, Kah-Wee

    2015-09-28

    Large size monolayer Molybdenum disulphide (MoS{sub 2}) was successfully grown by chemical vapor deposition method under an atmospheric pressure. The electrical transport properties of the fabricated back-gate monolayer MoS{sub 2} field effect transistors (FETs) were investigated under low temperatures; a peak field effect mobility of 59 cm{sup 2}V{sup −1}s{sup −1} was achieved. With the assist of Raman measurement under low temperature, this work identified the mobility limiting factor for the monolayer MoS{sub 2} FETs: homopolar phonon scattering under low temperature and electron-polar optical phonon scattering at room temperature.

  15. David A Gates | Princeton Plasma Physics Lab

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Physicist, Stellerator Physics Lead, Advanced Projects Division, Science Focus Group Leader for Macroscopic Stability David Gates is a principal research physicist for the...

  16. Optimization efforts in gated x-ray intensifiers (Conference...

    Office of Scientific and Technical Information (OSTI)

    Optimization efforts in gated x-ray intensifiers Citation Details In-Document Search Title: Optimization efforts in gated x-ray intensifiers Gated x-ray intensifiers are often ...

  17. Automatically closing swing gate closure assembly

    DOE Patents [OSTI]

    Chang, Shih-Chih; Schuck, William J.; Gilmore, Richard F.

    1988-01-01

    A swing gate closure assembly for nuclear reactor tipoff assembly wherein the swing gate is cammed open by a fuel element or spacer but is reliably closed at a desired closing rate primarily by hydraulic forces in the absence of a fuel charge.

  18. Retaining latch for a water pit gate

    DOE Patents [OSTI]

    Beale, Arden R. (Idaho Falls, ID)

    1997-01-01

    A retaining latch for use in a hazardous materials storage or handling facility to adjustably retain a water pit gate in a gate frame. A retaining latch is provided comprising a latch plate which is rotatably mounted to each end of the top of the gate and a recessed opening, formed in the gate frame, for engaging an edge of the latch plate. The latch plate is circular in profile with one side cut away or flat, such that the latch plate is D-shaped. The remaining circular edge of the latch plate comprises steps of successively reduced thickness. The stepped edge of the latch plate fits inside a recessed opening formed in the gate frame. As the latch plate is rotated, alternate steps of the latch plate are engaged by the recessed opening. When the latch plate is rotated such that the flat portion of the latch plate faces the recessed opening in the gate frame, there is no connection between the opening and the latch plate and the gate is unlatched from the gate frame.

  19. Retaining latch for a water pit gate

    DOE Patents [OSTI]

    Beale, A.R.

    1997-11-18

    A retaining latch is described for use in a hazardous materials storage or handling facility to adjustably retain a water pit gate in a gate frame. A retaining latch is provided comprising a latch plate which is rotatably mounted to each end of the top of the gate and a recessed opening, formed in the gate frame, for engaging an edge of the latch plate. The latch plate is circular in profile with one side cut away or flat, such that the latch plate is D-shaped. The remaining circular edge of the latch plate comprises steps of successively reduced thickness. The stepped edge of the latch plate fits inside a recessed opening formed in the gate frame. As the latch plate is rotated, alternate steps of the latch plate are engaged by the recessed opening. When the latch plate is rotated such that the flat portion of the latch plate faces the recessed opening in the gate frame, there is no connection between the opening and the latch plate and the gate is unlatched from the gate frame. 4 figs.

  20. Method for voltage-gated protein fractionation (Patent) | DOEPatents

    Office of Scientific and Technical Information (OSTI)

    Method for voltage-gated protein fractionation Title: Method for voltage-gated protein fractionation We report unique findings on the voltage dependence of protein exclusion from ...

  1. Unbalanced edge modes and topological phase transition in gated...

    Office of Scientific and Technical Information (OSTI)

    Unbalanced edge modes and topological phase transition in gated trilayer graphene Title: Unbalanced edge modes and topological phase transition in gated trilayer graphene Authors: ...

  2. Development of Dual-Gated Bilayer Graphene Device Structures...

    Office of Scientific and Technical Information (OSTI)

    Development of Dual-Gated Bilayer Graphene Device Structures. Citation Details In-Document Search Title: Development of Dual-Gated Bilayer Graphene Device Structures. Abstract not ...

  3. PENN STATE DOE GRADUATE AUTOMOTIVE TECHNOLOGY EDUCATION (GATE...

    Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

    PENN STATE DOE GRADUATE AUTOMOTIVE TECHNOLOGY EDUCATION (GATE) PROGRAM FOR PENN STATE DOE GRADUATE AUTOMOTIVE TECHNOLOGY EDUCATION (GATE) PROGRAM FOR 2009 DOE Hydrogen Program and ...

  4. Repeat-until-success cubic phase gate for universal continuous...

    Office of Scientific and Technical Information (OSTI)

    phase gate for universal continuous-variable quantum computation Citation Details In-Document Search Title: Repeat-until-success cubic phase gate for universal ...

  5. AgraGate Carbon Credits Corporation | Open Energy Information

    Open Energy Info (EERE)

    AgraGate Carbon Credits Corporation Jump to: navigation, search Name: AgraGate Carbon Credits Corporation Place: Des Moines, Iowa Zip: 50266 Product: Offset aggregators that work...

  6. University of Illinois at Urbana-Champaign's GATE Center for...

    Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

    Champaign's GATE Center for Advanced Automotive Bio-Fuel Combustion Engines University of Illinois at Urbana-Champaign's GATE Center for Advanced Automotive Bio-Fuel Combustion ...

  7. GATE Center of Excellence in Sustainable Vehicle Systems | Department...

    Broader source: Energy.gov (indexed) [DOE]

    More Documents & Publications GATE Center of Excellence in Sustainable Vehicle Systems Vehicle Technologies Office Merit Review 2015: GATE Center of Excellence in Sustainable ...

  8. GATE: Energy Efficient Vehicles for Sustainable Mobility | Department...

    Broader source: Energy.gov (indexed) [DOE]

    GATE: Energy Efficient Vehicles for Sustainable Mobility Vehicle Technologies Office Merit Review 2014: GATE: Energy Efficient Vehicles for Sustainable Mobility Vehicle ...

  9. Gate-tunable exchange coupling between cobalt clusters on graphene...

    Office of Scientific and Technical Information (OSTI)

    DOE PAGES Search Results Publisher's Accepted Manuscript: Gate-tunable exchange coupling between cobalt clusters on graphene Title: Gate-tunable exchange coupling between cobalt ...

  10. Locking apparatus for gate valves

    DOE Patents [OSTI]

    Fabyan, Joseph; Williams, Carl W.

    1988-01-01

    A locking apparatus for fluid operated valves having a piston connected to the valve actuator which moves in response to applied pressure within a cylinder housing having a cylinder head, a catch block is secured to the piston, and the cylinder head incorporates a catch pin. Pressure applied to the cylinder to open the valve moves the piston adjacent to the cylinder head where the catch pin automatically engages the catch block preventing futher movement of the piston or premature closure of the valve. Application of pressure to the cylinder to close the valve, retracts the catch pin, allowing the valve to close. Included are one or more selector valves, for selecting pressure application to other apparatus depending on the gate valve position, open or closed, protecting such apparatus from damage due to premature closing caused by pressure loss or operational error.

  11. Locking apparatus for gate valves

    DOE Patents [OSTI]

    Fabyan, J.; Williams, C.W.

    A locking apparatus for fluid operated valves having a piston connected to the valve actuator which moves in response to applied pressure within a cylinder housing having a cylinder head, a catch block is secured to the piston, and the cylinder head incorporates a catch pin. Pressure applied to the cylinder to open the valve moves the piston adjacent to the cylinder head where the catch pin automatically engages the catch block preventing further movement of the piston or premature closure of the valve. Application of pressure to the cylinder to close the valve, retracts the catch pin, allowing the valve to close. Included are one or more selector valves, for selecting pressure application to other apparatus depending on the gate valve position, open or closed, protecting such apparatus from damage due to premature closing caused by pressure loss or operational error.

  12. Correlation of interface states/border traps and threshold voltage shift on AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors

    SciTech Connect (OSTI)

    Wu, Tian-Li Groeseneken, Guido; Marcon, Denis; De Jaeger, Brice; Lin, H. C.; Franco, Jacopo; Stoffels, Steve; Van Hove, Marleen; Decoutere, Stefaan; Bakeroot, Benoit; Roelofs, Robin

    2015-08-31

    In this paper, three electrical techniques (frequency dependent conductance analysis, AC transconductance (AC-g{sub m}), and positive gate bias stress) were used to evaluate three different gate dielectrics (Plasma-Enhanced Atomic Layer Deposition Si{sub 3}N{sub 4}, Rapid Thermal Chemical Vapor Deposition Si{sub 3}N{sub 4}, and Atomic Layer Deposition (ALD) Al{sub 2}O{sub 3}) for AlGaN/GaN Metal-Insulator-Semiconductor High-Electron-Mobility Transistors. From these measurements, the interface state density (D{sub it}), the amount of border traps, and the threshold voltage (V{sub TH}) shift during a positive gate bias stress can be obtained. The results show that the V{sub TH} shift during a positive gate bias stress is highly correlated to not only interface states but also border traps in the dielectric. A physical model is proposed describing that electrons can be trapped by both interface states and border traps. Therefore, in order to minimize the V{sub TH} shift during a positive gate bias stress, the gate dielectric needs to have a lower interface state density and less border traps. However, the results also show that the commonly used frequency dependent conductance analysis technique to extract D{sub it} needs to be cautiously used since the resulting value might be influenced by the border traps and, vice versa, i.e., the g{sub m} dispersion commonly attributed to border traps might be influenced by interface states.

  13. Influence of surface charge on the transport characteristics of nanowire-field effect transistors in liquid environments

    SciTech Connect (OSTI)

    Nozaki, Daijiro E-mail: research@nano.tu-dresden.de; Kunstmann, Jens; Zörgiebel, Felix; Cuniberti, Gianaurelio

    2015-05-18

    One dimensional nanowire field effect transistors (NW-FETs) are a promising platform for sensor applications. The transport characteristics of NW-FETs are strongly modified in liquid environment due to the charging of surface functional groups accompanied with protonation or deprotonation. In order to investigate the influence of surface charges and ionic concentrations on the transport characteristics of Schottky-barrier NW-FETs, we have combined the modified Poisson-Boltzmann theory with the Landauer-Büttiker transport formalism. For a typical device, the model is able to capture the reduction of the sensitivity of NW-FETs in ionic solutions due to the screening from counter ions as well as a local gating from surface functional groups. Our approach allows to model, to investigate, and to optimize realistic Schottky-barrier NW-FET devices in liquid environment.

  14. Electron tunneling spectroscopy study of electrically active traps in AlGaN/GaN high electron mobility transistors

    SciTech Connect (OSTI)

    Yang, Jie Cui, Sharon; Ma, T. P.; Hung, Ting-Hsiang; Nath, Digbijoy; Krishnamoorthy, Sriram; Rajan, Siddharth

    2013-11-25

    We investigate the energy levels of electron traps in AlGaN/GaN high electron mobility transistors by the use of electron tunneling spectroscopy. Detailed analysis of a typical spectrum, obtained in a wide gate bias range and with both bias polarities, suggests the existence of electron traps both in the bulk of AlGaN and at the AlGaN/GaN interface. The energy levels of the electron traps have been determined to lie within a 0.5?eV band below the conduction band minimum of AlGaN, and there is strong evidence suggesting that these traps contribute to Frenkel-Poole conduction through the AlGaN barrier.

  15. Graphene nanoribbon field-effect transistors on wafer-scale epitaxial graphene on SiC substrates

    SciTech Connect (OSTI)

    Hwang, Wan Sik E-mail: djena@nd.edu; Zhao, Pei; Tahy, Kristof; Xing, Huili; Seabaugh, Alan; Jena, Debdeep E-mail: djena@nd.edu; Nyakiti, Luke O.; Wheeler, Virginia D.; Myers-Ward, Rachael L.; Eddy, Charles R.; Gaskill, D. Kurt; Robinson, Joshua A.; Haensch, Wilfried

    2015-01-01

    We report the realization of top-gated graphene nanoribbon field effect transistors (GNRFETs) of ∼10 nm width on large-area epitaxial graphene exhibiting the opening of a band gap of ∼0.14 eV. Contrary to prior observations of disordered transport and severe edge-roughness effects of graphene nanoribbons (GNRs), the experimental results presented here clearly show that the transport mechanism in carefully fabricated GNRFETs is conventional band-transport at room temperature and inter-band tunneling at low temperature. The entire space of temperature, size, and geometry dependent transport properties and electrostatics of the GNRFETs are explained by a conventional thermionic emission and tunneling current model. Our combined experimental and modeling work proves that carefully fabricated narrow GNRs behave as conventional semiconductors and remain potential candidates for electronic switching devices.

  16. Graduate Automotive Technology Education (GATE) Center

    SciTech Connect (OSTI)

    Jeffrey Hodgson; David Irick

    2005-09-30

    The Graduate Automotive Technology Education (GATE) Center at the University of Tennessee, Knoxville has completed its sixth year of operation. During this period the Center has involved thirteen GATE Fellows and ten GATE Research Assistants in preparing them to contribute to advanced automotive technologies in the center's focus area: hybrid drive trains and control systems. Eighteen GATE students have graduated, and three have completed their course work requirements. Nine faculty members from three departments in the College of Engineering have been involved in the GATE Center. In addition to the impact that the Center has had on the students and faculty involved, the presence of the center has led to the acquisition of resources that probably would not have been obtained if the GATE Center had not existed. Significant industry interaction such as internships, equipment donations, and support for GATE students has been realized. The value of the total resources brought to the university (including related research contracts) exceeds $4,000,000. Problem areas are discussed in the hope that future activities may benefit from the operation of the current program.

  17. Flexible, transparent thin film transistors raise hopes for flexible...

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    of the thin-film transistor, fabricated using single-atom-thick layers of graphene and tungsten diselenide, among other materials. The white scale bar shows 5 microns, which is...

  18. Stable organic field-effect-transistors with high mobilities unaffected by supporting dielectric based on phenylene-bridged thienobenzothiophene

    SciTech Connect (OSTI)

    Mathis, T. Batlogg, B.; Liu, Y.; Ai, L.; Ge, Z.; Lumpi, D. Horkel, E.; Holzer, B.; Froehlich, J.

    2014-01-28

    We report on the electrical properties of organic field-effect transistors (OFET) based on a new class of organic semiconductors. The molecules consist of the same thieno[2,3-b][1]benzothiophene building blocks, connected by different π-bridge spacers (ethylene, phenylene, and fluorophenylene). Molecular orbitals and highest occupied molecular orbital/lowest unoccupied molecular orbital energies were calculated and compared with results from cyclic voltammetric and UV-vis absorption measurements. In order to study the influence of the bridge groups on the molecular arrangement and surface interaction, the transistor performance on a wide range of dielectrics has been investigated in detail. These include as grown SiO{sub 2} and Al{sub 2}O{sub 3} and also treated with octadecyltrichrolosilane and octadecylphosphonic acid, as well as Cytop and Parylene C. An extended study of the multitude of combinations of these materials revealed mobilities up to ∼1 cm{sup 2}/Vs, measured for devices made of the phenylene-bridged compound. Surprisingly, the mobility was quite independent of the supporting gate dielectric. Stability over time has been observed with no degradation after 5 months. By eliminating the hysteresis using Cytop, we were able to show that some of the molecules form films without long-term charge carrier trapping. These are interesting features for practical industrial processing of organic electronics.

  19. Simulation-based design of a strained graphene field effect transistor incorporating the pseudo magnetic field effect

    SciTech Connect (OSTI)

    Souma, Satofumi Ueyama, Masayuki; Ogawa, Matsuto

    2014-05-26

    We present a numerical study on the performance of strained graphene-based field-effect transistors. A local strain less than 10% is applied over a central channel region of the graphene to induce the shift of the Dirac point in the channel region along the transverse momentum direction. The left and the right unstrained graphene regions are doped to be either n-type or p-type. By using the atomistic tight-binding model and a Green's function method, we predict that the gate voltage applied to the central strained graphene region can switch the drain current on and off with an on/off ratio of more than six orders of magnitude at room temperature. This is in spite of the absence of a bandgap in the strained channel region. Steeper subthreshold slopes below 60 mV/decade are also predicted at room temperature because of a mechanism similar to the band-to-band tunneling field-effect transistors.

  20. Reliable, High Performance Transistors on Flexible Substrates - Energy

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Innovation Portal Advanced Materials Advanced Materials Find More Like This Return to Search Reliable, High Performance Transistors on Flexible Substrates Lawrence Berkeley National Laboratory Contact LBL About This Technology Publications: PDF Document Publication Backplanes for Conformal Electronics and Sensors, "Nano Lett., 2011, 11, 5408-5413 (924 KB) Technology Marketing Summary Researchers at Berkeley Lab have produced uniform, high performance transistors on mechanically

  1. Large scale electromechanical transistor with application in mass sensing

    SciTech Connect (OSTI)

    Jin, Leisheng; Li, Lijie

    2014-12-07

    Nanomechanical transistor (NMT) has evolved from the single electron transistor, a device that operates by shuttling electrons with a self-excited central conductor. The unfavoured aspects of the NMT are the complexity of the fabrication process and its signal processing unit, which could potentially be overcome by designing much larger devices. This paper reports a new design of large scale electromechanical transistor (LSEMT), still taking advantage of the principle of shuttling electrons. However, because of the large size, nonlinear electrostatic forces induced by the transistor itself are not sufficient to drive the mechanical member into vibrationan external force has to be used. In this paper, a LSEMT device is modelled, and its new application in mass sensing is postulated using two coupled mechanical cantilevers, with one of them being embedded in the transistor. The sensor is capable of detecting added mass using the eigenstate shifts method by reading the change of electrical current from the transistor, which has much higher sensitivity than conventional eigenfrequency shift approach used in classical cantilever based mass sensors. Numerical simulations are conducted to investigate the performance of the mass sensor.

  2. Substrate dielectric effects on graphene field effect transistors

    SciTech Connect (OSTI)

    Hu, Zhaoying; Prasad Sinha, Dhiraj; Ung Lee, Ji, E-mail: jlee1@albany.edu; Liehr, Michael [College of Nanoscale Science and Engineering, The State University of New York at Albany, Albany, New York 12203 (United States)

    2014-05-21

    Graphene is emerging as a promising material for future electronics and optoelectronics applications due to its unique electronic structure. Understanding the graphene-dielectric interaction is of vital importance for the development of graphene field effect transistors (FETs) and other novel graphene devices. Here, we extend the exploration of substrate dielectrics from conventionally used thermally grown SiO{sub 2} and hexagonal boron nitride films to technologically relevant deposited dielectrics used in semiconductor industry. A systematic analysis of morphology and optical and electrical properties was performed to study the effects of different substrates (SiO{sub 2}, HfO{sub 2}, Al{sub 2}O{sub 3}, tetraethyl orthosilicate (TEOS)-oxide, and Si{sub 3}N{sub 4}) on the carrier transport of chemical vapor deposition-derived graphene FET devices. As baseline, we use graphene FETs fabricated on thermal SiO{sub 2} with a relatively high carrier mobility of 10?000 cm{sup 2}/(V s). Among the deposited dielectrics studied, silicon nitride showed the highest mobility, comparable to the properties of graphene fabricated on thermal SiO{sub 2}. We conclude that this result comes from lower long range scattering and short range scattering rates in the nitride compared those in the other deposited films. The carrier fluctuation caused by substrates, however, seems to be the main contributing factor for mobility degradation, as a universal mobility-disorder density product is observed for all the dielectrics examined. The extrinsic doping trend is further confirmed by Raman spectra. We also provide, for the first time, correlation between the intensity ratio of G peak and 2D peak in the Raman spectra to the carrier mobility of graphene for different substrates.

  3. Digital gate pulse generator for cycloconverter control

    DOE Patents [OSTI]

    Klein, Frederick F.; Mutone, Gioacchino A.

    1989-01-01

    The present invention provides a digital gate pulse generator which controls the output of a cycloconverter used for electrical power conversion applications by determining the timing and delivery of the firing pulses to the switching devices in the cycloconverter. Previous gate pulse generators have been built with largely analog or discrete digital circuitry which require many precision components and periodic adjustment. The gate pulse generator of the present invention utilizes digital techniques and a predetermined series of values to develop the necessary timing signals for firing the switching device. Each timing signal is compared with a reference signal to determine the exact firing time. The present invention is significantly more compact than previous gate pulse generators, responds quickly to changes in the output demand and requires only one precision component and no adjustments.

  4. Gates, Oregon: Energy Resources | Open Energy Information

    Open Energy Info (EERE)

    is a stub. You can help OpenEI by expanding it. Gates is a city in Linn County and Marion County, Oregon. It falls under Oregon's 4th congressional district and Oregon's 5th...

  5. Tuning the metal-insulator crossover and magnetism in SrRuO3 by ionic gating

    DOE Public Access Gateway for Energy & Science Beta (PAGES Beta)

    Yi, Hee Taek; Gao, Bin; Xie, Wei; Cheong, Sang -Wook; Podzorov, Vitaly

    2014-10-13

    Reversible control of charge transport and magnetic properties without degradation is a key for device applications of transition metal oxides. Chemical doping during the growth of transition metal oxides can result in large changes in physical properties, but in most of the cases irreversibility is an inevitable constraint. We report a reversible control of charge transport, metal-insulator crossover and magnetism in field-effect devices based on ionically gated archetypal oxide system - SrRuO3. In these thin-film devices, the metal-insulator crossover temperature and the onset of magnetoresistance can be continuously and reversibly tuned in the range 90–250 K and 70–100 K, respectively,more » by application of a small gate voltage. We infer that a reversible diffusion of oxygen ions in the oxide lattice dominates the response of these materials to the gate electric field. These findings provide critical insights into both the understanding of ionically gated oxides and the development of novel applications.« less

  6. Gate fidelity fluctuations and quantum process invariants

    SciTech Connect (OSTI)

    Magesan, Easwar; Emerson, Joseph [Institute for Quantum Computing and Department of Applied Mathematics, University of Waterloo, Waterloo, Ontario N2L 3G1 (Canada); Blume-Kohout, Robin [Theoretical Division, Los Alamos National Laboratory, Los Alamos, New Mexico 87545 (United States)

    2011-07-15

    We characterize the quantum gate fidelity in a state-independent manner by giving an explicit expression for its variance. The method we provide can be extended to calculate all higher order moments of the gate fidelity. Using these results, we obtain a simple expression for the variance of a single-qubit system and deduce the asymptotic behavior for large-dimensional quantum systems. Applications of these results to quantum chaos and randomized benchmarking are discussed.

  7. GaTe semiconductor for radiation detection

    DOE Patents [OSTI]

    Payne, Stephen A.; Burger, Arnold; Mandal, Krishna C.

    2009-06-23

    GaTe semiconductor is used as a room-temperature radiation detector. GaTe has useful properties for radiation detectors: ideal bandgap, favorable mobilities, low melting point (no evaporation), non-hygroscopic nature, and availability of high-purity starting materials. The detector can be used, e.g., for detection of illicit nuclear weapons and radiological dispersed devices at ports of entry, in cities, and off shore and for determination of medical isotopes present in a patient.

  8. Range gated strip proximity sensor

    DOE Patents [OSTI]

    McEwan, T.E.

    1996-12-03

    A range gated strip proximity sensor uses one set of sensor electronics and a distributed antenna or strip which extends along the perimeter to be sensed. A micro-power RF transmitter is coupled to the first end of the strip and transmits a sequence of RF pulses on the strip to produce a sensor field along the strip. A receiver is coupled to the second end of the strip, and generates a field reference signal in response to the sequence of pulse on the line combined with received electromagnetic energy from reflections in the field. The sensor signals comprise pulses of radio frequency signals having a duration of less than 10 nanoseconds, and a pulse repetition rate on the order of 1 to 10 MegaHertz or less. The duration of the radio frequency pulses is adjusted to control the range of the sensor. An RF detector feeds a filter capacitor in response to received pulses on the strip line to produce a field reference signal representing the average amplitude of the received pulses. When a received pulse is mixed with a received echo, the mixing causes a fluctuation in the amplitude of the field reference signal, providing a range-limited Doppler type signature of a field disturbance. 6 figs.

  9. Range gated strip proximity sensor

    DOE Patents [OSTI]

    McEwan, Thomas E.

    1996-01-01

    A range gated strip proximity sensor uses one set of sensor electronics and a distributed antenna or strip which extends along the perimeter to be sensed. A micro-power RF transmitter is coupled to the first end of the strip and transmits a sequence of RF pulses on the strip to produce a sensor field along the strip. A receiver is coupled to the second end of the strip, and generates a field reference signal in response to the sequence of pulse on the line combined with received electromagnetic energy from reflections in the field. The sensor signals comprise pulses of radio frequency signals having a duration of less than 10 nanoseconds, and a pulse repetition rate on the order of 1 to 10 MegaHertz or less. The duration of the radio frequency pulses is adjusted to control the range of the sensor. An RF detector feeds a filter capacitor in response to received pulses on the strip line to produce a field reference signal representing the average amplitude of the received pulses. When a received pulse is mixed with a received echo, the mixing causes a fluctuation in the amplitude of the field reference signal, providing a range-limited Doppler type signature of a field disturbance.

  10. Trapping in GaN-based metal-insulator-semiconductor transistors: Role of high drain bias and hot electrons

    SciTech Connect (OSTI)

    Meneghini, M. Bisi, D.; Meneghesso, G.; Zanoni, E.

    2014-04-07

    This paper describes an extensive analysis of the role of off-state and semi-on state bias in inducing the trapping in GaN-based power High Electron Mobility Transistors. The study is based on combined pulsed characterization and on-resistance transient measurements. We demonstrate thatby changing the quiescent bias point from the off-state to the semi-on stateit is possible to separately analyze two relevant trapping mechanisms: (i) the trapping of electrons in the gate-drain access region, activated by the exposure to high drain bias in the off-state; (ii) the trapping of hot-electrons within the AlGaN barrier or the gate insulator, which occurs when the devices are operated in the semi-on state. The dependence of these two mechanisms on the bias conditions and on temperature, and the properties (activation energy and cross section) of the related traps are described in the text.

  11. Extremely scaled high-k/In?.??Ga?.??As gate stacks with low leakage and low interface trap densities

    SciTech Connect (OSTI)

    Chobpattana, Varistha; Mikheev, Evgeny; Zhang, Jack Y.; Mates, Thomas E.; Stemmer, Susanne

    2014-09-28

    Highly scaled gate dielectric stacks with low leakage and low interface trap densities are required for complementary metal-oxide-semiconductor technology with III-V semiconductor channels. Here, we show that a novel pre-deposition technique, consisting of alternating cycles of nitrogen plasma and tetrakis(dimethylamino)titanium, allows for HfO? and ZrO? gate stacks with extremely high accumulation capacitance densities of more than 5 ?F/cm? at 1 MHz, low leakage current, low frequency dispersion, and low midgap interface trap densities (10cm?eV?range). Using x-ray photoelectron spectroscopy, we show that the interface contains TiO? and small quantities of In?O?, but no detectable Ga- or As-oxides, or As-As bonding. The results allow for insights into the microscopic mechanisms that control leakage and frequency dispersion in high-k/III-V gate stacks.

  12. Low temperature atomic layer deposited ZnO photo thin film transistors

    SciTech Connect (OSTI)

    Oruc, Feyza B.; Aygun, Levent E.; Donmez, Inci; Biyikli, Necmi; Okyay, Ali K.; Yu, Hyun Yong

    2015-01-01

    ZnO thin film transistors (TFTs) are fabricated on Si substrates using atomic layer deposition technique. The growth temperature of ZnO channel layers are selected as 80, 100, 120, 130, and 250?C. Material characteristics of ZnO films are examined using x-ray photoelectron spectroscopy and x-ray diffraction methods. Stoichiometry analyses showed that the amount of both oxygen vacancies and interstitial zinc decrease with decreasing growth temperature. Electrical characteristics improve with decreasing growth temperature. Best results are obtained with ZnO channels deposited at 80?C; I{sub on}/I{sub off} ratio is extracted as 7.8 10{sup 9} and subthreshold slope is extracted as 0.116 V/dec. Flexible ZnO TFT devices are also fabricated using films grown at 80?C. I{sub D}V{sub GS} characterization results showed that devices fabricated on different substrates (Si and polyethylene terephthalate) show similar electrical characteristics. Sub-bandgap photo sensing properties of ZnO based TFTs are investigated; it is shown that visible light absorption of ZnO based TFTs can be actively controlled by external gate bias.

  13. Field-effect transistor having a superlattice channel and high carrier velocities at high applied fields

    DOE Patents [OSTI]

    Chaffin, deceased, Roger J.; Dawson, Ralph; Fritz, Ian J.; Osbourn, Gordon C.; Zipperian, Thomas E.

    1989-01-01

    A field effect transistor comprises a semiconductor having a source, a drain, a channel and a gate in operational relationship. The semiconductor is a strained layer superlattice comprising alternating quantum well and barrier layers, the quantum well layers and barrier layers being selected from the group of layer pairs consisting of InGaAs/AlGaAs, InAs/InAlGaAs, and InAs/InAlAsP. The layer thicknesses of the quantum well and barrier layers are sufficiently thin that the alternating layers constitute a superlattice which has a superlattice conduction band energy level structure in k-vector space which includes a lowest energy .GAMMA.-valley and a next lowest energy L-valley, each k-vector corresponding to one of the orthogonal directions defined by the planes of said layers and the directions perpendicular thereto. The layer thicknesses of the quantum well layers are selected to provide a superlattice L.sub.2D -valley which has a shape which is substantially more two-dimensional than that of said bulk L-valley.

  14. Field-effect transistor having a superlattice channel and high carrier velocities at high applied fields

    DOE Patents [OSTI]

    Chaffin, R.J.; Dawson, L.R.; Fritz, I.J.; Osbourn, G.C.; Zipperian, T.E.

    1984-04-19

    In a field-effect transistor comprising a semiconductor having therein a source, a drain, a channel and a gate in operational relationship, there is provided an improvement wherein said semiconductor is a superlattice comprising alternating quantum well and barrier layers, the quantum well layers comprising a first direct gap semiconductor material which in bulk form has a certain bandgap and a curve of electron velocity versus applied electric field which has a maximum electron velocity at a certain electric field, the barrier layers comprising a second semiconductor material having a bandgap wider than that of said first semiconductor material, wherein the layer thicknesses of said quantum well and barrier layers are sufficiently thin that the alternating layers constitute a superlattice having a curve of electron velocity versus applied electric field which has a maximum electron velocity at a certain electric field, and wherein the thicknesses of said quantum well layers are selected to provide a superlattice curve of electron velocity versus applied electric field whereby, at applied electric fields higher than that at which the maximum electron velocity occurs in said first material when in bulk form, the electron velocities are higher in said superlattice than they are in said first semiconductor material in bulk form.

  15. Designing a Micro-Mechanical Transistor

    SciTech Connect (OSTI)

    Mainieri, R.

    1999-06-03

    This is the final report of a three-year, Laboratory-Directed Research and Development (LDRD) project at the Los Alamos National Laboratory (LANL). Micro-mechanical electronic systems are chips with moving parts. They are fabricated with the same techniques that are used to manufacture electronic chips, sharing their low cost. Micro-mechanical chips can also contain electronic components. By combining mechanical parts with electronic parts it becomes possible to process signal mechanically. To achieve designs comparable to those obtained with electronic components it is necessary to have a mechanical device that can change its behavior in response to a small input - a mechanical transistor. The work proposed will develop the design tools for these complex-shaped resonant structures using the geometrical ray technique. To overcome the limitations of geometrical ray chaos, the dynamics of the rays will be studied using the methods developed for the study of nonlinear dynamical systems. T his leads to numerical methods that execute well in parallel computer architectures, using a limited amount of memory and no inter-process communication.

  16. Sliding-gate valve for use with abrasive materials

    DOE Patents [OSTI]

    Ayers, Jr., William J.; Carter, Charles R.; Griffith, Richard A.; Loomis, Richard B.; Notestein, John E.

    1985-01-01

    The invention is a flow and pressure-sealing valve for use with abrasive solids. The valve embodies special features which provide for long, reliable operating lifetimes in solids-handling service. The valve includes upper and lower transversely slidable gates, contained in separate chambers. The upper gate provides a solids-flow control function, whereas the lower gate provides a pressure-sealing function. The lower gate is supported by means for (a) lifting that gate into sealing engagement with its seat when the gate is in its open and closed positions and (b) lowering the gate out of contact with its seat to permit abrasion-free transit of the gate between its open and closed positions. When closed, the upper gate isolates the lower gate from the solids. Because of this shielding action, the sealing surface of the lower gate is not exposed to solids during transit or when it is being lifted or lowered. The chamber containing the lower gate normally is pressurized slightly, and a sweep gas is directed inwardly across the lower-gate sealing surface during the vertical translation of the gate.

  17. Gate-modulated weak anti-localization and carrier trapping in individual Bi{sub 2}Se{sub 3} nanoribbons

    SciTech Connect (OSTI)

    Wang, Li-Xian; Yan, Yuan; Liao, Zhi-Min Yu, Da-Peng

    2015-02-09

    We report a gate-voltage modulation on the weak anti-localization of individual topological insulator Bi{sub 2}Se{sub 3} nanoribbons. The phase coherence length decreases with decreasing the carrier density of the surface states on the bottom surface of the Bi{sub 2}Se{sub 3} nanoribbon as tuning the gate voltage from 0 to −100 V, indicating that the electron-electron interaction dominates the decoherence at low carrier density. Furthermore, we observe an abnormal conductance decline at positive gate voltage regime, which is ascribed to the capture of surface carriers by the trapping centers in the surface oxidation layer.

  18. Hydrogen passivation of electron trap in amorphous In-Ga-Zn-O thin-film transistors

    SciTech Connect (OSTI)

    Hanyu, Yuichiro Domen, Kay; Nomura, Kenji; Hiramatsu, Hidenori; Kamiya, Toshio; Materials Research Center for Element Strategy, Tokyo Institute of Technology, Yokohama ; Kumomi, Hideya; Hosono, Hideo; Frontier Research Center, Tokyo Institute of Technology, Yokohama; Materials Research Center for Element Strategy, Tokyo Institute of Technology, Yokohama

    2013-11-11

    We report an experimental evidence that some hydrogens passivate electron traps in an amorphous oxide semiconductor, a-In-Ga-Zn-O (a-IGZO). The a-IGZO thin-film transistors (TFTs) annealed at 300?C exhibit good operation characteristics; while those annealed at ?400?C show deteriorated ones. Thermal desorption spectra (TDS) of H{sub 2}O indicate that this threshold annealing temperature corresponds to depletion of H{sub 2}O desorption from the a-IGZO layer. Hydrogen re-doping by wet oxygen annealing recovers the good TFT characteristic. The hydrogens responsible for this passivation have specific binding energies corresponding to the desorption temperatures of 300430?C. A plausible structural model is suggested.

  19. Berkeley Lab Scientists Grow Atomically Thin Transistors and Circuits |

    Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

    Department of Energy Berkeley Lab Scientists Grow Atomically Thin Transistors and Circuits Berkeley Lab Scientists Grow Atomically Thin Transistors and Circuits July 12, 2016 - 10:29am Addthis This schematic shows the chemical assembly of two-dimensional crystals. Graphene is first etched into channels and the TMDC molybdenum disulfide (MoS2) begins to nucleate around the edges and within the channel. On the edges, MoS2 slightly overlaps on top of the graphene. Finally, further growth

  20. Gated IR Images of Shocked Surfaces

    SciTech Connect (OSTI)

    S. S. Lutz; W. D. Turley; P. M. Rightley; L. E. Primas

    2001-06-01

    Gated infrared (IR) images have been taken of a series of shocked surface geometries in tin. Metal coupons machined with steps and flats were mounted directly to the high explosive. The explosive was point-initiated and 500-ns to 1-microsecond-wide gated images of the target were taken immediately following shock breakout using a Santa Barbara Focalplane InSb camera (SBF-134). Spatial distributions of surface radiance were extracted from the images of the shocked samples and found to be non-single-valued. Several geometries were modeled using CTH, a two-dimensional Eulerian hydrocode.

  1. Reduction of leakage current in In{sub 0.53}Ga{sub 0.47}As channel metal-oxide-semiconductor field-effect-transistors using AlAs{sub 0.56}Sb{sub 0.44} confinement layers

    SciTech Connect (OSTI)

    Huang, Cheng-Ying Lee, Sanghoon; Cohen-Elias, Doron; Law, Jeremy J. M.; Carter, Andrew D.; Rodwell, Mark J. W.; Chobpattana, Varistha; Stemmer, Susanne; Gossard, Arthur C.; Materials Department, University of California, Santa Barbara, California 93106

    2013-11-11

    We compare the DC characteristics of planar In{sub 0.53}Ga{sub 0.47}As channel MOSFETs using AlAs{sub 0.56}Sb{sub 0.44} barriers to similar MOSFETs using In{sub 0.52}Al{sub 0.48}As barriers. AlAs{sub 0.56}Sb{sub 0.44}, with ?1.0?eV conduction-band offset to In{sub 0.53}Ga{sub 0.47}As, improves electron confinement within the channel. At gate lengths below 100?nm and V{sub DS}?=?0.5?V, the MOSFETs with AlAs{sub 0.56}Sb{sub 0.44} barriers show steeper subthreshold swing (SS) and reduced drain-source leakage current. We attribute the greater leakage observed with the In{sub 0.52}Al{sub 0.48}As barrier to thermionic emission from the N?+?In{sub 0.53}Ga{sub 0.47}As source over the In{sub 0.53}Ga{sub 0.47}As/In{sub 0.52}Al{sub 0.48}As heterointerface. A 56?nm gate length device with the AlAs{sub 0.56}Sb{sub 0.44} barrier exhibits 1.96 mS/?m peak transconductance and SS?=?134?mV/dec at V{sub DS}?=?0.5?V.

  2. Chi-Nu "Gate Review" (Conference) | SciTech Connect

    Office of Scientific and Technical Information (OSTI)

    Chi-Nu "Gate Review" Citation Details In-Document Search Title: Chi-Nu "Gate Review" You are accessing a document from the Department of Energy's (DOE) SciTech Connect. This...

  3. Photo-modulated thin film transistor based on dynamic charge transfer within quantum-dots-InGaZnO interface

    SciTech Connect (OSTI)

    Liu, Xiang; Yang, Xiaoxia; Liu, Mingju; Tao, Zhi; Wei, Lei Li, Chi Zhang, Xiaobing; Wang, Baoping; Dai, Qing; Nathan, Arokia

    2014-03-17

    The temporal development of next-generation photo-induced transistor across semiconductor quantum dots and Zn-related oxide thin film is reported in this paper. Through the dynamic charge transfer in the interface between these two key components, the responsibility of photocurrent can be amplified for scales of times (?10{sup 4}?A/W 450?nm) by the electron injection from excited quantum dots to InGaZnO thin film. And this photo-transistor has a broader waveband (from ultraviolet to visible light) optical sensitivity compared with other Zn-related oxide photoelectric device. Moreover, persistent photoconductivity effect can be diminished in visible waveband which lead to a significant improvement in the device's relaxation time from visible illuminated to dark state due to the ultrafast quenching of quantum dots. With other inherent properties such as integrated circuit compatible, low off-state current and high external quantum efficiency resolution, it has a great potential in the photoelectric device application, such as photodetector, phototransistor, and sensor array.

  4. Sulfuric acid and hydrogen peroxide surface passivation effects on AlGaN/GaN high electron mobility transistors

    SciTech Connect (OSTI)

    Zaidi, Z. H. Lee, K. B.; Qian, H.; Jiang, S.; Houston, P. A.; Guiney, I.; Wallis, D. J.; Humphreys, C. J.

    2014-12-28

    In this work, we have compared SiN{sub x} passivation, hydrogen peroxide, and sulfuric acid treatment on AlGaN/GaN HEMTs surface after full device fabrication on Si substrate. Both the chemical treatments resulted in the suppression of device pinch-off gate leakage current below 1??A/mm, which is much lower than that for SiN{sub x} passivation. The greatest suppression over the range of devices is observed with the sulfuric acid treatment. The device on/off current ratio is improved (from 10{sup 4}10{sup 5} to 10{sup 7}) and a reduction in the device sub-threshold (S.S.) slope (from ?215 to 90?mV/decade) is achieved. The sulfuric acid is believed to work by oxidizing the surface which has a strong passivating effect on the gate leakage current. The interface trap charge density (D{sub it}) is reduced (from 4.86 to 0.90??10{sup 12?}cm{sup ?2} eV{sup ?1}), calculated from the change in the device S.S. The gate surface leakage current mechanism is explained by combined Mott hopping conduction and Poole Frenkel models for both untreated and sulfuric acid treated devices. Combining the sulfuric acid treatment underneath the gate with the SiN{sub x} passivation after full device fabrication results in the reduction of D{sub it} and improves the surface related current collapse.

  5. Designing robust unitary gates: Application to concatenated composite pulses

    SciTech Connect (OSTI)

    Ichikawa, Tsubasa; Bando, Masamitsu; Kondo, Yasushi; Nakahara, Mikio

    2011-12-15

    We propose a simple formalism to design unitary gates robust against given systematic errors. This formalism generalizes our previous observation [Y. Kondo and M. Bando, J. Phys. Soc. Jpn. 80, 054002 (2011)] that vanishing dynamical phase in some composite gates is essential to suppress pulse-length errors. By employing our formalism, we derive a composite unitary gate which can be seen as a concatenation of two known composite unitary operations. The obtained unitary gate has high fidelity over a wider range of error strengths compared to existing composite gates.

  6. Facile fabrication of high-performance InGaZnO thin film transistor using hydrogen ion irradiation at room temperature

    SciTech Connect (OSTI)

    Ahn, Byung Du [School of Electrical and Electronic Engineering, 50, Yonsei University, Seoul 120-749 (Korea, Republic of); Park, Jin-Seong [Division of Materials Science and Engineering, Hanyang University, Seoul 133-791 (Korea, Republic of); Chung, K. B., E-mail: kbchung@dongguk.edu [Division of Physics and Semiconductor Science, Dongguk University, Seoul 100-715 (Korea, Republic of)

    2014-10-20

    Device performance of InGaZnO (IGZO) thin film transistors (TFTs) are investigated as a function of hydrogen ion irradiation dose at room temperature. Field effect mobility is enhanced, and subthreshold gate swing is improved with the increase of hydrogen ion irradiation dose, and there is no thermal annealing. The electrical device performance is correlated with the electronic structure of IGZO films, such as chemical bonding states, features of the conduction band, and band edge states below the conduction band. The decrease of oxygen deficient bonding and the changes in electronic structure of the conduction band leads to the improvement of device performance in IGZO TFT with an increase of the hydrogen ion irradiation dose.

  7. Recovery in dc and rf performance of off-state step-stressed AlGaN/GaN high electron mobility transistors with thermal annealing

    SciTech Connect (OSTI)

    Kim, Byung-Jae; Hwang, Ya-Hsi; Ahn, Shihyun; Zhu, Weidi; Dong, Chen; Lu, Liu; Ren, Fan; Holzworth, M. R.; Jones, Kevin S.; Pearton, Stephen J.; Smith, David J.; Kim, Jihyun; Zhang, Ming-Lan

    2015-04-13

    The recovery effects of thermal annealing on dc and rf performance of off-state step-stressed AlGaN/GaN high electron mobility transistors were investigated. After stress, reverse gate leakage current and sub-threshold swing increased and drain current on-off ratio decreased. However, these degradations were completely recovered after thermal annealing at 450?C for 10 mins for devices stressed either once or twice. The trap densities, which were estimated by temperature-dependent drain-current sub-threshold swing measurements, increased after off-state step-stress and were reduced after subsequent thermal annealing. In addition, the small signal rf characteristics of stressed devices were completely recovered after thermal annealing.

  8. Electron density and currents of AlN/GaN high electron mobility transistors with thin GaN/AlN buffer layer

    SciTech Connect (OSTI)

    Bairamis, A.; Zervos, Ch.; Georgakilas, A.; Adikimenakis, A.; Kostopoulos, A.; Kayambaki, M.; Tsagaraki, K.; Konstantinidis, G.

    2014-09-15

    AlN/GaN high electron mobility transistor (HEMT) structures with thin GaN/AlN buffer layer have been analyzed theoretically and experimentally, and the effects of the AlN barrier and GaN buffer layer thicknesses on two-dimensional electron gas (2DEG) density and transport properties have been evaluated. HEMT structures consisting of [300?nm GaN/ 200?nm AlN] buffer layer on sapphire were grown by plasma-assisted molecular beam epitaxy and exhibited a remarkable agreement with the theoretical calculations, suggesting a negligible influence of the crystalline defects that increase near the heteroepitaxial interface. The 2DEG density varied from 6.8??10{sup 12} to 2.1 10{sup 13} cm{sup ?2} as the AlN barrier thickness increased from 2.2 to 4.5?nm, while a 4.5?nm AlN barrier would result to 3.1??10{sup 13} cm{sup ?2} on a GaN buffer layer. The 3.0?nm AlN barrier structure exhibited the highest 2DEG mobility of 900?cm{sup 2}/Vs for a density of 1.3??10{sup 13} cm{sup ?2}. The results were also confirmed by the performance of 1??m gate-length transistors. The scaling of AlN barrier thickness from 1.5?nm to 4.5?nm could modify the drain-source saturation current, for zero gate-source voltage, from zero (normally off condition) to 0.63?A/mm. The maximum drain-source current was 1.1?A/mm for AlN barrier thickness of 3.0?nm and 3.7?nm, and the maximum extrinsic transconductance was 320 mS/mm for 3.0?nm AlN barrier.

  9. Schottky barrier contrasts in single and bi-layer graphene contacts for MoS{sub 2} field-effect transistors

    SciTech Connect (OSTI)

    Du, Hyewon; Kim, Taekwang; Shin, Somyeong; Kim, Dahye; Seo, Sunae; Kim, Hakseong; Lee, Sang Wook; Sung, Ji Ho; Jo, Moon-Ho; Lee, Myoung Jae; Seo, David H.

    2015-12-07

    We have investigated single- and bi-layer graphene as source-drain electrodes for n-type MoS{sub 2} transistors. Ti-MoS{sub 2}-graphene heterojunction transistors using both single-layer MoS{sub 2} (1M) and 4-layer MoS{sub 2} (4M) were fabricated in order to compare graphene electrodes with commonly used Ti electrodes. MoS{sub 2}-graphene Schottky barrier provided electron injection efficiency up to 130 times higher in the subthreshold regime when compared with MoS{sub 2}-Ti, which resulted in V{sub DS} polarity dependence of device parameters such as threshold voltage (V{sub TH}) and subthreshold swing (SS). Comparing single-layer graphene (SG) with bi-layer graphene (BG) in 4M devices, SG electrodes exhibited enhanced device performance with higher on/off ratio and increased field-effect mobility (μ{sub FE}) due to more sensitive Fermi level shift by gate voltage. Meanwhile, in the strongly accumulated regime, we observed opposing behavior depending on MoS{sub 2} thickness for both SG and BG contacts. Differential conductance (σ{sub d}) of 1M increases with V{sub DS} irrespective of V{sub DS} polarity, while σ{sub d} of 4M ceases monotonic growth at positive V{sub DS} values transitioning to ohmic-like contact formation. Nevertheless, the low absolute value of σ{sub d} saturation of the 4M-graphene junction demonstrates that graphene electrode could be unfavorable for high current carrying transistors.

  10. Group-III nitride based high electron mobility transistor (HEMT) with barrier/spacer layer

    DOE Patents [OSTI]

    Chavarkar, Prashant; Smorchkova, Ioulia P.; Keller, Stacia; Mishra, Umesh; Walukiewicz, Wladyslaw; Wu, Yifeng

    2005-02-01

    A Group III nitride based high electron mobility transistors (HEMT) is disclosed that provides improved high frequency performance. One embodiment of the HEMT comprises a GaN buffer layer, with an Al.sub.y Ga.sub.1-y N (y=1 or y 1) layer on the GaN buffer layer. An Al.sub.x Ga.sub.1-x N (0.ltoreq.x.ltoreq.0.5) barrier layer on to the Al.sub.y Ga.sub.1-y N layer, opposite the GaN buffer layer, Al.sub.y Ga.sub.1-y N layer having a higher Al concentration than that of the Al.sub.x Ga.sub.1-x N barrier layer. A preferred Al.sub.y Ga.sub.1-y N layer has y=1 or y.about.1 and a preferred Al.sub.x Ga.sub.1-x N barrier layer has 0.ltoreq.x.ltoreq.0.5. A 2DEG forms at the interface between the GaN buffer layer and the Al.sub.y Ga.sub.1-y N layer. Respective source, drain and gate contacts are formed on the Al.sub.x Ga.sub.1-x N barrier layer. The HEMT can also comprising a substrate adjacent to the buffer layer, opposite the Al.sub.y Ga.sub.1-y N layer and a nucleation layer between the Al.sub.x Ga.sub.1-x N buffer layer and the substrate.