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1

Looking at Transistor Gate Oxide Formation in Real Time  

Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

Gate Oxide Formation in Real Time Looking at Transistor Gate Oxide Formation in Real Time Print Wednesday, 25 June 2008 00:00 The oxide gate layer is critical to every transistor,...

2

Looking at Transistor Gate Oxide Formation in Real Time  

Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

Looking at Transistor Gate Oxide Formation in Real Time Print The oxide gate layer is critical to every transistor, and present-day layer thicknesses are in the 10-20 range (1-2...

3

Looking at Transistor Gate Oxide Formation in Real Time  

Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

AFDC Printable Version Share this resource Send a link to EERE: Alternative Fuels Data Center Home Page to someone by E-mail Share EERE: Alternative Fuels Data Center Home Page on Facebook Tweet about EERE: Alternative Fuels Data Center Home Page on Twitter Bookmark EERE:1 First Use of Energy for All Purposes (Fuel and Nonfuel),Feet) Year Jan Feb Mar Apr MayAtmospheric Optical Depth7-1D: VegetationEquipment Surfaces and Interfaces Sample6,Local CorrelationsConditions.Looking at Transistor

4

Advanced insulated gate bipolar transistor gate drive  

DOE Patents [OSTI]

A gate drive for an insulated gate bipolar transistor (IGBT) includes a control and protection module coupled to a collector terminal of the IGBT, an optical communications module coupled to the control and protection module, a power supply module coupled to the control and protection module and an output power stage module with inputs coupled to the power supply module and the control and protection module, and outputs coupled to a gate terminal and an emitter terminal of the IGBT. The optical communications module is configured to send control signals to the control and protection module. The power supply module is configured to distribute inputted power to the control and protection module. The control and protection module outputs on/off, soft turn-off and/or soft turn-on signals to the output power stage module, which, in turn, supplies a current based on the signal(s) from the control and protection module for charging or discharging an input capacitance of the IGBT.

Short, James Evans (Monongahela, PA); West, Shawn Michael (West Mifflin, PA); Fabean, Robert J. (Donora, PA)

2009-08-04T23:59:59.000Z

5

Electroluminescence in ion gel gated organic polymer semiconductor transistors  

E-Print Network [OSTI]

This thesis reports the light emission in ion gel gated, thin film organic semiconductor transistors and investigates the light emission mechanism behind these devices. We report that ion gel gated organic polymer semiconductor transistors emit...

Bhat, Shrivalli

2011-07-12T23:59:59.000Z

6

Electron-beam patterning of polymer electrolyte films to make multiple nanoscale gates for nanowire transistors  

E-Print Network [OSTI]

We report an electron-beam based method for the nanoscale patterning of the poly(ethylene oxide)/LiClO$_{4}$ polymer electrolyte. We use the patterned polymer electrolyte as a high capacitance gate dielectric in single nanowire transistors and obtain subthreshold swings comparable to conventional metal/oxide wrap-gated nanowire transistors. Patterning eliminates gate/contact overlap which reduces parasitic effects and enables multiple, independently controllable gates. The method's simplicity broadens the scope for using polymer electrolyte gating in studies of nanowires and other nanoscale devices.

D. J. Carrad; A. M. Burke; R. W. Lyttleton; H. J. Joyce; H. H. Tan; C. Jagadish; K. Storm; H. Linke; L. Samuelson; A. P. Micolich

2014-04-08T23:59:59.000Z

7

A SIMULATION MODEL FOR FLOATING-GATE MOS SYNAPSE TRANSISTORS  

E-Print Network [OSTI]

A SIMULATION MODEL FOR FLOATING-GATE MOS SYNAPSE TRANSISTORS Kambiz Rahimi, Chris Diorio, Cecilia, Seattle, Washington ABSTRACT We propose an empirical simulation model for p-channel floating-gate MOS and accurate simulation model for the synaptic devices, many of these circuits were designed using equation

Diorio, Chris

8

Design, Simulation and Modeling of Insulated Gate Bipolar Transistor  

E-Print Network [OSTI]

The market for Insulated Gate Bipolar Transistor (IGBT) is growing and there is a need for techniques to improve the design, modeling and simulation of IGBT. In this thesis, we first developed a new method to optimize the layout and dimensions...

Gupta, Kaustubh

2013-07-09T23:59:59.000Z

9

Electrically-gated near-field radiative thermal transistor  

E-Print Network [OSTI]

In this work, we propose a near-field radiative thermal transistor made of two graphene-covered silicon carbide (SiC) plates separated by a nanometer vacuum gap. Thick SiC plates serve as the thermal "source" and "drain", while graphene sheets function as the "gate" to modulate the near-field photon tunneling by tuning chemical potential with applied voltage biases symmetrically or asymmetrically. The radiative heat flux calculated from fluctuational electrodynamics significantly varies with graphene chemical potentials, which can tune the coupling between graphene plasmon across the vacuum gap. Thermal modulation, switching, and amplification, which are the key features required for a thermal transistor, are theoretically realized and analyzed. This work will pave the way to active thermal management, thermal circuits, and thermal computing.

Yang, Yue

2015-01-01T23:59:59.000Z

10

New Silicon Carbide Schottky-gate Bipolar Mode Field Effect Transistor (SiC SBMFET)  

E-Print Network [OSTI]

New Silicon Carbide Schottky-gate Bipolar Mode Field Effect Transistor (SiC SBMFET) without PN. In this paper, we propose a novel Schottky-gate BMFET (SBMFET) using P- type 4H Silicon-Carbide 13,41, a wide, Silicon Carbide, Field effect transistor, Simulation. I. INTRODUCTION TH E BMFET operates in bipolar mode

Kumar, M. Jagadesh

11

Touch sensors based on planar liquid crystal-gated-organic field-effect transistors  

SciTech Connect (OSTI)

We report a tactile touch sensor based on a planar liquid crystal-gated-organic field-effect transistor (LC-g-OFET) structure. The LC-g-OFET touch sensors were fabricated by forming the 10 ?m thick LC layer (4-cyano-4{sup ?}-pentylbiphenyl - 5CB) on top of the 50 nm thick channel layer (poly(3-hexylthiophene) - P3HT) that is coated on the in-plane aligned drain/source/gate electrodes (indium-tin oxide - ITO). As an external physical stimulation to examine the tactile touch performance, a weak nitrogen flow (83.3 ?l/s) was employed to stimulate the LC layer of the touch device. The LC-g-OFET device exhibited p-type transistor characteristics with a hole mobility of 1.5 cm{sup 2}/Vs, but no sensing current by the nitrogen flow touch was measured at sufficiently high drain (V{sub D}) and gate (V{sub G}) voltages. However, a clear sensing current signal was detected at lower voltages, which was quite sensitive to the combination of V{sub D} and V{sub G}. The best voltage combination was V{sub D} = ?0.2 V and V{sub G} = ?1 V for the highest ratio of signal currents to base currents (i.e., signal-to-noise ratio). The change in the LC alignment upon the nitrogen flow touch was assigned as the mechanism for the present LC-g-OFET touch sensors.

Seo, Jooyeok; Lee, Chulyeon; Han, Hyemi; Lee, Sooyong; Nam, Sungho; Kim, Youngkyoo, E-mail: ykimm@knu.ac.kr [Organic Nanoelectronics Laboratory, Department of Chemical Engineering and Graduate School of Applied Chemical Engineering, Kyungpook National University, Daegu, 702-701 (Korea, Republic of); Kim, Hwajeong [Organic Nanoelectronics Laboratory, Department of Chemical Engineering and Graduate School of Applied Chemical Engineering, Kyungpook National University, Daegu, 702-701 (Korea, Republic of); Priority Research Center, Research Institute of Advanced Energy Technology, Kyungpook National University, Daegu, 702-701 (Korea, Republic of); Lee, Joon-Hyung [School of Materials Science and Engineering, Kyungpook National University, Daegu, 702-701 (Korea, Republic of); Park, Soo-Young; Kang, Inn-Kyu [Department of Polymer Science and Engineering and Graduate School of Applied Chemical Engineering, Kyungpook National University, Daegu, 702-701 (Korea, Republic of)

2014-09-15T23:59:59.000Z

12

Molecular doping for control of gate bias stress in organic thin film transistors  

SciTech Connect (OSTI)

The key active devices of future organic electronic circuits are organic thin film transistors (OTFTs). Reliability of OTFTs remains one of the most challenging obstacles to be overcome for broad commercial applications. In particular, bias stress was identified as the key instability under operation for numerous OTFT devices and interfaces. Despite a multitude of experimental observations, a comprehensive mechanism describing this behavior is still missing. Furthermore, controlled methods to overcome these instabilities are so far lacking. Here, we present the approach to control and significantly alleviate the bias stress effect by using molecular doping at low concentrations. For pentacene and silicon oxide as gate oxide, we are able to reduce the time constant of degradation by three orders of magnitude. The effect of molecular doping on the bias stress behavior is explained in terms of the shift of Fermi Level and, thus, exponentially reduced proton generation at the pentacene/oxide interface.

Hein, Moritz P., E-mail: hein@iapp.de; Lüssem, Björn; Jankowski, Jens; Tietze, Max L.; Riede, Moritz K. [Institut für Angewandte Photophysik, Technische Universität Dresden, George-Bähr-Straße 1, 01069 Dresden (Germany)] [Institut für Angewandte Photophysik, Technische Universität Dresden, George-Bähr-Straße 1, 01069 Dresden (Germany); Zakhidov, Alexander A. [Fraunhofer COMEDD, Maria-Reiche-Str. 2, 01109 Dresden (Germany)] [Fraunhofer COMEDD, Maria-Reiche-Str. 2, 01109 Dresden (Germany); Leo, Karl [Institut für Angewandte Photophysik, Technische Universität Dresden, George-Bähr-Straße 1, 01069 Dresden (Germany) [Institut für Angewandte Photophysik, Technische Universität Dresden, George-Bähr-Straße 1, 01069 Dresden (Germany); Fraunhofer COMEDD, Maria-Reiche-Str. 2, 01109 Dresden (Germany)

2014-01-06T23:59:59.000Z

13

All-Optical Switch and Transistor Gated by One Stored Photon  

E-Print Network [OSTI]

The realization of an all-optical transistor, in which one “gate” photon controls a “source” light beam, is a long-standing goal in optics. By stopping a light pulse in an atomic ensemble contained inside an optical ...

Chen, Wenlan

14

pH sensing properties of graphene solution-gated field-effect transistors  

E-Print Network [OSTI]

The use of graphene grown by chemical vapor deposition to fabricate solution-gated field-effect transistors (SGFET) on different substrates is reported. SGFETs were fabricated using graphene transferred on poly(ethylene ...

Mailly-Giacchetti, Benjamin

2013-01-01T23:59:59.000Z

15

Influence of Electrolyte Composition on Liquid-Gated Carbon Nanotube and Graphene Transistors  

E-Print Network [OSTI]

Influence of Electrolyte Composition on Liquid-Gated Carbon Nanotube and Graphene Transistors Iddo-walled carbon nanotubes (SWNTs) and graphene can function as highly sensitive nanoscale (bio)sensors in solution. Here, we compare experimentally how SWNT and graphene transistors respond to changes in the composition

Dekker, Cees

16

Graphene field-effect transistors based on boron nitride gate dielectrics Inanc Meric1  

E-Print Network [OSTI]

Graphene field-effect transistors based on boron nitride gate dielectrics Inanc Meric1 , Cory Dean1, 10027 Tel: (212) 854-2529, Fax: (212) 932-9421, Email: shepard@ee.columbia.edu Abstract Graphene field of graphene, as the gate dielectric. The devices ex- hibit mobility values exceeding 10,000 cm2 /V

Shepard, Kenneth

17

Coherent molecular transistor: Control through variation of the gate wave function  

SciTech Connect (OSTI)

In quantum interference transistors (QUITs), the current through the device is controlled by variation of the gate component of the wave function that interferes with the wave function component joining the source and the sink. Initially, mesoscopic QUITs have been studied and more recently, QUITs at the molecular scale have been proposed and implemented. Typically, in these devices the gate lead is subjected to externally adjustable physical parameters that permit interference control through modifications of the gate wave function. Here, we present an alternative model of a molecular QUIT in which the gate wave function is directly considered as a variable and the transistor operation is discussed in terms of this variable. This implies that we specify the gate current as well as the phase of the gate wave function component and calculate the resulting current through the source-sink channel. Thus, we extend on prior works that focus on the phase of the gate wave function component as a control parameter while having zero or certain discrete values of the current. We address a large class of systems, including finite graphene flakes, and obtain analytic solutions for how the gate wave function controls the transistor.

Ernzerhof, Matthias, E-mail: Matthias.Ernzerhof@UMontreal.ca [Département de Chimie, Université de Montréal, C.P. 6128 Succursale A, Montréal, Quebec H3C 3J7 (Canada)] [Département de Chimie, Université de Montréal, C.P. 6128 Succursale A, Montréal, Quebec H3C 3J7 (Canada)

2014-03-21T23:59:59.000Z

18

High-Performance Integrated Dual-Gate AlGaN/GaN Enhancement-Mode Transistor  

E-Print Network [OSTI]

In this letter, we present a new AlGaN/GaN enhancement-mode (E-mode) transistor based on a dual-gate structure. The dual gate allows the transistor to combine an E-mode behavior with low on-resistance and very high breakdown ...

Lu, Bin

19

Choosing a gate dielectric for graphene based transistors  

E-Print Network [OSTI]

Much attention has recently been focused on graphene as an alternative semiconductor to silicon. Transistors with graphene conduction channels have only recently been fabricated and their performance remains to be optimized. ...

Hsu, Pei-Lan, M. Eng. Massachusetts Institute of Technology

2008-01-01T23:59:59.000Z

20

Direct deposition of aluminum oxide gate dielectric on graphene channel using nitrogen plasma treatment  

SciTech Connect (OSTI)

Deposition of high-quality dielectric on a graphene channel is an essential technology to overcome structural constraints for the development of nano-electronic devices. In this study, we investigated a method for directly depositing aluminum oxide (Al{sub 2}O{sub 3}) on a graphene channel through nitrogen plasma treatment. The deposited Al{sub 2}O{sub 3} thin film on graphene demonstrated excellent dielectric properties with negligible charge trapping and de-trapping in the gate insulator. A top-gate-structural graphene transistor was fabricated using Al{sub 2}O{sub 3} as the gate dielectric with nitrogen plasma treatment on graphene channel region, and exhibited p-type transistor characteristics.

Lim, Taekyung; Kim, Dongchool; Ju, Sanghyun [Department of Physics, Kyonggi University, Suwon, Gyeonggi-Do 443-760 (Korea, Republic of)

2013-07-01T23:59:59.000Z

Note: This page contains sample records for the topic "transistor gate oxide" from the National Library of EnergyBeta (NLEBeta).
While these samples are representative of the content of NLEBeta,
they are not comprehensive nor are they the most current set.
We encourage you to perform a real-time search of NLEBeta
to obtain the most current and comprehensive results.


21

Silicon-on-insulator-based high-voltage, high-temperature integrated circuit gate driver for silicon carbide-based power field effect transistors  

SciTech Connect (OSTI)

Silicon carbide (SiC)-based field effect transistors (FETs) are gaining popularity as switching elements in power electronic circuits designed for high-temperature environments like hybrid electric vehicle, aircraft, well logging, geothermal power generation etc. Like any other power switches, SiC-based power devices also need gate driver circuits to interface them with the logic units. The placement of the gate driver circuit next to the power switch is optimal for minimising system complexity. Successful operation of the gate driver circuit in a harsh environment, especially with minimal or no heat sink and without liquid cooling, can increase the power-to-volume ratio as well as the power-to-weight ratio for power conversion modules such as a DC-DC converter, inverter etc. A silicon-on-insulator (SOI)-based high-voltage, high-temperature integrated circuit (IC) gate driver for SiC power FETs has been designed and fabricated using a commercially available 0.8--m, 2-poly and 3-metal bipolar-complementary metal oxide semiconductor (CMOS)-double diffused metal oxide semiconductor (DMOS) process. The prototype circuit-s maximum gate drive supply can be 40-V with peak 2.3-A sourcing/sinking current driving capability. Owing to the wide driving range, this gate driver IC can be used to drive a wide variety of SiC FET switches (both normally OFF metal oxide semiconductor field effect transistor (MOSFET) and normally ON junction field effect transistor (JFET)). The switching frequency is 20-kHz and the duty cycle can be varied from 0 to 100-. The circuit has been successfully tested with SiC power MOSFETs and JFETs without any heat sink and cooling mechanism. During these tests, SiC switches were kept at room temperature and ambient temperature of the driver circuit was increased to 200-C. The circuit underwent numerous temperature cycles with negligible performance degradation.

Tolbert, Leon M [ORNL; Huque, Mohammad A [ORNL; Blalock, Benjamin J [ORNL; Islam, Syed K [ORNL

2010-01-01T23:59:59.000Z

22

Dirac point and transconductance of top-gated graphene field-effect transistors operating at elevated temperature  

SciTech Connect (OSTI)

Top-gated graphene field-effect transistors (GFETs) have been fabricated using bilayer epitaxial graphene grown on the Si-face of 4H-SiC substrates by thermal decomposition of silicon carbide in high vacuum. Graphene films were characterized by Raman spectroscopy, Atomic Force Microscopy, Scanning Tunnelling Microscopy, and Hall measurements to estimate graphene thickness, morphology, and charge transport properties. A 27?nm thick Al{sub 2}O{sub 3} gate dielectric was grown by atomic layer deposition with an e-beam evaporated Al seed layer. Electrical characterization of the GFETs has been performed at operating temperatures up to 100?°C limited by deterioration of the gate dielectric performance at higher temperatures. Devices displayed stable operation with the gate oxide dielectric strength exceeding 4.5 MV/cm at 100?°C. Significant shifting of the charge neutrality point and an increase of the peak transconductance were observed in the GFETs as the operating temperature was elevated from room temperature to 100?°C.

Hopf, T.; Vassilevski, K. V., E-mail: k.vasilevskiy@ncl.ac.uk; Escobedo-Cousin, E.; King, P. J.; Wright, N. G.; O'Neill, A. G.; Horsfall, A. B.; Goss, J. P. [School of Electrical and Electronic Engineering, Newcastle University, Newcastle upon Tyne NE1 7RU (United Kingdom); Wells, G. H.; Hunt, M. R. C. [Department of Physics, Durham University, Durham DH1 3LE (United Kingdom)

2014-10-21T23:59:59.000Z

23

Electronic transport mechanisms in scaled gate-all-around silicon nanowire transistor arrays  

SciTech Connect (OSTI)

Low-frequency noise is used to study the electronic transport in arrays of 14?nm gate length vertical silicon nanowire devices. We demonstrate that, even at such scaling, the electrostatic control of the gate-all-around is sufficient in the sub-threshold voltage region to confine charges in the heart of the wire, and the extremely low noise level is comparable to that of high quality epitaxial layers. Although contact noise can already be a source of poor transistor operation above threshold voltage for few nanowires, nanowire parallelization drastically reduces its impact.

Clément, N., E-mail: nicolas.clement@iemn.univ-lille1.fr, E-mail: guilhem.larrieu@laas.fr; Han, X. L. [Institute of Electronics, Microelectronics and Nanotechnology, CNRS, Avenue Poincaré, 59652 Villeneuve d'Ascq (France)] [Institute of Electronics, Microelectronics and Nanotechnology, CNRS, Avenue Poincaré, 59652 Villeneuve d'Ascq (France); Larrieu, G., E-mail: nicolas.clement@iemn.univ-lille1.fr, E-mail: guilhem.larrieu@laas.fr [Laboratory for Analysis and Architecture of Systems (LAAS), CNRS, Universite de Toulouse, 7 Avenue Colonel Roche, 31077 Toulouse (France)

2013-12-23T23:59:59.000Z

24

Passivation effect on gate-bias stress instability of carbon nanotube thin film transistors  

SciTech Connect (OSTI)

A prior requirement of any developed transistor for practical use is the stability test. Random network carbon nanotube-thin film transistor (CNT-TFT) was fabricated on SiO{sub 2}/Si. Gate bias stress stability was investigated with various passivation layers of HfO{sub 2} and Al{sub 2}O{sub 3}. Compared to the threshold voltage shift without passivation layer, the measured values in the presence of passivation layers were reduced independent of gate bias polarity except HfO{sub 2} under positive gate bias stress (PGBS). Al{sub 2}O{sub 3} capping layer was found to be the best passivation layer to prevent ambient gas adsorption, while gas adsorption on HfO{sub 2} layer was unavoidable, inducing surface charges to increase threshold voltage shift in particular for PGBS. This high performance in the gate bias stress test of CNT-TFT even superior to that of amorphous silicon opens potential applications to active TFT industry for soft electronics.

Won Lee, Sang [Center for Integrated Nanostructure Physics (CINAP), Institute for Basic Science (IBS), Sungkyunkwan University, Suwon 440-746 (Korea, Republic of); Suh, Dongseok, E-mail: energy.suh@skku.edu [Center for Integrated Nanostructure Physics (CINAP), Institute for Basic Science (IBS), Sungkyunkwan University, Suwon 440-746 (Korea, Republic of); Department of Energy Science and Department of Physics, Sungkyunkwan University, Suwon 440-746 (Korea, Republic of); Young Lee, Si [Center for Integrated Nanostructure Physics (CINAP), Institute for Basic Science (IBS), Sungkyunkwan University, Suwon 440-746 (Korea, Republic of); Department of Physics, Sungkyunkwan Advanced Institute of Nanotechnology, Sungkyunkwan University, Suwon 440-746 (Korea, Republic of); Hee Lee, Young, E-mail: leeyoung@skku.edu [Center for Integrated Nanostructure Physics (CINAP), Institute for Basic Science (IBS), Sungkyunkwan University, Suwon 440-746 (Korea, Republic of); Department of Energy Science and Department of Physics, Sungkyunkwan University, Suwon 440-746 (Korea, Republic of); Department of Physics, Sungkyunkwan Advanced Institute of Nanotechnology, Sungkyunkwan University, Suwon 440-746 (Korea, Republic of)

2014-04-21T23:59:59.000Z

25

Spin transistor operation driven by the Rashba spin-orbit coupling in the gated nanowire  

SciTech Connect (OSTI)

A theoretical description has been proposed for the operation of the spin transistor in the gate-controlled InAs nanowire. The calculated current-voltage characteristics show that the electron current flowing from the source (spin injector) to the drain (spin detector) oscillates as a function of the gate voltage, which results from the precession of the electron spin caused by the Rashba spin-orbit interaction in the vicinity of the gate. We have studied the operation of the spin transistor under the following conditions: (A) the full spin polarization of electrons in the contacts, zero temperature, and the single conduction channel corresponding to the lowest-energy subband of the transverse motion and (B) the partial spin polarization of the electrons in the contacts, the room temperature, and the conduction via many transverse subbands taken into account. For case (A), the spin-polarized current can be switched on/off by the suitable tuning of the gate voltage, for case (B) the current also exhibits the pronounced oscillations but with no-zero minimal values. The computational results obtained for case (B) have been compared with the recent experimental data and a good agreement has been found.

Wójcik, P.; Adamowski, J., E-mail: adamowski@fis.agh.edu.pl; Spisak, B. J.; Wo?oszyn, M. [Faculty of Physics and Applied Computer Science, AGH University of Science and Technology, al. Mickiewicza 30, Kraków (Poland)

2014-03-14T23:59:59.000Z

26

P-type and N-type multi-gate polycrystalline silicon vertical thin film transistors based on low-temperature technology  

E-Print Network [OSTI]

is obtained. P-type and N-type vertical TFTs have shown symmetric electrical characteristics. DifferentP-type and N-type multi-gate polycrystalline silicon vertical thin film transistors based on low) ABSTRACT P-type and N-type multi-gate vertical thin film transistors (vertical TFTs) have been fabricated

Boyer, Edmond

27

Effects of fluorine incorporation into HfO{sub 2} gate dielectrics on InP and In{sub 0.53}Ga{sub 0.47}As metal-oxide-semiconductor field-effect-transistors  

SciTech Connect (OSTI)

In this work, the effects of fluorine (F) incorporation on electrical characteristics of HfO{sub 2}/InP and HfO{sub 2}/In{sub 0.53}Ga{sub 0.47}As gate stack are presented. F had been introduced into HfO{sub 2} gate dielectric by postgate CF{sub 4} plasma treatment, which was confirmed by x-ray photoelectron spectroscopy analysis and a secondary ion mass spectrometry technique. Compared to the control sample, fluorinated samples had great improvements in subthreshold swing, hysteresis, the normalized extrinsic transconductance, and the normalized drain current. These improvements can be attributed to the reduction in fixed charge in the HfO{sub 2} bulk and less interface trap density at the HfO{sub 2}/III-V interface.

Chen Yenting; Zhao Han; Wang Yanzhen; Xue Fei; Zhou Fei; Lee, Jack C. [Department of Electrical and Computer Engineering, Microelectronics Research Center, University of Texas at Austin, Texas 78758 (United States)

2010-06-21T23:59:59.000Z

28

Characterization of the pentacene thin-film transistors with an epoxy resin-based polymeric gate insulator  

E-Print Network [OSTI]

Characterization of the pentacene thin-film transistors with an epoxy resin-based polymeric gate seeking desirable semi- conductor/insulator combinations [3]. In this study, we adopted an epoxy resin fabricated and characterized. SU-8, a reliable epoxy-based pho- toresist, is tested as a potential highly

Boyer, Edmond

29

A Strained Organic Field-Effect-Transistor with a Gate-Tunable Superconducting Channel  

E-Print Network [OSTI]

In state-of-the-art silicon devices, mobility of the carrier is enhanced by the lattice strain from the back substrate. Such an extra control of device performance is significant in realizing high performance computing and should be valid for electric-field-induced superconducting devices, too. However, so far, the carrier density is the sole parameter for field-induced superconducting interfaces. Here we show an active organic superconducting field-effect-transistor whose lattice is modulated by the strain from the substrate. The soft organic lattice allows tuning of the strain by a choice of the back substrate to make an induced superconducting state accessible at low temperature with a paraelectric solid gate. An active three terminal Josephson junction device thus realized is useful both in advanced computing and in elucidating a direct connection between filling-controlled and bandwidth-controlled superconducting phases in correlated materials.

Hiroshi M. Yamamoto; Masaki Nakano; Masayuki Suda; Yoshihiro Iwasa; Masashi Kawasaki; Reizo Kato

2013-09-02T23:59:59.000Z

30

Poly(methyl methacrylate) as a self-assembled gate dielectric for graphene field-effect transistors  

SciTech Connect (OSTI)

We investigate poly(methyl methacrylate) (PMMA) as a low thermal budget organic gate dielectric for graphene field effect-transistors (GFETs) based on a simple process flow. We show that high temperature baking steps above the glass transition temperature (?130?°C) can leave a self-assembled, thin PMMA film on graphene, where we get a gate dielectric almost for “free” without additional atomic layer deposition type steps. Electrical characterization of GFETs with PMMA as a gate dielectric yields a dielectric constant of k?=?3.0. GFETs with thinner PMMA dielectrics have a lower dielectric constant due to decreased polarization arising from neutralization of dipoles and charged carriers as baking temperatures increase. The leakage through PMMA gate dielectric increases with decreasing dielectric thickness and increasing electric field. Unlike conventional high-k gate dielectrics, such low-k organic gate dielectrics are potentially attractive for devices such as the proposed Bilayer pseudoSpin Field-Effect Transistor or flexible high speed graphene electronics.

Sanne, A.; Movva, H. C. P.; Kang, S.; McClellan, C.; Corbet, C. M.; Banerjee, S. K. [Microelectronics Research Center, University of Texas, Austin, Texas 78758 (United States)

2014-02-24T23:59:59.000Z

31

Single trap dynamics in electrolyte-gated Si-nanowire field effect transistors  

SciTech Connect (OSTI)

Liquid-gated silicon nanowire (NW) field effect transistors (FETs) are fabricated and their transport and dynamic properties are investigated experimentally and theoretically. Random telegraph signal (RTS) fluctuations were registered in the nanolength channel FETs and used for the experimental and theoretical analysis of transport properties. The drain current and the carrier interaction processes with a single trap are analyzed using a quantum-mechanical evaluation of carrier distribution in the channel and also a classical evaluation. Both approaches are applied to treat the experimental data and to define an appropriate solution for describing the drain current behavior influenced by single trap resulting in RTS fluctuations in the Si NW FETs. It is shown that quantization and tunneling effects explain the behavior of the electron capture time on the single trap. Based on the experimental data, parameters of the single trap were determined. The trap is located at a distance of about 2?nm from the interface Si/SiO{sub 2} and has a repulsive character. The theory of dynamic processes in liquid-gated Si NW FET put forward here is in good agreement with experimental observations of transport in the structures and highlights the importance of quantization in carrier distribution for analyzing dynamic processes in the nanostructures.

Pud, S.; Li, J.; Offenhäusser, A.; Vitusevich, S. A., E-mail: s.vitusevich@fz-juelich.de [Peter Grünberg Institute (PGI-8), Forschungszentrum Jülich, 52425 Jülich (Germany); Gasparyan, F. [Peter Grünberg Institute (PGI-8), Forschungszentrum Jülich, 52425 Jülich (Germany); Department of Semiconductor Physics and Microelectronics, Yerevan State University, 1 Alex Manoogian St., 0025 Yerevan (Armenia); Petrychuk, M. [Radiophysics Faculty, T. Shevchenko National University of Kyiv, 60 Volodymyrska St., 01601 Kyiv (Ukraine)

2014-06-21T23:59:59.000Z

32

In–Ga–Zn–O thin film transistor with HfO{sub 2} gate insulator prepared using various O{sub 2}/(Ar + O{sub 2}) gas ratios  

SciTech Connect (OSTI)

We have investigated the effect of the deposition of an HfO{sub 2} thin film as a gate insulator with different O{sub 2}/(Ar + O{sub 2}) gas ratios using RF magnetron sputtering. The HfO{sub 2} thin film affected the device performance of amorphous indium–gallium–zinc oxide transistors. The performance of the fabricated transistors improved monotonously with increasing O{sub 2}/(Ar + O{sub 2}) gas ratio: at a ratio of 0.35, the field effect mobility of the amorphous InGaZnO thin film transistors was improved to 7.54 cm{sup 2}/(V s). Compared to those prepared with an O{sub 2}/(Ar + O{sub 2}) gas ratio of 0.05, the field effect mobility of the amorphous InGaZnO thin film transistors was increased to 1.64 cm{sup 2}/(V s) at a ratio of 0.35. This enhancement in the field effect mobility was attributed to the reduction of the root mean square roughness of the gate insulator layer, which might result from the trap states and surface scattering of the gate insulator layer at the lower O{sub 2}/(Ar + O{sub 2}) gas ratio.

Jo, Young Je [WCU Department of Printed Electronics, Sunchon National University, Chonnam 540-742 (Korea, Republic of)] [WCU Department of Printed Electronics, Sunchon National University, Chonnam 540-742 (Korea, Republic of); Lee, In-Hwan [School of Advanced Materials Engineering, Chonbuk National University, Chonju 561-756 (Korea, Republic of)] [School of Advanced Materials Engineering, Chonbuk National University, Chonju 561-756 (Korea, Republic of); Kwak, Joon Seop, E-mail: jskwak@sunchon.ac.kr [WCU Department of Printed Electronics, Sunchon National University, Chonnam 540-742 (Korea, Republic of)

2012-10-15T23:59:59.000Z

33

Enhancing controllability and stability of bottom-gated graphene thin-film transistors by passivation with methylamine  

SciTech Connect (OSTI)

This paper is intended to aid to bridge the gap between chemistry and electronic engineering. In this work, the fabrication of chemical vapour deposited graphene field-effect transistors employing silicon-nitride (Si{sub 3}N{sub 4}) gate dielectric is presented, showing originally p-type channel conduction due to ambient impurities yielding uncontrollable behaviour. Vacuum annealing has been performed to balance off hole and electron conduction in the channel, leading to the observation of the Dirac point and therefore improving controllability. Non-covalent functionalisation by methylamine has been performed for passivation and stability reasons yielding electron mobility of 4800?cm{sup 2}/V?s and hole mobility of 3800?cm{sup 2}/V?s as well as stabilised controllable behaviour of a bottom-gated transistor. The introduction of interface charge following the non-covalent functionalisation as well as the charge balance have been discussed and analysed.

Drapeko, Maksim, E-mail: maksim.drapeko.10@ucl.ac.uk, E-mail: md584@cam.ac.uk [London Centre for Nanotechnology, University College London, 17-19 Gordon Street, WC1H 0AH London, United Kingdom and Centre for Advanced Photonics and Electronics, Department of Engineering, Cambridge University, 9 J J Thomson Avenue, CB3 0HE Cambridge (United Kingdom)

2014-06-02T23:59:59.000Z

34

Radiation-damage phenomena in insulated-gate field-effect transistors  

SciTech Connect (OSTI)

This study reports on investigation of the electrical influences of ionizing radiation on the characteristics of Insulated Gate Field Effect Transistors. It includes two major parts, i.e., (A) The electrical effects of device characteristics of the defect generated by silicon or oxygen ion implantation has been examined in detail. Surprisingly, large quantities of neutral electron traps (NET) are generated, and only small quantities of fixed positive charge (FPC) is observed. These studies also raise the issue of the correlation between E{sub {gamma}}{prime} centers and FPC. A similar correlation can be made between E{sub {gamma}}{prime} centers and NET since processes that annihilate FPC tend to create fixed negative charge (FNC) from NET, and processes that would tend to generate FPC would tend to create NET from FNC. It was found that silicon or oxygen implanted gate insulators are more susceptible to X-ray radiation than unimplanted devices and that insulator damage due to silicon or oxygen ion implantation is essentially unannealable. (B) A new electron trapping model has been proposed to model experimental data better than is accomplished by existing first-order trapping kinetic approaches. This model includes a continuous decrease of the trapping cross section, {sigma}{sub 0}, as a function of the number of filled traps, N{sub D}. The dependency of {sigma}{sub 0} is believed to be related physically to the annihilation, or buildup of coulombic charge, which repulsive effect has heretofore been neglected in first-order trapping kinetics that describe the entire defect concentration range. It was found that an injection current density dependency of electron trapping at constant total injected charge occurs only when NETs are being filled.

Sune, Chingtzong.

1990-01-01T23:59:59.000Z

35

Looking at Transistor Gate Oxide Formation in Real Time  

Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

AFDC Printable Version Share this resource Send a link to EERE: Alternative Fuels Data Center Home Page to someone by E-mail Share EERE: Alternative Fuels Data Center Home Page on Facebook Tweet about EERE: Alternative Fuels Data Center Home Page on Twitter Bookmark EERE:1 First Use of Energy for All Purposes (Fuel and Nonfuel),Feet) Year Jan Feb Mar Apr MayAtmospheric Optical Depth7-1D: VegetationEquipment Surfaces and Interfaces Sample6,Local CorrelationsConditions. |SchoolLooking at

36

Looking at Transistor Gate Oxide Formation in Real Time  

Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

AFDC Printable Version Share this resource Send a link to EERE: Alternative Fuels Data Center Home Page to someone by E-mail Share EERE: Alternative Fuels Data Center Home Page on Facebook Tweet about EERE: Alternative Fuels Data Center Home Page on Twitter Bookmark EERE:1 First Use of Energy for All Purposes (Fuel and Nonfuel),Feet) Year Jan Feb Mar Apr MayAtmospheric Optical Depth7-1D: VegetationEquipment Surfaces and Interfaces Sample6,Local CorrelationsConditions. |SchoolLooking

37

Looking at Transistor Gate Oxide Formation in Real Time  

Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

AFDC Printable Version Share this resource Send a link to EERE: Alternative Fuels Data Center Home Page to someone by E-mail Share EERE: Alternative Fuels Data Center Home Page on Facebook Tweet about EERE: Alternative Fuels Data Center Home Page on Twitter Bookmark EERE:1 First Use of Energy for All Purposes (Fuel and Nonfuel),Feet) Year Jan Feb Mar Apr MayAtmospheric Optical Depth7-1D: VegetationEquipment Surfaces and Interfaces Sample6,Local CorrelationsConditions. |SchoolLookingLooking

38

Looking at Transistor Gate Oxide Formation in Real Time  

Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

AFDC Printable Version Share this resource Send a link to EERE: Alternative Fuels Data Center Home Page to someone by E-mail Share EERE: Alternative Fuels Data Center Home Page on Facebook Tweet about EERE: Alternative Fuels Data Center Home Page on Twitter Bookmark EERE:1 First Use of Energy for All Purposes (Fuel and Nonfuel),Feet) Year Jan Feb Mar Apr MayAtmospheric Optical Depth7-1D: VegetationEquipment Surfaces and Interfaces Sample6,Local CorrelationsConditions.

39

Looking at Transistor Gate Oxide Formation in Real Time  

Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

AFDC Printable Version Share this resource Send a link to EERE: Alternative Fuels Data Center Home Page to someone by E-mail Share EERE: Alternative Fuels Data Center Home Page on Facebook Tweet about EERE: Alternative Fuels Data Center Home Page on Twitter Bookmark EERE:1 First Use of Energy for All Purposes (Fuel and Nonfuel),Feet) Year Jan Feb Mar Apr May JunDatastreamsmmcrcalgovInstrumentsruc DocumentationP-SeriesFlickrinformationPostdocsCenterCentera A B C D ELong TermJefferson

40

Looking at Transistor Gate Oxide Formation in Real Time  

Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

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Note: This page contains sample records for the topic "transistor gate oxide" from the National Library of EnergyBeta (NLEBeta).
While these samples are representative of the content of NLEBeta,
they are not comprehensive nor are they the most current set.
We encourage you to perform a real-time search of NLEBeta
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41

Looking at Transistor Gate Oxide Formation in Real Time  

Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

AFDC Printable Version Share this resource Send a link to EERE: Alternative Fuels Data Center Home Page to someone by E-mail Share EERE: Alternative Fuels Data Center Home Page on Facebook Tweet about EERE: Alternative Fuels Data Center Home Page on Twitter Bookmark EERE:1 First Use of Energy for All Purposes (Fuel and Nonfuel),Feet) Year Jan Feb Mar Apr May JunDatastreamsmmcrcalgovInstrumentsruc DocumentationP-SeriesFlickrinformationPostdocsCenterCentera A B C D ELong

42

Physics of gate leakage current in N-polar InAlN/GaN heterojunction field effect transistors  

SciTech Connect (OSTI)

A physics based model of the gate leakage current in N-polar InAlN/GaN heterojunction field effect transistors is demonstrated. The model is based on the space charge limited current flow dominated by the effects of deep traps in the InAlN surface layer. The model predicts accurately the gate-leakage measurement data of the N-polar InAlN/GaN device with InAlN cap layer. In the pinch-off state, the gate leakage current conduction through the surface of the device in the drain access region dominates the current flow through the two dimensional electron gas channel. One deep trap level and two levels of shallow traps are extracted by fitting the model results with measurement data.

Goswami, Arunesh; Trew, Robert J.; Bilbro, Griff L. [ECE Department, Box 7911, North Carolina State University, Raleigh, North Carolina 27695-7911 (United States)

2014-10-28T23:59:59.000Z

43

Electron Transport Behavior on Gate Length Scaling in Sub-50 nm GaAs Metal Semiconductor Field Effect Transistors  

SciTech Connect (OSTI)

Short channel GaAs Metal Semiconductor Field Effect Transistors (MESFETs) have been fabricated with gate length to 20 nm, in order to examine the characteristics of sub-50 nm MESFET scaling. Here the rise in the measured transconductance is mainly attributed to electron velocity overshoot. For gate lengths below 40 nm, however, the transconductance drops suddenly. The behavior of velocity overshoot and its degradation is investigated and simulated by using a transport model based on the retarded Langevin equation (RLE). This indicates the existence of a minimum acceleration length needed for the carriers to reach the overshoot velocity. The argument shows that the source resistance must be included as an internal element, or appropriate boundary condition, of relative importance in any model where the gate length is comparable to the inelastic mean free path of the carriers.

Han, Jaeheon [Department of Electronic Engineering, Kangnam University, 111 Gugal-dong, Giheung-gu, Yongin-city, Gyeonggi-do, Korea 446-702 (Korea, Republic of)

2011-12-23T23:59:59.000Z

44

Thin Film Transistors On Plastic Substrates  

DOE Patents [OSTI]

A process for formation of thin film transistors (TFTs) on plastic substrates replaces standard thin film transistor fabrication techniques, and uses sufficiently lower processing temperatures so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The silicon based thin film transistor produced by the process includes a low temperature substrate incapable of withstanding sustained processing temperatures greater than about 250.degree. C., an insulating layer on the substrate, a layer of silicon on the insulating layer having sections of doped silicon, undoped silicon, and poly-silicon, a gate dielectric layer on the layer of silicon, a layer of gate metal on the dielectric layer, a layer of oxide on sections of the layer of silicon and the layer of gate metal, and metal contacts on sections of the layer of silicon and layer of gate metal defining source, gate, and drain contacts, and interconnects.

Carey, Paul G. (Mountain View, CA); Smith, Patrick M. (San Ramon, CA); Sigmon, Thomas W. (Portola Valley, CA); Aceves, Randy C. (Livermore, CA)

2004-01-20T23:59:59.000Z

45

Schottky barrier source-gated ZnO thin film transistors by low temperature atomic layer deposition  

SciTech Connect (OSTI)

We have fabricated ZnO source-gated thin film transistors (SGTFTs) with a buried TiW source Schottky barrier and a top gate contact. The ZnO active channel and thin high-? HfO{sub 2} dielectric utilized are both grown by atomic layer deposition at temperatures less than 130?°C, and their material and electronic properties are characterized. These SGTFTs demonstrate enhancement-mode operation with a threshold voltage of 0.91?V, electron mobility of 3.9 cm{sup 2} V{sup ?1} s{sup ?1}, and low subthreshold swing of 192?mV/decade. The devices also exhibit a unique combination of high breakdown voltages (>20?V) with low output conductances.

Ma, Alex M.; Gupta, Manisha; Shoute, Gem; Tsui, Ying Y.; Barlage, Douglas W., E-mail: barlage@ualberta.ca [Department of Electrical and Computer Engineering, University of Alberta, Edmonton, Alberta T6G 2V4 (Canada); Afshar, Amir; Cadien, Kenneth C. [Department of Chemical and Materials Engineering, University of Alberta, Edmonton, Alberta T6G 2V4 (Canada)] [Department of Chemical and Materials Engineering, University of Alberta, Edmonton, Alberta T6G 2V4 (Canada)

2013-12-16T23:59:59.000Z

46

Under-gate defect formation in Ni-gate AlGaN/GaN high electron mobility transistors  

E-Print Network [OSTI]

energy loss spectroscopy [23]. In contrast, HEMTs utilizing a Pt liner layer did not show the same gate electrical contact to the 2DEG. However, when stressing occurs in O2 or air, the O2 present reacts

Florida, University of

47

Gate-Controlled Punch Through Transistor Xiangli Li, Huadian Pan, Bogdan M. Wilamowski  

E-Print Network [OSTI]

of the device are simulated using SILVACO atlas device simulator. This device shows high voltage, high operation is proposed and simulated using SILVACO atlas device simulator. The punch through transistors can be used

Wilamowski, Bogdan Maciej

48

Highly specific and sensitive non-enzymatic determination of uric acid in serum and urine by extended gate field effect transistor sensors  

E-Print Network [OSTI]

by extended gate field effect transistor sensors Weihua Guan a,n , Xuexin Duan a , Mark A. Reed a unsuitable to be used for point of care testing. Electrochemical techniques for UA detection have attracted, along with high selectivity and sensitiv- ity (Xue et al., 2011). So far the electrochemical UA

Reed, Mark

49

Anomalous electron transport in back-gated field-effect transistors with TiTe2 semimetal thin-film channels  

E-Print Network [OSTI]

-like" mechanical exfoliation of thin films of titanium ditelluride and investigation of their electronic properties. The exfoliated crystalline TiTe2 films were used as the channel layers in the back-gated field-effect transistors. [doi:10.1063/1.3679679] Successful mechanical exfoliation of graphene1 and investigation of its unique

50

Ballistic performance comparison of monolayer transition metal dichalcogenide MX{sub 2} (M = Mo, W; X = S, Se, Te) metal-oxide-semiconductor field effect transistors  

SciTech Connect (OSTI)

We study the transport properties of monolayer MX{sub 2} (M?=?Mo, W; X?=?S, Se, Te) n- and p-channel metal-oxide-semiconductor field effect transistors (MOSFETs) using full-band ballistic non-equilibrium Green's function simulations with an atomistic tight-binding Hamiltonian with hopping potentials obtained from density functional theory. We discuss the subthreshold slope, drain-induced barrier lowering (DIBL), as well as gate-induced drain leakage (GIDL) for different monolayer MX{sub 2} MOSFETs. We also report the possibility of negative differential resistance behavior in the output characteristics of nanoscale monolayer MX{sub 2} MOSFETs.

Chang, Jiwon; Register, Leonard F.; Banerjee, Sanjay K. [Microelectronics Research Center, The University of Texas at Austin, Austin, Texas 78758 (United States)

2014-02-28T23:59:59.000Z

51

Metal-gate-induced reduction of the interfacial layer in Hf oxide gate stacks  

SciTech Connect (OSTI)

The properties of high-{kappa} metal oxide gate stacks are often determined in the final processing steps following dielectric deposition. We report here results from medium energy ion scattering and x-ray photoelectron spectroscopy studies of oxygen and silicon diffusion and interfacial layer reactions in multilayer gate stacks. Our results show that Ti metallization of HfO{sub 2}/SiO{sub 2}/Si stacks reduces the SiO{sub 2} interlayer and (to a more limited extent) the HfO{sub 2} layer. We find that Si atoms initially present in the interfacial SiO{sub 2} layer incorporate into the bottom of the high-{kappa} layer. Some evidence for Ti-Si interdiffusion through the high-{kappa} film in the presence of a Ti gate in the crystalline HfO{sub 2} films is also reported. This diffusion is likely to be related to defects in crystalline HfO{sub 2} films, such as grain boundaries. High-resolution transmission electron microscopy and corresponding electron energy loss spectroscopy scans show aggressive Ti-Si intermixing and oxygen diffusion to the outermost Ti layer, given high enough annealing temperature. Thermodynamic calculations show that the driving forces exist for some of the observed diffusion processes.

Goncharova, L. V.; Dalponte, M.; Gustafsson, T.; Celik, O.; Garfunkel, E.; Lysaght, P. S.; Bersuker, G. [Department of Physics and Astronomy, and Laboratory for Surface Modification, Rutgers University, 136 Frelinghuysen Rd., Piscataway, New Jersey 08854 (United States); Department of Chemistry and Chemical Biology, and Laboratory for Surface Modification, Rutgers University, 610 Taylor Rd., Piscataway, New Jersey 08854 (United States); SEMATECH, 2705 Montopolis Dr., Austin, Texas 78741 (United States)

2007-03-15T23:59:59.000Z

52

Controlling the Performance of a Three-Terminal Molecular Transistor: Conformational versus Conventional Gating  

E-Print Network [OSTI]

University, Houghton, Michigan 49931, United States Shashi P. Karna* U.S. Army Research Laboratory, Weapons *S Supporting Information ABSTRACT: The effect of conformational changes in the gate arm of a three of the gate field. The current modulation is found to reach its maximum only under exclusive effect of voltage

Pandey, Ravi

53

Hafnium-doped tantalum oxide high-k gate dielectric films for future CMOS technology  

E-Print Network [OSTI]

of the doped films were explained by their compositions and bond structures. The Hf-doped TaOx film is a potential high-k gate dielectric for future MOS transistors. A 5 Ã?Â? tantalum nitride (TaNx) interface layer has been inserted between the Hf-doped Ta...

Lu, Jiang

2007-04-25T23:59:59.000Z

54

High performance organic field-effect transistors with ultra-thin HfO{sub 2} gate insulator deposited directly onto the organic semiconductor  

SciTech Connect (OSTI)

We have produced stable organic field-effect transistors (OFETs) with an ultra-thin HfO{sub 2} gate insulator deposited directly on top of rubrene single crystals by atomic layer deposition (ALD). We find that ALD is a gentle deposition process to grow thin films without damaging rubrene single crystals, as results these devices have a negligibly small threshold voltage and are very stable against gate-bias-stress, and the mobility exceeds 1 cm{sup 2}/V s. Moreover, the devices show very little degradation even when kept in air for more than 2 months. These results demonstrate thin HfO{sub 2} layers deposited by ALD to be well suited as high capacitance gate dielectrics in OFETs operating at small gate voltage. In addition, the dielectric layer acts as an effective passivation layer to protect the organic semiconductor.

Ono, S., E-mail: shimpei@criepi.denken.or.jp [Central Research Institute of Electric Power Industry, Komae, Tokyo 201-8511 (Japan); Häusermann, R. [Central Research Institute of Electric Power Industry, Komae, Tokyo 201-8511 (Japan) [Central Research Institute of Electric Power Industry, Komae, Tokyo 201-8511 (Japan); Laboratory for Solid State Physics, ETH Zurich, Zurich 8093 (Switzerland); Chiba, D. [Institute for Chemical Research, Kyoto University, Gokasho, Uji, Kyoto 611-0011 (Japan) [Institute for Chemical Research, Kyoto University, Gokasho, Uji, Kyoto 611-0011 (Japan); PRESTO, Japan Science and Technology Agency, 4-1-8 Honcho Kawaguchi, Saitama 322-0012 (Japan); Department of Applied Physics, University of Tokyo, Tokyo 113-8656 (Japan); Shimamura, K.; Ono, T. [Institute for Chemical Research, Kyoto University, Gokasho, Uji, Kyoto 611-0011 (Japan)] [Institute for Chemical Research, Kyoto University, Gokasho, Uji, Kyoto 611-0011 (Japan); Batlogg, B. [Laboratory for Solid State Physics, ETH Zurich, Zurich 8093 (Switzerland)] [Laboratory for Solid State Physics, ETH Zurich, Zurich 8093 (Switzerland)

2014-01-06T23:59:59.000Z

55

AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors using barium strontium titanate  

E-Print Network [OSTI]

AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors using barium strontium-effect transistors have been formed by incorporating barium strontium titanate (BST) deposited by rf magnetron in increased leakage. Due to its large dielectric constant, barium strontium ti- tanate [Ba1-xSrxTiO3, (BST

York, Robert A.

56

L{sub g}?=?100?nm In{sub 0.7}Ga{sub 0.3}As quantum well metal-oxide semiconductor field-effect transistors with atomic layer deposited beryllium oxide as interfacial layer  

SciTech Connect (OSTI)

In this study, we have fabricated nanometer-scale channel length quantum-well (QW) metal-oxide-semiconductor field effect transistors (MOSFETs) incorporating beryllium oxide (BeO) as an interfacial layer. BeO has high thermal stability, excellent electrical insulating characteristics, and a large band-gap, which make it an attractive candidate for use as a gate dielectric in making MOSFETs. BeO can also act as a good diffusion barrier to oxygen owing to its small atomic bonding length. In this work, we have fabricated In{sub 0.53}Ga{sub 0.47}As MOS capacitors with BeO and Al{sub 2}O{sub 3} and compared their electrical characteristics. As interface passivation layer, BeO/HfO{sub 2} bilayer gate stack presented effective oxide thickness less 1 nm. Furthermore, we have demonstrated In{sub 0.7}Ga{sub 0.3}As QW MOSFETs with a BeO/HfO{sub 2} dielectric, showing a sub-threshold slope of 100?mV/dec, and a transconductance (g{sub m,max}) of 1.1 mS/?m, while displaying low values of gate leakage current. These results highlight the potential of atomic layer deposited BeO for use as a gate dielectric or interface passivation layer for III–V MOSFETs at the 7?nm technology node and/or beyond.

Koh, D., E-mail: dh.koh@utexas.edu, E-mail: Taewoo.Kim@sematech.org [Department of Electrical and Computer Engineering, Microelectronics Research Center, The University of Texas at Austin, Austin, Texas 78758 (United States); SEMATECH, Inc., Albany, New York 12203 (United States); Kwon, H. M. [Department of Electronics Engineering, Chungnam National University, Daejeon 305-764 (Korea, Republic of); Kim, T.-W., E-mail: dh.koh@utexas.edu, E-mail: Taewoo.Kim@sematech.org; Veksler, D.; Gilmer, D.; Kirsch, P. D. [SEMATECH, Inc., Albany, New York 12203 (United States); Kim, D.-H. [SEMATECH, Inc., Albany, New York 12203 (United States); GLOBALFOUNDRIES, Malta, New York 12020 (United States); Hudnall, Todd W. [Department of Chemistry and Biochemistry, Texas State University, San Marcos, Texas, 78666 (United States); Bielawski, Christopher W. [Department of Chemistry and Biochemistry, The University of Texas at Austin, Austin, Texas 78712 (United States); Maszara, W. [GLOBALFOUNDRIES, Santa Clara, California 95054 (United States); Banerjee, S. K. [Department of Electrical and Computer Engineering, Microelectronics Research Center, The University of Texas at Austin, Austin, Texas 78758 (United States)

2014-04-21T23:59:59.000Z

57

Case Studies on Variation Tolerant and Low Power Design Using Planar Asymmetric Double Gate Transistor  

E-Print Network [OSTI]

new circuit topology for IGFET, which on average shows 33.8% lower leakage and 34.9% lower area at the cost of 2.8% increase in total active mode power, for basic logic gates. Finally, we showed a technique for reducing leakage of minimum sized... ????????????????????????????????????????????????? 5 III.1 Power-delay product for FO4 inverter ????????????????????????????????????? 12 III.2 Power-delay product for 51 Stage ring oscillator ??????????????????????????? 12 IV.1 Delay distribution histogram...

Singh, Amrinder

2011-10-21T23:59:59.000Z

58

Dual operation characteristics of resistance random access memory in indium-gallium-zinc-oxide thin film transistors  

SciTech Connect (OSTI)

In this study, indium-gallium-zinc-oxide thin film transistors can be operated either as transistors or resistance random access memory devices. Before the forming process, current-voltage curve transfer characteristics are observed, and resistance switching characteristics are measured after a forming process. These resistance switching characteristics exhibit two behaviors, and are dominated by different mechanisms. The mode 1 resistance switching behavior is due to oxygen vacancies, while mode 2 is dominated by the formation of an oxygen-rich layer. Furthermore, an easy approach is proposed to reduce power consumption when using these resistance random access memory devices with the amorphous indium-gallium-zinc-oxide thin film transistor.

Yang, Jyun-Bao; Chen, Yu-Ting; Chu, Ann-Kuo [Department of Photonics, National Sun Yat-Sen University, Kaohsiung, Taiwan (China); Chang, Ting-Chang, E-mail: tcchang@mail.phys.nsysu.edu.tw [Department of Photonics, National Sun Yat-Sen University, Kaohsiung, Taiwan (China); Department of Physics, National Sun Yat-Sen University, Kaohsiung, Taiwan (China); Advanced Optoelectronics Technology Center, National Cheng Kung University, Taiwan (China); Huang, Jheng-Jie; Chen, Yu-Chun; Tseng, Hsueh-Chih [Department of Physics, National Sun Yat-Sen University, Kaohsiung, Taiwan (China); Sze, Simon M. [Department of Physics, National Sun Yat-Sen University, Kaohsiung, Taiwan (China); Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan (China)

2014-04-14T23:59:59.000Z

59

Current collapse imaging of Schottky gate AlGaN/GaN high electron mobility transistors by electric field-induced optical second-harmonic generation measurement  

SciTech Connect (OSTI)

Two-dimensional current collapse imaging of a Schottky gate AlGaN/GaN high electron mobility transistor device was achieved by optical electric field-induced second-harmonic generation (EFISHG) measurements. EFISHG measurements can detect the electric field produced by carriers trapped in the on-state of the device, which leads to current collapse. Immediately after (e.g., 1, 100, or 800??s) the completion of drain-stress voltage (200?V) in the off-state, the second-harmonic (SH) signals appeared within 2??m from the gate edge on the drain electrode. The SH signal intensity became weak with time, which suggests that the trapped carriers are emitted from the trap sites. The SH signal location supports the well-known virtual gate model for current collapse.

Katsuno, Takashi, E-mail: e1417@mosk.tytlabs.co.jp; Ishikawa, Tsuyoshi; Ueda, Hiroyuki; Uesugi, Tsutomu [Toyota Central R and D Laboratories Inc., Nagakute, Aichi 480-1192 (Japan); Manaka, Takaaki; Iwamoto, Mitsumasa [Department of Physical Electronics, Tokyo Institute of Technology, Meguro, Tokyo 152-8552 (Japan)

2014-06-23T23:59:59.000Z

60

Fast 8 kV metal-oxide semiconductor field-effect transistor switch R. E. Continetti, D. R. Cyr,al and D. M. Neumarkb)  

E-Print Network [OSTI]

V. A key to this approach is the use of a metal-oxide varistor (MOV) to clamp the voltage acrossa givenFast 8 kV metal-oxide semiconductor field-effect transistor switch R. E. Continetti, D. R. Cyr transformer-isolatedpower metal-oxide semiconductor field-effect transistors in seriesis described

Neumark, Daniel M.

Note: This page contains sample records for the topic "transistor gate oxide" from the National Library of EnergyBeta (NLEBeta).
While these samples are representative of the content of NLEBeta,
they are not comprehensive nor are they the most current set.
We encourage you to perform a real-time search of NLEBeta
to obtain the most current and comprehensive results.


61

New insights into self-heating in double-gate transistors by solving Boltzmann transport equations  

SciTech Connect (OSTI)

Electro-thermal effects become one of the most critical issues for continuing the downscaling of electron devices. To study this problem, a new efficient self-consistent electron-phonon transport model has been developed. Our model of phonon Boltzmann transport equation (pBTE) includes the decay of optical phonons into acoustic modes and a generation term given by electron-Monte Carlo simulation. The solution of pBTE uses an analytic phonon dispersion and the relaxation time approximation for acoustic and optical phonons. This coupled simulation is applied to investigate the self-heating effects in a 20?nm-long double gate MOSFET. The temperature profile per mode and the comparison between Fourier temperature and the effective temperature are discussed. Some significant differences occur mainly in the hot spot region. It is shown that under the influence of self-heating effects, the potential profile is modified and both the drain current and the electron ballisticity are reduced because of enhanced electron-phonon scattering rates.

Thu Trang Nghiêm, T., E-mail: tthutrang.nghiem@gmail.com [Institute of Fundamental Electronics, UMR 8622, CNRS-University of Paris-Sud, Orsay (France); The Center for Thermal Sciences of Lyon, UMR 5008, CNRS–INSA–University of Lyon 1, Villeurbanne (France); Saint-Martin, J.; Dollfus, P. [Institute of Fundamental Electronics, UMR 8622, CNRS-University of Paris-Sud, Orsay (France)

2014-08-21T23:59:59.000Z

62

Electro-oxidized Epitaxial Graphene Channel Field-Effect Transistors with Single-Walled Carbon Nanotube Thin Film  

E-Print Network [OSTI]

Electro-oxidized Epitaxial Graphene Channel Field-Effect Transistors with Single-Walled Carbon on the electronic properties of epitaxial graphene (EG) grown on silicon carbide substrates; we demonstrate the introduction of the reaction medium into the graphene galleries during electro-oxidation. The device

63

Part I:Part I: Degradation in 3.2 nm Gate Oxides:Degradation in 3.2 nm Gate Oxides: Effects on Inverter Performance and MOSFETEffects on Inverter Performance and MOSFET  

E-Print Network [OSTI]

on Inverter Performance and MOSFETEffects on Inverter Performance and MOSFET Characteristics.2 nm Gate Oxides: Effects on Inverter Performance and MOSFETEffects on Inverter Performance and MOSFET

Anlage, Steven

64

Inkjet printed ambipolar transistors and inverters based on carbon nanotube/zinc tin oxide heterostructures  

SciTech Connect (OSTI)

We report ambipolar field-effect transistors (FETs) consisting of inkjet printed semiconductor bilayer heterostructures utilizing semiconducting single-walled carbon nanotubes (SWCNTs) and amorphous zinc tin oxide (ZTO). The bilayer structure allows for electron transport to occur principally in the amorphous oxide layer and hole transport to occur exclusively in the SWCNT layer. This results in balanced electron and hole mobilities exceeding 2 cm{sup 2} V{sup ?1} s{sup ?1} at low operating voltages (<5?V) in air. We further show that the SWCNT-ZTO hybrid ambipolar FETs can be integrated into functional inverter circuits that display high peak gain (>10). This work provides a pathway for realizing solution processable, inkjet printable, large area electronic devices, and systems based on SWCNT-amorphous oxide heterostructures.

Kim, Bongjun; Jang, Seonpil; Dodabalapur, Ananth, E-mail: ananth.dodabalapur@engr.utexas.edu [Microelectronics Research Center, The University of Texas at Austin, Austin, Texas 78758 (United States); Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, Texas 78712 (United States); Geier, Michael L.; Prabhumirashi, Pradyumna L. [Department of Materials Science and Engineering, Northwestern University, Evanston, Illinois 60208 (United States); Hersam, Mark C. [Department of Materials Science and Engineering, Northwestern University, Evanston, Illinois 60208 (United States); Department of Chemistry, Northwestern University, Evanston, Illinois 60208 (United States); Department of Medicine, Northwestern University, Evanston, Illinois 60208 (United States)

2014-02-10T23:59:59.000Z

65

Radiation-hardened transistor and integrated circuit  

DOE Patents [OSTI]

A composite transistor is disclosed for use in radiation hardening a CMOS IC formed on an SOI or bulk semiconductor substrate. The composite transistor has a circuit transistor and a blocking transistor connected in series with a common gate connection. A body terminal of the blocking transistor is connected only to a source terminal thereof, and to no other connection point. The blocking transistor acts to prevent a single-event transient (SET) occurring in the circuit transistor from being coupled outside the composite transistor. Similarly, when a SET occurs in the blocking transistor, the circuit transistor prevents the SET from being coupled outside the composite transistor. N-type and P-type composite transistors can be used for each and every transistor in the CMOS IC to radiation harden the IC, and can be used to form inverters and transmission gates which are the building blocks of CMOS ICs.

Ma, Kwok K. (Albuquerque, NM)

2007-11-20T23:59:59.000Z

66

Thin film three-dimensional topological insulator metal-oxide-semiconductor field-effect-transistors: A candidate for sub-10?nm devices  

SciTech Connect (OSTI)

Three-dimensional (3D) topological insulators (TI) are a new state of quantum matter in which surface states reside in the bulk insulating energy bandgap and are protected by time-reversal symmetry. It is possible to create an energy bandgap as a consequence of the interaction between the conduction band and valence band surface states from the opposite surfaces of a TI thin film, and the width of the bandgap can be controlled by the thin film thickness. The formation of an energy bandgap raises the possibility of thin-film TI-based metal-oxide-semiconductor field-effect-transistors (MOSFETs). In this paper, we explore the performance of MOSFETs based on thin film 3D-TI structures by employing quantum ballistic transport simulations using the effective continuous Hamiltonian with fitting parameters extracted from ab-initio calculations. We demonstrate that thin film transistors based on a 3D-TI structure provide similar electrical characteristics compared to a Si-MOSFET for gate lengths down to 10?nm. Thus, such a device can be a potential candidate to replace Si-based MOSFETs in the sub-10?nm regime.

Akhavan, N. D., E-mail: nima.dehdashti@uwa.edu.au; Jolley, G.; Umana-Membreno, G. A.; Antoszewski, J.; Faraone, L. [Department of Electrical, Electronic and Computer Engineering, University of Western Australia, Crawley, WA 6009 (Australia)

2014-08-28T23:59:59.000Z

67

Characterization of device parameters in high-temperature metal-oxide-semiconductor field-effect transistors in. beta. -SiC thin films  

SciTech Connect (OSTI)

Both inversion- and depletion-mode n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) have been fabricated on ..beta..-SiC thin films grown by chemical-vapor deposition. The inversion-mode devices were made on in situ doped (Al) p-type ..beta..-SiC(100) thin films grown on Si(100) substrates. The depletion-mode MOSFETs were made on n-type ..beta..-SiC(111) thin films grown on the Si(0001) face of a 6H ..cap alpha..-SiC substrates. Stable saturation and low subthreshold currents were achieved at drain-source voltages exceeding 5 and 25 V for the inversion-mode and depletion-mode devices, respectively. The transconductance increased with temperature up to 673 K for the short-gate-length devices, of either mode, and then decreased with further increases in temperature. It is proposed that the transconductances and threshold voltages for the inversion-mode devices are greatly affected by minority-carrier injection from the source. Stable transistor action was observed for both types of devices at temperatures up to 823 K, with the depletion-mode devices operating very well up to 923 K.

Palmour, J.W.; Kong, H.S.; Davis, R.F.

1988-08-15T23:59:59.000Z

68

Double-dot charge transport in Si single-electronhole transistors L. P. Rokhinson,a)  

E-Print Network [OSTI]

­oxide­ semiconductor field-effect transistors MOSFETs brought to light several issues related to the electrical beneath the dot transforming it into a free-standing bridge. Subsequently, 40 or 50 nm of oxide are thermally grown which further reduce the size of the dot. Polysilicon gate is deposited over the bridge

Rokhinson, Leonid

69

Chemoresponsive monolayer transistors Xuefeng Guo*  

E-Print Network [OSTI]

in the gap and form transistors with large current modulation and high gate efficiency. Because these devices and drain (S D) electrodes, transistors can be made that have high gate efficiency and large ON OFF ratios; and §Condensed Matter Physics and Materials Science, Brookhaven National Laboratory, Upton, NY 11973 Edited

Hone, James

70

Lanthanum silicate gate dielectric stacks with subnanometer equivalent oxide thickness utilizing an interfacial silica consumption reaction  

E-Print Network [OSTI]

Lanthanum silicate gate dielectric stacks with subnanometer equivalent oxide thickness utilizing-8087 Received 13 April 2005; accepted 6 June 2005; published online 26 July 2005 A silicate reaction between process route to interface elimination, while producing a silicate dielectric with a higher temperature

Garfunkel, Eric

71

Significant electrical control of amorphous oxide thin film transistors by an ultrathin Ti surface polarity modifier  

SciTech Connect (OSTI)

We demonstrate an enhanced electrical stability through a Ti oxide (TiO{sub x}) layer on the amorphous InGaZnO (a-IGZO) back-channel; this layer acts as a surface polarity modifier. Ultrathin Ti deposited on the a-IGZO existed as a TiO{sub x} thin film, resulting in oxygen cross-binding with a-IGZO surface. The electrical properties of a-IGZO thin film transistors (TFTs) with TiO{sub x} depend on the surface polarity change and electronic band structure evolution. This result indicates that TiO{sub x} on the back-channel serves as not only a passivation layer protecting the channel from ambient molecules or process variables but also a control layer of TFT device parameters.

Cho, Byungsu [Division of Materials Science and Engineering, Hanyang University, Seoul 133-791 (Korea, Republic of); Samsung Display Co. Ltd., Tangjeong, Chungcheongnam-Do 336-741 (Korea, Republic of); Choi, Yonghyuk; Shin, Seokyoon [Division of Materials Science and Engineering, Hanyang University, Seoul 133-791 (Korea, Republic of); Jeon, Heeyoung [Department of Nano-scale Semiconductor Engineering, Hanyang University, Seoul 133-791 (Korea, Republic of); Seo, Hyungtak, E-mail: hseo@ajou.ac.kr [Department of Materials Science and Engineering and Energy Systems Research, Ajou University, Suwon 443-739 (Korea, Republic of); Jeon, Hyeongtag, E-mail: hjeon@hanyang.ac.kr [Division of Materials Science and Engineering, Hanyang University, Seoul 133-791 (Korea, Republic of); Department of Nano-scale Semiconductor Engineering, Hanyang University, Seoul 133-791 (Korea, Republic of)

2014-01-27T23:59:59.000Z

72

Prototypical Single-Molecule Chemical-Field-Effect Transistor with Nanometer-Sized Gates F. Jackel,1  

E-Print Network [OSTI]

or break junctions [7,8]. Field effect transistors have been fabricated with carbon nanotubes [9 defects in carbon nanotube field effect tran- sistors [13]. Under ultrahigh vacuum (UHV) conditions and a voltage ramp with 100 equidistant points between ÿ1:5 and 1.5 V was run with the feedback loop switched

Peters, Achim

73

Impact of SF{sub 6} plasma treatment on performance of TaN-HfO{sub 2}-InP metal-oxide-semiconductor field-effect transistor  

SciTech Connect (OSTI)

In this work, the experimental impact of SF{sub 6} plasma treatment on the performance of InP metal-oxide-semiconductor field-effect transistors is presented. S and F are incorporated into atomic layer deposited HfO{sub 2} via postgate SF{sub 6} plasma treatment. The decreased subthreshold swing, gate leakage (I{sub g}), and increased effective channel mobility ({mu}{sub eff}) indicate that better interface and bulk oxide quality have been achieved with SF{sub 6} plasma treatment due to the formation of stronger Hf-F bonds. Drive current (I{sub d}), transconductance (G{sub m}), and effective channel mobility ({mu}{sub eff}) are improved by 22.3%, 35%, and 35%, respectively, compared with those of control devices.

Wang Yanzhen; Chen Yenting; Zhao Han; Xue Fei; Zhou Fei; Lee, Jack C. [Department of Electrical and Computer Engineering, Microelectronics Research Center, University of Texas at Austin, Austin, Texas 78758 (United States)

2011-01-24T23:59:59.000Z

74

SiC Power MOSFET with Improved Gate Dielectric  

SciTech Connect (OSTI)

In this STTR program, Structured Materials Industries (SMI), and Cornell University are developing novel gate oxide technology, as a critical enabler for silicon carbide (SiC) devices. SiC is a wide bandgap semiconductor material, with many unique properties. SiC devices are ideally suited for high-power, highvoltage, high-frequency, high-temperature and radiation resistant applications. The DOE has expressed interest in developing SiC devices for use in extreme environments, in high energy physics applications and in power generation. The development of transistors based on the Metal Oxide Semiconductor Field Effect Transistor (MOSFET) structure will be critical to these applications.

Sbrockey, Nick M; Tompa, Gary S; Spencer, Michael G; Chandrashekhar, Chandra MVS

2010-08-23T23:59:59.000Z

75

Experimental study on vertical scaling of InAs-on-insulator metal-oxide-semiconductor field-effect transistors  

SciTech Connect (OSTI)

We have investigated effects of the vertical scaling on electrical properties in extremely thin-body InAs-on-insulator (-OI) metal-oxide-semiconductor field-effect transistors (MOSFETs). It is found that the body thickness (T{sub body}) scaling provides better short channel effect (SCE) control, whereas the T{sub body} scaling also causes the reduction of the mobility limited by channel thickness fluctuation (?T{sub body}) scattering (?{sub fluctuation}). Also, in order to achieve better SCEs control, the thickness of InAs channel layer (T{sub channel}) scaling is more favorable than the thickness of MOS interface buffer layer (T{sub buffer}) scaling from a viewpoint of a balance between SCEs control and ?{sub fluctuation} reduction. These results indicate necessity of quantum well channel structure in InAs-OI MOSFETs and these should be considered in future transistor design.

Kim, SangHyeon, E-mail: dadembyora@mosfet.t.u-tokyo.ac.jp, E-mail: sh-kim@kist.re.kr; Yokoyama, Masafumi; Nakane, Ryosho; Takenaka, Mitsuru; Takagi, Shinichi [Department of Electrical Engineering and Information Systems, The University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656 (Japan); Ichikawa, Osamu; Osada, Takenori; Hata, Masahiko [Sumitomo Chemical Co., Ltd., 6 Kitahara, Tsukuba, Ibaraki 300-3294 (Japan)

2014-06-30T23:59:59.000Z

76

Investigation of abnormal negative threshold voltage shift under positive bias stress in input/output n-channel metal-oxide-semiconductor field-effect transistors with TiN/HfO{sub 2} structure using fast I-V measurement  

SciTech Connect (OSTI)

This letter investigates abnormal negative threshold voltage shifts under positive bias stress in input/output (I/O) TiN/HfO{sub 2} n-channel metal-oxide-semiconductor field-effect transistors using fast I-V measurement. This phenomenon is attributed to a reversible charge/discharge effect in pre-existing bulk traps. Moreover, in standard performance devices, threshold-voltage (V{sub t}) shifts positively during fast I-V double sweep measurement. However, in I/O devices, V{sub t} shifts negatively since electrons escape from bulk traps to metal gate rather than channel electrons injecting to bulk traps. Consequently, decreasing pre-existing bulk traps in I/O devices, which can be achieved by adopting Hf{sub x}Zr{sub 1?x}O{sub 2} as gate oxide, can reduce the charge/discharge effect.

Ho, Szu-Han; Chen, Ching-En; Tseng, Tseung-Yuen [Department of Electronics Engineering, National Chiao Tung University, Hsinchu 300, Taiwan (China); Chang, Ting-Chang, E-mail: tcchang@mail.phys.nsysu.edu.tw; Lu, Ying-Hsin; Tsai, Jyun-Yu; Liu, Kuan-Ju [Department of Physics, National Sun Yat-Sen University, Kaohsiung 804, Taiwan (China); Cheng, Osbert; Huang, Cheng-Tung; Lu, Ching-Sen [Device Department, United Microelectronics Corporation, Tainan Science Park, Taiwan (China)

2014-03-17T23:59:59.000Z

77

Charge Noise in Graphene Transistors Iddo Heller,,  

E-Print Network [OSTI]

Charge Noise in Graphene Transistors Iddo Heller,,§ Sohail Chatoor, Jaan Ma¨nnik, Marcel A. G an experimental study of 1/f noise in liquid-gated graphene transistors. We show that the gate dependence to the graphene, while at high carrier density it is consistent with noise due to scattering in the channel

Dekker, Cees

78

Improvement of current-control induced by oxide crenel in very short field-effect-transistor  

E-Print Network [OSTI]

cedex 13, France 2 Device Modelling Group, Department of Electronics and Electrical Engineering (~ 80 %) results from the thermionic electrons whose energy is higher than the source-drain barrier. 2 for a DG MOSFET with a gate length LG = 7 nm, a silicon thickness TSi = 2 nm and a gate

Paris-Sud XI, Université de

79

E-Print Network 3.0 - aluminum oxide gate Sample Search Results  

Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

2 Charge Trapping Characteristics of SONOS Capacitors with Control Gates of Different Work Functions during ProgramErase Operations Summary: ABSTRACT The control gate...

80

Gate Metal-Induced Diffusion and Interface Reactions in Hf Oxide Films on Si  

SciTech Connect (OSTI)

When metal electrodes are deposited on a high-{kappa} metal-oxide/SiO{sub 2}/Si stack, chemical interactions may occur both at the metal/high-{kappa} and the high-{kappa}/Si interfaces, causing changes in electrical performance. We report here results from medium energy ion scattering (MEIS) and x-ray photoelectron (XPS) studies of oxygen and silicon transport and interfacial layer reactions in multilayer gate stacks. Our results show that Ti deposition on HfO{sub 2}/SiO{sub 2}/Si stacks causes reduction of the SiO{sub 2} interfacial layer and (to a lesser extent) the HfO{sub 2} layer. Silicon atoms initially present in the interfacial SiO{sub 2} layer incorporate into the bottom of the high-{kappa} layer. Some evidence for titanium-silicon interdiffusion through the high-{kappa} film in the presence of a titanium gate in crystalline HfO{sub 2} films is also reported.

Goncharova, Lyudmila V.; Dalponte, Mateus; Celik, Ozgur; Garfunkel, Eric; Gustafsson, Torgny [Departments of Physics and Chemistry, and Laboratory for Surface Modification, Rutgers University, Piscataway, NJ 08854 (United States); Lysaght, Pat S.; Bersuker, Gennadi I. [Sematech, Austin, Texas 78741 (United States)

2007-09-26T23:59:59.000Z

Note: This page contains sample records for the topic "transistor gate oxide" from the National Library of EnergyBeta (NLEBeta).
While these samples are representative of the content of NLEBeta,
they are not comprehensive nor are they the most current set.
We encourage you to perform a real-time search of NLEBeta
to obtain the most current and comprehensive results.


81

Abstract--Bias temperature instability, hot-carrier injection, and gate-oxide wearout will cause severe lifetime degradation in  

E-Print Network [OSTI]

Abstract--Bias temperature instability, hot-carrier injection, and gate-oxide wearout will cause mechanisms are bias temperature instability (BTI) [1] and hot-carrier injection (HCI) [2], both of which can is compounded by thermal feedback, since active devices located at die hot spots operate at an elevated

Lipasti, Mikko H.

82

Enhanced stability against bias-stress of metal-oxide thin film transistors deposited at elevated temperatures  

SciTech Connect (OSTI)

Transparent zinc-tin-oxide (ZTO) thin film transistors (TFTs) have been prepared by DC magnetron sputtering. Compared to reference devices with a channel deposited at room temperature and subsequently annealing at 400 deg. C, a substantially enhanced stability against bias stress is evidenced for devices with in-situ substrate heating during deposition (400 deg. C). A reduced density of sub-gap defect states in TFT channels prepared with in-situ substrate heating is found. Concomitantly, a reduced sensitivity to the adsorption of ambient gases is evidenced for the in-situ heated devices. This finding is of particular importance for an application as driver electronics for organic light emitting diode displays.

Fakhri, M.; Goerrn, P.; Riedl, T. [Institute of Electronic Devices, University of Wuppertal, Rainer-Gruenter-St. 21, 42119 Wuppertal (Germany); Weimann, T.; Hinze, P. [Physikalisch-Technische Bundesanstalt Braunschweig, Bundesallee 100, 38116 Braunschweig (Germany)

2011-09-19T23:59:59.000Z

83

Method for double-sided processing of thin film transistors  

DOE Patents [OSTI]

This invention provides methods for fabricating thin film electronic devices with both front- and backside processing capabilities. Using these methods, high temperature processing steps may be carried out during both frontside and backside processing. The methods are well-suited for fabricating back-gate and double-gate field effect transistors, double-sided bipolar transistors and 3D integrated circuits.

Yuan, Hao-Chih (Madison, WI); Wang, Guogong (Madison, WI); Eriksson, Mark A. (Madison, WI); Evans, Paul G. (Madison, WI); Lagally, Max G. (Madison, WI); Ma, Zhenqiang (Middleton, WI)

2008-04-08T23:59:59.000Z

84

Nanocrystals Embedded Zirconium-doped Hafnium Oxide High-k Gate Dielectric Films  

E-Print Network [OSTI]

nanoparticles. These results can be important to the novel metal gate/high-k/Si MOS structure. The Ru-modified ZrHfO gate dielectric film showed a large breakdown voltage and a long lifetime. The conventional polycrystalline Si (poly-Si) charge trapping layer...

Lin, Chen-Han

2012-10-19T23:59:59.000Z

85

Low temperature lithographically patterned metal oxide transistors for large area electronics  

E-Print Network [OSTI]

Optically transparent, wide bandgap metal oxide semiconductors are a promising candidate for large-area electronics technologies that require lightweight, temperature-sensitive flexible substrates. Because these thin films ...

Wang, Annie I. (Annie I-Jen), 1981-

2011-01-01T23:59:59.000Z

86

Electrodynamic model of the field effect transistor application for THz/subTHz radiation detection: Subthreshold and above threshold operation  

SciTech Connect (OSTI)

Developed in this work is an electrodynamic model of field effect transistor (FET) application for THz/subTHz radiation detection. It is based on solution of the Maxwell equations in the gate dielectric, expression for current in the channel, which takes into account both the drift and diffusion current components, and the equation of current continuity. For the regimes under and above threshold at the strong inversion the response voltage, responsivity, wave impedance, power of ohmic loss in the gate and channel have been found, and the electrical noise equivalent power (ENEP) has been estimated. The responsivity is orders of magnitude higher and ENEP under threshold is orders of magnitude less than these values above threshold. Under the threshold, the electromagnetic field in the gate oxide is identical to field of the plane waves in free-space. At the same time, for strong inversion the charging of the gate capacitance through the resistance of channel determines the electric field in oxide.

Dobrovolsky, V., E-mail: vdobrovolsky@voliacable.com [Institute of Semiconductor Physics, Nauki Av., 41, Kiev 03028 (Ukraine)

2014-10-21T23:59:59.000Z

87

Gate potential control of nanofluidic devices  

E-Print Network [OSTI]

The effect of an external gate potential control on the nanofluidic nanochannels was experimentally investigated in this work. Like in the field effect transistors (FET) in microelectronics, molecular transport in ...

Le Coguic, Arnaud

2005-01-01T23:59:59.000Z

88

On the origin of the two-dimensional electron gas at AlGaN/GaN heterojunctions and its influence on recessed-gate metal-insulator-semiconductor high electron mobility transistors  

SciTech Connect (OSTI)

It is commonly accepted that interface states at the passivation surface of AlGaN/GaN heterostructures play an important role in the formation of the 2DEG density. Several interface state models are cited throughout literature, some with discrete levels, others with different kinds of distributions, or a combination of both. The purpose of this article is to compare the existing interface state models with both direct and indirect measurements of these interface states from literature (e.g., through the hysteresis of transfer characteristics of Metal-Insulator-Semiconductor High Electron Mobility Transistors (MISHEMTs) employing such an interface in the gate region) and Technology Computer Aided Design (TCAD) simulations of 2DEG densities as a function of the AlGaN thickness. The discrepancies between those measurements and TCAD simulations (also those commonly found in literature) are discussed. Then, an alternative model inspired by the Disorder Induced Gap State model for compound semiconductors is proposed. It is shown that defining a deep border trap inside the insulator can solve these discrepancies and that this alternative model can explain the origin of the two dimensional electron gas in combination with a high-quality interface that, by definition, has a low interface state density.

Bakeroot, B., E-mail: Benoit.Bakeroot@elis.ugent.be [Centre for Microsystems Technology (CMST), imec and Ghent University, Technologiepark 914a, 9052 Gent (Belgium); You, S.; Van Hove, M.; De Jaeger, B.; Geens, K.; Stoffels, S.; Decoutere, S. [imec, Kapeldreef 75, 3001 Leuven (Belgium); Wu, T.-L.; Hu, J. [imec, Kapeldreef 75, 3001 Leuven (Belgium); Department of Electrical Engineering, KU Leuven, 3001 Leuven (Belgium)

2014-10-07T23:59:59.000Z

89

Photoemission spectroscopy study of the lanthanum lutetium oxide/silicon interface  

SciTech Connect (OSTI)

Rare earth oxides are promising candidates for future integration into nano-electronics. A key property of these oxides is their ability to form silicates in order to replace the interfacial layer in Si-based complementary metal-oxide field effect transistors. In this work a detailed study of lanthanum lutetium oxide based gate stacks is presented. Special attention is given to the silicate formation at temperatures typical for CMOS processing. The experimental analysis is based on hard x-ray photoemission spectroscopy complemented by standard laboratory experiments as Rutherford backscattering spectrometry and high-resolution transmission electron microscopy. Homogenously distributed La silicate and Lu silicate at the Si interface are proven to form already during gate oxide deposition. During the thermal treatment Si atoms diffuse through the oxide layer towards the TiN metal gate. This mechanism is identified to be promoted via Lu-O bonds, whereby the diffusion of La was found to be less important.

Nichau, A.; Schnee, M.; Schubert, J.; Bernardy, P.; Hollaender, B.; Buca, D.; Mantl, S. [Peter Gruenberg Institute 9 (PGI9-IT), Forschungszentrum Juelich, 52425 Juelich (Germany); JARA-Fundamentals of Future Information Technologies, 52425 Juelich (Germany); Besmehn, A.; Breuer, U. [Central Division for Chemical Analysis (ZCH), Forschungszentrum Juelich, 52425 Juelich (Germany); Rubio-Zuazo, J.; Castro, G. R. [Spanish CRG BM25 Beamline-SpLine, European Synchrotron Radiation Facility (ESRF), Rue Jules Horowitz BP 220, F-38043 Grenoble, Cedex 09 (France); Muecklich, A.; Borany, J. von [Institute of Ion Beam Physics and Materials Research, Helmholtz-Zentrum' Dresden-Rossendorf e.V., 01314 Dresden (Germany)

2013-04-21T23:59:59.000Z

90

Zirconium-doped tantalum oxide high-k gate dielectric films  

E-Print Network [OSTI]

A new high-k dielectric material, i.e., zirconium-doped tantalum oxide (Zr-doped TaOx), in the form of a sputter-deposited thin film with a thickness range of 5-100 nm, has been studied. Important applications of this new dielectric material include...

Tewg, Jun-Yen

2005-02-17T23:59:59.000Z

91

Single Carbon Nanotube Transistor at GHz Frequency  

E-Print Network [OSTI]

with a capacitance per unit gate length of lg, Cgeo/lg > CQ/lg ) 4e2/hVF 400 aF/µm for VF 4 � 105 m/s, a typical or semicon- ducting quantum dots use either single electron transistors15,16 or quantum point contact

Plaçais, Bernard

92

COOPER PAIR TRANSISTOR IN A TUNABLE ENVIRONMENT  

E-Print Network [OSTI]

COOPER PAIR TRANSISTOR IN A TUNABLE ENVIRONMENT S. Corlevi, W. Guichard, and D. B. Haviland* 1 measurements of the CPT, which are performed in a low impedance environment, the charging effects are observed as gate voltage modulation of the critical current. However, in a high impedance environment, a Coulomb

Haviland, David

93

On the electrical stress-induced oxide-trapped charges in thin HfO{sub 2}/SiO{sub 2} gate dielectric stack  

SciTech Connect (OSTI)

Oxide charge buildup and its generation kinetics during constant voltage stress in TaN/HfO{sub 2}/SiO{sub 2}/p-Si structures have been experimentally investigated. From the oxide charge relaxation experiments, nature and energy location of the as-fabricated intrinsic hole traps in the gate stack have also been determined. Our measurement results indicate that the dispersive proton transport through the interfacial SiO{sub 2} contributes larger than hole trapping in positive charge buildup in the stack. From the bias temperature stress measurement results in both control oxide and HfO{sub 2}/SiO{sub 2} stacks, we have identified overcoordinated [Si{sub 2}=OH]{sup +} centers as the proton-induced defects located in the interfacial SiO{sub 2} layer of the stack. Finally, an empirical equation is proposed to explain the stress-induced oxide positive charge buildup.

Samanta, Piyas; Zhu Chunxiang; Chan, Mansun [Department of Electronic and Computer Engineering, The Hong Kong University of Science and Technology, Clear Water Bay Road, Kowloon, Hong Kong (China); Department of Electrical and Computer Engineering, National University of Singapore, 10 Kent Ridge Crescent, Singapore 119260 (Singapore); Department of Electronic and Computer Engineering, The Hong Kong University of Science and Technology, Clear Water Bay Road, Kowloon, Hong Kong (China)

2007-09-10T23:59:59.000Z

94

Chemical Bonding, Interfaces and Defects in Hafnium Oxide/Germanium Oxynitride Gate Stacks on Ge (100)  

SciTech Connect (OSTI)

Correlations among interface properties and chemical bonding characteristics in HfO{sub 2}/GeO{sub x}N{sub y}/Ge MIS stacks were investigated using in-situ remote nitridation of the Ge (100) surface prior to HfO{sub 2} atomic layer deposition (ALD). Ultra thin ({approx}1.1 nm), thermally stable and aqueous etch-resistant GeO{sub x}N{sub y} interfaces layers that exhibited Ge core level photoelectron spectra (PES) similar to stoichiometric Ge{sub 3}N{sub 4} were synthesized. To evaluate GeO{sub x}N{sub y}/Ge interface defects, the density of interface states (D{sub it}) was extracted by the conductance method across the band gap. Forming gas annealed (FGA) samples exhibited substantially lower D{sub it} ({approx} 1 x 10{sup 12} cm{sup -2} eV{sup -1}) than did high vacuum annealed (HVA) and inert gas anneal (IGA) samples ({approx} 1x 10{sup 13} cm{sup -2} eV{sup -1}). Germanium core level photoelectron spectra from similar FGA-treated samples detected out-diffusion of germanium oxide to the HfO{sub 2} film surface and apparent modification of chemical bonding at the GeO{sub x}N{sub y}/Ge interface, which is related to the reduced D{sub it}.

Oshima, Yasuhiro; /Stanford U., Materials Sci. Dept.; Sun, Yun; /SLAC, SSRL; Kuzum, Duygu; /Stanford U.; Sugawara, Takuya; Saraswat, Krishna C.; Pianetta, Piero; /SLAC, SSRL; McIntyre, Paul C.; /Stanford U., Materials Sci. Dept.

2008-10-31T23:59:59.000Z

95

C-H surface diamond field effect transistors for high temperature (400?°C) and high voltage (500?V) operation  

SciTech Connect (OSTI)

By forming a highly stable Al{sub 2}O{sub 3} gate oxide on a C-H bonded channel of diamond, high-temperature, and high-voltage metal-oxide-semiconductor field-effect transistor (MOSFET) has been realized. From room temperature to 400?°C (673?K), the variation of maximum drain-current is within 30% at a given gate bias. The maximum breakdown voltage (V{sub B}) of the MOSFET without a field plate is 600?V at a gate-drain distance (L{sub GD}) of 7 ?m. We fabricated some MOSFETs for which V{sub B}/L{sub GD}?>?100?V/?m. These values are comparable to those of lateral SiC or GaN FETs. The Al{sub 2}O{sub 3} was deposited on the C-H surface by atomic layer deposition (ALD) at 450?°C using H{sub 2}O as an oxidant. The ALD at relatively high temperature results in stable p-type conduction and FET operation at 400?°C in vacuum. The drain current density and transconductance normalized by the gate width are almost constant from room temperature to 400?°C in vacuum and are about 10 times higher than those of boron-doped diamond FETs.

Kawarada, H., E-mail: kawarada@waseda.jp [Faculty of Science and Engineering, Waseda University, Shinjuku, Tokyo 169-8555 (Japan); Institute of Nano-Science and Nano-Engineering, Waseda University, Shinjuku, Tokyo 169-8555 (Japan); Kagami Memorial Laboratory for Material Science and Technology, Waseda University, Shinjuku, Tokyo 169-0051 (Japan); Tsuboi, H.; Naruo, T.; Yamada, T.; Xu, D.; Daicho, A.; Saito, T. [Faculty of Science and Engineering, Waseda University, Shinjuku, Tokyo 169-8555 (Japan); Hiraiwa, A. [Institute of Nano-Science and Nano-Engineering, Waseda University, Shinjuku, Tokyo 169-8555 (Japan)

2014-07-07T23:59:59.000Z

96

High-performance self-aligned inversion-channel In{sub 0.53}Ga{sub 0.47}As metal-oxide-semiconductor field-effect-transistors by in-situ atomic-layer-deposited HfO{sub 2}  

SciTech Connect (OSTI)

Self-aligned inversion-channel In{sub 0.53}Ga{sub 0.47}As metal-oxide-semiconductor field-effect-transistors (MOSFETs) have been fabricated using the gate dielectrics of in-situ directly atomic-layer-deposited (ALD) HfO{sub 2} followed by ALD-Al{sub 2}O{sub 3}. There were no surface pretreatments and no interfacial passivation/barrier layers prior to the ALD. TiN/Al{sub 2}O{sub 3} (4?nm)/HfO{sub 2} (1?nm)/In{sub 0.53}Ga{sub 0.47}As/InP MOS capacitors exhibited well-behaved capacitance-voltage characteristics with true inversion behavior, low leakage current densities of ?10{sup ?8}?A/cm{sup 2} at ±1?MV/cm, and thermodynamic stability at high temperatures. Al{sub 2}O{sub 3} (3?nm)/HfO{sub 2} (1?nm)/In{sub 0.53}Ga{sub 0.47}As MOSFETs of 1 ?m gate length, with 700?°C–800?°C rapid thermal annealing in source/drain activation, have exhibited high extrinsic drain current (I{sub D}) of 1.5?mA/?m, transconductance (G{sub m}) of 0.84 mS/?m, I{sub ON}/I{sub OFF} of ?10{sup 4}, low sub-threshold swing of 103?mV/decade, and field-effect electron mobility of 1100 cm{sup 2}/V?·?s. The devices have also achieved very high intrinsic I{sub D} and G{sub m} of 2?mA/?m and 1.2?mS/?m, respectively.

Lin, T. D.; Chang, W. H.; Chang, Y. C.; Hong, M., E-mail: raynien@phys.nthu.edu.tw, E-mail: mhong@phys.ntu.edu.tw [Graduate Institute of Applied Physics and Department of Physics, National Taiwan University, Taipei 10617, Taiwan (China); Chu, R. L.; Chang, Y. H. [Department of Materials Science and Engineering, National Tsing Hua University, Hsinchu 30013, Taiwan (China)] [Department of Materials Science and Engineering, National Tsing Hua University, Hsinchu 30013, Taiwan (China); Lee, M. Y.; Hong, P. F.; Chen, Min-Cheng [National Nano Device Laboratories, Hsinchu 30076, Taiwan (China)] [National Nano Device Laboratories, Hsinchu 30076, Taiwan (China); Kwo, J., E-mail: raynien@phys.nthu.edu.tw, E-mail: mhong@phys.ntu.edu.tw [Department of Physics, National Tsing Hua University, Hsinchu 30013, Taiwan (China)

2013-12-16T23:59:59.000Z

97

Femtosecond all-optical parallel logic gates based on tunable saturable to reverse saturable absorption in graphene-oxide thin films  

SciTech Connect (OSTI)

A detailed theoretical analysis of ultrafast transition from saturable absorption (SA) to reverse saturable absorption (RSA) has been presented in graphene-oxide thin films with femtosecond laser pulses at 800?nm. Increase in pulse intensity leads to switching from SA to RSA with increased contrast due to two-photon absorption induced excited-state absorption. Theoretical results are in good agreement with reported experimental results. Interestingly, it is also shown that increase in concentration results in RSA to SA transition. The switching has been optimized to design parallel all-optical femtosecond NOT, AND, OR, XOR, and the universal NAND and NOR logic gates.

Roy, Sukhdev, E-mail: sukhdevroy@dei.ac.in; Yadav, Chandresh [Department of Physics and Computer Science, Dayalbagh Educational Institute, Dayalbagh, Agra 282 005 (India)] [Department of Physics and Computer Science, Dayalbagh Educational Institute, Dayalbagh, Agra 282 005 (India)

2013-12-09T23:59:59.000Z

98

Positive bias temperature instability in p-type metal-oxide-semiconductor devices with HfSiON/SiO{sub 2} gate dielectrics  

SciTech Connect (OSTI)

We present a detailed investigation on positive-bias temperature stress (PBTS) induced degradation of nitrided hafnium silicate (HfSiON)/SiO{sub 2} gate stack in n{sup +}-poly crystalline silicon (polySi) gate p-type metal-oxide-semiconductor (pMOS) devices. The measurement results indicate that gate dielectric degradation is a composite effect of electron trapping in as-fabricated as well as newly generated neutral traps, resulting a significant amount of stress-induced leakage current and generation of surface states at the Si/SiO{sub 2} interface. Although, a significant amount of interface states are created during PBTS, the threshold voltage (V{sub T}) instability of the HfSiON based pMOS devices is primarily caused by electron trapping and detrapping. It is also shown that PBTS creates both acceptor- and donor-like interface traps via different depassivation mechanisms of the Si{sub 3}???SiH bonds at the Si/SiO{sub 2} interface in pMOS devices. However, the number of donor-like interface traps ?N{sub it}{sup D} is significantly greater than that of acceptor-like interface traps ?N{sup A}{sub it}, resulting the PBTS induced net interface traps as donor-like.

Samanta, Piyas, E-mail: piyas@vcfw.org [Department of Physics, Vidyasagar College for Women, 39 Sankar Ghosh Lane, Kolkata 700 006 (India); Huang, Heng-Sheng; Chen, Shuang-Yuan [Institute of Mechatronic Engineering, National Taipei University of Technology, No. 1, Sec. 3, Chung-Hsiao E. Rd., Taipei 106, Taiwan (China); Liu, Chuan-Hsi [Department of Mechatronic Technology, National Taiwan Normal University, No. 162, Sec. 1, He-Ping E. Rd., Taipei 106, Taiwan (China); Cheng, Li-Wei [Central R and D Division, United Microelectronics Corporation, No. 3, Li-Hsin Rd. II, Hsinchu 300, Taiwan (China)

2014-02-21T23:59:59.000Z

99

Integration of pentacene-based thin film transistors via photolithography for low and high voltage applications  

E-Print Network [OSTI]

An organic thin film transistor (OTFT) technology platform has been developed for flexible integrated circuits applications. OTFT performance is tuned by engineering the dielectric constant of the gate insulator and the ...

Smith, Melissa Alyson

2012-01-01T23:59:59.000Z

100

Sample size requirements for estimating effective dose from computed tomography using solid-state metal-oxide-semiconductor field-effect transistor dosimetry  

SciTech Connect (OSTI)

Purpose: Effective dose (ED) is a widely used metric for comparing ionizing radiation burden between different imaging modalities, scanners, and scan protocols. In computed tomography (CT), ED can be estimated by performing scans on an anthropomorphic phantom in which metal-oxide-semiconductor field-effect transistor (MOSFET) solid-state dosimeters have been placed to enable organ dose measurements. Here a statistical framework is established to determine the sample size (number of scans) needed for estimating ED to a desired precision and confidence, for a particular scanner and scan protocol, subject to practical limitations. Methods: The statistical scheme involves solving equations which minimize the sample size required for estimating ED to desired precision and confidence. It is subject to a constrained variation of the estimated ED and solved using the Lagrange multiplier method. The scheme incorporates measurement variation introduced both by MOSFET calibration, and by variation in MOSFET readings between repeated CT scans. Sample size requirements are illustrated on cardiac, chest, and abdomen–pelvis CT scans performed on a 320-row scanner and chest CT performed on a 16-row scanner. Results: Sample sizes for estimating ED vary considerably between scanners and protocols. Sample size increases as the required precision or confidence is higher and also as the anticipated ED is lower. For example, for a helical chest protocol, for 95% confidence and 5% precision for the ED, 30 measurements are required on the 320-row scanner and 11 on the 16-row scanner when the anticipated ED is 4 mSv; these sample sizes are 5 and 2, respectively, when the anticipated ED is 10 mSv. Conclusions: Applying the suggested scheme, it was found that even at modest sample sizes, it is feasible to estimate ED with high precision and a high degree of confidence. As CT technology develops enabling ED to be lowered, more MOSFET measurements are needed to estimate ED with the same precision and confidence.

Trattner, Sigal [Department of Medicine, Division of Cardiology, Columbia University Medical Center and New York-Presbyterian Hospital, New York, New York 10032 (United States)] [Department of Medicine, Division of Cardiology, Columbia University Medical Center and New York-Presbyterian Hospital, New York, New York 10032 (United States); Cheng, Bin [Department of Biostatistics, Columbia University Mailman School of Public Health, New York, New York 10032 (United States)] [Department of Biostatistics, Columbia University Mailman School of Public Health, New York, New York 10032 (United States); Pieniazek, Radoslaw L. [Center for Radiological Research, Columbia University Medical Center and New York-Presbyterian Hospital, New York, New York 10032 (United States)] [Center for Radiological Research, Columbia University Medical Center and New York-Presbyterian Hospital, New York, New York 10032 (United States); Hoffmann, Udo [Department of Radiology, Massachusetts General Hospital and Harvard Medical School, Boston, Massachusetts 02114 (United States)] [Department of Radiology, Massachusetts General Hospital and Harvard Medical School, Boston, Massachusetts 02114 (United States); Douglas, Pamela S. [Department of Medicine, Division of Cardiology, Duke University, Durham, North Carolina 27715 (United States)] [Department of Medicine, Division of Cardiology, Duke University, Durham, North Carolina 27715 (United States); Einstein, Andrew J., E-mail: andrew.einstein@columbia.edu [Department of Medicine, Division of Cardiology, Columbia University Medical Center and New York-Presbyterian Hospital, New York, New York and Department of Radiology, Columbia University Medical Center and New York-Presbyterian Hospital, New York, New York (United States)

2014-04-15T23:59:59.000Z

Note: This page contains sample records for the topic "transistor gate oxide" from the National Library of EnergyBeta (NLEBeta).
While these samples are representative of the content of NLEBeta,
they are not comprehensive nor are they the most current set.
We encourage you to perform a real-time search of NLEBeta
to obtain the most current and comprehensive results.


101

A methodology to identify and quantify mobility-reducing defects in 4H-silicon carbide power metal-oxide-semiconductor field-effect transistors  

SciTech Connect (OSTI)

In this paper, we present a methodology for the identification and quantification of defects responsible for low channel mobility in 4H-Silicon Carbide (SiC) power metal-oxide-semiconductor field-effect transistors (MOSFETs). To achieve this, we use an algorithm based on 2D-device simulations of a power MOSFET, density functional simulations, and measurement data. Using physical modeling of carrier mobility and interface traps, we reproduce the experimental I-V characteristics of a 4H-SiC doubly implanted MOSFET through drift-diffusion simulation. We extract the position of Fermi level and the occupied trap density as a function of applied bias and temperature. Using these inputs, our algorithm estimates the number of possible trap types, their energy levels, and concentrations at 4H-SiC/SiO{sub 2} interface. Subsequently, we use density functional theory (DFT)-based ab initio simulations to identify the atomic make-up of defects causing these trap levels. We study silicon vacancy and carbon di-interstitial defects in the SiC side of the interface. Our algorithm indicates that the D{sub it} spectrum near the conduction band edge (3.25?eV) is composed of three trap types located at 2.8–2.85?eV, 3.05?eV, and 3.1–3.2?eV, and also calculates their densities. Based on DFT simulations, this work attributes the trap levels very close to the conduction band edge to the C di-interstitial defect.

Ettisserry, D. P., E-mail: deva@umd.edu; Goldsman, N. [Department of Electrical and Computer Engineering, University of Maryland, College Park, Maryland 20742 (United States); Lelis, A. [U.S. Army Research Laboratory, 2800 Powder Mill Road, Adelphi, Maryland 20783 (United States)

2014-03-14T23:59:59.000Z

102

All diamond self-aligned thin film transistor  

DOE Patents [OSTI]

A substantially all diamond transistor with an electrically insulating substrate, an electrically conductive diamond layer on the substrate, and a source and a drain contact on the electrically conductive diamond layer. An electrically insulating diamond layer is in contact with the electrically conductive diamond layer, and a gate contact is on the electrically insulating diamond layer. The diamond layers may be homoepitaxial, polycrystalline, nanocrystalline or ultrananocrystalline in various combinations.A method of making a substantially all diamond self-aligned gate transistor is disclosed in which seeding and patterning can be avoided or minimized, if desired.

Gerbi, Jennifer (Champaign, IL)

2008-07-01T23:59:59.000Z

103

Electrical gating effects on the magnetic properties of (Ga,Mn)As diluted magnetic semiconductors  

E-Print Network [OSTI]

-effect transistor (FET) based on low-doped Ga0.975Mn0.025As was fabricated. It has an in-built n-GaAs back-gate, which, in addition to being a normal gate, enhances the gating effects, especially in the depletion of the epilayer, by decreasing the effective channel...

Owen, Man Hon Samuel

2010-11-16T23:59:59.000Z

104

A thermalization energy analysis of the threshold voltage shift in amorphous indium gallium zinc oxide thin film transistors under simultaneous negative gate bias and illumination  

E-Print Network [OSTI]

of the display industry as it moves from liquid crystal to organic light emitting diode technology and with requirements for larger areas and higher resolutions. A number of alternative material systems to a-Si:H have emerged, including organic semiconductors...

Flewitt, Andrew J.; Powell, M.J.

2014-01-01T23:59:59.000Z

105

Synthesis and charge-transport properties of polymers derived from the oxidation of 1-hydro-1'-(6-(pyrrol-1-yl)hexyl)-4,4'-bipyridium Bis(hexafluorophosphate) and demonstration of pH-sensitive microelectrochemical transistor derived from the redox properties of a conventional redox center  

SciTech Connect (OSTI)

This article describes the synthesis and electrochemical properties of redox polymers, having a polypyrrole backbone and viologen subunits, derived from oxidative electropolymerization of 1-methyl-1'-(6-(pyrrol-1-yl)hexyl)-4,4'-bipyridinium (P-V-Me/sup 2 +/) and 1-hydro-1'-(6-(pyrrol-1-yl)hexyl)-4,4'-bipyridinium (P-V-H/sup 2 +/). Closely spaced (approx. 1.5 ..mu..M) Au microelectrode arrays (approx. 2.5 ..mu..m wide /times/ 50 ..mu..m long /times/ 0.1 ..mu..m high) modified with the polymers can be used to study aspects of the charge-transport behavior of the viologen redox system. Poly(P-V-Me/sup 2 +/) have been used to investigate the characteristics of microelectrochemical transistors based on a viologen redox center and a similar redox center, protonated, monoquaternized bipyridinium, which is pH dependent. The interesting properties from poly(P-V-Me/sup 2 +/) and poly(P-V-H/sup 2 +/) stem from behavior of the pendant viologen redox centers. The device based on poly(P-V-Me/sup 2 +/) has a narrow region (approx. 200 mV) of gate voltage, V/sub G/, where the source-drain current, I/sub D/, is nonzero and has a sharp, pH-independent peak in the I/sub D/-V/sub G/ plot at approx. 0.53 V versus SCE associated with the reversible, one-electron reduction of viologen. This result is consistent with electron self-exchange between redox centers being the mechanism for charge transport. The device based on poly(P-V-H/sup 2 +/) shows a pH-dependent I/sub D/ at fixed V/sub G/, as expected from the electrochemical behavior from reversible protonation of the terminal N of the bipyridinium group of poly(P-V-H/sup 2 +/). The microelectrochemical transistor based on poly(P-V-H/sup 2 +/) illustrates the design of chemically sensitive, molecule-based devices using conventional redox materials.

Shu, C.F.; Wrighton, M.S.

1988-09-08T23:59:59.000Z

106

Single hole quantum dot transistors in silicon Effendi Leobandung, Lingjie Guo, and Stephen Y. Choua)  

E-Print Network [OSTI]

of the gate voltage have been observed at temperatures over 81 K and drain biases over 66 mV. The oscillations to the drain. As the gate voltage was scanned, the drain current i.e., the hole current oscil- lated Fig. 3-dot transistors were fabricated in silicon-on-insulator. Strong oscillations in the drain current as a function

107

Convex Delay Models for Transistor Sizing Mahesh Ketkar  

E-Print Network [OSTI]

for developing accurate con- vex delay models to be used for transistor sizing. A new rich class of convex]: minimize Area or Power subject to Delay Tspec: (1) There have been many significant attempts to solve. in the development of closed form models for inverters and then mapping other gates to an equivalent inverter [5, 6

Sapatnekar, Sachin

108

Bounding the total-dose response of modern bipolar transistors  

SciTech Connect (OSTI)

The base current in modern bipolar transistors saturates at large total doses once a critical oxide charge is reached. The saturated value of base current is dose-rate independent. Testing implications are discussed.

Kosier, S.L.; Wei, A.; Schrimpf, R.D. [Arizona Univ., Tucson, AZ (United States). Dept. of Electrical and Computer Engineering; Combs, W.E. [Naval Surface Warfare Center-Crane, Crane, IN (United States); Fleetwood, D.M. [Sandia National Labs., Albuquerque, NM (United States); DeLaus, M. [Analog Devices, Inc., Wilmington, MA (United States); Pease, R.L. [RLP Research, Albuquerque, NM (United States)

1994-03-01T23:59:59.000Z

109

Atomistic full-band simulations of monolayer MoS{sub 2} transistors  

SciTech Connect (OSTI)

We study the transport properties of deeply scaled monolayer MoS{sub 2} n-channel metal-oxide-semiconductor field effect transistors (MOSFETs), using full-band ballistic quantum transport simulations, with an atomistic tight-binding Hamiltonian obtained from density functional theory. Our simulations suggest that monolayer MoS{sub 2} MOSFETs can provide near-ideal subthreshold slope, suppression of drain-induced barrier lowering, and gate-induced drain leakage. However, these full-band simulations exhibit limited transconductance. These ballistic simulations also exhibit negative differential resistance (NDR) in the output characteristics associated with the narrow width in energy of the lowest conduction band, but this NDR may be substantially reduced or eliminated by scattering in MoS{sub 2}.

Chang, Jiwon; Register, Leonard F.; Banerjee, Sanjay K. [Microelectronics Research Center, The University of Texas at Austin, Austin, Texas 78758 (United States)] [Microelectronics Research Center, The University of Texas at Austin, Austin, Texas 78758 (United States)

2013-11-25T23:59:59.000Z

110

Detection of terahertz radiation by tightly concatenated InGaAs field-effect transistors integrated on a single chip  

SciTech Connect (OSTI)

A tightly concatenated chain of InGaAs field-effect transistors with an asymmetric T-gate in each transistor demonstrates strong terahertz photovoltaic response without using supplementary antenna elements. We obtain the responsivity above 1000?V/W and up to 2000?V/W for unbiased and drain-biased transistors in the chain, respectively, with the noise equivalent power below 10{sup ?11} W/Hz{sup 0.5} in the unbiased mode of the detector operation.

Popov, V. V., E-mail: popov-slava@yahoo.co.uk [Kotelnikov Institute of Radio Engineering and Electronics (Saratov Branch), Russian Academy of Sciences, Saratov 410019 (Russian Federation); Yermolaev, D. M.; Shapoval, S. Yu. [Institute of Microelectronic Technology and High-Purity Materials, Russian Academy of Sciences, Chernogolovka, Moscow Region 142432 (Russian Federation); Maremyanin, K. V.; Gavrilenko, V. I. [Institute for Physics of Microstructures, Russian Academy of Sciences, Nizhny Novgorod 603950 (Russian Federation); Lobachevsky State University of Nizhni Novgorod, Nizhni Novgorod 603950 (Russian Federation); Zemlyakov, V. E.; Bespalov, V. A.; Yegorkin, V. I. [National Research University of Electronic Technology, Zelenograd, Moscow 124498 (Russian Federation); Maleev, N. A.; Ustinov, V. M. [Ioffe Physical Technical Institute, Russian Academy of Sciences, St. Petersburg 194021 (Russian Federation)

2014-04-21T23:59:59.000Z

111

Self-aligned submicron gate length gallium arsenide MESFET  

E-Print Network [OSTI]

-biaserl saturation currents of 396. 67 + 83. 984 IzA were obtained for the transistors. Built- in voltages of 0. 8198 6 0. 007 V and ideality factors of 1. 456 6 0. 0079 were obtained for the Schottky diodes. The effect of gate length on transcond ictance... Geometrical and physical origins for the small signal equivalent circuit of FET Developed fabrication process for submicron gate length GaAs MESFET Transistor and Schottky diode mask patterns 10 13 15 16 18 19 21 23 23 25 25 32 34 18. Process...

Huang, Hsien-Ching

2012-06-07T23:59:59.000Z

112

Controlled ambient and temperature treatment of InGaZnO thin film transistors for improved bias-illumination stress reliability  

SciTech Connect (OSTI)

The failure mechanisms arising from the instability in operation of indium gallium zinc oxide based thin film transistors (TFTs) upon prolonged real application stresses (bias and illumination) have been extensively studied and reported. Positive and negative gate bias conditions, along with high photonic energy wavelengths within visible light spectrum are used as stress conditions. The increased carrier concentration due to photonic excitation of defects within bandgap and ionization of deep level vacancies is compensated by the reduction in off currents under illumination due to the trapping of carriers in the intermetal dielectric. Band lowering at the source-channel junction due to accumulation of negative carriers repelled due to negative gate bias stress further causes high carrier flow into the channel and drives the devices into failure. The defect identification during failure and degradation assisted in proposing suitable low temperature post processing in specific ambients. Reliability tests after specific anneals in oxygen, vacuum, and forming gas ambients confirm the correlation of the defect type with anneal ambient. Annealed TFTs demonstrate high stabilities under illumination stresses and do not fail when subjected to combined stresses that cause failure in as-fabricated TFTs. Oxygen and forming gas anneals are impactful on the reliability and opens an area of study on donor and vacancy behavior in amorphous mixed oxide based TFTs. The subthreshold swing, field-effect mobilities, and off currents provide knowledge on best anneal practices by understanding role of hydrogen and oxygen in vacancy annihilation and transistor switching properties.

Vemuri, Rajitha N. P., E-mail: rvemuri@asu.edu [School for Engineering of Matter, Transport and Energy, Arizona State University, Tempe 85287 (United States); Hasin, Muhammad R. [School of Electrical, Computer and Energy Engineering, Arizona State University, Tempe 85287 (United States); Alford, T. L., E-mail: TA@asu.edu [School for Engineering of Matter, Transport and Energy, Arizona State University, Tempe 85287 and School of Electrical, Computer and Energy Engineering, Arizona State University, Tempe 85287 (United States)

2014-03-15T23:59:59.000Z

113

Probing Organic Transistors with Infrared Beams  

Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

Probing Organic Transistors with Infrared Beams Probing Organic Transistors with Infrared Beams Print Wednesday, 26 July 2006 00:00 Silicon-based transistors are well-understood,...

114

IEEE ELECTRON DEVICE LETTERS, VOL. 29, NO. 2, FEBRUARY 2008 183 Externally Assembled Gate-All-Around Carbon  

E-Print Network [OSTI]

-All-Around Carbon Nanotube Field-Effect Transistor Zhihong Chen, Member, IEEE, Damon Farmer, Sheng Xu, Roy Gordon USA (e-mail: zchen@us.ibm.com; avouris@ us.ibm.com). D. Farmer is with the School of Engineering demonstrate a gate-all-around single- wall carbon nanotube field-effect transistor. This is the first suc

115

Printed inorganic transistors  

E-Print Network [OSTI]

Forty years of exponential growth of semiconductor technology have been predicated on the miniaturization of the transistors that comprise integrated circuits. While complexity has greatly increased within a given area of ...

Ridley, Brent (Brent Alan), 1974-

2003-01-01T23:59:59.000Z

116

Method for formation of thin film transistors on plastic substrates  

DOE Patents [OSTI]

A process for formation of thin film transistors (TFTs) on plastic substrates replaces standard thin film transistor fabrication techniques, and uses sufficiently lower processing temperatures so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The process relies on techniques for depositing semiconductors, dielectrics, and metals at low temperatures; crystallizing and doping semiconductor layers in the TFT with a pulsed energy source; and creating top-gate self-aligned as well as back-gate TFT structures. The process enables the fabrication of amorphous and polycrystalline channel silicon TFTs at temperatures sufficiently low to prevent damage to plastic substrates. The process has use in large area low cost electronics, such as flat panel displays and portable electronics.

Carey, Paul G. (Mountain View, CA); Smith, Patrick M. (San Ramon, CA); Sigmon, Thomas W. (Portola Valley, CA); Aceves, Randy C. (Livermore, CA)

1998-10-06T23:59:59.000Z

117

Method for formation of thin film transistors on plastic substrates  

DOE Patents [OSTI]

A process for formation of thin film transistors (TFTs) on plastic substrates replaces standard thin film transistor fabrication techniques, and uses sufficiently lower processing temperatures so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The process relies on techniques for depositing semiconductors, dielectrics, and metals at low temperatures; crystallizing and doping semiconductor layers in the TFT with a pulsed energy source; and creating top-gate self-aligned as well as back-gate TFT structures. The process enables the fabrication of amorphous and polycrystalline channel silicon TFTs at temperatures sufficiently low to prevent damage to plastic substrates. The process has use in large area low cost electronics, such as flat panel displays and portable electronics. 5 figs.

Carey, P.G.; Smith, P.M.; Sigmon, T.W.; Aceves, R.C.

1998-10-06T23:59:59.000Z

118

Application of the FETMOS transistor as a quasi-analog storage element  

E-Print Network [OSTI]

Tuneable Reference Current Generator. . . . . . 39 D. l Bias Arrangement For Threshold Voltage Measurement. . . . . . 62 D. 2 Example of Ids vs Vgs Plot Used To Measure Threshold Voltage . . . . . . . . 62 CHAPTER I INTRODUCTION hang and Sze of... to channel length ratio as defined by the source/drain regions and the floating gate. Vos is the contml gate to source bias Vr is the apparent threshold voltage for the transistor, and Vns is the drain to source bias. Appendix C contains a cotnplete...

Sweeney, John Hillabrant

2012-06-07T23:59:59.000Z

119

p Channel thin lm transistor and complementary metaloxidesilicon inverter made of microcrystalline silicon  

E-Print Network [OSTI]

p Channel thin ®lm transistor and complementary metal±oxide±silicon inverter made ®lm transistor (TFT) made of directly deposited microcrystalline silicon (lc-Si). The lc-Si channel°C. By integrating this p TFT on a single lc-Si ®lm with an n channel TFT, we fabricated

120

Device and circuit-level models for carbon nanotube and graphene nanoribbon transistors  

E-Print Network [OSTI]

Metal-oxide semiconductor field-effect transistor (MOSFET) scaling throughout the years has enabled us to pack million of MOS transistors on a single chip to keep in pace with Moore’s Law. After forty years of advances in integrated circuit (IC...

Tan, Michael Loong Peng

2011-06-07T23:59:59.000Z

Note: This page contains sample records for the topic "transistor gate oxide" from the National Library of EnergyBeta (NLEBeta).
While these samples are representative of the content of NLEBeta,
they are not comprehensive nor are they the most current set.
We encourage you to perform a real-time search of NLEBeta
to obtain the most current and comprehensive results.


121

Computational study of heterojunction graphene nanoribbon tunneling transistors with p-d orbital tight-binding method  

SciTech Connect (OSTI)

The graphene nanoribbon (GNR) tunneling field effect transistor (TFET) has been a promising candidate for a future low power logic device due to its sub-60?mV/dec subthreshold characteristic and its superior gate control on the channel electrons due to its one-dimensional nature. Even though many theoretical studies have been carried out, it is not clear that GNR TFETs would outperform conventional silicon metal oxide semiconductor field effect transistors (MOSFETs). With rigorous atomistic simulations using the p/d orbital tight-binding model, this study focuses on the optimization of GNR TFETs by tuning the doping density and the size of GNRs. It is found that the optimized GNR TFET can operate at a half of the supply voltage of silicon nanowire MOSFETs in the ballistic limit. However, a study on the effects of edge roughness on the performance of the optimized GNR TFET structure reveals that experimentally feasible edge roughness can deteriorates the on-current performance if the off-current is normalized with the low power requirement specified in the international technology roadmap for semiconductors.

Kim, SungGeun, E-mail: snugkim@gmail.com; Klimeck, Gerhard [Network for Computational Nanotechnology, Purdue University, West Lafayette, Indiana 47907 (United States); Luisier, Mathieu [Integrated Systems Laboratory, Gloriastrasse 35, ETH Zürich, 8092 Zürich (Switzerland); Boykin, Timothy B. [Department of Electrical and Computer Engineering, The University of Alabama in Huntsville, Huntsville, Alabama 35899 (United States)

2014-06-16T23:59:59.000Z

122

Quantum Behavior of Graphene Transistors near the Scaling Limit Yanqing Wu,,  

E-Print Network [OSTI]

Quantum Behavior of Graphene Transistors near the Scaling Limit Yanqing Wu,, * Vasili Perebeinos properties of graphene have been a key research focus for the past few years. However, external components interference effects were demonstrated in graphene heterojunctions formed by a top gate. Here phase coherent

Perebeinos, Vasili

123

Mechanisms for plasma etching of HfO{sub 2} gate stacks with Si selectivity and photoresist trimming  

SciTech Connect (OSTI)

To minimize leakage currents resulting from the thinning of the insulator in the gate stack of field effect transistors, high-dielectric constant (high-k) metal oxides, and HfO{sub 2} in particular, are being implemented as a replacement for SiO{sub 2}. To speed the rate of processing, it is desirable to etch the gate stack (e.g., metal gate, antireflection layers, and dielectric) in a single process while having selectivity to the underlying Si. Plasma etching using Ar/BCl{sub 3}/Cl{sub 2} mixtures effectively etches HfO{sub 2} while having good selectivity to Si. In this article, results from integrated reactor and feature scale modeling of gate-stack etching in Ar/BCl{sub 3}/Cl{sub 2} plasmas, preceded by photoresist trimming in Ar/O{sub 2} plasmas, are discussed. It was found that BCl{sub n} species react with HfO{sub 2}, which under ion impact, form volatile etch products such as B{sub m}OCl{sub n} and HfCl{sub n}. Selectivity to Si is achieved by creating Si-B bonding as a precursor to the deposition of a BCl{sub n} polymer which slows the etch rate relative to HfO{sub 2}. The low ion energies required to achieve this selectivity then challenge one to obtain highly anisotropic profiles in the metal gate portion of the stack. Validation was performed with data from literature. The effect of bias voltage and key reactant probabilities on etch rate, selectivity, and profile are discussed.

Shoeb, Juline; Kushner, Mark J. [Department of Electrical and Computer Engineering, Iowa State University, Ames, Iowa 50011 (United States); Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, Michigan 48109-2122 (United States)

2009-11-15T23:59:59.000Z

124

Low interface defect density of atomic layer deposition BeO with self-cleaning reaction for InGaAs metal oxide semiconductor field effect transistors  

SciTech Connect (OSTI)

In this paper, we discuss atomic configuration of atomic layer deposition (ALD) beryllium oxide (BeO) using the quantum chemistry to understand the theoretical origin. BeO has shorter bond length, higher reaction enthalpy, and larger bandgap energy compared with those of ALD aluminum oxide. It is shown that the excellent material properties of ALD BeO can reduce interface defect density due to the self-cleaning reaction and this contributes to the improvement of device performance of InGaAs MOSFETs. The low interface defect density and low leakage current of InGaAs MOSFET were demonstrated using X-ray photoelectron spectroscopy and the corresponding electrical results.

Shin, H. S. [Department of Electronics Engineering, Chungnam National University, Daejeon (Korea, Republic of) [Department of Electronics Engineering, Chungnam National University, Daejeon (Korea, Republic of); SEMATECH, 2706 Montopolis Dr., Austin, Texas 78741 (United States); The University of Texas, Austin, Texas 78758 (United States); Yum, J. H. [SEMATECH, 2706 Montopolis Dr., Austin, Texas 78741 (United States) [SEMATECH, 2706 Montopolis Dr., Austin, Texas 78741 (United States); The University of Texas, Austin, Texas 78758 (United States); Johnson, D. W. [SEMATECH, 2706 Montopolis Dr., Austin, Texas 78741 (United States) [SEMATECH, 2706 Montopolis Dr., Austin, Texas 78741 (United States); Texas A and M University College Station, Texas 77843 (United States); Harris, H. R. [Texas A and M University College Station, Texas 77843 (United States)] [Texas A and M University College Station, Texas 77843 (United States); Hudnall, Todd W. [Texas State University, 601 University Drive, San Marcos, Texas 78666 (United States)] [Texas State University, 601 University Drive, San Marcos, Texas 78666 (United States); Oh, J. [Yonsei University, Incheon, 406-840 (Korea, Republic of)] [Yonsei University, Incheon, 406-840 (Korea, Republic of); Kirsch, P.; Wang, W.-E. [SEMATECH, 2706 Montopolis Dr., Austin, Texas 78741 (United States)] [SEMATECH, 2706 Montopolis Dr., Austin, Texas 78741 (United States); Bielawski, C. W.; Banerjee, S. K.; Lee, J. C. [The University of Texas, Austin, Texas 78758 (United States)] [The University of Texas, Austin, Texas 78758 (United States); Lee, H. D. [Department of Electronics Engineering, Chungnam National University, Daejeon (Korea, Republic of)] [Department of Electronics Engineering, Chungnam National University, Daejeon (Korea, Republic of)

2013-11-25T23:59:59.000Z

125

Gating of Permanent Molds for ALuminum Casting  

SciTech Connect (OSTI)

This report summarizes a two-year project, DE-FC07-01ID13983 that concerns the gating of aluminum castings in permanent molds. The main goal of the project is to improve the quality of aluminum castings produced in permanent molds. The approach taken was determine how the vertical type gating systems used for permanent mold castings can be designed to fill the mold cavity with a minimum of damage to the quality of the resulting casting. It is evident that somewhat different systems are preferred for different shapes and sizes of aluminum castings. The main problems caused by improper gating are entrained aluminum oxide films and entrapped gas. The project highlights the characteristic features of gating systems used in permanent mold aluminum foundries and recommends gating procedures designed to avoid common defects. The study also provides direct evidence on the filling pattern and heat flow behavior in permanent mold castings.

David Schwam; John F. Wallace; Tom Engle; Qingming Chang

2004-03-30T23:59:59.000Z

126

Probing Organic Transistors with Infrared Beams  

Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

Probing Organic Transistors with Infrared Beams Print Silicon-based transistors are well-understood, basic components of contemporary electronic technology. In contrast, there is...

127

Reduced-dimension transistors: Reduced-dimension transistors  

E-Print Network [OSTI]

1 Reduced-dimension transistors: the HEMT LECTURE 20 · Reduced-dimension transistors · HEMT · 2-D;8 For a finite well · Wavefunction not completely confined · Use undoped spacer #12;9 Employment of a spacer scattering (µ ). · Electrons and donors separated no I I scattering, i.e., µ · Undoped spacer also helps

Pulfrey, David L.

128

Single atom impurity in a single molecular transistor  

SciTech Connect (OSTI)

The influence of an impurity atom on the electrostatic behaviour of a Single Molecular Transistor was investigated through Ab-initio calculations in a double-gated geometry. The charge stability diagram carries unique signature of the position of the impurity atom in such devices which together with the charging energy of the molecule could be utilised as an electronic fingerprint for the detection of such impurity states in a nano-electronic device. The two gated geometry allows additional control over the electrostatics as can be seen from the total energy surfaces (for a specific charge state), which is sensitive to the positions of the impurity. These devices which are operational at room temperature can provide significant advantages over the conventional silicon based single dopant devices functional at low temperature. The present approach could be a very powerful tool for the detection and control of individual impurity atoms in a single molecular device and for applications in future molecular electronics.

Ray, S. J., E-mail: ray.sjr@gmail.com [Institute of Materials Science, Technical University of Darmstadt, Alarich-Weiss Str. 2, 64287 Darmstadt (Germany)

2014-10-21T23:59:59.000Z

129

On the interest of carbon-coated plasma reactor for advanced gate stack etching processes  

SciTech Connect (OSTI)

In integrated circuit fabrication the most wide spread strategy to achieve acceptable wafer-to-wafer reproducibility of the gate stack etching process is to dry-clean the plasma reactor walls between each wafer processed. However, inherent exposure of the reactor walls to fluorine-based plasma leads to formation and accumulation of nonvolatile fluoride residues (such as AlF{sub x}) on reactor wall surfaces, which in turn leads to process drifts and metallic contamination of wafers. To prevent this while keeping an Al{sub 2}O{sub 3} reactor wall material, a coating strategy must be used, in which the reactor is coated by a protective layer between wafers. It was shown recently that deposition of carbon-rich coating on the reactor walls allows improvements of process reproducibility and reactor wall protection. The authors show that this strategy results in a higher ion-to-neutral flux ratio to the wafer when compared to other strategies (clean or SiOCl{sub x}-coated reactors) because the carbon walls load reactive radical densities while keeping the same ion current. As a result, the etching rates are generally smaller in a carbon-coated reactor, but a highly anisotropic etching profile can be achieved in silicon and metal gates, whose etching is strongly ion assisted. Furthermore, thanks to the low density of Cl atoms in the carbon-coated reactor, silicon etching can be achieved almost without sidewall passivation layers, allowing fine critical dimension control to be achieved. In addition, it is shown that although the O atom density is also smaller in the carbon-coated reactor, the selectivity toward ultrathin gate oxides is not reduced dramatically. Furthermore, during metal gate etching over high-k dielectric, the low level of parasitic oxygen in the carbon-coated reactor also allows one to minimize bulk silicon reoxidation through HfO{sub 2} high-k gate dielectric. It is then shown that the BCl{sub 3} etching process of the HfO{sub 2} high-k material is highly selective toward the substrate in the carbon-coated reactor, and the carbon-coating strategy thus allows minimizing the silicon recess of the active area of transistors. The authors eventually demonstrate that the carbon-coating strategy drastically reduces on-wafer metallic contamination. Finally, the consumption of carbon from the reactor during the etching process is discussed (and thus the amount of initial deposit that is required to protect the reactor walls) together with the best way of cleaning the reactor after a silicon etching process.

Ramos, R.; Cunge, G.; Joubert, O. [Freescale Semiconductor Inc., 850 Rue Jean Monnet, 38921 Crolles Cedex (France) and Laboratoire des Technologies de la Microelectronique, CNRS, 17 Rue des Martyrs (c/o CEA-LETI), 38054 Grenoble Cedex 9 (France); Laboratoire des Technologies de la Microelectronique, CNRS, 17 Rue des Martyrs (c/o CEA-LETI), 38054 Grenoble Cedex 9 (France)

2007-03-15T23:59:59.000Z

130

Metal-semiconductor hybrid thin films in field-effect transistors  

SciTech Connect (OSTI)

Metal-semiconductor hybrid thin films consisting of an amorphous oxide semiconductor and a number of aluminum dots in different diameters and arrangements are formed by electron beam lithography and employed for thin-film transistors (TFTs). Experimental and computational demonstrations systematically reveal that the field-effect mobility of the TFTs enhances but levels off as the dot density increases, which originates from variations of the effective channel length that strongly depends on the electric field distribution in a transistor channel.

Okamura, Koshi, E-mail: koshi.okamura@kit.edu; Dehm, Simone [Institute of Nanotechnology, Karlsruhe Institute of Technology (KIT), 76021 Karlsruhe (Germany)] [Institute of Nanotechnology, Karlsruhe Institute of Technology (KIT), 76021 Karlsruhe (Germany); Hahn, Horst [Institute of Nanotechnology, Karlsruhe Institute of Technology (KIT), 76021 Karlsruhe (Germany) [Institute of Nanotechnology, Karlsruhe Institute of Technology (KIT), 76021 Karlsruhe (Germany); KIT-TUD Joint Research Laboratory Nanomaterials, Technische Universität Darmstadt, Petersenstr. 32, 64287 Darmstadt (Germany)

2013-12-16T23:59:59.000Z

131

Ultrafast gating of proximity-focused microchannel-plate intensifiers  

SciTech Connect (OSTI)

Proximity-focused, microchannel-plate (MCP) image intensifiers have been used at Los Alamos for many years to allow single frame film and video exposure times in the range of 2.5 to 10 ns. There is now a program to reduce gating times to < 1 ns. This paper reviews previous work and the problems in achieving good resolution with gating times of < 1 ns. The key problems involve applying fast electrical gating signals to the tube elements. We present computer modeling studies of the combined tube, tube connection, and pulser system and show that low photocathode surface resistivity must be obtained to permit fast gating between the photocathode and the MCP input. We discuss ways of making low-resistivity S20 photocathodes, using gallium arsenide photocathodes, and various means of gating the tubes. A variety of pulser designs are being experimentally evaluated including spark gaps, avalanche transistors, Krytron tubes with sharpening gaps, step recovery diodes, and photoconductive elements (PCEs). The results of these studies are presented. Because of the high capacitances involved in most gating schemes, the tube connection geometry must be of low-impedance design, and our solution is presented. Finally, ways of testing these high-speed camera systems are discussed.

Lundy, A.S.; Iverson, A.E.

1982-01-01T23:59:59.000Z

132

Adiabatic Quantum Transistors  

DOE Public Access Gateway for Energy & Science Beta (PAGES Beta)

We describe a many-body quantum system that can be made to quantum compute by the adiabatic application of a large applied field to the system. Prior to the application of the field, quantum information is localized on one boundary of the device, and after the application of the field, this information propagates to the other side of the device, with a quantum circuit applied to the information. The applied circuit depends on the many-body Hamiltonian of the material, and the computation takes place in a degenerate ground space with symmetry-protected topological order. Such “adiabatic quantum transistors” are universal adiabatic quantum computing devices that have the added benefit of being modular. Here, we describe this model, provide arguments for why it is an efficient model of quantum computing, and examine these many-body systems in the presence of a noisy environment.

Bacon, Dave; Flammia, Steven T.; Crosswhite, Gregory M.

2013-06-01T23:59:59.000Z

133

Radio-frequency reflectometry on an undoped AlGaAs/GaAs single electron transistor  

SciTech Connect (OSTI)

Radio frequency reflectometry is demonstrated in a sub-micron undoped AlGaAs/GaAs device. Undoped single electron transistors (SETs) are attractive candidates to study single electron phenomena, due to their charge stability and robust electronic properties after thermal cycling. However, these devices require a large top-gate, which is unsuitable for the fast and sensitive radio frequency reflectometry technique. Here, we demonstrate that rf reflectometry is possible in an undoped SET.

MacLeod, S. J.; See, A. M.; Keane, Z. K.; Scriven, P.; Micolich, A. P.; Hamilton, A. R., E-mail: Alex.Hamilton@unsw.edu.au [School of Physics, University of New South Wales, Sydney, New South Wales 2052 (Australia); Aagesen, M.; Lindelof, P. E. [Nanoscience Center, University of Copenhagen, Universitetsparken 5, DK-2100 Copenhagen (Denmark)] [Nanoscience Center, University of Copenhagen, Universitetsparken 5, DK-2100 Copenhagen (Denmark)

2014-01-06T23:59:59.000Z

134

Demonstrating 1 nm-oxide-equivalent-thickness HfO{sub 2}/InSb structure with unpinning Fermi level and low gate leakage current density  

SciTech Connect (OSTI)

In this work, the band alignment, interface, and electrical characteristics of HfO{sub 2}/InSb metal-oxide-semiconductor structure have been investigated. By using x-ray photoelectron spectroscopy analysis, the conduction band offset of 1.78 ± 0.1 eV and valence band offset of 3.35 ± 0.1 eV have been extracted. The transmission electron microscopy analysis has shown that HfO{sub 2} layer would be a good diffusion barrier for InSb. As a result, 1 nm equivalent-oxide-thickness in the 4 nm HfO{sub 2}/InSb structure has been demonstrated with unpinning Fermi level and low leakage current of 10{sup ?4} A/cm{sup ?2}. The D{sub it} value of smaller than 10{sup 12} eV{sup ?1}cm{sup ?2} has been obtained using conduction method.

Trinh, Hai-Dang [Department of Materials Science and Engineering, National Chiao Tung University, 1001 University Road, Hsinchu, Taiwan (China) [Department of Materials Science and Engineering, National Chiao Tung University, 1001 University Road, Hsinchu, Taiwan (China); Department of Physics, Hanoi National University of Education, 136 Xuan Thuy, Cau Giay, Hanoi (Viet Nam); Lin, Yueh-Chin; Nguyen, Hong-Quan; Luc, Quang-Ho [Department of Materials Science and Engineering, National Chiao Tung University, 1001 University Road, Hsinchu, Taiwan (China)] [Department of Materials Science and Engineering, National Chiao Tung University, 1001 University Road, Hsinchu, Taiwan (China); Nguyen, Minh-Thuy; Duong, Quoc-Van; Nguyen, Manh-Nghia [Department of Physics, Hanoi National University of Education, 136 Xuan Thuy, Cau Giay, Hanoi (Viet Nam)] [Department of Physics, Hanoi National University of Education, 136 Xuan Thuy, Cau Giay, Hanoi (Viet Nam); Wang, Shin-Yuan [Department of Electronic Engineering, National Chiao Tung University 1001, University Rd., Hsinchu 300, Taiwan (China)] [Department of Electronic Engineering, National Chiao Tung University 1001, University Rd., Hsinchu 300, Taiwan (China); Yi Chang, Edward [Department of Materials Science and Engineering, National Chiao Tung University, 1001 University Road, Hsinchu, Taiwan (China) [Department of Materials Science and Engineering, National Chiao Tung University, 1001 University Road, Hsinchu, Taiwan (China); Department of Electronic Engineering, National Chiao Tung University 1001, University Rd., Hsinchu 300, Taiwan (China)

2013-09-30T23:59:59.000Z

135

Low interfacial trap density and sub-nm equivalent oxide thickness in In{sub 0.53}Ga{sub 0.47}As (001) metal-oxide-semiconductor devices using molecular beam deposited HfO{sub 2}/Al{sub 2}O{sub 3} as gate dielectrics  

SciTech Connect (OSTI)

We investigated the passivation of In{sub 0.53}Ga{sub 0.47}As (001) surface by molecular beam epitaxy techniques. After growth of strained In{sub 0.53}Ga{sub 0.47}As on InP (001) substrate, HfO{sub 2}/Al{sub 2}O{sub 3} high-{kappa} oxide stacks have been deposited in-situ after surface reconstruction engineering. Excellent capacitance-voltage characteristics have been demonstrated along with low gate leakage currents. The interfacial density of states (D{sub it}) of the Al{sub 2}O{sub 3}/In{sub 0.53}Ga{sub 0.47}As interface have been revealed by conductance measurement, indicating a downward D{sub it} profile from the energy close to the valence band (medium 10{sup 12} cm{sup -2}eV{sup -1}) towards that close to the conduction band (10{sup 11} cm{sup -2}eV{sup -1}). The low D{sub it}'s are in good agreement with the high Fermi-level movement efficiency of greater than 80%. Moreover, excellent scalability of the HfO{sub 2} has been demonstrated as evidenced by the good dependence of capacitance oxide thickness on the HfO{sub 2} thickness (dielectric constant of HfO{sub 2}{approx}20) and the remained low D{sub it}'s due to the thin Al{sub 2}O{sub 3} passivation layer. The sample with HfO{sub 2} (3.4 nm)/Al{sub 2}O{sub 3} (1.2 nm) as the gate dielectrics has exhibited an equivalent oxide thickness of {approx}0.93 nm.

Chu, L. K. [Department of Materials Science and Engineering, National Tsing Hua University, Hsinchu 30013, Taiwan (China); Katholieke Universiteit Leuven, 3001 Leuven (Belgium); Merckling, C.; Dekoster, J.; Caymax, M. [Interuniversity Microelectronics Center (IMEC vzw), 3001 Leuven (Belgium); Alian, A.; Heyns, M. [Katholieke Universiteit Leuven, 3001 Leuven (Belgium); Interuniversity Microelectronics Center (IMEC vzw), 3001 Leuven (Belgium); Kwo, J. [Department of Physics, National Tsing Hua University, Hsinchu 30013, Taiwan (China); Center for Condensed Matter Sciences, National Taiwan University, Taipei 10617, Taiwan (China); Hong, M. [Department of Materials Science and Engineering, National Tsing Hua University, Hsinchu 30013, Taiwan (China)

2011-07-25T23:59:59.000Z

136

Optical Determination of Gate--Tunable Bandgap in Bilayer Graphene  

SciTech Connect (OSTI)

The electronic bandgap is an intrinsic property of semiconductors and insulators that largely determines their transport and optical properties. As such, it has a central role in modern device physics and technology and governs the operation of semiconductor devices such as p-n junctions, transistors, photodiodes and lasers. A tunable bandgap would be highly desirable because it would allow great flexibility in design and optimization of such devices, in particular if it could be tuned by applying a variable external electric field. However, in conventional materials, the bandgap is fixed by their crystalline structure, preventing such bandgap control. Here we demonstrate the realization of a widely tunable electronic bandgap in electrically gated bilayer graphene. Using a dual-gate bilayer graphene field-effect transistor (FET) and infrared microspectroscopy, we demonstrate a gate-controlled, continuously tunable bandgap of up to 250 meV. Our technique avoids uncontrolled chemical doping and provides direct evidence of a widely tunable bandgap -- spanning a spectral range from zero to mid-infrared -- that has eluded previous attempts. Combined with the remarkable electrical transport properties of such systems, this electrostatic bandgap control suggests novel nanoelectronic and nanophotonic device applications based on graphene.

Zhang, Yuanbo; Tang, Tsung-Ta; Girit, Caglar; Hao, Zhao; Martin, Michael C.; Zettl, Alex; Crommie, Michael F.; Shen, Y. Ron; Wang, Feng

2009-08-11T23:59:59.000Z

137

Optical NAND gate  

SciTech Connect (OSTI)

An optical NAND gate is formed from two pair of optical waveguide devices on a substrate, with each pair of the optical waveguide devices consisting of an electroabsorption modulator and a photodetector. One pair of the optical waveguide devices is electrically connected in parallel to operate as an optical AND gate; and the other pair of the optical waveguide devices is connected in series to operate as an optical NOT gate (i.e. an optical inverter). The optical NAND gate utilizes two digital optical inputs and a continuous light input to provide a NAND function output. The optical NAND gate can be formed from III-V compound semiconductor layers which are epitaxially deposited on a III-V compound semiconductor substrate, and operates at a wavelength in the range of 0.8-2.0 .mu.m.

Skogen, Erik J. (Albuquerque, NM); Raring, James (Goleta, CA); Tauke-Pedretti, Anna (Albuquerque, NM)

2011-08-09T23:59:59.000Z

138

CHAPTER III POWER BIPOLAR JUNCTION TRANSISTOR  

E-Print Network [OSTI]

recovery waveform of the transistor. These were obtained using the Silvaco simulation package [15]. The 2D

Anand, Raghubir Singh

139

Optical XOR gate  

DOE Patents [OSTI]

An optical XOR gate is formed as a photonic integrated circuit (PIC) from two sets of optical waveguide devices on a substrate, with each set of the optical waveguide devices including an electroabsorption modulator electrically connected in series with a waveguide photodetector. The optical XOR gate utilizes two digital optical inputs to generate an XOR function digital optical output. The optical XOR gate can be formed from III-V compound semiconductor layers which are epitaxially deposited on a III-V compound semiconductor substrate, and operates at a wavelength in the range of 0.8-2.0 .mu.m.

Vawter, G. Allen

2013-11-12T23:59:59.000Z

140

Optical NOR gate  

DOE Patents [OSTI]

An optical NOR gate is formed from two pair of optical waveguide devices on a substrate, with each pair of the optical waveguide devices consisting of an electroabsorption modulator electrically connected in series with a waveguide photodetector. The optical NOR gate utilizes two digital optical inputs and a continuous light input to provide a NOR function digital optical output. The optical NOR gate can be formed from III-V compound semiconductor layers which are epitaxially deposited on a III-V compound semiconductor substrate, and operates at a wavelength in the range of 0.8-2.0 .mu.m.

Skogen, Erik J. (Albuquerque, NM); Tauke-Pedretti, Anna (Albuquerque, NM)

2011-09-06T23:59:59.000Z

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141

CARBON NANOTUBE TRANSISTORS: AN EVALUATION  

E-Print Network [OSTI]

CARBON NANOTUBE TRANSISTORS: AN EVALUATION L.C. Castro, D.L. John, and D.L. Pulfrey Department A simple, non-equilibrium model is used to evaluate the likely DC performance of carbon nanotube field and transcon- ductance close to the low-quantum-capacitance limit. Keywords: Carbon nanotubes, field

Pulfrey, David L.

142

Reliability of AlGaN/GaN high electron mobility transistors on low dislocation density bulk GaN substrate: Implications of surface step edges  

SciTech Connect (OSTI)

To enable gaining insight into degradation mechanisms of AlGaN/GaN high electron mobility transistors, devices grown on a low-dislocation-density bulk-GaN substrate were studied. Gate leakage current and electroluminescence (EL) monitoring revealed a progressive appearance of EL spots during off-state stress which signify the generation of gate current leakage paths. Atomic force microscopy evidenced the formation of semiconductor surface pits at the failure location, which corresponds to the interaction region of the gate contact edge and the edges of surface steps.

Killat, N., E-mail: Nicole.Killat@bristol.ac.uk, E-mail: Martin.Kuball@bristol.ac.uk; Montes Bajo, M.; Kuball, M., E-mail: Nicole.Killat@bristol.ac.uk, E-mail: Martin.Kuball@bristol.ac.uk [Center for Device Thermography and Reliability (CDTR), H.H. Wills Physics Laboratory, Tyndall Avenue, Bristol BS8 1TL (United Kingdom); Paskova, T. [Kyma Technologies, Inc., Raleigh, North Carolina 27617 (United States) [Kyma Technologies, Inc., Raleigh, North Carolina 27617 (United States); Materials Science and Engineering Department, North Carolina State University, Raleigh, North Carolina 27695 (United States); Evans, K. R. [Kyma Technologies, Inc., Raleigh, North Carolina 27617 (United States)] [Kyma Technologies, Inc., Raleigh, North Carolina 27617 (United States); Leach, J. [Kyma Technologies, Inc., Raleigh, North Carolina 27617 (United States) [Kyma Technologies, Inc., Raleigh, North Carolina 27617 (United States); Electrical and Computer Engineering Department, Virginia Commonwealth University, Richmond, Virginia 23284 (United States); Li, X.; Özgür, Ü.; Morkoç, H. [Electrical and Computer Engineering Department, Virginia Commonwealth University, Richmond, Virginia 23284 (United States)] [Electrical and Computer Engineering Department, Virginia Commonwealth University, Richmond, Virginia 23284 (United States); Chabak, K. D.; Crespo, A.; Gillespie, J. K.; Fitch, R.; Kossler, M.; Walker, D. E.; Trejo, M.; Via, G. D.; Blevins, J. D. [Air Force Research Laboratory, Wright-Patterson Air Force Base, Dayton, Ohio 45433 (United States)] [Air Force Research Laboratory, Wright-Patterson Air Force Base, Dayton, Ohio 45433 (United States)

2013-11-04T23:59:59.000Z

143

Performance limits of tunnel transistors based on mono-layer transition-metal dichalcogenides  

SciTech Connect (OSTI)

Performance limits of tunnel field-effect transistors based on mono-layer transition metal dichalcogenides are investigated through numerical quantum mechanical simulations. The atomic mono-layer nature of the devices results in a much smaller natural length ?, leading to much larger electric field inside the tunneling diodes. As a result, the inter-band tunneling currents are found to be very high as long as ultra-thin high-k gate dielectric is possible. The highest on-state driving current is found to be close to 600??A/?m at V{sub g}?=?V{sub d}?=?0.5?V when 2?nm thin HfO{sub 2} layer is used for gate dielectric, outperforming most of the conventional semiconductor tunnel transistors. In the five simulated transition-metal dichalcogenides, mono-layer WSe{sub 2} based tunnel field-effect transistor shows the best potential. Deep analysis reveals that there is plenty room to further enhance the device performance by either geometry, alloy, or strain engineering on these mono-layer materials.

Jiang, Xiang-Wei, E-mail: xwjiang@semi.ac.cn; Li, Shu-Shen [State Key Laboratory of Superlattices and Microstructures, Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083 (China); Synergetic Innovation Center of Quantum Information and Quantum Physics, University of Science and Technology of China, Hefei, Anhui 230026 (China)

2014-05-12T23:59:59.000Z

144

Realizing high-voltage thin film lateral bipolar transistors on SOI with a collector-tub  

E-Print Network [OSTI]

Realizing high-voltage thin film lateral bipolar transistors on SOI with a collector-tub Sukhendu-dimensional device simulation to examine the effect of a collector tub on the collector breakdown of the SOI based BJTs. This method involves creating a collector tub by etching the buried oxide followed by an n

Kumar, M. Jagadesh

145

E-Print Network 3.0 - attenuates oxidative stress Sample Search...  

Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

Stefan... describe the use of spectroscopic ellipsometry and other characterization techniques for gate oxide process... dielectrics (silicon oxynitride or metal oxides), and...

146

E-Print Network 3.0 - attenuating oxidative stress Sample Search...  

Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

Stefan... describe the use of spectroscopic ellipsometry and other characterization techniques for gate oxide process... dielectrics (silicon oxynitride or metal oxides), and...

147

E-Print Network 3.0 - attenuate oxidative stress Sample Search...  

Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

Stefan... describe the use of spectroscopic ellipsometry and other characterization techniques for gate oxide process... dielectrics (silicon oxynitride or metal oxides), and...

148

Tetracene air-gap single-crystal field-effect transistors Yu Xia, Vivek Kalihari, and C. Daniel Frisbiea  

E-Print Network [OSTI]

Tetracene air-gap single-crystal field-effect transistors Yu Xia, Vivek Kalihari, and C. Daniel FETs utilizing an air or vacuum gap as the gate dielectric. The linear mobility of the device can be as high as 1.6 cm2 /V s in air, with a subthreshold slope lower than 0.5 V nF/decade cm2 . By changing

Rogers, John A.

149

Alternative Gate Dielectrics on Semiconductors for MOSFET Device Applications  

SciTech Connect (OSTI)

We have investigated the synthesis and properties of deposited oxides on Si and Ge for use as alternative gate dielectrics in MOSFET applications. The capacitance and leakage current behavior of polycrystalline Y{sub 2}O{sub 3} films synthesized by pulsed-laser deposition is reported. In addition, we also discuss the growth of epitaxial oxide structures. In particular, we have investigated the use of silicide termination for oxide growth on (001) Si using laser-molecular beam epitaxy. In addition, we discuss a novel approach involving the use of hydrogen to eliminate native oxide during initial dielectric oxide nucleation on (001) Ge.

Norton, D.P.; Budai, J.D.; Chisholm, M.F.; Pennycook, S.J.; McKee, R.; Walker, F.; Lee, Y.; Park, C.

1999-12-06T23:59:59.000Z

150

Cardiac gated ventilation  

SciTech Connect (OSTI)

There are several theoretic advantages to synchronizing positive pressure breaths with the cardiac cycle, including the potential for improving distribution of pulmonary and myocardial blood flow and enhancing cardiac output. The authors evaluated the effects of synchronizing respiration to the cardiac cycle using a programmable ventilator and electron beam CT (EBCT) scanning. The hearts of anesthetized dogs were imaged during cardiac gated respiration with a 50 msec scan aperture. Multi slice, short axis, dynamic image data sets spanning the apex to base of the left ventricle were evaluated to determine the volume of the left ventricular chamber at end-diastole and end-systole during apnea, systolic and diastolic cardiac gating. The authors observed an increase in cardiac output of up to 30% with inspiration gated to the systolic phase of the cardiac cycle in a non-failing model of the heart.

Hanson, C.W. III [Hospital of the Univ. of Pennsylvania, Philadelphia, PA (United States). Dept. Anesthesia; Hoffman, E.A. [Univ. of Iowa College of Medicine, Iowa City, IA (United States). Div. of Physiologic Imaging

1995-12-31T23:59:59.000Z

151

Complementary junction heterostructure field-effect transistor  

DOE Patents [OSTI]

A complimentary pair of compound semiconductor junction heterostructure field-effect transistors and a method for their manufacture are disclosed. The p-channel junction heterostructure field-effect transistor uses a strained layer to split the degeneracy of the valence band for a greatly improved hole mobility and speed. The n-channel device is formed by a compatible process after removing the strained layer. In this manner, both types of transistors may be independently optimized. Ion implantation is used to form the transistor active and isolation regions for both types of complimentary devices. The invention has uses for the development of low power, high-speed digital integrated circuits.

Baca, Albert G. (Albuquerque, NM); Drummond, Timothy J. (Albuquerque, NM); Robertson, Perry J. (Albuquerque, NM); Zipperian, Thomas E. (Albuquerque, NM)

1995-01-01T23:59:59.000Z

152

Complementary junction heterostructure field-effect transistor  

DOE Patents [OSTI]

A complimentary pair of compound semiconductor junction heterostructure field-effect transistors and a method for their manufacture are disclosed. The p-channel junction heterostructure field-effect transistor uses a strained layer to split the degeneracy of the valence band for a greatly improved hole mobility and speed. The n-channel device is formed by a compatible process after removing the strained layer. In this manner, both types of transistors may be independently optimized. Ion implantation is used to form the transistor active and isolation regions for both types of complimentary devices. The invention has uses for the development of low power, high-speed digital integrated circuits. 10 figs.

Baca, A.G.; Drummond, T.J.; Robertson, P.J.; Zipperian, T.E.

1995-12-26T23:59:59.000Z

153

Golden Gate Park Marina Blvd.  

E-Print Network [OSTI]

St. Eureka S.VanNessAve. M arket St. Broadway St. To Golden Gate Bridge H ow ard St. Folsom St. Bryant St. 10 North / Golden Gate Bridge 2. Exit I­280 North toward Downtown San Francisco 3. Exit Mariposa St. toward80 280 Presidio Golden Gate Park Lincoln Park Buena Vista Park 101 101 101 101 1 1 Marina Blvd. Bay

Derisi, Joseph

154

High-voltage field effect transistors with wide-bandgap ?-Ga{sub 2}O{sub 3} nanomembranes  

SciTech Connect (OSTI)

Nanoscale semiconductor materials have been extensively investigated as the channel materials of transistors for energy-efficient low-power logic switches to enable scaling to smaller dimensions. On the opposite end of transistor applications is power electronics for which transistors capable of switching very high voltages are necessary. Miniaturization of energy-efficient power switches can enable the integration with various electronic systems and lead to substantial boosts in energy efficiency. Nanotechnology is yet to have an impact in this arena. In this work, it is demonstrated that nanomembranes of the wide-bandgap semiconductor gallium oxide can be used as channels of transistors capable of switching high voltages, and at the same time can be integrated on any platform. The findings mark a step towards using lessons learnt in nanomaterials and nanotechnology to address a challenge that yet remains untouched by the field.

Hwang, Wan Sik, E-mail: whwang@kau.ac.kr, E-mail: djena@nd.edu [Department of Materials Engineering, Korea Aerospace University, Gyeonggi, 412791 (Korea, Republic of); Verma, Amit; Protasenko, Vladimir; Rouvimov, Sergei; Xing, Huili; Seabaugh, Alan; Jena, Debdeep, E-mail: whwang@kau.ac.kr, E-mail: djena@nd.edu [Department of Electrical Engineering, University of Notre Dame, Notre Dame, Indiana 46556 (United States); Peelaers, Hartwin; Van de Walle, Chris [Materials Department, University of California Santa Barbara, California 93106 (United States); Haensch, Wilfried [IBM T. J. Watson Research Center, Yorktown Heights, New York 10598 (United States); Galazka, Zbigniew; Albrecht, Martin [Leibniz Institute for Crystal Growth, Max-Born Str., D-12489 Berlin (Germany); Fornari, Roberto [Leibniz Institute for Crystal Growth, Max-Born Str., D-12489 Berlin (Germany); Department of Physics and Earth Science, University of Parma, Parma, 43124 Italy (Italy)

2014-05-19T23:59:59.000Z

155

Heterostructure unipolar spin transistors M. E. Flatta  

E-Print Network [OSTI]

carriers on one side of the device are spin-down spin-up electrons and on the other side of the device semiconductor electronics and spin-based unipolar electronics by considering unipolar spin transistors electrons to the collector limits the performance of "homojunction" unipolar spin transistors, in which

Flatte, Michael E.

156

CARBON NANOTUBE TRANSISTORS, SENSORS, AND A Dissertation  

E-Print Network [OSTI]

CARBON NANOTUBE TRANSISTORS, SENSORS, AND BEYOND A Dissertation Presented to the Faculty of Philosophy by Xinjian Zhou January 2008 #12;#12;CARBON NANOTUBE TRANSISTORS, SENSORS, AND BEYOND Xinjian Zhou, Ph. D. Cornell University 2008 Carbon nanotubes are tiny hollow cylinders, made from a single

McEuen, Paul L.

157

Universal power transistor base drive control unit  

SciTech Connect (OSTI)

A saturation condition regulator system for a power transistor which achieves the regulation objectives of a Baker clamp but without dumping excess base drive current into the transistor output circuit. The base drive current of the transistor is sensed and used through an active feedback circuit to produce an error signal which modulates the base drive current through a linearly operating FET. The collector base voltage of the power transistor is independently monitored to develop a second error signal which is also used to regulate base drive current. The current-sensitive circuit operates as a limiter. In addition, a fail-safe timing circuit is disclosed which automatically resets to a turn OFF condition in the event the transistor does not turn ON within a predetermined time after the input signal transition.

Gale, Allan R. (Allen Park, MI); Gritter, David J. (Racine, WI)

1988-01-01T23:59:59.000Z

158

New Technology, New People, New Organizations: The Rise of the MOS Transistor,  

E-Print Network [OSTI]

The MOS (Metal-Oxide-Semiconductor) transistor, as the fundamental element in all digital electronics, is the base technology of late twentieth centmy American society. It has been the vehicle through which digital electronics has entered almost every area of American life, first through the electronicalcuhtor, then through the digital watch, and finally through the microprocessor. And while the proliferation of the microprocessor has been most apparent through the personal computer, it has spread almost everywhere: to automobiles, sewing machines, cameras, and dishwashers, to name only a few of its endless applications. In 1994, over 2 billion 4- and 8-bit microprocessors and microcontrollers 0ong out of date for use as central processing units for computers) were produced [Slater, 1996, p. 41]. The MOS Transistor and Technological Revolutions The story of the MOS transistor is the story of a technological revolution. The first technologically important transistor was the bipolar transistor, invented in 1948 by William Shockley at Bell Labs. It was extremely successful,

Ross Bassett

159

Giant amplification of tunnel magnetoresistance in a molecular junction: Molecular spin-valve transistor  

SciTech Connect (OSTI)

Amplification of tunnel magnetoresistance by gate field in a molecular junction is the most important requirement for the development of a molecular spin valve transistor. Herein, we predict a giant amplification of tunnel magnetoresistance in a single molecular spin valve junction, which consists of Ru-bis-terpyridine molecule as a spacer between two ferromagnetic nickel contacts. Based on the first-principles quantum transport approach, we show that a modest change in the gate field that is experimentally accessible can lead to a substantial amplification (320%) of tunnel magnetoresistance. The origin of such large amplification is attributed to the spin dependent modification of orbitals at the molecule-lead interface and the resultant Stark effect induced shift in channel position with respect to the Fermi energy.

Dhungana, Kamal B.; Pati, Ranjit, E-mail: patir@mtu.edu [Department of Physics, Michigan Technological University, Houghton, Michigan 49931 (United States)

2014-04-21T23:59:59.000Z

160

The susceptibility of silicon-ion implanted gate insulators to x-ray radiation-induced defect generation  

SciTech Connect (OSTI)

This paper examines the x-ray susceptibility of silicon-ion implanted gate insulators of insulated gate-field effect transistors (IGFETs). It is found that silicon-ion implanted gate insulators appear to be much more susceptible to x-ray radiation induced defect generation than unimplanted devices. The residual defect density in silicon-implanted devices, following x-ray radiation, and subsequent postmetal annealing for up to 60 min is found to be greater than that in unimplanted devices. The results with silicon ions indicate that if the insulator is damaged by such a species during processing, as might occur due to knock-on from the gate electrode during source/drain formation, unannealable defects will form which would also tend to make the device structure more susceptible to radiation damage in a hostile environment, or to large hot- electron drift in conventional use.

Reisman, A.; Sune, C.T.; Williams, C.K. (MCNC, Research Triangle Park, NC (US))

1991-03-01T23:59:59.000Z

Note: This page contains sample records for the topic "transistor gate oxide" from the National Library of EnergyBeta (NLEBeta).
While these samples are representative of the content of NLEBeta,
they are not comprehensive nor are they the most current set.
We encourage you to perform a real-time search of NLEBeta
to obtain the most current and comprehensive results.


161

Conductance modulation in topological insulator Bi{sub 2}Se{sub 3} thin films with ionic liquid gating  

SciTech Connect (OSTI)

A Bi{sub 2}Se{sub 3} topological insulator field effect transistor is investigated by using ionic liquid as an electric double layer gating material, leading to a conductance modulation of 365% at room temperature. We discuss the role of charged impurities on the transport properties. The conductance modulation with gate bias is due to a change in the carrier concentration, whereas the temperature dependent conductance change is originated from a change in mobility. Large conductance modulation at room temperature along with the transparent optical properties makes topological insulators as an interesting (opto)electronic material.

Son, Jaesung; Banerjee, Karan; Yang, Hyunsoo, E-mail: eleyang@nus.edu.sg [Department of Electrical and Computer Engineering, National University of Singapore, 4 Engineering Drive 3, Singapore 117576 (Singapore)] [Department of Electrical and Computer Engineering, National University of Singapore, 4 Engineering Drive 3, Singapore 117576 (Singapore); Brahlek, Matthew; Koirala, Nikesh; Oh, Seongshik [Department of Physics and Astronomy, Rutgers, The State University of New Jersey, 136 Frelinghuysen Road, Piscataway, New Jersey 08854 (United States)] [Department of Physics and Astronomy, Rutgers, The State University of New Jersey, 136 Frelinghuysen Road, Piscataway, New Jersey 08854 (United States); Lee, Seoung-Ki [School of Advanced Materials Science and Engineering, Sungkyunkwan University, Suwon 440-746 (Korea, Republic of) [School of Advanced Materials Science and Engineering, Sungkyunkwan University, Suwon 440-746 (Korea, Republic of); School of Electrical and Electronic Engineering, Yonsei University, Seoul 120-749 (Korea, Republic of); Ahn, Jong-Hyun [School of Electrical and Electronic Engineering, Yonsei University, Seoul 120-749 (Korea, Republic of)] [School of Electrical and Electronic Engineering, Yonsei University, Seoul 120-749 (Korea, Republic of)

2013-11-18T23:59:59.000Z

162

Spin effects in single-electron transistors  

E-Print Network [OSTI]

Basic electron transport phenomena observed in single-electron transistors (SETs) are introduced, such as Coulomb-blockade diamonds, inelastic cotunneling thresholds, the spin-1/2 Kondo effect, and Fano interference. With ...

Granger, Ghislain

2005-01-01T23:59:59.000Z

163

Method of fabrication of display pixels driven by silicon thin film transistors  

DOE Patents [OSTI]

Display pixels driven by silicon thin film transistors are fabricated on plastic substrates for use in active matrix displays, such as flat panel displays. The process for forming the pixels involves a prior method for forming individual silicon thin film transistors on low-temperature plastic substrates. Low-temperature substrates are generally considered as being incapable of withstanding sustained processing temperatures greater than about 200.degree. C. The pixel formation process results in a complete pixel and active matrix pixel array. A pixel (or picture element) in an active matrix display consists of a silicon thin film transistor (TFT) and a large electrode, which may control a liquid crystal light valve, an emissive material (such as a light emitting diode or LED), or some other light emitting or attenuating material. The pixels can be connected in arrays wherein rows of pixels contain common gate electrodes and columns of pixels contain common drain electrodes. The source electrode of each pixel TFT is connected to its pixel electrode, and is electrically isolated from every other circuit element in the pixel array.

Carey, Paul G. (Mountain View, CA); Smith, Patrick M. (San Ramon, CA)

1999-01-01T23:59:59.000Z

164

Penn State DOE GATE Program  

SciTech Connect (OSTI)

The Graduate Automotive Technology Education (GATE) Program at The Pennsylvania State University (Penn State) was established in October 1998 pursuant to an award from the U.S. Department of Energy (U.S. DOE). The focus area of the Penn State GATE Program is advanced energy storage systems for electric and hybrid vehicles.

Anstrom, Joel

2012-08-31T23:59:59.000Z

165

Developing Language Processing Components with GATE  

E-Print Network [OSTI]

Developing Language Processing Components with GATE (a User Guide) For GATE version 3 beta 1 (July.3 Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.4 [D] Get Started

Maynard, Diana

166

Wafer-scale solution-derived molecular gate dielectrics for low-voltage graphene electronics  

SciTech Connect (OSTI)

Graphene field-effect transistors are integrated with solution-processed multilayer hybrid organic-inorganic self-assembled nanodielectrics (SANDs). The resulting devices exhibit low-operating voltage (2?V), negligible hysteresis, current saturation with intrinsic gain >1.0 in vacuum (pressure?gate dielectrics. Statistical analysis of the field-effect mobility and residual carrier concentration demonstrate high spatial uniformity of the dielectric interfacial properties and graphene transistor characteristics over full 3 in. wafers. This work thus establishes SANDs as an effective platform for large-area, high-performance graphene electronics.

Sangwan, Vinod K.; Jariwala, Deep; McMorrow, Julian J.; He, Jianting; Lauhon, Lincoln J. [Department of Materials Science and Engineering, Northwestern University, Evanston, Illinois 60208 (United States); Everaerts, Ken [Department of Chemistry, Northwestern University, Evanston, Illinois 60208 (United States); Grayson, Matthew [Department of Electrical Engineering and Computer Science, Northwestern University, Evanston, Illinois 60208 (United States); Marks, Tobin J., E-mail: t-marks@northwestern.edu, E-mail: m-hersam@northwestern.edu; Hersam, Mark C., E-mail: t-marks@northwestern.edu, E-mail: m-hersam@northwestern.edu [Department of Materials Science and Engineering, Northwestern University, Evanston, Illinois 60208 (United States); Department of Chemistry, Northwestern University, Evanston, Illinois 60208 (United States)

2014-02-24T23:59:59.000Z

167

Low temperature thin film transistors with hollow cathode plasma-assisted atomic layer deposition based GaN channels  

SciTech Connect (OSTI)

We report GaN thin film transistors (TFT) with a thermal budget below 250?°C. GaN thin films are grown at 200?°C by hollow cathode plasma-assisted atomic layer deposition (HCPA-ALD). HCPA-ALD-based GaN thin films are found to have a polycrystalline wurtzite structure with an average crystallite size of 9.3?nm. TFTs with bottom gate configuration are fabricated with HCPA-ALD grown GaN channel layers. Fabricated TFTs exhibit n-type field effect characteristics. N-channel GaN TFTs demonstrated on-to-off ratios (I{sub ON}/I{sub OFF}) of 10{sup 3} and sub-threshold swing of 3.3?V/decade. The entire TFT device fabrication process temperature is below 250?°C, which is the lowest process temperature reported for GaN based transistors, so far.

Bolat, S., E-mail: bolat@ee.bilkent.edu.tr, E-mail: aokyay@ee.bilkent.edu.tr; Tekcan, B. [Department of Electrical and Electronics Engineering, Bilkent University, Ankara 06800 (Turkey); UNAM, National Nanotechnology Research Center, Bilkent University, Ankara 06800 (Turkey); Ozgit-Akgun, C.; Biyikli, N. [UNAM, National Nanotechnology Research Center, Bilkent University, Ankara 06800 (Turkey); Institute of Materials Science and Nanotechnology, Bilkent University, Ankara 06800 (Turkey); Okyay, A. K., E-mail: bolat@ee.bilkent.edu.tr, E-mail: aokyay@ee.bilkent.edu.tr [Department of Electrical and Electronics Engineering, Bilkent University, Ankara 06800 (Turkey); UNAM, National Nanotechnology Research Center, Bilkent University, Ankara 06800 (Turkey); Institute of Materials Science and Nanotechnology, Bilkent University, Ankara 06800 (Turkey)

2014-06-16T23:59:59.000Z

168

High Performance Lateral Schottky Collector Bipolar Transistors on SOI  

E-Print Network [OSTI]

C-emitter lateral NPM Schottky collector transistor. To study the novel characteristics of these lateral Schottky junction of the proposed lateral PNM (NPM) transistor consists of a Schottky junction between N-base (P

Kumar, M. Jagadesh

169

Graphene nanopore field effect transistors  

SciTech Connect (OSTI)

Graphene holds great promise for replacing conventional Si material in field effect transistors (FETs) due to its high carrier mobility. Previously proposed graphene FETs either suffer from low ON-state current resulting from constrained channel width or require complex fabrication processes for edge-defecting or doping. Here, we propose an alternative graphene FET structure created on intrinsic metallic armchair-edged graphene nanoribbons with uniform width, where the channel region is made semiconducting by drilling a pore in the interior, and the two ends of the nanoribbon act naturally as connecting electrodes. The proposed GNP-FETs have high ON-state currents due to seamless atomic interface between the channel and electrodes and are able to be created with arbitrarily wide ribbons. In addition, the performance of GNP-FETs can be tuned by varying pore size and ribbon width. As a result, their performance and fabrication process are more predictable and controllable in comparison to schemes based on edge-defects and doping. Using first-principle transport calculations, we show that GNP-FETs can achieve competitive leakage current of ?70?pA, subthreshold swing of ?60?mV/decade, and significantly improved On/Off current ratios on the order of 10{sup 5} as compared with other forms of graphene FETs.

Qiu, Wanzhi; Skafidas, Efstratios, E-mail: sskaf@unimelb.edu.au [Centre for Neural Engineering, The University of Melbourne, 203 Bouverie Street, Carlton, Victoria 3053 (Australia); Department of Electrical and Electronic Engineering, The University of Melbourne, Parkville, Victoria 3010 (Australia)

2014-07-14T23:59:59.000Z

170

Carbon Nanotube Field-effect Transistors: AC Performance Capabilities.  

E-Print Network [OSTI]

Carbon Nanotube Field-effect Transistors: AC Performance Capabilities. D.L. Pulfrey, D.L. John-barrier carbon nanotube field-effect transistors are examined via simulations using a self-consistent Schrödinger is known about the DC capabilities of carbon nanotube field-effect transistors [1,2,3], and devices

Pulfrey, David L.

171

Fermi-level shifts in graphene transistors with dual-cut channels scraped by atomic force microscope tips  

SciTech Connect (OSTI)

We investigate the electronic properties of p-type graphene transistors on silicon dioxide with dual-cut channels that were scraped using atomic force microscope tips. In these devices, the current is forced to squeeze into the path between the two cuts rather than flow directly through the graphene sheet. We observe that the gate voltages with minimum current shift toward zero bias as the sizes of the dual-cut regions increase. These phenomena suggest that the Fermi levels in the dual-cut regions are shifted toward the Dirac points after the mechanical scraping process.

Lin, Meng-Yu [Institute of Electronics, National Taiwan University, Taipei 10617, Taiwan (China); Research Center for Applied Sciences, Academia Sinica, Taipei 11529, Taiwan (China); Chen, Yen-Hao [Department of Photonics, National Chiao Tung University, Hsinchu 30010, Taiwan (China); Su, Chen-Fung [College of Photonics, National Chiao Tung University, Tainan 71150, Taiwan (China); Chang, Shu-Wei [Research Center for Applied Sciences, Academia Sinica, Taipei 11529, Taiwan (China); Department of Photonics, National Chiao Tung University, Hsinchu 30010, Taiwan (China); Lee, Si-Chen [Institute of Electronics, National Taiwan University, Taipei 10617, Taiwan (China); Lin, Shih-Yen, E-mail: shihyen@gate.sinica.edu.tw [Institute of Electronics, National Taiwan University, Taipei 10617, Taiwan (China); Research Center for Applied Sciences, Academia Sinica, Taipei 11529, Taiwan (China); Department of Photonics, National Chiao Tung University, Hsinchu 30010, Taiwan (China)

2014-01-13T23:59:59.000Z

172

Non-Hermitian quantum gates are more common than Hermitian quantum gates  

E-Print Network [OSTI]

Most of the frequently used quantum gates (e.g., NOT, Hadamard, CNOT, SWAP, Toffoli, Fredkin and Pauli gates) are self-inverse (Hermitian). However, with a simple minded argument it is established that most of the allowed quantum gates are non-Hermitian (non-self-inverse). It is also shown that the % of non-Hermitian gates increases with the dimension. For example, 58.33% of the 2-qubit gates, 98.10% of the 3-qubit gates and 99.99% of the 4-qubit gates are non-Hermitian. As classical reversible gates are essentially permutation gates so the above statistics is strictly valid for classical reversible gates. Further, since Hermiticity is not of much interest in context of the classical reversible gate, hence the result implies that most of the allowed classical reversible gates are non-self-inverse.

Anirban Pathak

2013-09-16T23:59:59.000Z

173

Electronics MOS Field-Effect Transistors  

E-Print Network [OSTI]

Department of Electrical and Computer Engineering #12;NMOS Physical StructureNMOS Physical Structure p-Martinez - 1 - Jose Silva-Martinez Texas A&M University Department of Electrical Engineering Analog and Mixed substrate N+ N+ VS=0 VG>0 VD=0 P P+ B D S B G N-type transistorInversion: channel is created D-S current

Palermo, Sam

174

Gallium nitride junction field-effect transistor  

DOE Patents [OSTI]

An all-ion implanted gallium-nitride (GaN) junction field-effect transistor (JFET) and method of making the same. Also disclosed are various ion implants, both n- and p-type, together with or without phosphorous co-implantation, in selected III-V semiconductor materials.

Zolper, John C. (Albuquerque, NM); Shul, Randy J. (Albuquerque, NM)

1999-01-01T23:59:59.000Z

175

GaSb molecular beam epitaxial growth on p-InP(001) and passivation with in situ deposited Al{sub 2}O{sub 3} gate oxide  

SciTech Connect (OSTI)

The integration of high carrier mobility materials into future CMOS generations is presently being studied in order to increase drive current capability and to decrease power consumption in future generation CMOS devices. If III-V materials are the candidates of choice for n-type channel devices, antimonide-based semiconductors present high hole mobility and could be used for p-type channel devices. In this work we first demonstrate the heteroepitaxy of fully relaxed GaSb epilayers on InP(001) substrates. In a second part, the properties of the Al{sub 2}O{sub 3}/GaSb interface have been studied by in situ deposition of an Al{sub 2}O{sub 3} high-{kappa} gate dielectric. The interface is abrupt without any substantial interfacial layer, and is characterized by high conduction and valence band offsets. Finally, MOS capacitors show well-behaved C-V with relatively low D{sub it} along the bandgap, these results point out an efficient electrical passivation of the Al{sub 2}O{sub 3}/GaSb interface.

Merckling, C.; Brammertz, G.; Hoffmann, T. Y.; Caymax, M.; Dekoster, J. [Interuniversity Microelectronics Center (IMEC vzw), Kapeldreef 75, 3001, Leuven (Belgium); Sun, X. [Katholieke Universiteit Leuven, Celestijnelaan 200D, 3001, Leuven (Belgium); Department of Electrical Engineering, Yale University, New Haven, Connecticut 06520-8284 (United States); Alian, A.; Heyns, M. [Interuniversity Microelectronics Center (IMEC vzw), Kapeldreef 75, 3001, Leuven (Belgium); Katholieke Universiteit Leuven, Celestijnelaan 200D, 3001, Leuven (Belgium); Afanas'ev, V. V. [Katholieke Universiteit Leuven, Celestijnelaan 200D, 3001, Leuven (Belgium)

2011-04-01T23:59:59.000Z

176

Gate-Dependent Carrier Diffusion Length in Lead Selenide Quantum Dot Field-Effect Transistors  

E-Print Network [OSTI]

-generation solar panels. Strongly confined QDs such as lead selenide (PbSe) also have the potential to benefit from- generation photovoltaic devices and sensitive photodetec- tors.1-3 The potential for low fabrication cost improvements are still necessary for QD solar cells to compete with commercial technologies. In particular

Yu, Dong

177

Solution-gated graphene transistors for chemical and biological sensing applications  

E-Print Network [OSTI]

Various fabrication processes were developed in order to make graphene-based chemical and biological sensors on different substrates. Single-layer graphene is grown by chemical vapor deposition and then transferred to ...

Mailly, Benjamin

2013-01-01T23:59:59.000Z

178

Halogen-Based Plasma Etching of Novel Field-Effect Transistor Gate Materials  

E-Print Network [OSTI]

Surface Interactions in Fluorocarbon Etching of Silicon2706. Xu, S.L. , et al. , Fluorocarbon polymer formation,

Kiehlbaugh, Kasi Michelle

2009-01-01T23:59:59.000Z

179

Improved Stability Of Amorphous Zinc Tin Oxide Thin Film Transistors...  

Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

shifts, as opposed to charge injection into the dielectric or trapping due to oxygen vacancies. Citation: Rajachidambaram MS, A Pandey, S Vilayur Ganapathy, P Nachimuthu, S...

180

Radio-frequency dispersive detection of donor atoms in a field-effect transistor  

SciTech Connect (OSTI)

Radio-frequency dispersive read-out can provide a useful probe to nano-scale structures, such as nano-wire devices, especially, when the implementation of charge sensing is not straightforward. Here, we demonstrate dispersive “gate-only” read-out of phosphor donors in a silicon nano-scale transistor. The technique enables access to states that are only tunnel-coupled to one contact, which is not easily achievable by other methods. This allows us to locate individual randomly placed donors in the device channel. Furthermore, the setup is naturally compatible with high bandwidth access to the probed donor states and may aid the implementation of a qubit based on coupled donors.

Verduijn, J., E-mail: a.verduijn@unsw.edu.au; Rogge, S. [Centre for Quantum Computation and Communication Technology, University of New South Wales, Sydney NSW 2052 (Australia)] [Centre for Quantum Computation and Communication Technology, University of New South Wales, Sydney NSW 2052 (Australia); Vinet, M. [CEA/LETI-MINATEC, CEA-Grenoble, 17 rue des martyrs, F-38054 Grenoble (France)] [CEA/LETI-MINATEC, CEA-Grenoble, 17 rue des martyrs, F-38054 Grenoble (France)

2014-03-10T23:59:59.000Z

Note: This page contains sample records for the topic "transistor gate oxide" from the National Library of EnergyBeta (NLEBeta).
While these samples are representative of the content of NLEBeta,
they are not comprehensive nor are they the most current set.
We encourage you to perform a real-time search of NLEBeta
to obtain the most current and comprehensive results.


181

Single qubit, two qubit gates and no signalling principle  

E-Print Network [OSTI]

In this work we investigate that whether one can construct single and two qubit gates for arbitrary quantum states from the principle of no signalling. We considered the problem for Pauli gates, Hadamard gate, C-Not gate.

Indranil Chakrabarty

2009-01-31T23:59:59.000Z

182

Free electron gas primary thermometer: The bipolar junction transistor  

SciTech Connect (OSTI)

The temperature of a bipolar transistor is extracted probing its carrier energy distribution through its collector current, obtained under appropriate polarization conditions, following a rigorous mathematical method. The obtained temperature is independent of the transistor physical properties as current gain, structure (Homo-junction or hetero-junction), and geometrical parameters, resulting to be a primary thermometer. This proposition has been tested using off the shelf silicon transistors at thermal equilibrium with water at its triple point, the transistor temperature values obtained involve an uncertainty of a few milli-Kelvin. This proposition has been successfully tested in the temperature range of 77–450?K.

Mimila-Arroyo, J., E-mail: jmimila@cinvestav.mx [Centro de Investigación y de Estudios Avanzados del Instituto Politécnico Nacional, Dpto. de Ing. Eléctrica-SEES, Av. Instituto Politécnico Nacional No 2508, México D.F. CP 07360 (Mexico)

2013-11-04T23:59:59.000Z

183

The role of oxygen in hydrogen sensing by a platinum-gate silicon carbide gas sensor: An ultrahigh vacuum study  

E-Print Network [OSTI]

The role of oxygen in hydrogen sensing by a platinum-gate silicon carbide gas sensor: An ultrahigh conditions that elucidate the role of oxygen in the functioning of silicon carbide field-effect gas sensors hydrogen-depleted state; competition between hydrogen oxidation and hydrogen diffusion to metal/ oxide

Tobin, Roger G.

184

Rational Design and Preparation of Organic Semiconductors for use in Field Effect Transistors and Photovoltaic Cells  

E-Print Network [OSTI]

in thin film organic photovoltaic cells (OPVs) is presented.Effect Transistors and Photovoltaic Cells By Clayton EdwardEffect Transistors and Photovoltaic Cells By Clayton Edward

Mauldin, Clayton Edward

2010-01-01T23:59:59.000Z

185

Doping suppression and mobility enhancement of graphene transistors fabricated using an adhesion promoting dry transfer process  

SciTech Connect (OSTI)

We present the facile dry transfer of graphene synthesized via chemical vapor deposition on copper film to a functional device substrate. High quality uniform dry transfer of graphene to oxidized silicon substrate was achieved by exploiting the beneficial features of a poly(4-vinylphenol) adhesive layer involving a strong adhesion energy to graphene and negligible influence on the electronic and structural properties of graphene. The graphene field effect transistors (FETs) fabricated using the dry transfer process exhibit excellent electrical performance in terms of high FET mobility and low intrinsic doping level, which proves the feasibility of our approach in graphene-based nanoelectronics.

Cheol Shin, Woo; Hun Mun, Jeong; Yong Kim, Taek; Choi, Sung-Yool; Jin Cho, Byung, E-mail: bjcho@kaist.edu, E-mail: tskim1@kaist.ac.kr [Department of Electrical Engineering, Graphene Research Center, KAIST, 373-1 Guseong-dong, Yuseong-gu, Daejeon 305-701 (Korea, Republic of); Yoon, Taeshik; Kim, Taek-Soo, E-mail: bjcho@kaist.edu, E-mail: tskim1@kaist.ac.kr [Department of Mechanical Engineering, Graphene Research Center, KAIST, 373-1 Guseong-dong, Yuseong-gu, Daejeon 305-701 (Korea, Republic of)] [Department of Mechanical Engineering, Graphene Research Center, KAIST, 373-1 Guseong-dong, Yuseong-gu, Daejeon 305-701 (Korea, Republic of)

2013-12-09T23:59:59.000Z

186

Composite two-qubit quantum gates  

E-Print Network [OSTI]

We design composite two-qubit gates, based on the Ising-type interaction. The gates are robust against systematic errors in the qubits' interaction strength and the gate's implementation time. We give composite sequences, which cancel the error up to 6th order, and give a method to achieve even higher accuracy. Our sequences can compensate either relative or absolute errors. For relative error compensation the number of the ingredient gates grows linearly with the desired accuracy, while for absolute compensation only two gates are required to achieve infinitely accurate gates. We also consider an ion-trap implementation of our composite gates, where our sequences achieve simultaneous cancellation of the error in both the pulse area and the detuning.

Svetoslav S. Ivanov; Nikolay V. Vitanov

2015-03-30T23:59:59.000Z

187

Design, fabrication, and analysis of p-channel arsenide/antimonide hetero-junction tunnel transistors  

SciTech Connect (OSTI)

In this paper, we demonstrate InAs/GaSb hetero-junction (hetJ) and GaSb homo-junction (homJ) p-channel tunneling field effect transistors (pTFET) employing a low temperature atomic layer deposited high-? gate dielectric. HetJ pTFET exhibited drive current of 35 ?A/?m in comparison to homJ pTFET, which exhibited drive current of 0.3 ?A/?m at V{sub DS}?=??0.5?V under DC biasing conditions. Additionally, with pulsing of 1 ?s gate voltage, hetJ pTFET exhibited enhanced drive current of 85 ?A/?m at V{sub DS}?=??0.5?V, which is the highest reported in the category of III-V pTFET. Detailed device characterization was performed through analysis of the capacitance-voltage characteristics, pulsed current-voltage characteristics, and x-ray diffraction studies.

Rajamohanan, Bijesh, E-mail: bor5067@psu.edu; Mohata, Dheeraj; Hollander, Matthew; Datta, Suman [Department of Electrical Engineering, The Pennsylvania State University, University Park, Pennsylvania 16802 (United States); Zhu, Yan; Hudait, Mantu [Bradley Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, Virginia 24061 (United States); Jiang, Zhengping; Klimeck, Gerhard [Department of Electrical and Computer Engineering, Purdue University, West Lafayette, Indiana 47906 (United States)

2014-01-28T23:59:59.000Z

188

Diamond logic inverter with enhancement-mode metal-insulator-semiconductor field effect transistor  

SciTech Connect (OSTI)

A diamond logic inverter is demonstrated using an enhancement-mode hydrogenated-diamond metal-insulator-semiconductor field effect transistor (MISFET) coupled with a load resistor. The gate insulator has a bilayer structure of a sputtering-deposited LaAlO{sub 3} layer and a thin atomic-layer-deposited Al{sub 2}O{sub 3} buffer layer. The source-drain current maximum, extrinsic transconductance, and threshold voltage of the MISFET are measured to be ?40.7?mA·mm{sup ?1}, 13.2?±?0.1?mS·mm{sup ?1}, and ?3.1?±?0.1?V, respectively. The logic inverters show distinct inversion (NOT-gate) characteristics for input voltages ranging from 4.0 to ?10.0?V. With increasing the load resistance, the gain of the logic inverter increases from 5.6 to as large as 19.4. The pulse response against the high and low input voltages shows the inversion response with the low and high output voltages.

Liu, J. W., E-mail: liu.jiangwei@nims.go.jp [International Center for Young Scientists (ICYS), National Institute for Materials Science (NIMS), 1-1 Namiki, Tsukuba, Ibaraki 305-0044 (Japan); Liao, M. Y.; Imura, M. [Optical and Electronic Materials Unit, NIMS, 1-1 Namiki, Tsukuba, Ibaraki 305-0044 (Japan); Watanabe, E.; Oosato, H. [Nanofabrication Platform, NIMS, 1-2-1 Sengen, Tsukuba, Ibaraki 305-0047 (Japan); Koide, Y., E-mail: koide.yasuo@nims.go.jp [Optical and Electronic Materials Unit, NIMS, 1-1 Namiki, Tsukuba, Ibaraki 305-0044 (Japan); Nanofabrication Platform, NIMS, 1-2-1 Sengen, Tsukuba, Ibaraki 305-0047 (Japan); Center of Materials Research for Low Carbon Emission, NIMS, 1-1 Namiki, Tsukuba, Ibaraki 305-0044 (Japan)

2014-08-25T23:59:59.000Z

189

Sulfur surface chemistry on the platinum gate of a silicon carbide based hydrogen sensor  

E-Print Network [OSTI]

monitoring, solid-oxide fuel cells, and coal gasification, require operation at much higher temperatures thanSulfur surface chemistry on the platinum gate of a silicon carbide based hydrogen sensor Yung Ho to hydrogen sulfide, even in the presence of hydrogen or oxygen at partial pressures of 20­600 times greater

Tobin, Roger G.

190

Low-temperature processable amorphous In-W-O thin-film transistors with high mobility and stability  

SciTech Connect (OSTI)

Thin-film transistors (TFTs) with a high stability and a high field-effect mobility have been achieved using W-doped indium oxide semiconductors in a low-temperature process (?150?°C). By incorporating WO{sub 3} into indium oxide, TFTs that were highly stable under a negative bias stress were reproducibly achieved without high-temperature annealing, and the degradation of the field-effect mobility was not pronounced. This may be due to the efficient suppression of the excess oxygen vacancies in the film by the high dissociation energy of the bond between oxygen and W atoms and to the different charge states of W ions.

Kizu, Takio; Aikawa, Shinya; Mitoma, Nobuhiko; Shimizu, Maki; Gao, Xu; Lin, Meng-Fang; Tsukagoshi, Kazuhito, E-mail: TSUKAGOSHI.Kazuhito@nims.go.jp [International Center for Materials Nanoarchitectonics (WPI-MANA), National Institute for Materials Science (NIMS), 1-1 Namiki, Tsukuba, Ibaraki 305-0044 (Japan); Nabatame, Toshihide [MANA Foundry and MANA Advanced Device Materials Group, National Institute for Materials Science (NIMS), 1-1 Namiki, Tsukuba, Ibaraki 305-0044 (Japan)

2014-04-14T23:59:59.000Z

191

Flexible Graphene Field-Effect Transistors for Microwave Electronics  

E-Print Network [OSTI]

Flexible Graphene Field-Effect Transistors for Microwave Electronics Inanc Meric , Nicholas Petrone-frequency characteristics of graphene field-effect transistors (GFETs) has received significant interest due the very high carrier velocities in graphene. In addition to excellent electronic performance, graphene possesses

Shepard, Kenneth

192

aluminum oxide thin: Topics by E-print Network  

Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

DEVICE LETTERS, VOL. 19, NO. 12, DECEMBER 1998 High-Performance Polycrystalline SiGe Thin-Film Materials Science Websites Summary: --The use of aluminum oxide as the gate...

193

Comparative study of InGaP/GaAs high electron mobility transistors with upper and lower delta-doped supplied layers  

SciTech Connect (OSTI)

Influence corresponding to the position of {delta}-doped supplied layer on InGaP/GaAs high electron mobility transistors is comparatively studied by two-dimensional simulation analysis. The simulated results exhibit that the device with lower {delta}-doped supplied layer shows a higher gate potential barrier height, a higher saturation output current, a larger magnitude of negative threshold voltage, and broader gate voltage swing, as compared to the device with upper {delta}-doped supplied layer. Nevertheless, it has smaller transconductance and inferior high-frequency characteristics in the device with lower {delta}-doped supplied layer. Furthermore, a knee effect in current-voltage curves is observed at low drain-to-source voltage in the two devices, which is investigated in this article.

Tsai, Jung-Hui, E-mail: jhtsai@nknucc.nknu.edu.tw; Ye, Sheng-Shiun [National Kaohsiung Normal University, Department of Electronic Engineering, Taiwan (China); Guo, Der-Feng [Air Force Academy, Kaohsiung, Department of Electronic Engineering, Taiwan (China); Lour, Wen-Shiung [National Taiwan Ocean University, Department of Electrical Engineering, Taiwan (China)

2012-04-15T23:59:59.000Z

194

Combined Transistor Sizing with Bu er Insertion for Timing Optimization  

E-Print Network [OSTI]

, to achieve bet- ter power-delay and area-delay tradeo s. The delay model incorporates placement-based information and the e ect of input slew rates on gate delays. The re- sults obtained by using the new method gate Gi is mod- eled by an equivalent inverter. The relation between the gate sizes in the equivalent

Sapatnekar, Sachin

195

Quantum logic gates for superconducting resonator qudits  

SciTech Connect (OSTI)

We study quantum information processing using superpositions of Fock states in superconducting resonators as quantum d-level systems (qudits). A universal set of single and coupled logic gates is theoretically proposed for resonators coupled by superconducting circuits of Josephson junctions. These gates use experimentally demonstrated interactions and provide an attractive route to quantum information processing using harmonic oscillator modes.

Strauch, Frederick W. [Williams College, Williamstown, Massachusetts 01267 (United States)

2011-11-15T23:59:59.000Z

196

Automatically closing swing gate closure assembly  

DOE Patents [OSTI]

A swing gate closure assembly for nuclear reactor tipoff assembly wherein the swing gate is cammed open by a fuel element or spacer but is reliably closed at a desired closing rate primarily by hydraulic forces in the absence of a fuel charge.

Chang, Shih-Chih (Richland, WA); Schuck, William J. (Richland, WA); Gilmore, Richard F. (Kennewick, WA)

1988-01-01T23:59:59.000Z

197

GATE Center of Excellence at UAB in Lightweight Materials for...  

Broader source: Energy.gov (indexed) [DOE]

GATE Center of Excellence at UAB in Lightweight Materials for Automotive Applications GATE Center of Excellence at UAB in Lightweight Materials for Automotive Applications 2011 DOE...

198

PENN STATE DOE GRADUATE AUTOMOTIVE TECHNOLOGY EDUCATION (GATE...  

Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

PENN STATE DOE GRADUATE AUTOMOTIVE TECHNOLOGY EDUCATION (GATE) PROGRAM FOR PENN STATE DOE GRADUATE AUTOMOTIVE TECHNOLOGY EDUCATION (GATE) PROGRAM FOR 2009 DOE Hydrogen Program and...

199

GATE Center of Excellence at UAB in Lightweight Materials for...  

Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

& Publications GATE Center of Excellence at UAB in Lightweight Materials for Automotive Applications GATE Center of Excellence at UAB in Lightweight Materials for...

200

Vehicle Technologies Office Merit Review 2014: GATE Center of...  

Broader source: Energy.gov (indexed) [DOE]

GATE Center of Excellence at UAB for Lightweight Materials and Manufacturing for Automotive, Truck and Mass Transit. ti026vaidya2014p.pdf More Documents & Publications GATE...

Note: This page contains sample records for the topic "transistor gate oxide" from the National Library of EnergyBeta (NLEBeta).
While these samples are representative of the content of NLEBeta,
they are not comprehensive nor are they the most current set.
We encourage you to perform a real-time search of NLEBeta
to obtain the most current and comprehensive results.


201

Penn State DOE Graduate Automotive Technology Education (Gate...  

Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

DOE Graduate Automotive Technology Education (Gate) Program for In-Vehicle, High-Power Energy Storage Systems Penn State DOE Graduate Automotive Technology Education (Gate)...

202

University of Illinois at Urbana-Champaign's GATE Center for...  

Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

Urbana-Champaign's GATE Center for Advanced Automotive Bio-Fuel Combustion Engines University of Illinois at Urbana-Champaign's GATE Center for Advanced Automotive Bio-Fuel...

203

GATE Center of Excellence at UAB in Lightweight Materials for...  

Broader source: Energy.gov (indexed) [DOE]

vaidya.pdf More Documents & Publications GATE Center of Excellence at UAB in Lightweight Materials for Automotive Applications GATE Center of Excellence at UAB in Lightweight...

204

A Stochastic Approach for the Analysis of Fault Trees with Priority AND Gates  

E-Print Network [OSTI]

dependency gate PAND priority AND gate SEQ sequence enforcing gate WSP warm spare gate CSP cold spare gate time [1]. Failures can be disastrous for systems such as chemical plants, nuclear reactors, airplane gates that include the warm spare gate (WSP) and cold spare gate (CSP), and the functional dependency

Han, Jie

205

Focused Ion Beam Induced Effects on MOS Transistor Parameters  

SciTech Connect (OSTI)

We report on recent studies of the effects of 50 keV focused ion beam (FIB) exposure on MOS transistors. We demonstrate that the changes in value of transistor parameters (such as threshold voltage, V{sub t}) are essentially the same for exposure to a Ga+ ion beam at 30 and 50 keV under the same exposure conditions. We characterize the effects of FIB exposure on test transistors fabricated in both 0.5 {micro}m and 0.225 {micro}m technologies from two different vendors. We report on the effectiveness of overlying metal layers in screening MOS transistors from FIB-induced damage and examine the importance of ion dose rate and the physical dimensions of the exposed area.

Abramo, Marsha T.; Antoniou, Nicholas; Campbell, Ann N.; Fleetwood, Daniel M.; Hembree, Charles E.; Jessing, Jeffrey R.; Soden, Jerry M.; Swanson, Scot E.; Tangyunyong, Paiboon; Vanderlinde, William E.

1999-07-28T23:59:59.000Z

206

Proposal for a phase-coherent thermoelectric transistor  

E-Print Network [OSTI]

solution since their near perfect electron-hole symmetry leads to a negligible thermoelectric response; however, here we demonstrate theoretically a superconducting thermoelectric transistor which offers unparalleled figures of merit of up to ~ 45...

Giazotto, F.; Robinson, J. W. A.; Moodera, J. S.; Bergeret, F. S.

2014-01-01T23:59:59.000Z

207

Delay Analysis of Graphene Field-Effect Transistors  

E-Print Network [OSTI]

In this letter, we analyze the carrier transit delay in graphene field-effect transistors (GFETs).The extraction of the intrinsic delay provides a new way to directly estimate carrier velocity from the experimental data, ...

Wang, Han

208

Fabrication of graphene-on-GaN vertical transistors  

E-Print Network [OSTI]

The excellent transport properties of graphene make it an excellent option for very high frequency electronics. However, the poor output resistance and difficult lithography of lateral transistors significantly limit its ...

Zubair, Ahmad, S.M. Massachusetts Institute of Technology

2014-01-01T23:59:59.000Z

209

BN/Graphene/BN Transistors for RF Applications  

E-Print Network [OSTI]

In this letter, we demonstrate the first BN/graphene/BN field-effect transistor for RF applications. This device structure can preserve the high mobility and the high carrier velocity of graphene, even when it is sandwiched ...

Taychatanapat, Thiti

210

Simulation-based design of a strained graphene field effect transistor incorporating the pseudo magnetic field effect  

SciTech Connect (OSTI)

We present a numerical study on the performance of strained graphene-based field-effect transistors. A local strain less than 10% is applied over a central channel region of the graphene to induce the shift of the Dirac point in the channel region along the transverse momentum direction. The left and the right unstrained graphene regions are doped to be either n-type or p-type. By using the atomistic tight-binding model and a Green's function method, we predict that the gate voltage applied to the central strained graphene region can switch the drain current on and off with an on/off ratio of more than six orders of magnitude at room temperature. This is in spite of the absence of a bandgap in the strained channel region. Steeper subthreshold slopes below 60?mV/decade are also predicted at room temperature because of a mechanism similar to the band-to-band tunneling field-effect transistors.

Souma, Satofumi, E-mail: ssouma@harbor.kobe-u.ac.jp; Ueyama, Masayuki; Ogawa, Matsuto [Department of Electrical and Electronic Engineering, Kobe University, 1-1 Rokkodai, Nada, Kobe 657-8501 (Japan)

2014-05-26T23:59:59.000Z

211

Locking apparatus for gate valves  

DOE Patents [OSTI]

A locking apparatus for fluid operated valves having a piston connected to the valve actuator which moves in response to applied pressure within a cylinder housing having a cylinder head, a catch block is secured to the piston, and the cylinder head incorporates a catch pin. Pressure applied to the cylinder to open the valve moves the piston adjacent to the cylinder head where the catch pin automatically engages the catch block preventing futher movement of the piston or premature closure of the valve. Application of pressure to the cylinder to close the valve, retracts the catch pin, allowing the valve to close. Included are one or more selector valves, for selecting pressure application to other apparatus depending on the gate valve position, open or closed, protecting such apparatus from damage due to premature closing caused by pressure loss or operational error.

Fabyan, Joseph (Livermore, CA); Williams, Carl W. (Manteca, CA)

1988-01-01T23:59:59.000Z

212

Substrate dielectric effects on graphene field effect transistors  

SciTech Connect (OSTI)

Graphene is emerging as a promising material for future electronics and optoelectronics applications due to its unique electronic structure. Understanding the graphene-dielectric interaction is of vital importance for the development of graphene field effect transistors (FETs) and other novel graphene devices. Here, we extend the exploration of substrate dielectrics from conventionally used thermally grown SiO{sub 2} and hexagonal boron nitride films to technologically relevant deposited dielectrics used in semiconductor industry. A systematic analysis of morphology and optical and electrical properties was performed to study the effects of different substrates (SiO{sub 2}, HfO{sub 2}, Al{sub 2}O{sub 3}, tetraethyl orthosilicate (TEOS)-oxide, and Si{sub 3}N{sub 4}) on the carrier transport of chemical vapor deposition-derived graphene FET devices. As baseline, we use graphene FETs fabricated on thermal SiO{sub 2} with a relatively high carrier mobility of 10?000 cm{sup 2}/(V s). Among the deposited dielectrics studied, silicon nitride showed the highest mobility, comparable to the properties of graphene fabricated on thermal SiO{sub 2}. We conclude that this result comes from lower long range scattering and short range scattering rates in the nitride compared those in the other deposited films. The carrier fluctuation caused by substrates, however, seems to be the main contributing factor for mobility degradation, as a universal mobility-disorder density product is observed for all the dielectrics examined. The extrinsic doping trend is further confirmed by Raman spectra. We also provide, for the first time, correlation between the intensity ratio of G peak and 2D peak in the Raman spectra to the carrier mobility of graphene for different substrates.

Hu, Zhaoying; Prasad Sinha, Dhiraj; Ung Lee, Ji, E-mail: jlee1@albany.edu; Liehr, Michael [College of Nanoscale Science and Engineering, The State University of New York at Albany, Albany, New York 12203 (United States)

2014-05-21T23:59:59.000Z

213

Graduate Automotive Technology Education (GATE) Center  

SciTech Connect (OSTI)

The Graduate Automotive Technology Education (GATE) Center at the University of Tennessee, Knoxville has completed its sixth year of operation. During this period the Center has involved thirteen GATE Fellows and ten GATE Research Assistants in preparing them to contribute to advanced automotive technologies in the center's focus area: hybrid drive trains and control systems. Eighteen GATE students have graduated, and three have completed their course work requirements. Nine faculty members from three departments in the College of Engineering have been involved in the GATE Center. In addition to the impact that the Center has had on the students and faculty involved, the presence of the center has led to the acquisition of resources that probably would not have been obtained if the GATE Center had not existed. Significant industry interaction such as internships, equipment donations, and support for GATE students has been realized. The value of the total resources brought to the university (including related research contracts) exceeds $4,000,000. Problem areas are discussed in the hope that future activities may benefit from the operation of the current program.

Jeffrey Hodgson; David Irick

2005-09-30T23:59:59.000Z

214

Digital gate pulse generator for cycloconverter control  

DOE Patents [OSTI]

The present invention provides a digital gate pulse generator which controls the output of a cycloconverter used for electrical power conversion applications by determining the timing and delivery of the firing pulses to the switching devices in the cycloconverter. Previous gate pulse generators have been built with largely analog or discrete digital circuitry which require many precision components and periodic adjustment. The gate pulse generator of the present invention utilizes digital techniques and a predetermined series of values to develop the necessary timing signals for firing the switching device. Each timing signal is compared with a reference signal to determine the exact firing time. The present invention is significantly more compact than previous gate pulse generators, responds quickly to changes in the output demand and requires only one precision component and no adjustments.

Klein, Frederick F. (Monroeville, PA); Mutone, Gioacchino A. (Pleasant Hills, PA)

1989-01-01T23:59:59.000Z

215

Yuanmingyuan East Gate of Peking University  

E-Print Network [OSTI]

Dingxiangyuan Cafeteria SupermarketI Parking 32 Northeast Gate C Building C Swimming Hall East Playground and New Energy Technology 32 Institute of Education Schools & Departments A Foreign Student Affairs

Gu, Jin

216

GaTe semiconductor for radiation detection  

DOE Patents [OSTI]

GaTe semiconductor is used as a room-temperature radiation detector. GaTe has useful properties for radiation detectors: ideal bandgap, favorable mobilities, low melting point (no evaporation), non-hygroscopic nature, and availability of high-purity starting materials. The detector can be used, e.g., for detection of illicit nuclear weapons and radiological dispersed devices at ports of entry, in cities, and off shore and for determination of medical isotopes present in a patient.

Payne, Stephen A. (Castro Valley, CA); Burger, Arnold (Nashville, TN); Mandal, Krishna C. (Ashland, MA)

2009-06-23T23:59:59.000Z

217

Gate fidelity fluctuations and quantum process invariants  

SciTech Connect (OSTI)

We characterize the quantum gate fidelity in a state-independent manner by giving an explicit expression for its variance. The method we provide can be extended to calculate all higher order moments of the gate fidelity. Using these results, we obtain a simple expression for the variance of a single-qubit system and deduce the asymptotic behavior for large-dimensional quantum systems. Applications of these results to quantum chaos and randomized benchmarking are discussed.

Magesan, Easwar; Emerson, Joseph [Institute for Quantum Computing and Department of Applied Mathematics, University of Waterloo, Waterloo, Ontario N2L 3G1 (Canada); Blume-Kohout, Robin [Theoretical Division, Los Alamos National Laboratory, Los Alamos, New Mexico 87545 (United States)

2011-07-15T23:59:59.000Z

218

Nondestructive characterization of a TiN metal gate: Chemical and structural properties by means of standing-wave hard x-ray  

E-Print Network [OSTI]

Nondestructive characterization of a TiN metal gate: Chemical and structural properties by means (HXPS, HAXPES) is applied to a thick (100 A° ) film of a metal gate TiN grown on top of a Si/MoSi2 of TiN, as well as the buried interface between TiN and the native oxide on top of the mirror

Fadley, Charles

219

Effect of buffer structures on AlGaN/GaN high electron mobility transistor reliability  

SciTech Connect (OSTI)

AlGaN/GaN high electron mobility transistors (HEMTs) with three different types of buffer layers, including a GaN/AlGaN composite layer, or 1 or 2 lm GaN thick layers, were fabricated and their reliability compared. The HEMTs with the thick GaN buffer layer showed the lowest critical voltage (Vcri) during off-state drain step-stress, but this was increased by around 50% and 100% for devices with the composite AlGaN/GaN buffer layers or thinner GaN buffers, respectively. The Voff - state for HEMTs with thin GaN and composite buffers were 100 V, however, this degraded to 50 60V for devices with thick GaN buffers due to the difference in peak electric field near the gate edge. A similar trend was observed in the isolation breakdown voltage measurements, with the highest Viso achieved based on thin GaN or composite buffer designs (600 700 V), while a much smaller Viso of 200V was measured on HEMTs with the thick GaN buffer layers. These results demonstrate the strong influence of buffer structure and defect density on AlGaN/GaN HEMT performance and reliability.

Liu, L. [University of Florida, Gainesville; Xi, Y. Y. [University of Florida, Gainesville; Ren, F. [University of Florida; Pearton, S. J. [University of Florida; Laboutin, O. [Kopin Corporation, Taunton, MA; Cao, Yu [Kopin Corporation, Taunton, MA; Johnson, Wayne J. [Kopin Corporation, Taunton, MA; Kravchenko, Ivan I [ORNL

2012-01-01T23:59:59.000Z

220

Low temperature atomic layer deposited ZnO photo thin film transistors  

SciTech Connect (OSTI)

ZnO thin film transistors (TFTs) are fabricated on Si substrates using atomic layer deposition technique. The growth temperature of ZnO channel layers are selected as 80, 100, 120, 130, and 250?°C. Material characteristics of ZnO films are examined using x-ray photoelectron spectroscopy and x-ray diffraction methods. Stoichiometry analyses showed that the amount of both oxygen vacancies and interstitial zinc decrease with decreasing growth temperature. Electrical characteristics improve with decreasing growth temperature. Best results are obtained with ZnO channels deposited at 80?°C; I{sub on}/I{sub off} ratio is extracted as 7.8 × 10{sup 9} and subthreshold slope is extracted as 0.116 V/dec. Flexible ZnO TFT devices are also fabricated using films grown at 80?°C. I{sub D}–V{sub GS} characterization results showed that devices fabricated on different substrates (Si and polyethylene terephthalate) show similar electrical characteristics. Sub-bandgap photo sensing properties of ZnO based TFTs are investigated; it is shown that visible light absorption of ZnO based TFTs can be actively controlled by external gate bias.

Oruc, Feyza B.; Aygun, Levent E.; Donmez, Inci; Biyikli, Necmi; Okyay, Ali K., E-mail: aokyay@ee.bilkent.edu.tr [Institute of Materials Science and Nanotechnology, Bilkent University, Bilkent, 06800 Ankara (Turkey); UNAM—National Nanotechnology Research Center, Bilkent University, Bilkent, 06800 Ankara (Turkey); Department of Electrical and Electronics Engineering, Bilkent University, Bilkent, 06800 Ankara (Turkey); Yu, Hyun Yong [The School of Electrical Engineering, Korea University, Seoul 136-701 (Korea, Republic of)

2015-01-01T23:59:59.000Z

Note: This page contains sample records for the topic "transistor gate oxide" from the National Library of EnergyBeta (NLEBeta).
While these samples are representative of the content of NLEBeta,
they are not comprehensive nor are they the most current set.
We encourage you to perform a real-time search of NLEBeta
to obtain the most current and comprehensive results.


221

Investigation of the tunneling emitter bipolar transistor as spin-injector into silicon  

E-Print Network [OSTI]

In this thesis is discussed the tunneling emitter bipolar transistor as a possible spin-injector into silicon. The transistor has a metallic emitter which as a spin-injector will be a ferromagnet. Spin-polarized electrons ...

Van Veenhuizen, Marc Julien

2010-01-01T23:59:59.000Z

222

Graphene-on-Insulator Transistors Made Using C on Ni Chemical-Vapor Deposition  

E-Print Network [OSTI]

Graphene transistors are made by transferring a thin graphene film grown on Ni onto an insulating SiO[subscript 2] substrate. The properties and integration of these graphene-on-insulator transistors are presented and ...

Keast, Craig L.

223

Hydrogen passivation of electron trap in amorphous In-Ga-Zn-O thin-film transistors  

SciTech Connect (OSTI)

We report an experimental evidence that some hydrogens passivate electron traps in an amorphous oxide semiconductor, a-In-Ga-Zn-O (a-IGZO). The a-IGZO thin-film transistors (TFTs) annealed at 300?°C exhibit good operation characteristics; while those annealed at ?400?°C show deteriorated ones. Thermal desorption spectra (TDS) of H{sub 2}O indicate that this threshold annealing temperature corresponds to depletion of H{sub 2}O desorption from the a-IGZO layer. Hydrogen re-doping by wet oxygen annealing recovers the good TFT characteristic. The hydrogens responsible for this passivation have specific binding energies corresponding to the desorption temperatures of 300–430?°C. A plausible structural model is suggested.

Hanyu, Yuichiro, E-mail: y-hanyu@lucid.msl.titech.ac.jp; Domen, Kay [Materials and Structures Laboratory, Tokyo Institute of Technology, Yokohama (Japan)] [Materials and Structures Laboratory, Tokyo Institute of Technology, Yokohama (Japan); Nomura, Kenji [Frontier Research Center, Tokyo Institute of Technology, Yokohama (Japan)] [Frontier Research Center, Tokyo Institute of Technology, Yokohama (Japan); Hiramatsu, Hidenori; Kamiya, Toshio [Materials and Structures Laboratory, Tokyo Institute of Technology, Yokohama (Japan) [Materials and Structures Laboratory, Tokyo Institute of Technology, Yokohama (Japan); Materials Research Center for Element Strategy, Tokyo Institute of Technology, Yokohama (Japan); Kumomi, Hideya [Materials Research Center for Element Strategy, Tokyo Institute of Technology, Yokohama (Japan)] [Materials Research Center for Element Strategy, Tokyo Institute of Technology, Yokohama (Japan); Hosono, Hideo [Materials and Structures Laboratory, Tokyo Institute of Technology, Yokohama (Japan) [Materials and Structures Laboratory, Tokyo Institute of Technology, Yokohama (Japan); Frontier Research Center, Tokyo Institute of Technology, Yokohama (Japan); Materials Research Center for Element Strategy, Tokyo Institute of Technology, Yokohama (Japan)

2013-11-11T23:59:59.000Z

224

Paying the Toll: A Political History of the Golden Gate Bridge and Highway District, 1923-1971  

E-Print Network [OSTI]

Gate: the Construction of the Golden Gate Bridge and HighwayCommittee on Golden Gate Bridge and Highway District,versus the Golden Gate Bridge . . . . . . . . . . . . . . .

Dyble, Amy Louise Nelson

2003-01-01T23:59:59.000Z

225

Mechanics of thin-film transistors and solar cells on flexible substrates Helena Gleskova*  

E-Print Network [OSTI]

1 Mechanics of thin-film transistors and solar cells on flexible substrates Helena Gleskova* , I be minimized throughout the fabrication process. Amorphous silicon thin-film transistors and solar cells, thin-film transistor, solar cell, flexible electronics Phone: (609) 258-4626, Fax: (609) 258-3585, E

226

Behavior of the drain leakage current in metal-induced laterally crystallized thin lm transistors  

E-Print Network [OSTI]

Behavior of the drain leakage current in metal-induced laterally crystallized thin ®lm transistors crystallized (MILC) thin ®lm transistors (TFTs) are better than solid phase crystallized (SPC) TFTs in many. � 2000 Elsevier Science Ltd. All rights reserved. Keywords: Thin ®lm transistors; Leakage current

227

Voltage-gated Ion Channels and Gating Modifier Toxins William A. Catterall,* Sandrine Cestle,  

E-Print Network [OSTI]

;2 Abstract Voltage-gated sodium, calcium, and potassium channels generate electrical signals required and a pore loop. Their pores are formed by the S5/S6 segments and the pore loop between them and are gated and participate in calcium signaling pathways in nonexcitable cells. Because of their importance in many aspects

Paris-Sud XI, Université de

228

The Defeat of the Golden Gate Authority: Regional Planning and Local Power  

E-Print Network [OSTI]

Regional Politics and the Golden Gate Bridge, Philadelphia:Politics and the Golden Gate Bridge, won the Abel WolmanBridge and the Golden Gate Bridge. Moreover, interregional

Dyble, Louise Nelson

2012-01-01T23:59:59.000Z

229

Heralded quantum gates with integrated error detection in optical cavitites  

E-Print Network [OSTI]

We propose and analyze heralded quantum gates between qubits in optical cavities. They employ an auxiliary qubit to report if a successful gate occurred. In this manner, the errors, which would have corrupted a deterministic gate, are converted into a non-unity probability of success: once successful the gate has a much higher fidelity than a similar deterministic gate. Specifically, we describe that a heralded , near-deterministic controlled phase gate (CZ-gate) with the conditional error arbitrarily close to zero and the success probability that approaches unity as the cooperativity of the system, C, becomes large. Furthermore, we describe an extension to near-deterministic N- qubit Toffoli gate with a favorable error scaling. These gates can be directly employed in quantum repeater networks to facilitate near-ideal entanglement swapping, thus greatly speeding up the entanglement distribution.

J. Borregaard; P. Kómár; E. M. Kessler; A. S. Sørensen; M. D. Lukin

2015-01-05T23:59:59.000Z

230

Photo-modulated thin film transistor based on dynamic charge transfer within quantum-dots-InGaZnO interface  

SciTech Connect (OSTI)

The temporal development of next-generation photo-induced transistor across semiconductor quantum dots and Zn-related oxide thin film is reported in this paper. Through the dynamic charge transfer in the interface between these two key components, the responsibility of photocurrent can be amplified for scales of times (?10{sup 4}?A/W 450?nm) by the electron injection from excited quantum dots to InGaZnO thin film. And this photo-transistor has a broader waveband (from ultraviolet to visible light) optical sensitivity compared with other Zn-related oxide photoelectric device. Moreover, persistent photoconductivity effect can be diminished in visible waveband which lead to a significant improvement in the device's relaxation time from visible illuminated to dark state due to the ultrafast quenching of quantum dots. With other inherent properties such as integrated circuit compatible, low off-state current and high external quantum efficiency resolution, it has a great potential in the photoelectric device application, such as photodetector, phototransistor, and sensor array.

Liu, Xiang [Electronic Science and Engineering School, Southeast University, Nanjing (China); National Center for Nanoscience and Technology, Beijing (China); Yang, Xiaoxia; Liu, Mingju [National Center for Nanoscience and Technology, Beijing (China); Tao, Zhi; Wei, Lei, E-mail: lw@seu.edu.cn; Li, Chi, E-mail: lichi@seu.edu.cn; Zhang, Xiaobing; Wang, Baoping [Electronic Science and Engineering School, Southeast University, Nanjing (China); Dai, Qing, E-mail: daiq@nanoctr.cn [National Center for Nanoscience and Technology, Beijing (China); London Center for Nanotechnology, University College London, London WC1H 0AH (United Kingdom); Nathan, Arokia [Electronic Science and Engineering School, Southeast University, Nanjing (China); London Center for Nanotechnology, University College London, London WC1H 0AH (United Kingdom)

2014-03-17T23:59:59.000Z

231

Engineering integrated photonics for heralded quantum gates  

E-Print Network [OSTI]

Scaling up linear-optics quantum computing will require multi-photon gates which are compact, phase-stable, exhibit excellent quantum interference, and have success heralded by the detection of ancillary photons. We investigate implementation of the optimal known gate design which meets these requirements: the Knill controlled-Z gate, implemented in integrated laser-written waveguide arrays. We show that device performance is more sensitive to the small deviations in the coupler reflectivity, arising due to the tolerance values of the fabrication method, than phase variations in the circuit. The mode fidelity was also shown to be less sensitive to reflectivity and phase errors than process fidelity. Our best device achieves a fidelity of 0.931+/-0.001 with the ideal 4x4 unitary circuit and a process fidelity of 0.680+/-0.005 with the ideal computational-basis process.

T. Meany; D. N. Biggerstaff; M. A. Broome; A. Fedrizzi; M. Delanty; A. Gilchrist; G. D. Marshall; M. J. Steel; A. G. White; M. J. Withford

2015-02-11T23:59:59.000Z

232

Investigation of channel width-dependent threshold voltage variation in a-InGaZnO thin-film transistors  

SciTech Connect (OSTI)

This Letter investigates abnormal channel width-dependent threshold voltage variation in amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors. Unlike drain-induced source barrier lowering effect, threshold voltage increases with increasing drain voltage. Furthermore, the wider the channel, the larger the threshold voltage observed. Because of the surrounding oxide and other thermal insulating material and the low thermal conductivity of the IGZO layer, the self-heating effect will be pronounced in wider channel devices and those with a larger operating drain bias. To further clarify the physical mechanism, fast IV measurement is utilized to demonstrate the self-heating induced anomalous channel width-dependent threshold voltage variation.

Liu, Kuan-Hsien; Chou, Wu-Ching [Department of Electrophysics, National Chiao Tung University, Hsinchu, Taiwan (China); Chang, Ting-Chang, E-mail: tcchang@mail.phys.nsysu.edu.tw [Department of Physics, National Sun Yat-Sen University, Kaohsiung 804, Taiwan (China); Advanced Optoelectronics Technology Center, National Cheng Kung University, Taiwan (China); Wu, Ming-Siou; Hung, Yi-Syuan; Sze, Simon M. [Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan (China); Hung, Pei-Hua; Chu, Ann-Kuo [Department of Photonics, National Sun Yat-Sen University, Kaohsiung 804, Taiwan (China); Hsieh, Tien-Yu [Department of Physics, National Sun Yat-Sen University, Kaohsiung 804, Taiwan (China); Yeh, Bo-Liang [Advanced Display Technology Research Center, AU Optronics, No. 1, Li-Hsin Rd. 2, Hsinchu Science Park, Hsinchu 30078, Taiwan (China)

2014-03-31T23:59:59.000Z

233

Sandia National Laboratories: i-GATE  

Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

AFDC Printable Version Share this resource Send a link to EERE: Alternative Fuels Data Center Home Page to someone by E-mail Share EERE: Alternative Fuels Data Center Home Page on Facebook Tweet about EERE: Alternative Fuels Data Center Home Page on Twitter Bookmark EERE:1 First Use of Energy for All Purposes (Fuel and Nonfuel),Feet) Year Jan Feb Mar Apr MayAtmosphericNuclear Security Administration the1development Sandia,evaluatingfullhigher-performancestoragei-GATE ECIS and i-GATE:

234

InP-and Graphene-based grating-gated transistors for tunable THz and mm-wave detection  

E-Print Network [OSTI]

layer. Silvaco Atlas 2-D device simulator (FEM analysis software) was used to determine the free carrier

Peale, Robert E.

235

Si-CMOS-Like Integration of AlGaN/GaN Dielectric-Gated High-Electron-Mobility Transistors  

E-Print Network [OSTI]

the engineering of high mobility, high carrier density channels at III-Nitride heterointerfaces. In order to seize market share from silicon, the cost of manufacturing GaN-based devices must be further reduced. With the successful realization of 200mm Ga...

Johnson, Derek Wade

2014-07-31T23:59:59.000Z

236

Effect of Oxygen on Ni-Silicided FUSI Metal Gate  

E-Print Network [OSTI]

Continual evolution of the CMOS technology requires thinner gate dielectric to maintain high performance. However, when moving into the sub-65 nm CMOS generation, the traditional poly-Si gate approach cannot effectively ...

Yu, H.P.

237

abnormal sensorimotor gating: Topics by E-print Network  

Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

double dots can be effectively tuned from weak to strong regime by both the in-plane plunger gates and back gate. All the relevant energy scales and parameters of the bilayer...

238

GATE Center of Excellence at UAB for Lightweight Materials and...  

Broader source: Energy.gov (indexed) [DOE]

Constante (PhD candidate) and Samuel Jasper (PhD candidate) working on composite beams 9 Accomplishments and Progress: GATE Directly Funded Students (2005-2011) GATE SCHOLAR...

239

Buffer Minimization in Pass Transistor Logic Advanced Technology Group  

E-Print Network [OSTI]

function cells and four inverters with various drive capabilities. The approach in [2] also utilizesBuffer Minimization in Pass Transistor Logic Hai Zhou Advanced Technology Group Synopsys, Inc are inverters, where phase assignment need to be done with buffer insertion. Exper­ iments are done on MCNC

Zhou, Hai

240

Carbon Nanotube Transistor Arrays for Multistage Complementary Logic and  

E-Print Network [OSTI]

and resistors.5 Several issues need to be addressed in order to impart complexity and advanced functionality, Qian Wang, Ant Ural, Yiming Li, and Hongjie Dai* Department of Chemistry and Laboratory for AdVanced into field effect transistors (FETs)1 and intratube p-n junctions.3,4 Inverters, the simplest form of logic

Ural, Ant

Note: This page contains sample records for the topic "transistor gate oxide" from the National Library of EnergyBeta (NLEBeta).
While these samples are representative of the content of NLEBeta,
they are not comprehensive nor are they the most current set.
We encourage you to perform a real-time search of NLEBeta
to obtain the most current and comprehensive results.


241

Negative quantum capacitance in graphene nanoribbons with lateral gates  

E-Print Network [OSTI]

Negative quantum capacitance in graphene nanoribbons with lateral gates R. Reiter1, , U. Derra2 , S numerical simulations of the capacitive coupling between graphene nanoribbons of various widths and gate electrodes in different configurations. We compare the influence of lateral metallic or graphene side gate

Florian, Libisch

242

Clustering of cyclic-nucleotide-gated channels in olfactory cilia  

E-Print Network [OSTI]

Clustering of cyclic-nucleotide-gated channels in olfactory cilia Richard J. Flannery* , Donald A channel clusters in olfactory cilia Key words: olfaction, receptor neuron, cyclic-nucleotide-gated channel of olfactory signal transduction, including a high density of cyclic-nucleotide-gated (CNG) channels. CNG

French, Donald A.

243

Quantum Logic Gates using q-deformed Oscillators  

E-Print Network [OSTI]

We show that the quantum logic gates, {\\it viz.} the single qubit Hadamard and Phase Shift gates, can also be realised using q-deformed angular momentum states constructed via the Jordan-Schwinger mechanism with two q-deformed oscillators. {\\it Keywords :} quantum logic gates ; q-deformed oscillators ; quantum computation {\\it PACS:} 03.67.Lx ; 02.20.Uw

Debashis Gangopadhyay; Mahendra Nath Sinha Roy

2006-07-14T23:59:59.000Z

244

Accuracy and Consistency of Respiratory Gating in Abdominal Cancer Patients  

SciTech Connect (OSTI)

Purpose: To evaluate respiratory gating accuracy and intrafractional consistency for abdominal cancer patients treated with respiratory gated treatment on a regular linear accelerator system. Methods and Materials: Twelve abdominal patients implanted with fiducials were treated with amplitude-based respiratory-gated radiation therapy. On the basis of daily orthogonal fluoroscopy, the operator readjusted the couch position and gating window such that the fiducial was within a setup margin (fiducial-planning target volume [f-PTV]) when RPM indicated “beam-ON.” Fifty-five pre- and post-treatment fluoroscopic movie pairs with synchronized respiratory gating signal were recorded. Fiducial motion traces were extracted from the fluoroscopic movies using a template matching algorithm and correlated with f-PTV by registering the digitally reconstructed radiographs with the fluoroscopic movies. Treatment was determined to be “accurate” if 50% of the fiducial area stayed within f-PTV while beam-ON. For movie pairs that lost gating accuracy, a MATLAB program was used to assess whether the gating window was optimized, the external-internal correlation (EIC) changed, or the patient moved between movies. A series of safety margins from 0.5 mm to 3 mm was added to f-PTV for reassessing gating accuracy. Results: A decrease in gating accuracy was observed in 44% of movie pairs from daily fluoroscopic movies of 12 abdominal patients. Three main causes for inaccurate gating were identified as change of global EIC over time (?43%), suboptimal gating setup (?37%), and imperfect EIC within movie (?13%). Conclusions: Inconsistent respiratory gating accuracy may occur within 1 treatment session even with a daily adjusted gating window. To improve or maintain gating accuracy during treatment, we suggest using at least a 2.5-mm safety margin to account for gating and setup uncertainties.

Ge, Jiajia; Santanam, Lakshmi; Yang, Deshan [Department of Radiation Oncology, Washington University School of Medicine, St Louis, Missouri (United States)] [Department of Radiation Oncology, Washington University School of Medicine, St Louis, Missouri (United States); Parikh, Parag J., E-mail: pparikh@radonc.wustl.edu [Department of Radiation Oncology, Washington University School of Medicine, St Louis, Missouri (United States)

2013-03-01T23:59:59.000Z

245

Gate-controlled ultraviolet photo-etching of graphene edges  

SciTech Connect (OSTI)

The chemical reactivity of graphene under ultraviolet (UV) light irradiation is investigated under positive and negative gate electric fields. Graphene edges are selectively etched when negative gate voltages are applied while the reactivity is significantly suppressed for positive gate voltages. Oxygen adsorption onto graphene is significantly affected by the Fermi level of the final state achieved during previous electrical measurements. UV irradiation after negative-to-positive gate sweeps causes predominant oxygen desorption while UV irradiation after gate sweeps in the opposite direction causes etching of graphene edges.

Mitoma, Nobuhiko; Nouchi, Ryo [Nanoscience and Nanotechnology Research Center, Osaka Prefecture University, Sakai, Osaka 599-8570 (Japan)] [Nanoscience and Nanotechnology Research Center, Osaka Prefecture University, Sakai, Osaka 599-8570 (Japan)

2013-11-11T23:59:59.000Z

246

A Dual Platform for Selective Analyte Enrichment and Ionization in Mass Spectrometry Using Aptamer-Conjugated Graphene Oxide  

E-Print Network [OSTI]

-Conjugated Graphene Oxide Basri Gulbakan, Emir Yasun, M. Ibrahim Shukoor, Zhi Zhu, Mingxu You, Xiaohong Tan,, Hernan: This study demonstrates the use of aptamer-conju- gated graphene oxide as an affinity extraction a matrix and with greatly improved signal- to-noise ratios. Aptamer-conjugated graphene oxide has clear

Tan, Weihong

247

Classification of transversal gates in qubit stabilizer codes  

E-Print Network [OSTI]

This work classifies the set of diagonal gates that can implement a single or two-qubit transversal logical gate for qubit stabilizer codes. We show that individual physical gates on the underlying qubits that compose the code are restricted to have entries of the form $e^{i \\pi c/2^k}$ along their diagonal, resulting in a similarly restricted class of logical gates that can be implemented in this manner. Moreover, we show that all diagonal logical gates that can be implemented transversally by individual physical diagonal gates must belong to the Clifford hierarchy. Furthermore, we can use this result to prove a conjecture about transversal gates made by Zeng et al. in 2007.

Jonas T. Anderson; Tomas Jochym-O'Connor

2014-09-29T23:59:59.000Z

248

Arbitrary two-qubit computation in 23 elementary gates  

SciTech Connect (OSTI)

We address the problem of constructing quantum circuits to implement an arbitrary two-qubit quantum computation. We pursue circuits without ancilla qubits and as small a number of elementary quantum gates as possible. Our lower bound for worst-case optimal two-qubit circuits calls for at least 17 gates: 15 one-qubit rotations and 2 controlled-NOT (CNOT) gates. We also constructively prove a worst-case upper bound of 23 elementary gates, of which at most four (CNOT gates) entail multiqubit interactions. Our analysis shows that synthesis algorithms suggested in previous work, although more general, entail larger quantum circuits than ours in the special case of two qubits. One such algorithm has a worst case of 61 gates, of which 18 may be CNOT gates.

Bullock, Stephen S.; Markov, Igor L. [Department of Mathematics, The University of Michigan, Ann Arbor, Michigan 48109-2122, USA (United States); Mathematical and Computational Sciences Division, National Institute of Standards and Technology, Gaithersburg, Maryland 20899-8910, USA (United States); Department of Electrical Engineering and Computer Science, The University of Michigan, 1301 Beal Avenue-EECS, Ann Arbor, Michigan 48109-2122, USA (United States)

2003-07-01T23:59:59.000Z

249

As-Received, Ozone Cleaned and Ar+ Sputtered Surfaces of Hafnium Oxide Grown by Atomic Layer Deposition and Studied by XPS  

SciTech Connect (OSTI)

In this study, X-ray photoelectron spectroscopy (XPS) characterization was performed on 47 nm thick hafnium oxide (HfO{sub 2}) films grown by atomic layer deposition using TEMA-Hf/H{sub 2}O at 250 C substrate temperature. HfO{sub 2} is currently being studied as a possible replacement for Silicon Oxide (SiO{sub 2}) as a gate dielectric in electronics transistors. XPS spectra were collected on a Physical Electronics Quantum 2000 Scanning ESCA Microprobe using a monochromatic Al K{sub a} X-ray (1486.7 eV) excitation source. The sample was analyzed under the following conditions: as received, after UV irradiation for five minutes, and after sputter cleaning with 2 kV Ar{sup +} ions for 180 seconds. Survey scans showed carbon, oxygen, and hafnium as the major species in the film, while the only minor species of argon and carbide was detected after sputtering. Adventitious carbon initially composed approximately 18.6 AT% of the surface, but after UV cleaning it was reduced to 2.4 AT%. This demonstrated that that the majority of carbon was due to adventitious carbon. However, after 2 kV Ar{sup +} sputtering there was still only trace amounts of carbon at {approx}1 AT%, Some of this trace carbon is now in the form of a carbide due to the interaction with Ar{sup +} used for sputter cleaning. Furthermore, the stoiciometric ratio of oxygen and hafnium is consistent with a high quality HfO{sub 2} film.

Engelhard, Mark H.; Herman, Jacob A.; Wallace, Robert; Baer, Donald R.

2012-06-27T23:59:59.000Z

250

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 29, NO. 9, SEPTEMBER 2010 1409 Gate-Sizing-Based Single Vdd Test for Bridge  

E-Print Network [OSTI]

complementary metal- oxide-semiconductor and can constitute 50% or more, of total defect count [1]. A bridge, SEPTEMBER 2010 1409 Gate-Sizing-Based Single Vdd Test for Bridge Defects in Multivoltage Designs Saqib design technique. Recent research has shown that testing for resistive bridging faults in such designs

Chakrabarty, Krishnendu

251

Method for voltage-gated protein fractionation  

DOE Patents [OSTI]

We report unique findings on the voltage dependence of protein exclusion from the pores of nanoporous polymer exclusion membranes. The pores are small enough that proteins are excluded from passage with low applied electric fields, but increasing the field enables proteins to pass through. The requisite field necessary for a change in exclusion is protein-specific with a correlation to protein size. The field-dependence of exclusion is important to consider for preconcentration applications. The ability to selectively gate proteins at exclusion membranes is also a promising means for manipulating and characterizing proteins. We show that field-gated exclusion can be used to selectively remove proteins from a mixture, or to selectively trap protein at one exclusion membrane in a series.

Hatch, Anson (Tracy, CA); Singh, Anup K. (Danville, CA)

2012-04-24T23:59:59.000Z

252

The design of a frequency modulated transistor oscillator  

E-Print Network [OSTI]

THE DESIGN OF A. FREQUENCY MODULATED TRANSISTOR OSCILLATOR A Thesis PHIL DEWEY FISHER Submitted to the Graduate School of the Agricultural and Mechanical College of Texas in partial fulfillment of the requirements for the degree of MASTER... OF SCIENCE August 19/9 ELECTRICAL ENGINEERING THE DESLGE OP A FREQUEECT MODULATED TRAESZSTOR OSCILLATOR A Thesis PHIL DEWEY PISHER Approved as to style and content hyt ai an of Co ittee ead of DepaFtnent August 1959 ACKNOWLEDGMENTS The author...

Fisher, Phil Dewey

1959-01-01T23:59:59.000Z

253

Bottom-up graphene nanoribbon field-effect transistors  

SciTech Connect (OSTI)

Recently developed processes have enabled bottom-up chemical synthesis of graphene nanoribbons (GNRs) with precise atomic structure. These GNRs are ideal candidates for electronic devices because of their uniformity, extremely narrow width below 1?nm, atomically perfect edge structure, and desirable electronic properties. Here, we demonstrate nano-scale chemically synthesized GNR field-effect transistors, made possible by development of a reliable layer transfer process. We observe strong environmental sensitivity and unique transport behavior characteristic of sub-1?nm width GNRs.

Bennett, Patrick B. [Applied Science and Technology, University of California, Berkeley, California 94720 (United States) [Applied Science and Technology, University of California, Berkeley, California 94720 (United States); Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, California 94720 (United States); Pedramrazi, Zahra [Department of Physics, University of California, Berkeley, California 94720 (United States)] [Department of Physics, University of California, Berkeley, California 94720 (United States); Madani, Ali [Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, California 94720 (United States)] [Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, California 94720 (United States); Chen, Yen-Chia; Crommie, Michael F. [Department of Physics, University of California, Berkeley, California 94720 (United States) [Department of Physics, University of California, Berkeley, California 94720 (United States); Materials Sciences Division, Lawrence Berkeley National Laboratories, Berkeley, California 94720 (United States); Oteyza, Dimas G. de [Department of Physics, University of California, Berkeley, California 94720 (United States) [Department of Physics, University of California, Berkeley, California 94720 (United States); Centro de Física de Materiales CSIC/UPV-EHU-Materials Physics Center, San Sebastián E-20018 (Spain); Chen, Chen [Department of Chemistry, University of California, Berkeley, California 94720 (United States)] [Department of Chemistry, University of California, Berkeley, California 94720 (United States); Fischer, Felix R. [Department of Chemistry, University of California, Berkeley, California 94720 (United States) [Department of Chemistry, University of California, Berkeley, California 94720 (United States); Materials Sciences Division, Lawrence Berkeley National Laboratories, Berkeley, California 94720 (United States); Bokor, Jeffrey, E-mail: jbokor@eecs.berkeley.edu [Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, California 94720 (United States) [Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, California 94720 (United States); Materials Sciences Division, Lawrence Berkeley National Laboratories, Berkeley, California 94720 (United States)

2013-12-16T23:59:59.000Z

254

E-Print Network 3.0 - arsenide junction-field-effect transistors...  

Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

technique holds Summary: arsenide chips manufactured in multilayer stacks: light sensors, high-speed transistors and solar cells... material available. For example, the...

255

Transistor-based filter for inhibiting load noise from entering a power supply  

DOE Patents [OSTI]

A transistor-based filter for inhibiting load noise from entering a power supply is disclosed. The filter includes a first transistor having an emitter coupled to a power supply, a collector coupled to a load, and a base. The filter also includes a first capacitor coupled between the base of the first transistor and a ground terminal. The filter further includes an impedance coupled between the base and a node between the collector and the load, or a second transistor and second capacitor. The impedance can be a resistor or an inductor.

Taubman, Matthew S

2013-07-02T23:59:59.000Z

256

Dependence on proton energy of degradation of AlGaN/GaN high electron mobility transistors  

SciTech Connect (OSTI)

The effects of proton irradiation energy on dc, small signal, and large signal rf characteristics of AlGaN/GaN high electron mobility transistors (HEMTs) were investigated. AlGaN/GaN HEMTs were irradiated with protons at fixed fluence of 51015/cm2 and energies of 5, 10, and 15 MeV. Both dc and rf characteristics revealed more degradation at lower irradiation energy, with reductions of maximum transconductance of 11%, 22%, and 38%, and decreases in drain saturation current of 10%, 24%, and 46% for HEMTs exposed to 15, 10, and 5MeV protons, respectively. The increase in device degradation with decreasing proton energy is due to the increase in linear energy transfer and corresponding increase in nonionizing energy loss with decreasing proton energy in the active region of the HEMTs. After irradiation, both subthreshold drain leakage current and reverse gate current decreased more than 1 order of magnitude for all samples. The carrier removal rate was in the range 121 336 cm1 over the range of proton energies employed in this study

Liu, L. [University of Florida, Gainesville; Xi, Y. Y. [University of Florida, Gainesville; Wang, Y.l. [University of Florida; Ren, F. [University of Florida; Pearton, S. J. [University of Florida; Kim, H.-Y. [Korea University; Kim, J. [Korea University; Fitch, Robert C [Air Force Research Laboratory, Wright-Patterson AFB, OH; Walker, Dennis E [Air Force Research Laboratory, Wright-Patterson AFB, OH; Chabak, Kelson D [Air Force Research Laboratory, Wright-Patterson AFB, OH; Gillespie, James k [Air Force Research Laboratory, Wright-Patterson AFB, OH; Tetlak, Stephen E [Air Force Research Laboratory, Wright-Patterson AFB, OH; Via, Glen D [Air Force Research Laboratory, Wright-Patterson AFB, OH; Crespo, Antonio [Air Force Research Laboratory, Wright-Patterson AFB, OH; Kravchenko, Ivan I [ORNL

2013-01-01T23:59:59.000Z

257

The effect of Ta doping in polycrystalline TiO{sub x} and the associated thin film transistor properties  

SciTech Connect (OSTI)

Tantalum (Ta) is suggested to act as an electron donor and crystal phase stabilizer in titanium oxide (TiO{sub x}). A transition occurs from an amorphous state to a crystalline phase at an annealing temperature above 300?°C in a vacuum ambient. As the annealing temperature increases from 300?°C to 450?°C, the mobility increases drastically from 0.07 cm{sup 2}/Vs to 0.61 cm{sup 2}/Vs. The remarkable enhancement of thin film transistor performance is suggested to be due to the splitting of Ti 3d band orbitals as well as the increase in Ta{sup 5+} ions that can act as electron donors.

Ok, Kyung-Chul, E-mail: kchul2926@naver.com; Park, Yoseb, E-mail: jozeph.park@gmail.com; Park, Jin-Seong, E-mail: kbchung@dankook.ac.kr, E-mail: jsparklime@hanyang.ac.kr [Division of Materials Science and Engineering, Hanyang University, 222 Wangsimni-ro, Seongdong-gu, Seoul 133-791 (Korea, Republic of)] [Division of Materials Science and Engineering, Hanyang University, 222 Wangsimni-ro, Seongdong-gu, Seoul 133-791 (Korea, Republic of); Chung, Kwun-Bum, E-mail: kbchung@dankook.ac.kr, E-mail: jsparklime@hanyang.ac.kr [Department of Physics, Dankook University, 119 Dandae-ro, Dongnam-gu, Cheonan 330-714 (Korea, Republic of)] [Department of Physics, Dankook University, 119 Dandae-ro, Dongnam-gu, Cheonan 330-714 (Korea, Republic of)

2013-11-18T23:59:59.000Z

258

An elementary optical gate for expanding entanglement web  

E-Print Network [OSTI]

We introduce an elementary optical gate for expanding polarization entangled W states, in which every pair of photons are entangled alike. The gate is composed of a pair of 50:50 beamsplitters and ancillary photons in the two-photon Fock state. By seeding one of the photons in an $n$-photon W state into this gate, we obtain an $(n+2)$-photon W state after post-selection. This gate gives a better efficiency and a simpler implementation than previous proposals for $\\rm W$-state preparation.

Toshiyuki Tashima; Sahin Kaya Ozdemir; Takashi Yamamoto; Masato Koashi; Nobuyuki Imoto

2008-03-13T23:59:59.000Z

259

Vehicle Technologies Office Merit Review 2014: GATE Center of...  

Broader source: Energy.gov (indexed) [DOE]

GATE Center of Excellence at UAB for Lightweight Materials and Manufacturing for Automotive, Truck and Mass Transit. lm081vaidya2014o.pdf More Documents & Publications...

260

GATE Center of Excellence at UAB for Lightweight Materials and...  

Broader source: Energy.gov (indexed) [DOE]

at UAB for Lightweight Materials and Manufacturing for Automotive, Truck and Mass Transit GATE Center of Excellence at UAB for Lightweight Materials and Manufacturing for...

Note: This page contains sample records for the topic "transistor gate oxide" from the National Library of EnergyBeta (NLEBeta).
While these samples are representative of the content of NLEBeta,
they are not comprehensive nor are they the most current set.
We encourage you to perform a real-time search of NLEBeta
to obtain the most current and comprehensive results.


261

High Temperature, High Voltage Fully Integrated Gate Driver Circuit  

Broader source: Energy.gov (indexed) [DOE]

temperature gate drive is being developed for use with future wide band gap (silicon carbide and gallium nitride) switching devices. * Universal drive that is capable of driving...

262

PIA - Savannah River Nuclear Solution (SRNS) MedGate Occupational...  

Office of Environmental Management (EM)

Occupational Health and Safety Medical System (OHS) (Includes the Drug and Alcohol Testing System (Assistant)) PIA - Savannah River Nuclear Solution (SRNS) MedGate...

263

GATE Center of Excellence at UAB for Lightweight Materials and...  

Broader source: Energy.gov (indexed) [DOE]

Constante (PhD candidate) and Samuel Jasper (PhD candidate) working on composite beams GATE courses (some newly developed, some based on tailoring content in existing...

264

Sandia National Laboratories: ECIS and i-GATE: Innovation Hub...  

Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

support system to accelerate the commercialization of innovative technologies related to green transportation and clean energy. There are now eight i-GATE clients developing fuel...

265

Gate Fidelities, Quantum Broadcasting, and Assessing Experimental Realization  

E-Print Network [OSTI]

We relate gate fidelities of experimentally realized quantum operations to the broadcasting property of their ideal operations, and show that the more parties a given quantum operation can broadcast to, the higher gate fidelities of its experimental realization are in general. This is shown by establishing the correspondence between two operational quantities, quantum state shareability and quantum broadcasting. This suggests that, to assess an experimental realization using gate fidelities, the worst case of realization such as noisy operations should be taken into account and then compared to obtained gate fidelities. In addition, based on the correspondence, we also translate results in quantum state shareability to their counterparts in quantum operations.

Hyang-Tag Lim; Young-Sik Ra; Yong-Su Kim; Yoon-Ho Kim; Joonwoo Bae

2011-06-29T23:59:59.000Z

266

Optical Determination of Gate--Tunable Bandgap in Bilayer Graphene  

E-Print Network [OSTI]

Tunable Bandgap in Bilayer Graphene Yuanbo Zhang* 1 , Tsung-gate-tunable bandgap in graphene bilayers with magnitude asbands. In two- dimensional graphene bilayers this bandgap

Zhang, Yuanbo

2010-01-01T23:59:59.000Z

267

A 200 C Universal Gate Driver Integrated Circuit for Extreme Environment Applications  

SciTech Connect (OSTI)

High-temperature power converters (dc-dc, dc-ac, etc.) have enormous potential in extreme environment applications, including automotive, aerospace, geothermal, nuclear, and well logging. For successful realization of such high-temperature power conversion modules, the associated control electronics also need to perform at high temperature. This paper presents a silicon-on-insulator (SOI) based high-temperature gate driver integrated circuit (IC) incorporating an on-chip low-power temperature sensor and demonstrating an improved peak output current drive over our previously reported work. This driver IC has been primarily designed for automotive applications, where the underhood temperature can reach 200 C. This new gate driver prototype has been designed and implemented in a 0.8 {micro}m, 2-poly, and 3-metal bipolar CMOS-DMOS (Double-Diffused Metal-Oxide Semiconductor) on SOI process and has been successfully tested for up to 200 C ambient temperature driving a SiC MOSFET and a SiC normally-ON JFET. The salient feature of the proposed universal gate driver is its ability to drive power switches over a wide range of gate turn-ON voltages such as MOSFET (0 to 20 V), normally-OFF JFET (-7 to 3 V), and normally-ON JFET (-20 to 0 V). The measured peak output current capability of the driver is around 5 A and is thus capable of driving several power switches connected in parallel. An ultralow-power on-chip temperature supervisory circuit has also been integrated into the die to safeguard the driver circuit against excessive die temperature ({ge}220 C). This approach utilizes increased diode leakage current at higher temperature to monitor the die temperature. The power consumption of the proposed temperature sensor circuit is below 10 {micro}W for operating temperature up to 200 C.

Tolbert, Leon M [ORNL; Huque, Mohammad A [ORNL; Islam, Syed K [ORNL; Blalock, Benjamin J [ORNL

2012-01-01T23:59:59.000Z

268

A 500 MHz carbon nanotube transistor oscillator A. A. Pesetski,1  

E-Print Network [OSTI]

A 500 MHz carbon nanotube transistor oscillator A. A. Pesetski,1 J. E. Baumgardner,1 S. V Operation of a carbon nanotube field effect transistor FET oscillator at a record frequency of 500 MHz enabled greater than unity net oscillator loop gain to be achieved at 500 MHz. © 2008 American Institute

Rogers, John A.

269

Evaluation of the Radiation Tolerance of SiGe Heterojunction Bipolar Transistors Under  

E-Print Network [OSTI]

in a modified 5HP process. The current gain as a function of collector current has been measured at several and for signal- level discrimination. We will discuss the behavior of both kinds of transistors bipolar transistors manufactured in a modified 5HP process, taken before and after irradiation at fluences

California at Santa Cruz, University of

270

DESIGN, MODELING, TESTING, AND SPICE PARAMETER EXTRACTION OF DIMOS TRANSISTOR IN 4H-SILICON CARBIDE  

E-Print Network [OSTI]

DESIGN, MODELING, TESTING, AND SPICE PARAMETER EXTRACTION OF DIMOS TRANSISTOR IN 4H-SILICON CARBIDE (DIMOS) transistor structure in 4H-Silicon Carbide (SiC) is presented. Simulation for transport Silicon carbide (SiC), a wide bandgap material, shows a tremendous potential for high temperature

Tolbert, Leon M.

271

Photovoltaic transistors based on a steady-state internal polarization effect in asymmetric semiconductor superlattices  

E-Print Network [OSTI]

Photovoltaic transistors based on a steady-state internal polarization effect in asymmetric that a modified structure can generate a steady-state photovoltage. We then propose a new class of photovoltaic novelty is such a photovoltaic transistor (PVT) aspect. Our idea of the PVT arises from the well known

Luryi, Serge

272

Base-contact proximity effects in bipolar transistors with nitride-spacer technology  

E-Print Network [OSTI]

-lithographic dimensions. For example, in the double polysilicon bipolar transistor, spacers are used to separate the baseBase-contact proximity effects in bipolar transistors with nitride-spacer technology Henk van Zeijl-BJT's with spacer separated Al/Si emitter and base contacts are fabricated and characterized. Due to the proximity

Technische Universiteit Delft

273

Graphene Transistors Fabricated via Transfer-Printing In Device Active-Areas  

E-Print Network [OSTI]

Graphene Transistors Fabricated via Transfer-Printing In Device Active-Areas on Large Wafer Xiaogan graphene islands from a graphite and then uses transfer printing to place the islands from the stamp from the printed graphene. The transistors show a hole and electron mobility of 3735 and 795 cm2/V

274

Hybrid single-electron transistor as a source of quantized electric current  

E-Print Network [OSTI]

LETTERS Hybrid single-electron transistor as a source of quantized electric current JUKKA P. PEKOLA of a hybrid normal-metal­ superconductor turnstile in the form of a one-island single- electron transistor currents in the nano-ampere range but their accuracy is still limited. Surprisingly, a simple hybrid single

Loss, Daniel

275

Highly Stable Hysteresis-Free Carbon Nanotube Thin-Film Transistors by Fluorocarbon Polymer Encapsulation  

E-Print Network [OSTI]

Highly Stable Hysteresis-Free Carbon Nanotube Thin-Film Transistors by Fluorocarbon Polymer report hysteresis-free carbon nanotube thin-film transistors (CNT-TFTs) employing a fluorocarbon polymer (Teflon-AF) as an encapsulation layer. Such fluorocarbon encapsulation improves device uniformity

Javey, Ali

276

Cavity-QED-based quantum phase gate  

E-Print Network [OSTI]

are detuned by an amount D from the cavity mode 1, i.e., vbc5n11D . A quantum phase gate with a p phase shift is implemented if the atom in its ground state uc& passes through the cavity such that ~1! the detuning D is equal to g2, and ~2! the interaction...- lowing. The effective Hamiltonian for the interaction, in the di- pole and rotating-wave approximations, is H5H01H1 , ~3! where H05\

Zubairy, M. Suhail; Kim, M.; Scully, Marlan O.

2003-01-01T23:59:59.000Z

277

Gate-teleportation-based blind quantum computation  

E-Print Network [OSTI]

Blind quantum computation (BQC) is a model in which a computation is performed on a server by a client such that the server is kept blind about the input, the algorithm, and the output of the computation. Here we layout a general framework for BQC which, unlike the previous BQC models, does not constructed on specific computational model. A main ingredient of our construction is gate teleportation. We demonstrate that our framework can be straightforwardly implemented on circuit-based models as well as measurement-based models of quantum computation. We illustrate our construction by showing that universal BQC is possible on correlation-space measurement-based quantum computation models.

Mear M. R. Koochakie

2014-12-25T23:59:59.000Z

278

David A Gates | Princeton Plasma Physics Lab  

Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

AFDC Printable Version Share this resource Send a link to EERE: Alternative Fuels Data Center Home Page to someone by E-mail Share EERE: Alternative Fuels Data Center Home Page on Facebook Tweet about EERE: Alternative Fuels Data Center Home Page on Twitter Bookmark EERE:1 First Use of Energy for All Purposes (Fuel and Nonfuel),Feet) Year Jan Feb Mar Apr May JunDatastreamsmmcrcalgovInstrumentsruc DocumentationP-Series to UserProduct: CrudeOffice ofINL is aID Service FirstMeetingsA Gates

279

Testing tri-state and pass transistor circuit structures  

E-Print Network [OSTI]

Tri-state structures are used to implement multiplexers and buses because these structures are faster than AND/OR logic structures. But testing of tri-state structures has some issues associated with it. A stuck open control line of a tri-state gate...

Parikh, Shaishav Shailesh

2005-11-01T23:59:59.000Z

280

EMSL - oxides  

Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

oxides en Influence of Adsorption Site and Wavelength on the Photodesorption of NO from the (Fe,Cr)3O4(111) Mixed Oxide Surface. http:www.emsl.pnl.govemslwebpublications...

Note: This page contains sample records for the topic "transistor gate oxide" from the National Library of EnergyBeta (NLEBeta).
While these samples are representative of the content of NLEBeta,
they are not comprehensive nor are they the most current set.
We encourage you to perform a real-time search of NLEBeta
to obtain the most current and comprehensive results.


281

Optical AND and NOT gates at 40 Gbps using electro-absorption modulator/photodiode pairs.  

SciTech Connect (OSTI)

We demonstrate an optical gate architecture using electro-absorption modulator/photodiode pairs to perform AND and NOT functions. Optical bandwidth for both gates reach 40 GHz. Also shown are AND gate waveforms at 40 Gbps.

Tauke-Pedretti, Anna; Overberg, Mark E.; Skogen, Erik J.; Alford, Charles Fred; Sullivan, Charles Thomas; Vawter, Gregory Allen; Peake, Gregory Merwin; Torres, David L.

2010-06-01T23:59:59.000Z

282

High-current, fast-switching transistor development  

SciTech Connect (OSTI)

Work that shows how the results obtained under a previous contract (NAS3-18916) have been applied to a larger-diameter (33-mm) transistor are described. An improved base contact for equalizing the base-emitter voltage at high currents has been developed along with an improved emitter contact preform which increases the silicon area available for current conduction. The electrical performance achieved is consistent with the proposed optimum design. The device design, wafer-processing techniques, and various measurements which include forward SOA, dc characteristics, and switching times are described.

Hower, P.L.

1981-03-15T23:59:59.000Z

283

Modeling gated neutron images of THD capsules  

SciTech Connect (OSTI)

Time gating a neutron detector 28m from a NIF implosion can produce images at different energies. The brighter image near 14 MeV reflects the size and symmetry of the capsule 'hot spot'. Scattered neutrons, {approx}9.5-13 MeV, reflect the size and symmetry of colder, denser fuel, but with only {approx}1-7% of the neutrons. The gated detector records both the scattered neutron image, and, to a good approximation, an attenuated copy of the primary image left by scintillator decay. By modeling the imaging system the energy band for the scattered neutron image (10-12 MeV) can be chosen, trading off the decayed primary image and the decrease of scattered image brightness with energy. Modeling light decay from EJ399, BC422, BCF99-55, Xylene, DPAC-30, and Liquid A leads to a preference from BCF99-55 for the first NIF detector, but DPAC 30 and Liquid A would be preferred if incorporated into a system. Measurement of the delayed light from the NIF scintillator using implosions at the Omega laser shows BCF99-55 to be a good choice for down-scattered imaging at 28m.

Wilson, Douglas Carl [Los Alamos National Laboratory; Grim, Gary P [Los Alamos National Laboratory; Tregillis, Ian L [Los Alamos National Laboratory; Wilke, Mark D [Los Alamos National Laboratory; Morgan, George L [Los Alamos National Laboratory; Loomis, Eric N [Los Alamos National Laboratory; Wilde, Carl H [Los Alamos National Laboratory; Oertel, John A [Los Alamos National Laboratory; Fatherley, Valerie E [Los Alamos National Laboratory; Clark, David D [Los Alamos National Laboratory; Schmitt, Mark J [Los Alamos National Laboratory; Merrill, Frank E [Los Alamos National Laboratory; Wang, Tai - Sen F [Los Alamos National Laboratory; Danly, Christopher R [Los Alamos National Laboratory; Batha, Steven H [Los Alamos National Laboratory; Patel, M [LLNL; Sepke, S [LLNL; Hatarik, R [LLNL; Fittinghoff, D [LLNL; Bower, D [LLNL; Marinak, M [LLNL; Munro, D [LLNL; Moran, M [LLNL; Hilko, R [NSTEC; Frank, M [LLNL; Buckles, R [NSTEC

2010-01-01T23:59:59.000Z

284

Sizing sliding gate valves for steam service  

SciTech Connect (OSTI)

Sliding gate valves have been used in thousands of applications during the past 40 yr. While steam control is a common application for these valves, thy are also used to control other gases and liquids. The sliding gate design provides straight-through flow, which minimizes turbulence, vibration, and noise. Seats are self-cleaning and self-lapping to provide a tight, long-lasting shutoff. A correctly sized valve is essential for accurate control. Valve size should be determined by service and system requirements, not by the size of the existing pipeline. Sizing a valve on the basis of pipeline size usually results in an oversized valve and poor control. Generally, regulator size is smaller than pipe size. Whenever complete information is known (inlet pressure, outlet pressure, or pressure drop, and required flow), determine the valve flow coefficient (C{sub v}) using the equations in ANSI/ISA S75.01 or a flow sizing chart. Tables of values for various types of valves are available from manufacturers. However, when complete system requirements are not known, valve oversizing is prevented by determining the design capacity of piping downstream from the valve. The valve should not be sized to pass more flow than the maximum amount the pipe can handle at a reasonable velocity. An example calculation is given.

Bollinger, R. [Jordan Value, Cincinnati, OH (United States)

1995-11-06T23:59:59.000Z

285

A p-cell approach to integer gate sizing  

E-Print Network [OSTI]

cell (p-cell) approach to the generation of layouts of standard gates is presented. The use of constant delay model for gate delay estimation is proposed which eliminates the need for maintaining huge volumes of delay tables in the standard cell library...

Doddannagari, Uday

2009-05-15T23:59:59.000Z

286

University of Illinois at Urbana-Champaigns GATE Center for...  

Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

Urbana-Champaigns GATE Center for Advanced Automotive Bio-Fuel Combustion Engines University of Illinois at Urbana-Champaigns GATE Center for Advanced Automotive Bio-Fuel...

287

University of Illinois at Urbana Champaigns GATE Center forAdvanced...  

Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

Urbana Champaigns GATE Center forAdvanced Automotive Bio-Fuel Combustion Engines University of Illinois at Urbana Champaigns GATE Center forAdvanced Automotive Bio-Fuel...

288

Paying the Toll: A Political History of the Golden Gate Bridge and Highway District, 1923-1971  

E-Print Network [OSTI]

Final Environmental Statement Golden Gate Bridge, HighwayGolden Gate Bridge Highway and Transportation District, Draft Environmental

Dyble, Amy Louise Nelson

2003-01-01T23:59:59.000Z

289

Gallium phosphide high-temperature bipolar junction transistor  

SciTech Connect (OSTI)

Preliminary results are reported on the development of a high-temperature (> 350/sup 0/C) gallium phosphide bipolar junction transistor (BJT) for goethermal and other energy applications. This four-layer p/sup +/n/sup -/pp/sup +/ structure was fromed by liquid phase epitaxy using a supercooling technique to insure uniform nucleation of the thin layers. Magnesium was used as the p-type dopant to avoid excessive out-diffusion into the lightly doped base. By appropriate choice of electrodes, the device may also be driven as an n-channel junction field-effect transistor. The gallium phosphide BJT is observed to have a common-emitter current gain peaking in the range of 6 to 10 (for temperatures from 20/sup 0/C to 400/sup 0/C) and a room-temperature, punchthrough-limited, collector-emitter breakdown voltage of approximately -6V. Other parameters of interest include an f/sub/ = 400 KHz (at 20/sup 0/C) and a collector base leakage current = 200 ..mu..A (at 350/sup 0/C).

Zipperian, T.E.; Dawson, L.R.; Caffin, R.J.

1981-03-01T23:59:59.000Z

290

Improved Stability Of Amorphous Zinc Tin Oxide Thin Film Transistors Using  

Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

AFDC Printable Version Share this resource Send a link to EERE: Alternative Fuels Data Center Home Page to someone by E-mail Share EERE: Alternative Fuels Data Center Home Page on Facebook Tweet about EERE: Alternative Fuels Data Center Home Page on Twitter Bookmark EERE:1 First Use of Energy for All Purposes (Fuel and Nonfuel),Feet) Year Jan Feb Mar Apr MayAtmospheric Optical Depth7-1D: Vegetation ProposedUsingFun withconfinementEtching.348 270 300 219 255Retrievals of Temperature

291

Gated x-ray detector for the National Ignition Facility  

SciTech Connect (OSTI)

Two new gated x-ray imaging cameras have recently been designed, constructed, and delivered to the National Ignition Facility in Livermore, CA. These gated x-Ray detectors are each designed to fit within an aluminum airbox with a large capacity cooling plane and are fitted with an array of environmental housekeeping sensors. These instruments are significantly different from earlier generations of gated x-ray images due, in part, to an innovative impedance matching scheme, advanced phosphor screens, pulsed phosphor circuits, precision assembly fixturing, unique system monitoring, and complete remote computer control. Preliminary characterization has shown repeatable uniformity between imaging strips, improved spatial resolution, and no detectable impedance reflections.

Oertel, John A.; Aragonez, Robert; Archuleta, Tom; Barnes, Cris; Casper, Larry; Fatherley, Valerie; Heinrichs, Todd; King, Robert; Landers, Doug; Lopez, Frank; Sanchez, Phillip; Sandoval, George; Schrank, Lou; Walsh, Peter; Bell, Perry; Brown, Matt; Costa, Robert; Holder, Joe; Montelongo, Sam; Pederson, Neal [Los Alamos National Laboratory, Los Alamos, New Mexico 87544 (United States); Lawrence Livermore National Laboratory, Livermore, California 94551-0808 (United States); VI Control Systems Ltd., Los Alamos, New Mexico 87544 (United States)

2006-10-15T23:59:59.000Z

292

Influence of an anomalous dimension effect on thermal instability in amorphous-InGaZnO thin-film transistors  

SciTech Connect (OSTI)

This paper investigates abnormal dimension-dependent thermal instability in amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors. Device dimension should theoretically have no effects on threshold voltage, except for in short channel devices. Unlike short channel drain-induced source barrier lowering effect, threshold voltage increases with increasing drain voltage. Furthermore, for devices with either a relatively large channel width or a short channel length, the output drain current decreases instead of saturating with an increase in drain voltage. Moreover, the wider the channel and the shorter the channel length, the larger the threshold voltage and output on-state current degradation that is observed. Because of the surrounding oxide and other thermal insulating material and the low thermal conductivity of the IGZO layer, the self-heating effect will be pronounced in wider/shorter channel length devices and those with a larger operating drain bias. To further clarify the physical mechanism, fast I{sub D}-V{sub G} and modulated peak/base pulse time I{sub D}-V{sub D} measurements are utilized to demonstrate the self-heating induced anomalous dimension-dependent threshold voltage variation and on-state current degradation.

Liu, Kuan-Hsien; Chou, Wu-Ching, E-mail: tcchang3708@gmail.com, E-mail: wuchingchou@mail.nctu.edu.tw [Department of Electrophysics, National Chiao Tung University, Hsin-chu 300, Taiwan (China); Chang, Ting-Chang, E-mail: tcchang3708@gmail.com, E-mail: wuchingchou@mail.nctu.edu.tw [Department of Physics, National Sun Yat-Sen University, Kaohsiung 804, Taiwan (China); Advanced Optoelectronics Technology Center, National Cheng Kung University, Taiwan (China); Chen, Hua-Mao; Tai, Ya-Hsiang [Department of Photonics and Institute of Electro-Optical Engineering, National Chiao Tung University, Hsin-chu 300, Taiwan (China); Tsai, Ming-Yen; Hung, Pei-Hua; Chu, Ann-Kuo [Department of Photonics, National Sun Yat-Sen University, Kaohsiung 804, Taiwan (China); Wu, Ming-Siou; Hung, Yi-Syuan [Department of Electronics Engineering, National Chiao Tung University, Hsin-Chu 300, Taiwan (China); Hsieh, Tien-Yu [Department of Physics, National Sun Yat-Sen University, Kaohsiung 804, Taiwan (China); Yeh, Bo-Liang [Advanced Display Technology Research Center, AU Optronics, No.1, Li-Hsin Rd. 2, Hsinchu Science Park, Hsin-Chu 30078, Taiwan (China)

2014-10-21T23:59:59.000Z

293

Nanowire-based ternary transistor by threshold-voltage manipulation  

SciTech Connect (OSTI)

We report on a ternary device consisting of two nanowire channels that have different threshold voltage (V{sub th}) values and show that three current stages can be produced. A microscale laser-beam shot was utilized to selectively anneal the nanowire channel area to be processed, and the amount of V{sub th} shift could be controlled by adjusting the laser wavelength. Microscale laser annealing process could control V{sub th} of the individual nanowire transistors while maintaining the other parameters the constant, such as the subthreshold slope, on–off current ratio, and mobility. This result could provide a potential for highly integrated and high-speed ternary circuits.

Han, Junebeom; Lim, Taekyung; Bong, Jihye; Seo, Keumyoung; Ju, Sanghyun, E-mail: shju@kgu.ac.kr [Department of Physics, Kyonggi University, Suwon, Gyeonggi-Do 443-760 (Korea, Republic of); Kim, Sunkook [Department of Electronics and Radio Engineering, Kyung Hee University, Yongin, Gyeonggi-Do 446-701 (Korea, Republic of)

2014-04-07T23:59:59.000Z

294

An Area Efficien Low Power High Speed S-Box Implementation Using Power-Gated PLA  

E-Print Network [OSTI]

An Area Efficien Low Power High Speed S-Box Implementation Using Power-Gated PLA Ho Joon Lee- sign of Rijndael S-Box for the SubByte transformation using power-gating and PLA design techniques arrays,VLSI General Terms Cryptography, Power Gate, Low Power Keywords AES, PLA, Power Gate, S-Box 1

Ayers, Joseph

295

Electric field engineering in GaN high electron mobility transistors  

E-Print Network [OSTI]

In the last few years, AlGaN/GaN high electron mobility transistors (HEMTs) have become the top choice for power amplification at frequencies up to 20 GHz. Great interest currently exists in industry and academia to increase ...

Zhao, Xu, S.M. Massachusetts Institute of Technology

2008-01-01T23:59:59.000Z

296

Physics of electrical degradation in GaN high electron mobility transistors  

E-Print Network [OSTI]

The deployment of GaN high electron mobility transistors (HEMT) in RF power applications is currently bottlenecked by their limited reliability. Obtaining the required reliability is a difficult issue due to the high voltage ...

Joh, Jungwoo

2009-01-01T23:59:59.000Z

297

Simulation and fabrication of GaN-based vertical and lateral normally-off power transistors  

E-Print Network [OSTI]

This thesis is divided in two parts. First, self-consistent electro-thermal simulations have been performed for single finger and multi-finger GaN-based vertical and lateral power transistors and were validated with ...

Zhang, Yuhao, S.M. Massachusetts Institute of Technology

2013-01-01T23:59:59.000Z

298

Deeply-scaled GaN high electron mobility transistors for RF applications  

E-Print Network [OSTI]

Due to the unique combination of large critical breakdown field and high electron velocity, GaN-based high electron mobility transistors (HEMTs) have great potential for next generation high power RF amplifiers. The ...

Lee, Dong Seup

2014-01-01T23:59:59.000Z

299

Low Voltage, Low Power Organic Light Emitting Transistors for AMOLED Displays  

SciTech Connect (OSTI)

Low voltage, low power dissipation, high aperture ratio organic light emitting transistors are demonstrated. The high level of performance is enabled by a carbon nanotube source electrode that permits integration of the drive transistor and the organic light emitting diode into an efficient single stacked device. Given the demonstrated performance, this technology could break the technical logjam holding back widespread deployment of active matrix organic light emitting displays at flat panel screen sizes.

McCarthy, M. A. [University of Florida, Gainesville; Liu, B. [University of Florida, Gainesville; Donoghue, E. P. [University of Florida, Gainesville; Kravchenko, Ivan I [ORNL; Kim, D. Y. [University of Florida, Gainesville; Reynolds, J. R. [University of Florida, Gainesville; So, Franky [University of Florida, Gainesville; Rinzler, A. G. [University of Florida, Gainesville

2011-01-01T23:59:59.000Z

300

JOURNAL DE PHYSIQUE Colloque C4, supplkment au n09, Tome 49, septembre 1988  

E-Print Network [OSTI]

by ion implantation through an 80 nm thick gate'oxide. CIT 1 uses a metal gate. This process is very thick layer of platinum silicide with a resistivity of 8 Ohms per square is selectively deposited. The bipolar transistor surface is completely covered by this silicide. Both collector-base and base

Paris-Sud XI, Université de

Note: This page contains sample records for the topic "transistor gate oxide" from the National Library of EnergyBeta (NLEBeta).
While these samples are representative of the content of NLEBeta,
they are not comprehensive nor are they the most current set.
We encourage you to perform a real-time search of NLEBeta
to obtain the most current and comprehensive results.


301

Parameter Mismatches, Chaos Synchronization and Fast Dynamic Logic Gates  

E-Print Network [OSTI]

By using chaos synchronization between non-identical multiple time delay semiconductor lasers with optoelectronic feedbacks, we demonstrate numerically how fast dynamic logic gates can be constructed. The results may be helpful to obtain a computational hardware with reconfigurable properties.

E. M. Shahverdiev

2009-07-02T23:59:59.000Z

302

Micro-mechanical logic for field produceable gate arrays  

E-Print Network [OSTI]

A paradigm of micro-mechanical gates for field produceable logic is explored. A desktop manufacturing system is sought after which is capable of printing functional logic devices in the field. A logic scheme which induces ...

Prakash, Manu

2005-01-01T23:59:59.000Z

303

Single-Step Implementation of Universal Quantum Gates  

SciTech Connect (OSTI)

We construct optimized implementations of the controlled-NOT and other universal two-qubit gates that, unlike many of the previously proposed protocols, are carried out in a single step. The new protocols require tunable interqubit couplings but, in return, show a significant improvement in the quality of gate operations. We make specific predictions for coupled Josephson junction qubits and compare them with the results of recent experiments.

Grigorenko, I.A.; Khveshchenko, D.V. [Department of Physics and Astronomy, University of North Carolina, Chapel Hill, North Carolina 27599 (United States)

2005-09-09T23:59:59.000Z

304

Rapidly reconfigurable all-optical universal logic gate  

DOE Patents [OSTI]

A new reconfigurable cascadable all-optical on-chip device is presented. The gate operates by combining the Vernier effect with a novel effect, the gain-index lever, to help shift the dominant lasing mode from a mode where the laser light is output at one facet to a mode where it is output at the other facet. Since the laser remains above threshold, the speed of the gate for logic operations as well as for reprogramming the function of the gate is primarily limited to the small signal optical modulation speed of the laser, which can be on the order of up to about tens of GHz. The gate can be rapidly and repeatedly reprogrammed to perform any of the basic digital logic operations by using an appropriate analog optical or electrical signal at the gate selection port. Other all-optical functionality includes wavelength conversion, signal duplication, threshold switching, analog to digital conversion, digital to analog conversion, signal routing, and environment sensing. Since each gate can perform different operations, the functionality of such a cascaded circuit grows exponentially.

Goddard, Lynford L. (Hayward, CA); Bond, Tiziana C. (Livermore, CA); Kallman, Jeffrey S. (Pleasanton, CA)

2010-09-07T23:59:59.000Z

305

The gated community: residents' crime experience and perception of safety behind gates and fences in the urban area  

E-Print Network [OSTI]

The primary purpose of the study is to explore the connections between residents' perception of safety and their crime experience, and the existence of gates and fences in multi-family housing communities in urban areas. For cultivating discussions...

Kim, Suk Kyung

2006-10-30T23:59:59.000Z

306

Subthreshold-swing physics of tunnel field-effect transistors Wei Cao, Deblina Sarkar, Yasin Khatami, Jiahao Kang, and Kaustav Banerjee  

E-Print Network [OSTI]

Subthreshold-swing physics of tunnel field-effect transistors Wei Cao, Deblina Sarkar, Yasin) Subthreshold-swing physics of tunnel field-effect transistors Wei Cao, Deblina Sarkar, Yasin Khatami, Jiahao

307

The effects of buffer layers on the performance and stability of flexible InGaZnO thin film transistors on polyimide substrates  

SciTech Connect (OSTI)

We demonstrated the fabrication of flexible amorphous indium gallium zinc oxide thin-film transistors (TFTs) on high-temperature polyimide (PI) substrates, which were debonded from the carrier glass after TFT fabrication. The application of appropriate buffer layers on the PI substrates affected the TFT performance and stability. The adoption of the SiN{sub x}/AlO{sub x} buffer layers as water and hydrogen diffusion barriers significantly improved the device performance and stability against the thermal annealing and negative bias stress, compared to single SiN{sub x} or SiO{sub x} buffer layers. The substrates could be bent down to a radius of curvature of 15?mm and the devices remained normally functional.

Ok, Kyung-Chul; Park, Jin-Seong, E-mail: hkim-2@naver.com, E-mail: jsparklime@hanyang.ac.kr [Division of Materials Science and Engineering, Hanyang University, 222, Wangsimni-ro, Seongdong-gu, Seoul 133-791 (Korea, Republic of); Ko Park, Sang-Hee; Kim, H., E-mail: hkim-2@naver.com, E-mail: jsparklime@hanyang.ac.kr [Department of Materials Science and Engineering, Korea Advanced Institute of Science and Technology, 291 Daehak-ro, Yuseong-gu, Daejeon 305-701 (Korea, Republic of); Hwang, Chi-Sun [Transparent Electronics Team, ETRI, Daejeon 305-350 (Korea, Republic of); Soo Shin, Hyun; Bae, Jonguk [LG Display R and D Center, LG Display Co., Ltd., Paju 413-811 (Korea, Republic of)

2014-02-10T23:59:59.000Z

308

Identification of a reversible quantum gate: assessing the resources  

E-Print Network [OSTI]

We assess the resources needed to identify a reversible quantum gate among a finite set of alternatives, including in our analysis both deterministic and probabilistic strategies. Among the probabilistic strategies we consider unambiguous gate discrimination, where errors are not tolerated but inconclusive outcomes are allowed, and we prove that parallel strategies are sufficient to unambiguously identify the unknown gate with minimum number of queries. This result is used to provide upper and lower bounds on the query complexity and on the minimum ancilla dimension. In addition, we introduce the notion of generalized t-designs, which includes unitary t-designs and group representations as special cases. For gates forming a generalized t-design we give an explicit expression for the maximum probability of correct gate identification and we prove that there is no gap between the performances of deterministic strategies an those of probabilistic strategies. Hence, evaluating of the query complexity of perfect deterministic discrimination is reduced to the easier problem of evaluating the query complexity of unambiguous discrimination. Finally, we consider discrimination strategies where the use of ancillas is forbidden, providing upper bounds on the number of additional queries needed to make up for the lack of entanglement with the ancillas.

Giulio Chiribella; Giacomo Mauro D'Ariano; Martin Roetteler

2014-09-12T23:59:59.000Z

309

Proposal for a phase-coherent thermoelectric transistor  

SciTech Connect (OSTI)

Identifying materials and devices which offer efficient thermoelectric effects at low temperature is a major obstacle for the development of thermal management strategies for low-temperature electronic systems. Superconductors cannot offer a solution since their near perfect electron-hole symmetry leads to a negligible thermoelectric response; however, here we demonstrate theoretically a superconducting thermoelectric transistor which offers unparalleled figures of merit of up to ?45 and Seebeck coefficients as large as a few mV/K at sub-Kelvin temperatures. The device is also phase-tunable meaning its thermoelectric response for power generation can be precisely controlled with a small magnetic field. Our concept is based on a superconductor-normal metal-superconductor interferometer in which the normal metal weak-link is tunnel coupled to a ferromagnetic insulator and a Zeeman split superconductor. Upon application of an external magnetic flux, the interferometer enables phase-coherent manipulation of thermoelectric properties whilst offering efficiencies which approach the Carnot limit.

Giazotto, F., E-mail: giazotto@sns.it [NEST, Instituto Nanoscienze-CNR and Scuola Normale Superiore, I-56127 Pisa (Italy); Robinson, J. W. A., E-mail: jjr33@cam.ac.uk [Department of Materials Science and Metallurgy, University of Cambridge, 27 Charles Babbage Road, Cambridge CB3 0FS (United Kingdom); Moodera, J. S. [Department of Physics and Francis Bitter Magnet Lab, Massachusetts Institute of Technology, Cambridge, Massachusetts 02139 (United States); Bergeret, F. S., E-mail: sebastian-bergeret@ehu.es [Centro de Física de Materiales (CFM-MPC), Centro Mixto CSIC-UPV/EHU, Manuel de Lardizabal 4, E-20018 San Sebastián (Spain); Donostia International Physics Center (DIPC), Manuel de Lardizabal 5, E-20018 San Sebastián (Spain)

2014-08-11T23:59:59.000Z

310

Modeling Low-Dose-Rate Effects in Irradiated Bipolar-Base Oxides  

SciTech Connect (OSTI)

A physical model is developed to quantify the contribution of oxide-trapped charge to enhanced low-dose-rate gain degradation in bipolar junction transistors. Multiple-trapping simulations show that space charge limited transport is partially responsible for low-dose-rate enhancement. At low dose rates, more holes are trapped near the silicon-oxide interface than at high dose rates, resulting in larger midgap voltage shifts at lower dose rates. The additional trapped charge near the interface may cause an exponential increase in excess base current, and a resultant decrease in current gain for some NPN bipolar technologies.

Cirba, C.R.; Fleetwood, D.M.; Graves, R.J.; Michez, A.; Milanowski, R.J.; Saigne, F.; Schrimpf, R.D.; Witczak, S.C.

1998-10-26T23:59:59.000Z

311

Liquid crystal terahertz phase shifters with functional indium-tin-oxide nanostructures for biasing and alignment  

SciTech Connect (OSTI)

Indium Tin Oxide (ITO) nanowhiskers (NWhs) obliquely evaporated by electron-beam glancing-angle deposition can serve simultaneously as transparent electrodes and alignment layer for liquid crystal (LC) devices in the terahertz (THz) frequency range. To demonstrate, we constructed a THz LC phase shifter with ITO NWhs. Phase shift exceeding ?/2 at 1.0 THz was achieved in a ?517??m-thick cell. The phase shifter exhibits high transmittance (?78%). The driving voltage required for quarter-wave operation is as low as 5.66?V (rms), compatible with complementary metal-oxide-semiconductor (CMOS) and thin-film transistor (TFT) technologies.

Yang, Chan-Shan [Department of Physics, National Tsing Hua University, Hsinchu 30013, Taiwan (China); Chemical Sciences Division, Lawrence Berkeley National Laboratory, Berkeley, California 94720 (United States); Tang, Tsung-Ta [Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan (China); Pan, Ru-Pin [Department of Electrophysics, National Chiao Tung University, Hsinchu 30078, Taiwan (China); Yu, Peichen [Department of Photonics and Institute of Electro-Optical Engineering, National Chiao Tung University, Hsinchu 30010, Taiwan (China); Pan, Ci-Ling, E-mail: clpan@phys.nthu.edu.tw [Department of Physics, National Tsing Hua University, Hsinchu 30013, Taiwan (China); Frontier Research Center on Fundamental and Applied Science of Matters, Hsinchu 30013, Taiwan (China)

2014-04-07T23:59:59.000Z

312

Proposal and design of a new SiC-emitter lateral NPM Schottky collector bipolar transistor on  

E-Print Network [OSTI]

Proposal and design of a new SiC-emitter lateral NPM Schottky collector bipolar transistor on SOI, a SiC emitter lateral NPM Schottky collector bipolar transistor (SCBT) with a silicon-on-insulator (SOI on simulation results, the authors demonstrate for the first time that the proposed SiC emitter lateral NPM

Kumar, M. Jagadesh

313

1070 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, NO. 6, JUNE 2002 A New Lateral PNM Schottky Collector Bipolar Transistor  

E-Print Network [OSTI]

Collector Bipolar Transistor (SCBT) on SOI for Nonsaturating VLSI Logic Design M. Jagadesh Kumar and D. The collector-base junction of the proposed lateral PNM transistor consists of a Schottky junction between n PNM, numerical simulation, Schottky collector, silicon-on-insulator (SOI). I. INTRODUCTION Because

Kumar, M. Jagadesh

314

Oxidation catalyst  

DOE Patents [OSTI]

The present invention generally relates to catalyst systems and methods for oxidation of carbon monoxide. The invention involves catalyst compositions which may be advantageously altered by, for example, modification of the catalyst surface to enhance catalyst performance. Catalyst systems of the present invention may be capable of performing the oxidation of carbon monoxide at relatively lower temperatures (e.g., 200 K and below) and at relatively higher reaction rates than known catalysts. Additionally, catalyst systems disclosed herein may be substantially lower in cost than current commercial catalysts. Such catalyst systems may be useful in, for example, catalytic converters, fuel cells, sensors, and the like.

Ceyer, Sylvia T. (Cambridge, MA); Lahr, David L. (Cambridge, MA)

2010-11-09T23:59:59.000Z

315

Transport properties of single-walled carbon nanotube transistors after gamma radiation treatment  

E-Print Network [OSTI]

potential for high-speed nanosize electronics and biosensors utilizing their superior electronic properties by the gate voltage. At the same time, this different behavior with gate voltage allows us to study is registered at the metal/ semiconductor interface as a result of combined effect of metal work function

Ural, Ant

316

Design Aspects of Carry Lookahead Adders with Vertically-Stacked Nanowire Transistors  

E-Print Network [OSTI]

advanced processing and additional effort in the evaluation of the state-of-the-art technology. One] or used for new functionalities [6]. However, only a few works have assessed the impact of nanowire gates, such as an inverter. Then Section IV reports on the assumptions and the modeling for logic gate

De Micheli, Giovanni

317

Workfunction Tuning of n-Channel MOSFETs Using Interfacial Yttrium Layer in Fully Silicided Nickel Gate  

E-Print Network [OSTI]

Continual scaling of the CMOS technology requires thinner gate dielectric to maintain high performance. However, when moving into the sub-45 nm CMOS generation, the traditional poly-Si gate approach cannot effectively ...

Yu, Hongpeng

318

E-Print Network 3.0 - alternative gate dielectric Sample Search...  

Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

poor quality Ge native dielectrics for gate insulator and field... of the optimum ALD HfO on thin Ge oxynitride (GeO N ) gate ... Source: Chui, Chi On - Electrical Engineering...

319

UC Davis Fuel Cell, Hydrogen, and Hybrid Vehicle (FCH2V) GATE...  

Energy Savers [EERE]

UC Davis Fuel Cell, Hydrogen, and Hybrid Vehicle (FCH2V) GATE Center of Excellence UC Davis Fuel Cell, Hydrogen, and Hybrid Vehicle (FCH2V) GATE Center of Excellence Presentation...

320

Penn State DOE GATE Center of Exellence for In-Vehicle, High...  

Energy Savers [EERE]

Penn State DOE GATE Center of Exellence for In-Vehicle, High-Power Energy Storage Systems Penn State DOE GATE Center of Exellence for In-Vehicle, High-Power Energy Storage Systems...

Note: This page contains sample records for the topic "transistor gate oxide" from the National Library of EnergyBeta (NLEBeta).
While these samples are representative of the content of NLEBeta,
they are not comprehensive nor are they the most current set.
We encourage you to perform a real-time search of NLEBeta
to obtain the most current and comprehensive results.


321

High performance transistors via aligned polyfluorene-sorted carbon nanotubes  

SciTech Connect (OSTI)

We evaluate the performance of exceptionally electronic-type sorted, semiconducting, aligned single-walled carbon nanotubes (s-SWCNTs) in field effect transistors (FETs). High on-conductance and high on/off conductance modulation are simultaneously achieved at channel lengths which are both shorter and longer than individual s-SWCNTs. The s-SWCNTs are isolated from heterogeneous mixtures using a polyfluorene-derivative as a selective agent and aligned on substrates via dose-controlled, floating evaporative self-assembly at densities of ?50 s-SWCNTs ?m{sup ?1}. At a channel length of 9??m the s-SWCNTs percolate to span the FET channel, and the on/off ratio and charge transport mobility are 2.2?×?10{sup 7} and 46?cm{sup 2}?V{sup ?1}?s{sup ?1}, respectively. At a channel length of 400?nm, a large fraction of the s-SWCNTs directly span the channel, and the on-conductance per width is 61??S??m{sup ?1} and the on/off ratio is 4?×?10{sup 5}. These results are considerably better than previous solution-processed FETs, which have suffered from poor on/off ratio due to spurious metallic nanotubes that bridge the channel. 4071 individual and small bundles of s-SWCNTs are tested in 400?nm channel length FETs, and all show semiconducting behavior, demonstrating the high fidelity of polyfluorenes as selective agents and the promise of assembling s-SWCNTs from solution to create high performance semiconductor electronic devices.

Brady, Gerald J.; Joo, Yongho; Singha Roy, Susmit; Gopalan, Padma; Arnold, Michael S., E-mail: msarnold@wisc.edu [Department of Materials Science and Engineering, University of Wisconsin-Madison, 1509 University Avenue, Madison, Wisconsin 53706 (United States)

2014-02-24T23:59:59.000Z

322

The design of a regulated variable power supply for transistor circuits  

E-Print Network [OSTI]

LI BRARg A & M COLLEGE OF TE)gS THE DESIGN OF A REGULATED VARIARLE POMER SUPPLY FOR TRANSISTOR CIRCUITS A THESIS Oscar David Graham Submitted to the Graduate School of the Agricultural snd Mechanical College of Texas in partial fulfillment... of the recpirements for the degree of MASTER OF SCIENCE May 1959 Major Sub/cot: Electrical ~ineering THE DESIGN OF A REGULATED VARIA33LE POWER SUPPLY FOR TRANSISTOR CIRCUITS A Thesis Oscar David Graham Approved as to style and content, by: Cha rman...

Graham, Oscar David

1959-01-01T23:59:59.000Z

323

HfO{sub x}N{sub y} gate dielectric on p-GaAs  

SciTech Connect (OSTI)

Plasma nitridation method is used for nitrogen incorporation in HfO{sub 2} based gate dielectrics for future GaAs-based devices. The nitrided HfO{sub 2} (HfO{sub x}N{sub y}) films on p-GaAs improve metal-oxide-semiconductor device characteristics such as interface state density, accumulation capacitance, hysteresis, and leakage current. An equivalent oxide thickness of 3.6 nm and a leakage current density of 10{sup -6} A cm{sup -2} have been achieved at V{sub FB}-1 V for nitrided HfO{sub 2} films. A nitride interfacial layer (GaAsO:N) was observed at HfO{sub 2}-GaAs interface, which can reduce the outdiffusion of elemental Ga and As during post-thermal annealing process. Such suppression of outdiffusion led to a substantial enhancement in the overall dielectric properties of the HfO{sub 2} film.

Dalapati, G. K.; Sridhara, A.; Wong, A. S. W.; Chia, C. K.; Chi, D. Z. [Institute of Materials Research and Engineering, A-STAR - Agency for Science, Technology and Research, 3 Research Link, Singapore 117602 (Singapore)

2009-02-16T23:59:59.000Z

324

Electron Injection Mechanism in Top-gate Amorphous Silicon Thin-film Transistors with Self-Aligned Silicide Source and Drain  

E-Print Network [OSTI]

Institute for the Science and Technology of Materials (PRISM), Department of Elect. Eng., Princeton. The devices exhibit a threshold voltage of 2.7V, saturation mobility of 1cm2 /Vs, subthreshold slope of 600m from 1cm2 /Vs at L=100µm to 0.65 cm2 /Vs at L=5µm while the observed effective threshold is independent

325

Top-gate thin-film transistors based on GaN channel layer Rongsheng Chen, Wei Zhou, and Hoi Sing Kwok  

E-Print Network [OSTI]

liquid gallium target. The GaN TFTs exhibit good electrical performance such as field effect mobility of 1 cm2 /Vs, threshold voltage of Ã?0.4 V, on/off current ratio of 105 , and subthreshold swing of 0 electrical sta- bility of ZnO-based TFTs is still a main issue preventing from commercialization.9 Bottom

326

Top-gate thin-film transistors based on GaN channel layer Rongsheng Chen, Wei Zhou, and Hoi Sing Kwok  

E-Print Network [OSTI]

exhibit good electrical performance such as field effect mobility of 1 cm2 /Vs, threshold voltage of �0 and poly-Si TFTs.6­8 However, the poor electrical sta- bility of ZnO-based TFTs is still a main issue mobility (6 � 10�2 cm2 /Vs) and low on/off current ratio (3 � 103 ), due to local- ized gap states in Ga

327

Compressed sensing quantum process tomography for superconducting quantum gates  

E-Print Network [OSTI]

We apply the method of compressed sensing (CS) quantum process tomography (QPT) to characterize quantum gates based on superconducting Xmon and phase qubits. Using experimental data for a two-qubit controlled-Z gate, we obtain an estimate for the process matrix $\\chi$ with reasonably high fidelity compared to full QPT, but using a significantly reduced set of initial states and measurement configurations. We show that the CS method still works when the amount of used data is so small that the standard QPT would have an underdetermined system of equations. We also apply the CS method to the analysis of the three-qubit Toffoli gate with numerically added noise, and similarly show that the method works well for a substantially reduced set of data. For the CS calculations we use two different bases in which the process matrix $\\chi$ is approximately sparse, and show that the resulting estimates of the process matrices match each ther with reasonably high fidelity. For both two-qubit and three-qubit gates, we characterize the quantum process by not only its process matrix and fidelity, but also by the corresponding standard deviation, defined via variation of the state fidelity for different initial states.

Andrey V. Rodionov; Andrzej Veitia; R. Barends; J. Kelly; Daniel Sank; J. Wenner; John M. Martinis; Robert L. Kosut; Alexander N. Korotkov

2014-07-03T23:59:59.000Z

328

Quantum phase gate for optical qubits with cavity quantum optomechanics  

E-Print Network [OSTI]

We show that a cavity optomechanical system formed by a mechanical resonator simultaneously coupled to two modes of an optical cavity can be used for the implementation of quantum phase gate between optical qubits associated with the two intracavity modes. The scheme is realizable for sufficiently strong single-photon optomechanical coupling in the resolved sideband regime, and is robust against cavity losses.

Muhammad Asjad; Paolo Tombesi; David Vitali

2015-01-16T23:59:59.000Z

329

ECG Gated Tomographic reconstruction for 3-D Rotational Coronary Angiography  

E-Print Network [OSTI]

imaging techniques to improve both the safety and the efficacy of coronary angiography interventions the ground for a platform dedicated to the planning and execution of percutaneous coronary inter- ventionsECG Gated Tomographic reconstruction for 3-D Rotational Coronary Angiography Yining HU, Lizhe XIE

Paris-Sud XI, Université de

330

Advanced Gate Drive for the SNS High Voltage Converter Modulator  

SciTech Connect (OSTI)

SLAC National Accelerator Laboratory is developing a next generation H-bridge switch plate [1], a critical component of the SNS High Voltage Converter Modulator [2]. As part of that effort, a new IGBT gate driver has been developed. The drivers are an integral part of the switch plate, which are essential to ensuring fault-tolerant, high-performance operation of the modulator. The redesigned driver improves upon the existing gate drive in several ways. The new gate driver has improved fault detection and suppression capabilities; suppression of shoot-through and over-voltage conditions, monitoring of dI/dt and Vce(sat) for fast over-current detection and suppression, and redundant power isolation are some of the added features. In addition, triggering insertion delay is reduced by a factor of four compared to the existing driver. This paper details the design and performance of the new IGBT gate driver. A simplified schematic and description of the construction are included. The operation of the fast over-current detection circuits, active IGBT over-voltage protection circuit, shoot-through prevention circuitry, and control power isolation breakdown detection circuit are discussed.

Nguyen, M.N.; Burkhart, C.; Kemp, M.A.; /SLAC; Anderson, D.E.; /Oak Ridge

2009-05-07T23:59:59.000Z

331

An overview of the gate and panel industry  

E-Print Network [OSTI]

acquiring raw materials, its pre-fabrication, welding, touch-up, and delivery of the product. My first major responsibility for Texas Gate and Panel was to expand its sales territory. It soon became obvious that a thorough knowledge of my competitors...

Fisher, C. West

2000-01-01T23:59:59.000Z

332

Controlling attosecond electron dynamics by phase-stabilized polarization gating  

E-Print Network [OSTI]

LETTERS Controlling attosecond electron dynamics by phase-stabilized polarization gating I. J. SOLA the signature of a single return of the electron wavepacket over a large range of energies. This temporally (low energy) and cut-off (high energy) harmonics, specific focusing conditions ensure that only

Loss, Daniel

333

Optical gating of perylene bisimide fluorescence using dithienylcyclopentene photochromic switches  

SciTech Connect (OSTI)

The emission of millions of fluorescence photons from a chromophore is controlled by the absorption of a few tens of photons in a photochromic molecule. The parameters that determine the efficiency of this process are investigated, providing insights for the development of an all-optical gate.

Pärs, Martti; Köhler, Jürgen, E-mail: juergen.koehler@uni-bayreuth.de [Experimental Physics IV, University of Bayreuth, 95440 Bayreuth (Germany)] [Experimental Physics IV, University of Bayreuth, 95440 Bayreuth (Germany); Gräf, Katja; Bauer, Peter; Thelakkat, Mukundan [Applied Functional Polymers, University of Bayreuth, 95440 Bayreuth (Germany)] [Applied Functional Polymers, University of Bayreuth, 95440 Bayreuth (Germany)

2013-11-25T23:59:59.000Z

334

Controlling Wild Mobile Robots Using Virtual Gates and Discrete Transitions  

E-Print Network [OSTI]

Controlling Wild Mobile Robots Using Virtual Gates and Discrete Transitions Leonardo Bobadilla purposely design them to execute wild motions, which means each will strike every open set infinitely often, "wildly behaving" robots that move more-or-less straight until a wall is contacted. They then pick

LaValle, Steven M.

335

TECH FORUM: [VERIFIED RTL TO GATES] Efficient RC power grid  

E-Print Network [OSTI]

TECH FORUM: [VERIFIED RTL TO GATES] Efficient RC power grid verification using node elimination proposes a novel approach to systematically reduce the power grid and accurately compute an upper bound on the voltage drops at power grid nodes that are retained. Furthermore, acriterion for the safety of nodes

Najm, Farid N.

336

AN ADAPTIVE MIXED SCHEME FOR ENERGY-TRANSPORT SIMULATIONS OF FIELD-EFFECT TRANSISTORS  

E-Print Network [OSTI]

AN ADAPTIVE MIXED SCHEME FOR ENERGY-TRANSPORT SIMULATIONS OF FIELD-EFFECT TRANSISTORS #3; STEFAN HOLST, ANSGAR J  UNGEL y AND PAOLA PIETRA z Abstract. Energy-transport models are used in semiconductor and energy of the electrons, coupled to the Poisson equation for the electrostatic potential. The movement

Pietra, Paola

337

HIGH-LEVEL MULTI-STEP INVERTER OPTIMIZATION, USING A MINIMUM NUMBER OF POWER TRANSISTORS.  

E-Print Network [OSTI]

HIGH-LEVEL MULTI-STEP INVERTER OPTIMIZATION, USING A MINIMUM NUMBER OF POWER TRANSISTORS. Juan 56-41-246-999 e-mail lmoran@renoir.die.udec.cl ABSTRACT Multilevel inverters with a large number-5]. Multi-level inverters can operate not only with PWM techniques but also with amplitude modulation (AM

Catholic University of Chile (Universidad Católica de Chile)

338

Physics 326 Spring 2014 1/15/14 Lab 4: DIODES AND TRANSISTORS  

E-Print Network [OSTI]

Physics 326 Spring 2014 1/15/14 1 Lab 4: DIODES AND TRANSISTORS Please read Faissler Chapters. The transformer has a center tap (i.e. a line connected to the center of the coil). Characterize the transformer Spring 2014 1/15/14 2 Describe the effect of the capacitor on the output. Repeat with a 0.1 F capacitor

Glashausser, Charles

339

SELF-HEATING PROCESS IN MICROWAVE TRANSISTORS Anthony E. Parker(1) and James G. Rathmell(2)  

E-Print Network [OSTI]

by the complex signals used in communication systems. Self-heating [1] and charge-trapping related to impactSELF-HEATING PROCESS IN MICROWAVE TRANSISTORS Anthony E. Parker(1) and James G. Rathmell(2) (1 of Electrical and Information Engineering, The University of Sydney, AUSTRALIA 2006, mailto: jimr

340

Transistor Sizing of Energy-DelayEfficient Circuits Paul I. Penzes, Mika Nystrom, Alain J. Martin  

E-Print Network [OSTI]

-off, not only the trade-off through voltage scaling, between the energy and the delay of a computation [4Transistor Sizing of Energy-Delay­Efficient Circuits Paul I. P´enzes, Mika Nystr¨om, Alain J optimized for energy-delay efficiency, i.e., for optimal ¢¤£¦¥ where ¢ is the energy consumption

Note: This page contains sample records for the topic "transistor gate oxide" from the National Library of EnergyBeta (NLEBeta).
While these samples are representative of the content of NLEBeta,
they are not comprehensive nor are they the most current set.
We encourage you to perform a real-time search of NLEBeta
to obtain the most current and comprehensive results.


341

Bendable single crystal silicon thin film transistors formed by printing on plastic substrates  

E-Print Network [OSTI]

Bendable single crystal silicon thin film transistors formed by printing on plastic substrates E on plastic substrates using an efficient dry transfer printing technique. In these devices, free standing-Si is then transferred, to a specific location and with a controlled orientation, onto a thin plastic sheet

Rogers, John A.

342

CBC Reduction in InP Heterojunction Bipolar Transistor with Selectively Implanted Collector Pedestal  

E-Print Network [OSTI]

CBC Reduction in InP Heterojunction Bipolar Transistor with Selectively Implanted Collector-3812 Fax: (805) 893-8714 Email: yingda@ece.ucsb.edu The base-collector junction capacitance (Cbc) is a key with a collector pedestal under the HBT's intrinsic region by using selective ion implantation and MBE regrowth

Rodwell, Mark J. W.

343

Jet-printed electrodes and semiconducting oligomers for elaboration of organic thin-film transistors  

E-Print Network [OSTI]

demonstrated the possibility to fabricate inexpensive OTFTs by direct writing paving the way toward using candidates to make organic thin-film transistors (OTFTs) active components for the fab- rication of low-cost], and OTFT display backplanes [3]. However, the carrying out of OTFTs does not attain the low-cost expected

Hone, James

344

Ann. Phys. (Leipzig) 9 (2000) 1112, 885 894 The single electron transistor and artificial atoms  

E-Print Network [OSTI]

Ann. Phys. (Leipzig) 9 (2000) 11­12, 885 ­ 894 The single electron transistor and artificial atoms M. A. Kastner Department of Physics, Massachusetts Institute of Technology, Cambridge, MA 02139 USA, there is a close analogy between the confined electrons inside an SET and an atom. In this review, the physics

Wilczek, Frank

345

A real-time respiration position based passive breath gating equipment for gated radiotherapy: A preclinical evaluation  

SciTech Connect (OSTI)

Purpose: To develop a passive gating system incorporating with the real-time position management (RPM) system for the gated radiotherapy. Methods: Passive breath gating (PBG) equipment, which consists of a breath-hold valve, a controller mechanism, a mouthpiece kit, and a supporting frame, was designed. A commercial real-time positioning management system was implemented to synchronize the target motion and radiation delivery on a linear accelerator with the patient's breathing cycle. The respiratory related target motion was investigated by using the RPM system for correlating the external markers with the internal target motion while using PBG for passively blocking patient's breathing. Six patients were enrolled in the preclinical feasibility and efficiency study of the PBG system. Results: PBG equipment was designed and fabricated. The PBG can be manually triggered or released to block or unblock patient's breathing. A clinical workflow was outlined to integrate the PBG with the RPM system. After implementing the RPM based PBG system, the breath-hold period can be prolonged to 15-25 s and the treatment delivery efficiency for each field can be improved by 200%-400%. The results from the six patients showed that the diaphragm motion caused by respiration was reduced to less than 3 mm and the position of the diaphragm was reproducible for difference gating periods. Conclusions: A RPM based PBG system was developed and implemented. With the new gating system, the patient's breath-hold time can be extended and a significant improvement in the treatment delivery efficiency can also be achieved.

Hu Weigang; Xu Anjie; Li Guichao; Zhang Zhen; Housley, Dave; Ye Jinsong [Department of Radiation Oncology, Fudan University Shanghai Cancer Center and Department of Oncology, Shanghai Medical College, Fudan University, Shanghai 200032 (China); Department of Radiation Oncology, Swedish Cancer Institute, Seattle, Washington 98104 (United States)

2012-03-15T23:59:59.000Z

346

Presented at the 2003 USSD Annual Lecture, Charleston, South Carolina. April 2003. SPILLWAY GATE RELIABILITY IN THE CONTEXT OF  

E-Print Network [OSTI]

and operations are listed and illustrated through their application to the Thames Flood Barrier gates

Bowles, David S.

347

THE GROWTH MECHANISMS OF ULTRATHIN GATE DIELECTRICS ON SILICON  

E-Print Network [OSTI]

in the passive oxidation regime, while etching in the active oxidation regime made the surface slightly rougher. A roughening regime is also observed in between the active and passive oxidation regimes and causes, I was fortunate to share a house with Alex See, from whom Qing-Tang heard about me and recruited me

Gustafsson, Torgny

348

Role of the dielectric for the charging dynamics of the dielectric/barrier interface in AlGaN/GaN based metal-insulator-semiconductor structures under forward gate bias stress  

SciTech Connect (OSTI)

The high density of defect states at the dielectric/III-N interface in GaN based metal-insulator-semiconductor structures causes tremendous threshold voltage drifts, ?V{sub th}, under forward gate bias conditions. A comprehensive study on different dielectric materials, as well as varying dielectric thickness t{sub D} and barrier thickness t{sub B}, is performed using capacitance-voltage analysis. It is revealed that the density of trapped electrons, ?N{sub it}, scales with the dielectric capacitance under spill-over conditions, i.e., the accumulation of a second electron channel at the dielectric/AlGaN barrier interface. Hence, the density of trapped electrons is defined by the charging of the dielectric capacitance. The scaling behavior of ?N{sub it} is explained universally by the density of accumulated electrons at the dielectric/III-N interface under spill-over conditions. We conclude that the overall density of interface defects is higher than what can be electrically measured, due to limits set by dielectric breakdown. These findings have a significant impact on the correct interpretation of threshold voltage drift data and are of relevance for the development of normally off and normally on III-N/GaN high electron mobility transistors with gate insulation.

Lagger, P., E-mail: peter.lagger@infineon.com [Infineon Technologies Austria AG, Siemensstraße 2, 9500 Villach (Austria); Institute of Solid State Electronics, Vienna University of Technology, Floragasse 7, 1040 Wien (Austria); Steinschifter, P.; Reiner, M.; Stadtmüller, M.; Denifl, G.; Ostermaier, C. [Infineon Technologies Austria AG, Siemensstraße 2, 9500 Villach (Austria); Naumann, A.; Müller, J.; Wilde, L.; Sundqvist, J. [Fraunhofer IPMS-CNT, Königsbrücker Straße 178, 01099 Dresden (Germany); Pogany, D. [Institute of Solid State Electronics, Vienna University of Technology, Floragasse 7, 1040 Wien (Austria)

2014-07-21T23:59:59.000Z

349

DOI: 10.1002/adma.200601908 Piezoelectric Gated Diode of a Single ZnO Nanowire**  

E-Print Network [OSTI]

Institute of Physics. DOI: 10.1063/1.2193468 Electrical and optoelectronic devices such as field class of organic optoelectronic devices has been demonstrated, i.e., organic light-emitting transistors

Wang, Zhong L.

350

Current limiters based on silicon pillar un-gated FET for field emission application  

E-Print Network [OSTI]

This research investigates the use of vertical silicon ungated field effect transistors (FETs) as current limiters to individuallycontrol emission current in a field emitter and provide a simple solution to three problems ...

Niu, Ying, M. Eng. Massachusetts Institute of Technology

2009-01-01T23:59:59.000Z

351

Fabrication and characterization of modulation-doped-field-effect-transistors with antidot-patterned passivation layers  

E-Print Network [OSTI]

layer with 1 1017 cm 3 Si doping, 50 nm Al0.3Ga0.7As spacer with 1 1018 cm 3 Si doping, 15 nm undoped Al0.3Ga0.7As spacer, 500 nm un- doped GaAs channel layer, 20 periods of 5/5 nm GaAs/ Al. For the demonstration of the internal gate patterning, two types of MODFET's with the same overall gate dimensions

Hwang, Sung Woo

352

Mixing at 50 GHz using a single-walled carbon nanotube transistor Sami Rosenblatt,a  

E-Print Network [OSTI]

. The nanotubes were contacted with 50-nm-thick Pd.4 For probing, pads were made with a 5 nm Cr adhesion layer, 50 nm Au, and 10 nm Au­Pd alloy. Evaporation of 10 nm of evaporated silicon dioxide for the gate insulator16 was fol- lowed by evaporation of 50 nm Al for the top gate electrode. The source-drain contact

McEuen, Paul L.

353

Project Profile: High Performance Reduction/Oxidation Metal Oxides...  

Office of Environmental Management (EM)

High Performance ReductionOxidation Metal Oxides for Thermochemical Energy Storage Project Profile: High Performance ReductionOxidation Metal Oxides for Thermochemical Energy...

354

Improved phase gate reliability in systems with neutral Ising anyons  

E-Print Network [OSTI]

Recent proposals using heterostructures of superconducting and either topologically insulating or semiconducting layers have been put forth as possible platforms for topological quantum computation. These systems are predicted to contain Ising anyons and share the feature of having only neutral edge excitations. In this note, we show that these proposals can be combined with the recently proposed "sack geometry" for implementation of a phase gate in order to conduct robust universal quantum computation. In addition, we propose a general method for adjusting edge tunneling rates in such systems, which is necessary for the control of interferometric devices. The error rate for the phase gate in neutral Ising systems is parametrically smaller than for a similar geometry in which the edge modes carry charge: it goes as $T^3$ rather than $T$ at low temperatures. At zero temperature, the phase variance becomes constant at long times rather than carrying a logarithmic divergence.

David J. Clarke; Kirill Shtengel

2010-09-01T23:59:59.000Z

355

Photon-photon gates in Bose-Einstein condensates  

E-Print Network [OSTI]

It has recently been shown that light can be stored in Bose-Einstein condensates for over a second. Here we propose a method for realizing a controlled phase gate between two stored photons. The photons are both stored in the ground state of the effective trapping potential inside the condensate. The collision-induced interaction is enhanced by adiabatically increasing the trapping frequency and by using a Feshbach resonance. A controlled phase shift of $\\pi$ can be achieved in one second.

Arnaud Rispe; Bing He; Christoph Simon

2010-09-30T23:59:59.000Z

356

A compact transport and charge model for GaN-based high electron mobility transistors for RF applications  

E-Print Network [OSTI]

Gallium Nitride (GaN)-based high electron mobility transistors (HEMTs) are rapidly emerging as front-runners in high-power mm-wave circuit applications. For circuit design with current devices and to allow sensible future ...

Radhakrishna, Ujwal

2013-01-01T23:59:59.000Z

357

Glow Discharge Characteristics of Non-thermal Microplasmas at above Atmospheric Pressures and their Applications in Microscale Plasma Transistors  

E-Print Network [OSTI]

A microscale plasma transistor capable of high speed switching was manufactured using microfabrication techniques and operated using microplasma discharges. Such a device has feature sizes on the order of 25 ?m, is robust against spikes in power...

Wakim, Dani Ghassan

2013-07-25T23:59:59.000Z

358

Ultrathin organic transistors for chemical sensing Richard D. Yang, T. Gredig, Corneliu N. Colesniuc, Jeongwon Park, Ivan K. Schuller,  

E-Print Network [OSTI]

Lab, Materials Science and Engineering, Department of Physics and Department of Chemistry in the ultrathin transistors. CoPc was purchased from Sigma-Aldrich and purified by zone sublimation below 10

Kummel, Andrew C.

359

GATE Center for Automotive Fuel Cell Systems at Virginia Tech  

SciTech Connect (OSTI)

The Virginia Tech GATE Center for Automotive Fuel Cell Systems (CAFCS) achieved the following objectives in support of the domestic automotive industry: â?¢ Expanded and updated fuel cell and vehicle technologies education programs; â?¢ Conducted industry directed research in three thrust areas â?? development and characterization of materials for PEM fuel cells; performance and durability modeling for PEM fuel cells; and fuel cell systems design and optimization, including hybrid and plug-in hybrid fuel cell vehicles; â?¢ Developed MS and Ph.D. engineers and scientists who are pursuing careers related to fuel cells and automotive applications; â?¢ Published research results that provide industry with new knowledge which contributes to the advancement of fuel cell and vehicle systems commercialization. With support from the Dept. of Energy, the CAFCS upgraded existing graduate course offerings; introduced a hands-on laboratory component that make use of Virginia Techâ??s comprehensive laboratory facilities, funded 15 GATE Fellowships over a five year period; and expanded our program of industry interaction to improve student awareness of challenges and opportunities in the automotive industry. GATE Center graduate students have a state-of-the-art research experience preparing them for a career to contribute to the advancement fuel cell and vehicle technologies.

Douglas Nelson

2011-05-31T23:59:59.000Z

360

Two-dimensional electron gases in strained quantum wells for AlN/GaN/AlN double heterostructure field-effect transistors on AlN  

SciTech Connect (OSTI)

Double heterostructures of strained GaN quantum wells (QWs) sandwiched between relaxed AlN layers provide a platform to investigate the quantum-confined electronic and optical properties of the wells. The growth of AlN/GaN/AlN heterostructures with varying GaN quantum well thicknesses on AlN by plasma molecular beam epitaxy (MBE) is reported. Photoluminescence spectra provide the optical signature of the thin GaN QWs. Reciprocal space mapping in X-ray diffraction shows that a GaN layer as thick as ?28 nm is compressively strained to the AlN layer underneath. The density of the polarization-induced two-dimensional electron gas (2DEG) in the undoped heterostructures increases with the GaN QW thickness, reaching ?2.5?×?10{sup 13}/cm{sup 2}. This provides a way to tune the 2DEG channel density without changing the thickness of the top barrier layer. Electron mobilities less than ?400 cm{sup 2}/Vs are observed, leaving ample room for improvement. Nevertheless, owing to the high 2DEG density, strained GaN QW field-effect transistors with MBE regrown ohmic contacts exhibit an on-current density ?1.4?A/mm, a transconductance ?280 mS/mm, and a cut off frequency f{sub T}?104?GHz for a 100-nm-gate-length device. These observations indicate high potential for high-speed radio frequency and high voltage applications that stand to benefit from the extreme-bandgap and high thermal conductivity of AlN.

Li, Guowang; Song, Bo; Ganguly, Satyaki; Zhu, Mingda; Wang, Ronghua; Yan, Xiaodong; Verma, Jai; Protasenko, Vladimir; Grace Xing, Huili; Jena, Debdeep, E-mail: djena@nd.edu [Department of Electrical Engineering, University of Notre Dame, Indiana 46556 (United States)

2014-05-12T23:59:59.000Z

Note: This page contains sample records for the topic "transistor gate oxide" from the National Library of EnergyBeta (NLEBeta).
While these samples are representative of the content of NLEBeta,
they are not comprehensive nor are they the most current set.
We encourage you to perform a real-time search of NLEBeta
to obtain the most current and comprehensive results.


361

Asphalt Oxidation Kinetics and Pavement Oxidation Modeling  

E-Print Network [OSTI]

Most paved roads in the United States are surfaced with asphalt. These asphalt pavements suffer from fatigue cracking and thermal cracking, aggravated by the oxidation and hardening of asphalt. This negative impact of asphalt oxidation on pavement...

Jin, Xin

2012-07-16T23:59:59.000Z

362

Use of a hard mask for formation of gate and dielectric via nanofilament field emission devices  

DOE Patents [OSTI]

A process for fabricating a nanofilament field emission device in which a via in a dielectric layer is self-aligned to gate metal via structure located on top of the dielectric layer. By the use of a hard mask layer located on top of the gate metal layer, inert to the etch chemistry for the gate metal layer, and in which a via is formed by the pattern from etched nuclear tracks in a trackable material, a via is formed by the hard mask will eliminate any erosion of the gate metal layer during the dielectric via etch. Also, the hard mask layer will protect the gate metal layer while the gate structure is etched back from the edge of the dielectric via, if such is desired. This method provides more tolerance for the electroplating of a nanofilament in the dielectric via and sharpening of the nanofilament.

Morse, Jeffrey D. (Martinez, CA); Contolini, Robert J. (Lake Oswego, OR)

2001-01-01T23:59:59.000Z

363

Growth and properties of crystalline barium oxide on the GaAs(100) substrate  

SciTech Connect (OSTI)

Growing a crystalline oxide film on III-V semiconductor renders possible approaches to improve operation of electronics and optoelectronics heterostructures such as oxide/semiconductor junctions for transistors and window layers for solar cells. We demonstrate the growth of crystalline barium oxide (BaO) on GaAs(100) at low temperatures, even down to room temperature. Photoluminescence (PL) measurements reveal that the amount of interface defects is reduced for BaO/GaAs, compared to Al{sub 2}O{sub 3}/GaAs, suggesting that BaO is a useful buffer layer to passivate the surface of the III-V device material. PL and photoemission data show that the produced junction tolerates the post heating around 600?°C.

Yasir, M.; Dahl, J.; Lång, J.; Tuominen, M.; Punkkinen, M. P. J.; Laukkanen, P., E-mail: pekka.laukkanen@utu.fi; Kokko, K. [Department of Physics and Astronomy, University of Turku, FI-20014 Turku (Finland)] [Department of Physics and Astronomy, University of Turku, FI-20014 Turku (Finland); Kuzmin, M. [Department of Physics and Astronomy, University of Turku, FI-20014 Turku (Finland) [Department of Physics and Astronomy, University of Turku, FI-20014 Turku (Finland); Ioffe Physical-Technical Institute, Russian Academy of Sciences, St. Petersburg 194021 (Russian Federation); Korpijärvi, V.-M.; Polojärvi, V.; Guina, M. [Optoelectronics Research Centre, Tampere University of Technology, FI-33101 Tampere (Finland)] [Optoelectronics Research Centre, Tampere University of Technology, FI-33101 Tampere (Finland)

2013-11-04T23:59:59.000Z

364

Nanoporous carbon tunable resistor/transistor and methods of production thereof  

DOE Patents [OSTI]

In one embodiment, a tunable resistor/transistor includes a porous material that is electrically coupled between a source electrode and a drain electrode, wherein the porous material acts as an active channel, an electrolyte solution saturating the active channel, the electrolyte solution being adapted for altering an electrical resistance of the active channel based on an applied electrochemical potential, wherein the active channel comprises nanoporous carbon arranged in a three-dimensional structure. In another embodiment, a method for forming the tunable resistor/transistor includes forming a source electrode, forming a drain electrode, and forming a monolithic nanoporous carbon material that acts as an active channel and selectively couples the source electrode to the drain electrode electrically. In any embodiment, the electrolyte solution saturating the nanoporous carbon active channel is adapted for altering an electrical resistance of the nanoporous carbon active channel based on an applied electrochemical potential.

Biener, Juergen; Baumann, Theodore F; Dasgupta, Subho; Hahn, Horst

2014-04-22T23:59:59.000Z

365

Simple trapped-ion architecture for high-fidelity Toffoli gates  

SciTech Connect (OSTI)

We discuss a simple architecture for a quantum toffoli gate implemented using three trapped ions. The gate, which, in principle, can be implemented with a single laser-induced operation, is effective under rather general conditions and is strikingly robust (within any experimentally realistic range of values) against dephasing, heating, and random fluctuations of the Hamiltonian parameters. We provide a full characterization of the unitary and noise-affected gate using three-qubit quantum process tomography.

Borrelli, Massimo [CM-DTC, SUPA, EPS/School of Engineering and Physical Sciences, Heriot-Watt University, Edinburgh EH14 4AS (United Kingdom); Mazzola, Laura [Turku Centre for Quantum Physics, Department of Physics and Astronomy, University of Turku, FI-20014 Turun yliopisto (Finland); School of Mathematics and Physics, Queen's University, BT7 1NN Belfast (United Kingdom); Paternostro, Mauro [School of Mathematics and Physics, Queen's University, BT7 1NN Belfast (United Kingdom); Maniscalco, Sabrina [CM-DTC, SUPA, EPS/School of Engineering and Physical Sciences, Heriot-Watt University, Edinburgh EH14 4AS (United Kingdom); Turku Centre for Quantum Physics, Department of Physics and Astronomy, University of Turku, FI-20014 Turun yliopisto (Finland)

2011-07-15T23:59:59.000Z

366

Thin film transistors on plastic substrates with reflective coatings for radiation protection  

DOE Patents [OSTI]

Fabrication of silicon thin film transistors (TFT) on low-temperature plastic substrates using a reflective coating so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The TFT can be used in large area low cost electronics, such as flat panel displays and portable electronics such as video cameras, personal digital assistants, and cell phones.

Wolfe, Jesse D.; Theiss, Steven D.; Carey, Paul G.; Smith, Patrick M.; Wickboldt, Paul

2003-11-04T23:59:59.000Z

367

Thin film transistors on plastic substrates with reflective coatings for radiation protection  

DOE Patents [OSTI]

Fabrication of silicon thin film transistors (TFT) on low-temperature plastic substrates using a reflective coating so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The TFT can be used in large area low cost electronics, such as flat panel displays and portable electronics such as video cameras, personal digital assistants, and cell phones.

Wolfe, Jesse D. (Fairfield, CA); Theiss, Steven D. (Woodbury, MN); Carey, Paul G. (Mountain View, CA); Smith, Patrick M. (San Ramon, CA); Wickbold, Paul (Walnut Creek, CA)

2006-09-26T23:59:59.000Z

368

Bill Gates and Deputy Secretary Poneman Discuss the Energy Technology Landscape  

Broader source: Energy.gov [DOE]

Bill Gates and Deputy Secretary of Energy Daniel Poneman discuss the future of energy technology during the twenty-second Plenary Meeting of the Nuclear Suppliers Group.

369

Locally observable conditions for the successful implementation of entangling multi-qubit quantum gates  

E-Print Network [OSTI]

The information obtained from the operation of a quantum gate on only two complementary sets of input states is sufficient to estimate the quantum process fidelity of the gate. In the case of entangling gates, these conditions can be used to predict the multi qubit entanglement capability from the fidelities of two non-entangling local operations. It is then possible to predict highly non-classical features of the gate such as violations of local realism from the fidelities of two completely classical input-output relations, without generating any actual entanglement.

Holger F. Hofmann; Ryo Okamoto; Shigeki Takeuchi

2005-09-01T23:59:59.000Z

370

Rapid optimization of working parameters of microwave-driven multilevel qubits for minimal gate leakage  

E-Print Network [OSTI]

.0134 is the interaction between the qubits, .0020 .0136 M=L is the coupling constant, and x i , x ei , and h.0133x i .0134 (i .0136 1 and 2) are the canonical coordinate, normal- ized external flux, and Hamiltonian of the ith single qubit. Note... for the gate at the point B. The quality of a gate can be described by gate fidelity F .0017 Trace.0137.0026 P .0026 I .0138, where .0026 P and.0026 I are the physical and ideal density matrices after gate operation and the overline denotes averaging over all...

Zhou, Zhongyuan; Han, Siyuan; Chu, Shih-I

2005-09-16T23:59:59.000Z

371

Use of high-level design information for enabling automation of fine-grained power gating  

E-Print Network [OSTI]

Leakage power reduction through power gating requires considerable design and verification effort. Conventionally, extensive analysis is required for dividing a heterogeneous design into power domains and generating control ...

Agarwal, Abhinav

2014-01-01T23:59:59.000Z

372

Error Compensation of Single-Qubit Gates in a Surface Electrode Ion Trap Using Composite Pulses  

E-Print Network [OSTI]

The trapped atomic ion qubits feature desirable properties for use in a quantum computer such as long coherence times (Langer et al., 2005), high qubit measurement fidelity (Noek et al., 2013), and universal logic gates (Home et al., 2009). The quality of quantum logic gate operations on trapped ion qubits has been limited by the stability of the control fields at the ion location used to implement the gate operations. For this reason, the logic gates utilizing microwave fields (Brown et al., 2011; Shappert et al., 2013; Harty et al., 2014) have shown gate fidelities several orders of magnitude better than those using laser fields (Knill et al., 2008; Benhelm et al., 2008; Ballance et al., 2014). Here, we demonstrate low-error single-qubit gates performed using stimulated Raman transitions on an ion qubit trapped in a microfabricated chip trap. Gate errors are measured using a randomized benchmarking protocol (Knill et al., 2008; Wallman et al., 2014; Magesan et al., 2012), where amplitude error in the control beam is compensated using various pulse sequence techniques (Wimperis, 1994; Low et al., 2014). Using B2 compensation (Wimperis, 1994), we demonstrate single qubit gates with an average error per randomized Clifford group gate of $3.6(3)\\times10^{-4}$. We also show that compact palindromic pulse compensation sequences (PD$n$) (Low et al., 2014) compensate for amplitude errors as designed.

Emily Mount; Chingiz Kabytayev; Stephen Crain; Robin Harper; So-Young Baek; Geert Vrijsen; Steven Flammia; Kenneth R. Brown; Peter Maunz; Jungsang Kim

2015-04-06T23:59:59.000Z

373

2006-2010 GATE program at Ohio State University Center for Automotive...  

Broader source: Energy.gov (indexed) [DOE]

DOE Office of Vehicle Technologies "Mega" Merit Review 2008 on February 25, 2008 in Bethesda, Maryland. merit08guezennec.pdf More Documents & Publications GATE: Energy Efficient...

374

Three-qubit phase gate based on cavity quantum electrodynamics  

E-Print Network [OSTI]

- mentation, such as linear ion traps #4;1#5;, liquid-state nuclear magnetic resonance #1;NMR#2; #4;2#5;, and cavity QED systems #4;3,4#5;. There are three requirements for implementing a quantum computer: Efficient manipulation and read out of an indi.... #4;6#5;, a scheme to implement a two-qubit quantum phase gate and one-qubit unitary operation implementation based on cavity QED was described. They choose the Fock states #6;0#7; and #6;1#7; of a high Q cavity mode as the two logical states of a...

Chang, Jun-Tao; Zubairy, M. Suhail

2008-01-01T23:59:59.000Z

375

Gate Hours & Services | Stanford Synchrotron Radiation Lightsource  

Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

AFDC Printable Version Share this resource Send a link to EERE: Alternative Fuels Data Center Home Page to someone by E-mail Share EERE: Alternative Fuels Data Center Home Page on Facebook Tweet about EERE: Alternative Fuels Data Center Home Page on Twitter Bookmark EERE:1 First Use of Energy for All Purposes (Fuel and Nonfuel),Feet) Year Jan Feb Mar Apr May JunDatastreamsmmcrcalgovInstrumentsruc DocumentationP-SeriesFlickr Flickr Editor'sshort version) Thelong version)shortGate Hours &

376

Photo-oxidation catalysts  

DOE Patents [OSTI]

Photo-oxidation catalysts and methods for cleaning a metal-based catalyst are disclosed. An exemplary catalyst system implementing a photo-oxidation catalyst may comprise a metal-based catalyst, and a photo-oxidation catalyst for cleaning the metal-based catalyst in the presence of light. The exposure to light enables the photo-oxidation catalyst to substantially oxidize absorbed contaminants and reduce accumulation of the contaminants on the metal-based catalyst. Applications are also disclosed.

Pitts, J. Roland (Lakewood, CO); Liu, Ping (Irvine, CA); Smith, R. Davis (Golden, CO)

2009-07-14T23:59:59.000Z

377

Low-frequency 1/f noise in MoS{sub 2} transistors: Relative contributions of the channel and contacts  

SciTech Connect (OSTI)

We report on the results of the low-frequency (1/f, where f is frequency) noise measurements in MoS{sub 2} field-effect transistors revealing the relative contributions of the MoS{sub 2} channel and Ti/Au contacts to the overall noise level. The investigation of the 1/f noise was performed for both as fabricated and aged transistors. It was established that the McWhorter model of the carrier number fluctuations describes well the 1/f noise in MoS{sub 2} transistors, in contrast to what is observed in graphene devices. The trap densities extracted from the 1/f noise data for MoS{sub 2} transistors, are 2?×?10{sup 19}?eV{sup ?1}cm{sup ?3} and 2.5?×?10{sup 20}?eV{sup ?1}cm{sup ?3} for the as fabricated and aged devices, respectively. It was found that the increase in the noise level of the aged MoS{sub 2} transistors is due to the channel rather than the contact degradation. The obtained results are important for the proposed electronic applications of MoS{sub 2} and other van der Waals materials.

Renteria, J.; Jiang, C. [Nano-Device Laboratory, Department of Electrical Engineering, Bourns College of Engineering, University of California – Riverside, Riverside, California 92521 (United States); Samnakay, R. [Materials Science and Engineering Program, Bourns College of Engineering, University of California – Riverside, Riverside, California 92521 (United States); Rumyantsev, S. L. [Department of Electrical, Computer, and Systems Engineering, Center for Integrated Electronics, Rensselaer Polytechnic Institute, Troy, New York 12180 (United States); Ioffe Physical-Technical Institute, St. Petersburg 194021 (Russian Federation); Goli, P.; Balandin, A. A., E-mail: balandin@ee.ucr.edu [Nano-Device Laboratory, Department of Electrical Engineering, Bourns College of Engineering, University of California – Riverside, Riverside, California 92521 (United States); Materials Science and Engineering Program, Bourns College of Engineering, University of California – Riverside, Riverside, California 92521 (United States); Shur, M. S. [Department of Electrical, Computer, and Systems Engineering, Center for Integrated Electronics, Rensselaer Polytechnic Institute, Troy, New York 12180 (United States)

2014-04-14T23:59:59.000Z

378

Gate Reliability Assessment for a Spillway Upgrade Design in Queensland, Australia USSD 2006 Conference Page 1  

E-Print Network [OSTI]

Gate Reliability Assessment for a Spillway Upgrade Design in Queensland, Australia USSD 2006 Conference Page 1 RELIABILITY ASSESSMENT FOR A SPILLWAY GATE UPGRADE DESIGN IN QUEENSLAND, AUSTRALIA Malcolm of reliability analysis, and how the results influenced the spillway system design and overall risk evaluation

Bowles, David S.

379

Ambipolar silicon nanowire FETs with stenciled-deposited metal gate Davide Sacchetto  

E-Print Network [OSTI]

Ambipolar silicon nanowire FETs with stenciled-deposited metal gate Davide Sacchetto , Veronica Keywords: Schottky barrier Ambipolarity Si nanowire Stencil lithography FET Silicide a b s t r a c t We chemical vapor deposition (LPCVD) of amorphous Si (a-Si) and SiO2 layers as well as metal gate patterning

De Micheli, Giovanni

380

Surface application of molybdenum silicide onto gated poly-Si emitters for enhanced field emission performance  

E-Print Network [OSTI]

the merits of molybdenum Mo silicide formation on gated polycrystalline silicon poly-Si field emitters. Metal, any metal silicide can be adopted without reSurface application of molybdenum silicide onto gated poly-Si emitters for enhanced field emission

Lee, Jong Duk

Note: This page contains sample records for the topic "transistor gate oxide" from the National Library of EnergyBeta (NLEBeta).
While these samples are representative of the content of NLEBeta,
they are not comprehensive nor are they the most current set.
We encourage you to perform a real-time search of NLEBeta
to obtain the most current and comprehensive results.


381

Probabilistic quantum gates between remote atoms through interference of optical frequency qubits  

E-Print Network [OSTI]

Probabilistic quantum gates between remote atoms through interference of optical frequency qubits L gates on remote trapped atom qubits through interference of optical frequency qubits. The method does be localized well under the Lamb-Dicke limit through laser cooling in a strong trap, the elimination

Madsen, Martin John

382

Directions to USC, Gate 6 (Parking Structure A) 110 (Harbor Freeway) North  

E-Print Network [OSTI]

on Vermont Avenue Turn right at 36th Place/Downey Way and enter USC at Gate 6 5 (Golden State/Santa AnaDirections to USC, Gate 6 (Parking Structure A) 110 (Harbor Freeway) North Take the Exposition Boulevard exit Go straight through the 37th Street light. Keep left Go under the freeway bridge and across

Valero-Cuevas, Francisco

383

Efficient polarization gating of high-order harmonic generation by polarization-shaped ultrashort pulses  

E-Print Network [OSTI]

Polarization gating of high-order harmonic generation takes advantage of the significant reduction of har for generation of polarization gated pulses using wave-plate combinations is inefficient, and propose photon energy radiation from the harmonic spectrum. Need- less to say, the generation of near single

Silberberg, Yaron

384

Electrochemical gating of individual single-wall carbon nanotubes observed by electron transport measurements and resonant  

E-Print Network [OSTI]

, the Fermi energy of a nanotube can be changed, as ions from the solution accu- mulate on the surface gating of nanotubes has been shown previously to effectively shift the Fermi energy of semiconducting with the laser energy, we can observe the Raman spectrum from a single SWNT.7 Electrochemical gating of nanotubes

385

Optimal Control of Airport Operations with Gate Capacity Constraints Harshad Khadilkar and Hamsa Balakrishnan  

E-Print Network [OSTI]

at Boston's Logan International Airport in the US are used to illustrate the advantages of the proposed for Boston Logan International Airport (BOS) is shown in Fig. 1. Gates at each of the four main terminalsOptimal Control of Airport Operations with Gate Capacity Constraints Harshad Khadilkar and Hamsa

Gummadi, Ramakrishna

386

Classification : Original Article VOLTAGE-GATED SODIUM CHANNELS POTENTIATE THE INVASIVE  

E-Print Network [OSTI]

- gated sodium channels in non-small-cell lung cancer cell lines. Functional voltage-gated sodium channels cancerous cell lines H23, H460 and Calu-1 possess functional sodium channels while normal and weakly metastatic cell lines do not. While all the cell lines expressed mRNA for numerous sodium channel isoforms

Boyer, Edmond

387

Microfluidic logic gates and timers{ Michael W. Toepke, Vinay V. Abhyankar and David J. Beebe*  

E-Print Network [OSTI]

Microfluidic logic gates and timers{ Michael W. Toepke, Vinay V. Abhyankar and David J. Beebe to create a number of microfluidic analogs to electronic circuit components. Three classes of components are demonstrated: (1) OR/AND, NOR/NAND, and XNOR digital microfluidic logic gates; (2) programmable, autonomous

Beebe, David J.

388

Design and characterization of a signal insulation coreless transformer integrated in a CMOS gate driver chip  

E-Print Network [OSTI]

Design and characterization of a signal insulation coreless transformer integrated in a CMOS gate transformer integrated in a CMOS silicon die together with the gate driver and other required functions frequency through the coreless transformer. The chosen design methodology will be explained and experimental

Paris-Sud XI, Université de

389

Oxidation of propylene over copper oxide catalysts  

E-Print Network [OSTI]

work on other phases of this project concerning cata- lytic oxidation of hydrocarbons has been described by Sanderson (59), Looney (34), Burns (11), Dunlop (17), Woodham (71), and Perkins (49). The early work of Sanderson indicated that chromia-alumina... and pro- moted chromia?alumina agents possessed the ability to catalyze the oxidation of propane by air. Subsequent work of Looney suggested that propylene was a primary product of this oxidation; hence most investigations since then have been confined...

Billingsley, David Stuart

1958-01-01T23:59:59.000Z

390

Performance analysis of boron nitride embedded armchair graphene nanoribbon metal–oxide–semiconductor field effect transistor with Stone Wales defects  

SciTech Connect (OSTI)

We study the performance of a hybrid Graphene-Boron Nitride armchair nanoribbon (a-GNR-BN) n-MOSFET at its ballistic transport limit. We consider three geometric configurations 3p, 3p + 1, and 3p + 2 of a-GNR-BN with BN atoms embedded on either side (2, 4, and 6 BN) on the GNR. Material properties like band gap, effective mass, and density of states of these H-passivated structures are evaluated using the Density Functional Theory. Using these material parameters, self-consistent Poisson-Schrodinger simulations are carried out under the Non Equilibrium Green's Function formalism to calculate the ballistic n-MOSFET device characteristics. For a hybrid nanoribbon of width ?5?nm, the simulated ON current is found to be in the range of 265??A–280??A with an ON/OFF ratio 7.1 × 10{sup 6}–7.4 × 10{sup 6} for a V{sub DD}?=?0.68?V corresponding to 10?nm technology node. We further study the impact of randomly distributed Stone Wales (SW) defects in these hybrid structures and only 2.5% degradation of ON current is observed for SW defect density of 3.18%.

Chanana, Anuja; Sengupta, Amretashis; Mahapatra, Santanu [Nano Scale Device Research Laboratory, Department of Electronic Systems Engineering, Indian Institute of Science, Bangalore 560 012 (India)

2014-01-21T23:59:59.000Z

391

Cerium Oxide Coating for Oxidation Reduction  

Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

Award In order to produce power more efficiently and cleanly, the next generation of power plant boilers, turbines, solid oxide fuel cells (SOFCs) and other essential...

392

Analytical approach to swift non-leaky entangling gates in superconducting qubits  

E-Print Network [OSTI]

We develop schemes for designing pulses that implement fast and precise entangling quantum gates in superconducting qubit systems despite the presence of nearby harmful transitions. Our approach is based on purposely involving the nearest harmful transition in the quantum evolution instead of trying to avoid it. Using analytical tools, we design simple microwave control fields that implement maximally entangling gates with fidelities exceeding 99% in times as low as 40 ns. We demonstrate our approach in a two-qubit circuit QED system by designing the two most important quantum entangling gates: a conditional-NOT gate and a conditional-Z gate. Our results constitute an important step toward overcoming the problem of spectral crowding, one of the primary challenges in controlling multi-qubit systems.

Sophia E. Economou; Edwin Barnes

2014-11-03T23:59:59.000Z

393

A proposal for the realization of universal quantum gates via superconducting qubits inside a cavity  

SciTech Connect (OSTI)

A family of quantum logic gates is proposed via superconducting (SC) qubits coupled to a SC-cavity. The Hamiltonian for SC-charge qubits inside a single mode cavity is considered. Three- and two-qubit operations are generated by applying a classical magnetic field with the flux. Therefore, a number of quantum logic gates are realized. Numerical simulations and calculation of the fidelity are used to prove the success of these operations for these gates. -- Highlights: •A family of quantum logic gates is proposed via SC-qubits coupled to a cavity. •Three- and two-qubit operations are generated via a classical field with the flux. •Numerical simulations and calculation of the fidelity are used to prove the success of these operations for these gates.

Obada, A.-S.F. [Faculty of Science, Al-Azhar University, Nasr City, Cairo (Egypt)] [Faculty of Science, Al-Azhar University, Nasr City, Cairo (Egypt); Hessian, H.A. [Faculty of Science, Assiut University, Assiut (Egypt)] [Faculty of Science, Assiut University, Assiut (Egypt); Mohamed, A.-B.A. [Faculty of Science, Assiut University, Assiut (Egypt) [Faculty of Science, Assiut University, Assiut (Egypt); Community College, Salman Bin Abdulaziz University, Al-Aflaj (Saudi Arabia); Homid, Ali H., E-mail: alihimad@yahoo.com [Faculty of Science, Al-Azhar University, Assiut (Egypt)

2013-07-15T23:59:59.000Z

394

Experimental Estimation of Average Fidelity of a Clifford Gate on a 7-qubit Quantum Processor  

E-Print Network [OSTI]

Quantum gates in experiment are inherently prone to errors that need to be characterized before they can be corrected. Full characterization via quantum process tomography is impractical and often unnecessary. For most practical purposes, it is enough to estimate more general quantities such as the average fidelity. Here we use a unitary 2-design and twirling protocol for efficiently estimating the average fidelity of Clifford gates, to certify a 7-qubit entangling gate in a nuclear magnetic resonance quantum processor. Compared with more than $10^8$ experiments required by full process tomography, we conducted 1656 experiments to satisfy a statistical confidence level of 99%. The average fidelity of this Clifford gate in experiment is 55.1%, and rises to 87.5% if the infidelity due to decoherence is removed. The entire protocol of certifying Clifford gates is efficient and scalable, and can easily be extended to any general quantum information processor with minor modifications.

Dawei Lu; Hang Li; Denis-Alexandre Trottier; Jun Li; Aharon Brodutch; Anthony P. Krismanich; Ahmad Ghavami; Gary I. Dmitrienko; Guilu Long; Jonathan Baugh; Raymond Laflamme

2014-11-28T23:59:59.000Z

395

Single carbon nanotube transistor at GHz frequency J. Chaste,1, 2  

E-Print Network [OSTI]

- pacitance per unit gate length lg, Cgeo/lg > CQ/lg = Electronic address: Bernard.Placais@lpa.ens.fr G D S Cgs0 Cds0 Cgd0 Cgd Rgd Cgs Rgs g .Vm gs Rgd A) B) D S S G G FIG. 1: Panel A : scanning electron

Boyer, Edmond

396

Silicon single-electron quantum-dot transistor switch operating at room temperature  

E-Print Network [OSTI]

, which showed drain current oscillations at room temperature. These oscillations are attributed current­voltage characteristic indicates that the energy level separation is about 110 meV and the silicon current (Id) as a function of the gate voltage (Vg) (I­V) was measured at different temperatures

397

A CAD tool for the power estimation of CMOS, BiCMOS and BiNMOS gates  

E-Print Network [OSTI]

This thesis describes a CAD tool for the power estimation of CMOS, BiCMOS and BiNMOS gates. Using analytical models for the transient behavior of the gates, accurate estimates of the power dissipated by each type of gate during a typical transition...

Islam, Kazi Inamul

1995-01-01T23:59:59.000Z

398

REVUE DE PHYSIQUE APPLIQUE Simulation d'un transistor MOS silicium-sur-isolant dsertion profonde  

E-Print Network [OSTI]

tensions de grilles avant (Vg1) et arrière (Vg2) appliquées. Nous dédui- sons aussi les caractéristiques Id(Vg1, Vg2) à faible tension de drain. Les caractéristiques Id(Vg2) simulées sont comparées aux caractéristiques Id(Vg2) obtenues avec des transistors CMOS/SOS. Le saphir de ces dispositifs a été localement

Boyer, Edmond

399

Total dose and dose rate models for bipolar transistors in circuit simulation.  

SciTech Connect (OSTI)

The objective of this work is to develop a model for total dose effects in bipolar junction transistors for use in circuit simulation. The components of the model are an electrical model of device performance that includes the effects of trapped charge on device behavior, and a model that calculates the trapped charge densities in a specific device structure as a function of radiation dose and dose rate. Simulations based on this model are found to agree well with measurements on a number of devices for which data are available.

Campbell, Phillip Montgomery; Wix, Steven D.

2013-05-01T23:59:59.000Z

400

A Graphene Quantum Dot with a Single Electron Transistor as Integrated Charge Sensor  

E-Print Network [OSTI]

We have developed an etching process to fabricate a quantum dot and a nearby single electron transistor as a charge detector in a single layer graphene. The high charge sensitivity of the detector is used to probe Coulomb diamonds as well as excited spectrum in the dot, even in the regime where the current through the quantum dot is too small to be measured by conventional transport means. The graphene based quantum dot and integrated charge sensor serve as an essential building block to form a solid-state qubit in a nuclear-spin-free quantum world.

Ling-Jun Wang; Gang Cao; Tao Tu; Hai-Ou Li; Cheng Zhou; Xiao-Jie Hao; Zhan Su; Guang-Can Guo; Guo-Ping Guo; Hong-Wen Jiang

2010-08-28T23:59:59.000Z

Note: This page contains sample records for the topic "transistor gate oxide" from the National Library of EnergyBeta (NLEBeta).
While these samples are representative of the content of NLEBeta,
they are not comprehensive nor are they the most current set.
We encourage you to perform a real-time search of NLEBeta
to obtain the most current and comprehensive results.


401

Logic and transistor circuit verification using regression testing and hierarchical recursive learning  

E-Print Network [OSTI]

2670 c3540, opt c3540 c5315, opt c5315 c6288, opt c6288 c7552, opt c7552 RLI 10 73 48 148 30 20 144 Re@. Test 14 26 RL ATPG 14 385 12 22 0 190 6 154 2 572 17 2787 0 other Total 16 28 473 87 376 12 14 168 646 2819 205... Algorithm of Verifast C. Learning at Level One D. Potential Equivalent Node Identification E. Potential Equivalent Node Checking F. Final Verification 10 12 14 15 17 20 22 IV LOGIC TO TRANSISTOR CIRCUIT VERIFICATION vu CHAPTER Page A. Review...

Shao, Li

1996-01-01T23:59:59.000Z

402

Impact of graphene polycrystallinity on the performance of graphene field-effect transistors  

SciTech Connect (OSTI)

We have used a multi-scale physics-based model to predict how the grain size and different grain boundary morphologies of polycrystalline graphene will impact the performance metrics of graphene field-effect transistors. We show that polycrystallinity has a negative impact on the transconductance, which translates to a severe degradation of the maximum and cutoff frequencies. On the other hand, polycrystallinity has a positive impact on current saturation, and a negligible effect on the intrinsic gain. These results reveal the complex role played by graphene grain boundaries and can be used to guide the further development and optimization of graphene-based electronic devices.

Jiménez, David; Chaves, Ferney [Departament d'Enginyeria Electrònica, Escola d'Enginyeria, Universitat Autònoma de Barcelona, 08193-Bellaterra (Spain); Cummings, Aron W.; Van Tuan, Dinh [ICN2, Institut Català de Nanociencia i Nanotecnologia, Campus UAB, 08193 Bellaterra (Barcelona) (Spain); Kotakoski, Jani [Faculty of Physics, University of Vienna, Boltzmanngasse 5, 1090 Wien (Austria); Department of Physics, University of Helsinki, P.O. Box 43, 00014 University of Helsinki (Finland); Roche, Stephan [ICN2, Institut Català de Nanociencia i Nanotecnologia, Campus UAB, 08193 Bellaterra (Barcelona) (Spain); ICREA, Institució Catalana de Recerca i Estudis Avançats, 08070 Barcelona (Spain)

2014-01-27T23:59:59.000Z

403

Simultaneous Modification of Bottom-Contact Electrode and Dielectric Surfaces for Organic Thin-Film Transistors Through Single-Component Spin-Cast Monolayers  

SciTech Connect (OSTI)

An efficient process is developed by spin-coating a single-component, self-assembled monolayer (SAM) to simultaneously modify the bottom-contact electrode and dielectric surfaces of organic thin-film transistors (OTFTs). This efficient interface modification is achieved using n-alkyl phosphonic acid based SAMs to prime silver bottom-contacts and hafnium oxide (HfO{sub 2}) dielectrics in low-voltage OTFTs. Surface characterization using near edge X-ray absorption fine structure (NEXAFS) spectroscopy, X-ray photoelectron spectroscopy (XPS), attenuated total reflectance Fourier transform infrared (ATR-FTIR) spectroscopy, atomic force microscopy (AFM), and spectroscopic ellipsometry suggest this process yields structurally well-defined phosphonate SAMs on both metal and oxide surfaces. Rational selection of the alkyl length of the SAM leads to greatly enhanced performance for both n-channel (C60) and p-channel (pentacene) based OTFTs. Specifically, SAMs of n-octylphos-phonic acid (OPA) provide both low-contact resistance at the bottom-contact electrodes and excellent interfacial properties for compact semiconductor grain growth with high carrier mobilities. OTFTs based on OPA modifi ed silver electrode/HfO{sub 2} dielectric bottom-contact structures can be operated using < 3V with low contact resistance (down to 700 Ohm-cm), low subthreshold swing (as low as 75 mV dec{sup -1}), high on/off current ratios of 107, and charge carrier mobilities as high as 4.6 and 0.8 cm{sup 2} V{sup -1} s{sup -1}, for C60 and pentacene, respectively. These results demonstrate that this is a simple and efficient process for improving the performance of bottom-contact OTFTs.

O Acton; M Dubey; t Weidner; K OMalley; T Kim; G Ting; D Hutchins; J Baio; T Lovejoy; et al.

2011-12-31T23:59:59.000Z

404

After-gate attack on a quantum cryptosystem  

E-Print Network [OSTI]

We present a method to control the detection events in quantum key distribution systems that use gated single-photon detectors. We employ bright pulses as faked states, timed to arrive at the avalanche photodiodes outside the activation time. The attack can remain unnoticed, since the faked states do not increase the error rate per se. This allows for an intercept-resend attack, where an eavesdropper transfers her detection events to the legitimate receiver without causing any errors. As a side effect, afterpulses, originating from accumulated charge carriers in the detectors, increase the error rate. We have experimentally tested detectors of the system id3110 (Clavis2) from ID Quantique. We identify the parameter regime in which the attack is feasible despite the side effect. Furthermore, we outline how simple modifications in the implementation can make the device immune to this attack.

Carlos Wiechers; Lars Lydersen; Christoffer Wittmann; Dominique Elser; Johannes Skaar; Christoph Marquardt; Vadim Makarov; Gerd Leuchs

2010-09-14T23:59:59.000Z

405

Gas-controlled dynamic vacuum insulation with gas gate  

DOE Patents [OSTI]

Disclosed is a dynamic vacuum insulation comprising sidewalls enclosing an evacuated chamber and gas control means for releasing hydrogen gas into a chamber to increase gas molecule conduction of heat across the chamber and retrieving hydrogen gas from the chamber. The gas control means includes a metal hydride that absorbs and retains hydrogen gas at cooler temperatures and releases hydrogen gas at hotter temperatures; a hydride heating means for selectively heating the metal hydride to temperatures high enough to release hydrogen gas from the metal hydride; and gate means positioned between the metal hydride and the chamber for selectively allowing hydrogen to flow or not to flow between said metal hydride and said chamber. 25 figs.

Benson, D.K.; Potter, T.F.

1994-06-07T23:59:59.000Z

406

Gas-controlled dynamic vacuum insulation with gas gate  

DOE Patents [OSTI]

Disclosed is a dynamic vacuum insulation comprising sidewalls enclosing an evacuated chamber and gas control means for releasing hydrogen gas into a chamber to increase gas molecule conduction of heat across the chamber and retrieving hydrogen gas from the chamber. The gas control means includes a metal hydride that absorbs and retains hydrogen gas at cooler temperatures and releases hydrogen gas at hotter temperatures; a hydride heating means for selectively heating the metal hydride to temperatures high enough to release hydrogen gas from the metal hydride; and gate means positioned between the metal hydride and the chamber for selectively allowing hydrogen to flow or not to flow between said metal hydride and said chamber.

Benson, David K. (Golden, CO); Potter, Thomas F. (Denver, CO)

1994-06-07T23:59:59.000Z

407

Low Power, Red, Green and Blue Carbon Nanotube Enabled Vertical Organic Light Emitting Transistors for Active Matrix OLED Displays  

SciTech Connect (OSTI)

Organic semiconductors are potential alternatives to polycrystalline silicon as the semiconductor used in the backplane of active matrix organic light emitting diode displays. Demonstrated here is a light-emitting transistor with an organic channel, operating with low power dissipation at low voltage, and high aperture ratio, in three colors: red, green and blue. The single-wall carbon nanotube network source electrode is responsible for the high level of performance demonstrated. A major benefit enabled by this architecture is the integration of the drive transistor, storage capacitor and light emitter into a single device. Performance comparable to commercialized polycrystalline-silicon TFT driven OLEDs is demonstrated.

McCarthy, M. A. [University of Florida, Gainesville; Liu, B. [University of Florida, Gainesville; Donoghue, E. P. [University of Florida, Gainesville; Kravchenko, Ivan I [ORNL; Kim, D. Y. [University of Florida, Gainesville; So, Franky [University of Florida, Gainesville; Rinzler, A. G. [University of Florida, Gainesville

2011-01-01T23:59:59.000Z

408

Demonstration of a fully tuneable entangling gate for continuous-variable one-way quantum computation  

E-Print Network [OSTI]

We introduce a fully tuneable entangling gate for continuous-variable one-way quantum computation. We present a proof-of-principle demonstration by propagating two independent optical inputs through a three-mode linear cluster state and applying the gate in various regimes. The genuine quantum nature of the gate is confirmed by verifying the entanglement strength in the output state. Our protocol can be readily incorporated into efficient multi-mode interaction operations in the context of large-scale one-way quantum computation, as our tuning process is the generalisation of cluster state shaping.

Shota Yokoyama; Ryuji Ukai; Seiji C. Armstrong; Jun-ichi Yoshikawa; Peter van Loock; Akira Furusawa

2014-10-02T23:59:59.000Z

409

Stripline microchannel plate image intensifier tubes (MCPTS) for nanosecond optical gating applications  

SciTech Connect (OSTI)

Shuttering characteristics of low impedance stripline geometry microchannel plate image intensifier tubes (MCPTs) with 50% transmissive nickel undercoated S-20 photocathodes are discussed. Iris-free shutter sequences with 50 to 75 micron resolution at optical gate times of 500ps to 2ns were measured for typical samples from two manufacturers. Shutter sequences clearly showing gate pulse propagation velocities for this MCPT design when externally driven by impedance matched circuitry are contrasted with non-directional sequences obtained from unmatched coupling of the gate pulse. 7 refs., 7 figs.

Yates, G.J.; Jaramillo, S.A.; Zagarino, P.; Thomas, M.

1986-01-01T23:59:59.000Z

410

Gates controlled parallel-coupled double quantum dot on both single layer and bilayer graphene  

E-Print Network [OSTI]

Here we report the fabrication and quantum transport measurements of gates controlled parallel-coupled double quantum dot on both bilayer and single layer graphene. It is shown that the interdot coupling strength of the parallel double dots can be effectively tuned from weak to strong regime by both the in-plane plunger gates and back gate. All the relevant energy scales and parameters of the graphene parallel-coupled double dot can be extracted from the honeycomb charge stability diagrams revealed through the transport measurements.

Lin-Jun Wang; Guo-Ping Guo; Da Wei; Gang Cao; Tao Tu; Ming Xiao; Guang-Can Guo; A. M. Chang

2011-04-22T23:59:59.000Z

411

Repeat-until-success cubic phase gate for universal continuous-variable quantum computation  

E-Print Network [OSTI]

In order to achieve universal quantum computation using continuous variables, one needs to jump out of the set of Gaussian operations and have a non-Gaussian element, such as the cubic phase gate. However, such a gate is currently very difficult to implement in practice. Here we introduce an experimentally viable 'repeat-until-success' approach to generating the cubic phase gate, which is achieved using sequential photon subtractions and Gaussian operations. We find that our scheme offers benefits in terms of the expected time until success, although we require a primitive quantum memory.

Kevin Marshall; Raphael Pooser; George Siopsis; Christian Weedbrook

2014-12-01T23:59:59.000Z

412

High-performance MoS{sub 2} transistors with low-resistance molybdenum contacts  

SciTech Connect (OSTI)

In this Letter, molybdenum (Mo) is introduced and evaluated as an alternative contact metal to atomically-thin molybdenum disulphide (MoS{sub 2}), and high-performance field-effect transistors are experimentally demonstrated. In order to understand the physical nature of the interface and highlight the role of the various factors contributing to the Mo-MoS{sub 2} contacts, density functional theory (DFT) simulations are employed, which reveal that Mo can form high quality contact interface with monolayer MoS{sub 2} with zero tunnel barrier and zero Schottky barrier under source/drain contact, as well as an ultra-low Schottky barrier (0.1?eV) at source/drain-channel junction due to strong Fermi level pinning. In agreement with the DFT simulations, high mobility, high ON-current, and low contact resistance are experimentally demonstrated on both monolayer and multilayer MoS{sub 2} transistors using Mo contacts. The results obtained not only reveal the advantages of using Mo as a contact metal for MoS{sub 2} but also highlight the fact that the properties of contacts with 2-dimensional materials cannot be intuitively predicted by solely considering work function values and Schottky theory.

Kang, Jiahao; Liu, Wei; Banerjee, Kaustav, E-mail: kaustav@ece.ucsb.edu [Department of Electrical and Computer Engineering, University of California, Santa Barbara, California 93106 (United States)

2014-03-03T23:59:59.000Z

413

Simulation of neutron displacement damage in bipolar junction transistors using high-energy heavy ion beams.  

SciTech Connect (OSTI)

Electronic components such as bipolar junction transistors (BJTs) are damaged when they are exposed to radiation and, as a result, their performance can significantly degrade. In certain environments the radiation consists of short, high flux pulses of neutrons. Electronics components have traditionally been tested against short neutron pulses in pulsed nuclear reactors. These reactors are becoming less and less available; many of them were shut down permanently in the past few years. Therefore, new methods using radiation sources other than pulsed nuclear reactors needed to be developed. Neutrons affect semiconductors such as Si by causing atomic displacements of Si atoms. The recoiled Si atom creates a collision cascade which leads to displacements in Si. Since heavy ions create similar cascades in Si we can use them to create similar damage to what neutrons create. This LDRD successfully developed a new technique using easily available particle accelerators to provide an alternative to pulsed nuclear reactors to study the displacement damage and subsequent transient annealing that occurs in various transistor devices and potentially qualify them against radiation effects caused by pulsed neutrons.

Doyle, Barney Lee; Buller, Daniel L.; Hjalmarson, Harold Paul; Fleming, Robert M; Bielejec, Edward Salvador; Vizkelethy, Gyorgy

2006-12-01T23:59:59.000Z

414

THE MICROSTRUCTURAL LOCATION OF THE INTERGRANULAR METAL OXIDE PHASE IN A ZINC OXIDE VARISTOR  

E-Print Network [OSTI]

OXIDE PHASE IN A ZINC OXIDE VARISTOR MICROSI'RUCTIJRALMETAL OXIDE PHASE IN A ZINC OXIDE VARISTOR David R. Clarke

Clarke, D. E

2011-01-01T23:59:59.000Z

415

SRP4760R List of Lots By Purchaser As at :-13-feb-2013:08:07 CENTRAL ENGLAND (Wharncliffe Plank Gate)  

E-Print Network [OSTI]

ENGLAND (Wharncliffe Plank Gate) CENTRAL ENGLAND (Coach Road) NORTH ENGLAND (Guns Crag (Redesdale)) NORTH

416

Benchmarking the performance of ultrathin body InAs-on-insulator transistors as a function of body thickness  

E-Print Network [OSTI]

-effect transistors (FETs) to enable low-power and high- speed electronics.1­6 In this regard, the use of ultrathin InAs XOI n-FETs have been experimentally reported with the effective electron mobility of ln ¼ 1000, especially when scaled to short channel lengths, LG. Here, we report on the detailed device characterization

Krishna, Sanjay

417

Abstract --Design guidelines are provided to improve the thermal stability of three-finger bipolar transistors. Experiments  

E-Print Network [OSTI]

in selfheating and mutual thermal resistances, which are extracted through accurate 3-D numerical simulations. To avoid strong asymmetries between the mutual thermal resistances of two adjacent fingers compared to two of the thermal resistance of the transistors; as a consequence, selfheating and thermal coupling among

Technische Universiteit Delft

418

Comparison of the Catalytic Oxidation Reaction on Graphene Oxide and Reduced Graphene Oxide  

E-Print Network [OSTI]

Comparison of the Catalytic Oxidation Reaction on Graphene Oxide and Reduced Graphene Oxide Laboratory (PAL), Pohang 790-784, Republic of Korea ABSTRACT: The capacities of graphene oxide (GO) and reduced graphene oxide (rGO) films grown on silicon substrate to cause the aniline to azobenzene oxidation

Kim, Sehun

419

A linear programming solution to the gate assignment problem at airport terminals  

E-Print Network [OSTI]

This research solves the flight-to-gate assignment problem at airports in such a way as to minimize, or at least reduce, walking distances for passengers inside terminals. Two solution methods are suggested. The first is ...

Mangoubi, Rami

1980-01-01T23:59:59.000Z

420

E-Print Network 3.0 - arbitrary phase gates Sample Search Results  

Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

<< < 1 2 3 4 5 > >> Page: << < 1 2 3 4 5 > >> 41 Optical simulation of quantum logic N. J. Cerf,1 Summary: of universal quantum gates using simple optical components beam...

Note: This page contains sample records for the topic "transistor gate oxide" from the National Library of EnergyBeta (NLEBeta).
While these samples are representative of the content of NLEBeta,
they are not comprehensive nor are they the most current set.
We encourage you to perform a real-time search of NLEBeta
to obtain the most current and comprehensive results.


421

The civic forum in ancient Israel : the form, function, and symbolism of city gates  

E-Print Network [OSTI]

of City Gates by Daniel Allan Frese Doctor of Philosophy inC. Michael Hall, and Allan M. Williams. Oxford: Blackwell,in History by Daniel Allan Frese Committee in Charge:

Frese, Daniel Allan

2012-01-01T23:59:59.000Z

422

E-Print Network 3.0 - affects voltage-gated calcium Sample Search...  

Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

, 1115-1118 3 Dolphin, A.C. (2003) b subunits of voltage-gated calcium channels. J. Bioenerg. Biomembr... . 35, 599-620 4 Van Petegem, F. et al. (2004) Structure of a complex...

423

Thermosensitive gating effect and selective gas adsorption in a porous coordination nanocage  

SciTech Connect (OSTI)

A porous coordination nanocage functionalized with 24 triisopropylsilyl groups exhibits a remarkable thermosensitive gate opening phenomenon and demonstrates a molecular sieving effect at a certain temperature range, which can be used for gas separation purposes.

Zhao, Dan; Yuan, Daqiang; Krishna, Rajamani; van Baten, Jasper M.; Zhou, Hong-Cai (TAM); (U. Amsterdam)

2010-10-22T23:59:59.000Z

424

Thermosensitive gating effect and selective gas adsorption in a porous coordination nanocage  

SciTech Connect (OSTI)

A porous coordination nanocage functionalized with 24 triisopropylsilyl groups exhibits a remarkable thermosensitive gate opening phenomenon and demonstrates a molecular sieving effect at a certain temperature range, which can be used for gas separation purposes.

Zhao, Dan; Yuan, Daqiang; Krishna, Rajamani; van Baten, Jasper M; Zhou, Hong-Cai

2010-01-01T23:59:59.000Z

425

Process fidelity estimation of linear optical quantum CZ gate: A comparative study  

E-Print Network [OSTI]

We present a systematic comparison of different methods of fidelity estimation of a linear optical quantum controlled-Z gate implemented by two-photon interference on a partially polarizing beam splitter. We have utilized a linear fidelity estimator based on the Monte Carlo sampling technique as well as a non-linear estimator based on maximum likelihood reconstruction of a full quantum process matrix. In addition, we have also evaluated lower bound on quantum gate fidelity determined by average quantum state fidelities for two mutually unbiased bases. In order to probe various regimes of operation of the gate we have introduced a tunable delay line between the two photons. This allowed us to move from high-fidelity operation to a regime where the photons become distinguishable and the success probability of the scheme significantly depends on input state. We discuss in detail possible systematic effects that could influence the gate fidelity estimation.

M. Micuda; M. Sedlak; I. Straka; M. Mikova; M. Dusek; M. Jezek; J. Fiurasek

2014-03-19T23:59:59.000Z

426

Ligand-Gated Chloride Channels Are Receptors for Biogenic Amines in C. elegans  

E-Print Network [OSTI]

Biogenic amines such as serotonin and dopamine are intercellular signaling molecules that function widely as neurotransmitters and neuromodulators. We have identified in the nematode Caenorhabditis elegans three ligand-gated ...

Ringstad, Niels

427

Transient Turbulent Flow Simulation with Water Model Validation and Application to Slide Gate Dithering  

E-Print Network [OSTI]

) 244-6534 Email: bgthomas@illinois.edu Bruce Forman and Hongbin Yin ArcelorMittal Global R&D East) 399-3899 Email: bruce.forman@arcelormittal.com, Hongbin.Yin@arcelormittal.com ABSTRACT Slide gate

Thomas, Brian G.

428

Vehicle Technologies Office Merit Review 2014: GATE: Energy Efficient Vehicles for Sustainable Mobility  

Broader source: Energy.gov [DOE]

Presentation given by Ohio State University at 2014 DOE Hydrogen and Fuel Cells Program and Vehicle Technologies Office Annual Merit Review and Peer Evaluation Meeting about GATE: energy efficient...

429

Vehicle Technologies Office Merit Review 2014: DOE GATE Center of Excellence in Sustainable Vehicle Systems  

Broader source: Energy.gov [DOE]

Presentation given by Clemson University at 2014 DOE Hydrogen and Fuel Cells Program and Vehicle Technologies Office Annual Merit Review and Peer Evaluation Meeting about DOE GATE Center of...

430

Infrared Imaging of the Nanometer-Thick Accumulation Layer in Organic Field-Effect Transistors  

E-Print Network [OSTI]

We report on infrared (IR) spectro-microscopy of the electronic excitations in nanometer-thick accumulation layers in FET devices based on poly(3-hexylthiophene). IR data allows us to explore the charge injection landscape and uncovers the critical role of the gate insulator in defining relevant length scales. This work demonstrates the unique potential of IR spectroscopy for the investigation of physical phenomena at the nanoscale occurring at the semiconductor-insulator interface in FET devices.

Z. Q. Li; G. M. Wang; N. Sai; D. Moses; M. C. Martin; M. Di Ventra; A. J. Heeger; D. N. Basov

2006-02-09T23:59:59.000Z

431

Oxidation Resistant Graphite Studies  

SciTech Connect (OSTI)

The Very High Temperature Reactor (VHTR) Graphite Research and Development Program is investigating doped nuclear graphite grades exhibiting oxidation resistance. During a oxygen ingress accident the oxidation rates of the high temperature graphite core region would be extremely high resulting in significant structural damage to the core. Reducing the oxidation rate of the graphite core material would reduce the structural effects and keep the core integrity intact during any air-ingress accident. Oxidation testing of graphite doped with oxidation resistant material is being conducted to determine the extent of oxidation rate reduction. Nuclear grade graphite doped with varying levels of Boron-Carbide (B4C) was oxidized in air at nominal 740°C at 10/90% (air/He) and 100% air. The oxidation rates of the boronated and unboronated graphite grade were compared. With increasing boron-carbide content (up to 6 vol%) the oxidation rate was observed to have a 20 fold reduction from unboronated graphite. Visual inspection and uniformity of oxidation across the surface of the specimens were conducted. Future work to determine the remaining mechanical strength as well as graphite grades with SiC doped material are discussed.

W. Windes; R. Smith

2014-07-01T23:59:59.000Z

432

AN AUTOZEROING FLOATING-GATE BANDPASS FILTER Paul Hasler, Bradley A. Minch, and Chris Diorio  

E-Print Network [OSTI]

is the thermal Figure 1: An autozeroing oating-gate ampli er AFGA that uses pFET hot-electron injection a bandpass oating-gate ampli er that uses tunneling and pFET hot-electron injection to set its DC operating the current through the pFET. Steady state occurs when the injection current is equal to the tunneling current

Diorio, Chris

433

A review of "Gate of Heaven." by Abraham Cohen de Herrera  

E-Print Network [OSTI]

, and always with a complex sensation compounded of affinity with, and unbridgeable distance from, the man whose pen marked the pages so idiosyncratically. Abraham Cohen de Herrera. Gate of Heaven. Translated from the Spanish with Introduction and Notes... ready access to Herrera?s Gate of Heaven. Not only is this the first English translation of Puerta del Cielo, but it is also the first complete annotated edition of 198 SEVENTEENTH-CENTURY NEWS this important work of Jewish mysticism in any language...

William E. Engel

2003-01-01T23:59:59.000Z

434

Logic gates at the surface code threshold: Superconducting qubits poised for fault-tolerant quantum computing  

E-Print Network [OSTI]

A quantum computer can solve hard problems - such as prime factoring, database searching, and quantum simulation - at the cost of needing to protect fragile quantum states from error. Quantum error correction provides this protection, by distributing a logical state among many physical qubits via quantum entanglement. Superconductivity is an appealing platform, as it allows for constructing large quantum circuits, and is compatible with microfabrication. For superconducting qubits the surface code is a natural choice for error correction, as it uses only nearest-neighbour coupling and rapidly-cycled entangling gates. The gate fidelity requirements are modest: The per-step fidelity threshold is only about 99%. Here, we demonstrate a universal set of logic gates in a superconducting multi-qubit processor, achieving an average single-qubit gate fidelity of 99.92% and a two-qubit gate fidelity up to 99.4%. This places Josephson quantum computing at the fault-tolerant threshold for surface code error correction. Our quantum processor is a first step towards the surface code, using five qubits arranged in a linear array with nearest-neighbour coupling. As a further demonstration, we construct a five-qubit Greenberger-Horne-Zeilinger (GHZ) state using the complete circuit and full set of gates. The results demonstrate that Josephson quantum computing is a high-fidelity technology, with a clear path to scaling up to large-scale, fault-tolerant quantum circuits.

R. Barends; J. Kelly; A. Megrant; A. Veitia; D. Sank; E. Jeffrey; T. C. White; J. Mutus; A. G. Fowler; B. Campbell; Y. Chen; Z. Chen; B. Chiaro; A. Dunsworth; C. Neill; P. O`Malley; P. Roushan; A. Vainsencher; J. Wenner; A. N. Korotkov; A. N. Cleland; John M. Martinis

2014-02-19T23:59:59.000Z

435

GATE Center of Excellence at UAB in Lightweight Materials for Automotive Applications  

SciTech Connect (OSTI)

This report summarizes the accomplishments of the UAB GATE Center of Excellence in Lightweight Materials for Automotive Applications. The first Phase of the UAB DOE GATE center spanned the period 2005-2011. The UAB GATE goals coordinated with the overall goals of DOE's FreedomCAR and Vehicles Technologies initiative and DOE GATE program. The FCVT goals are: (1) Development and validation of advanced materials and manufacturing technologies to significantly reduce automotive vehicle body and chassis weight without compromising other attributes such as safety, performance, recyclability, and cost; (2) To provide a new generation of engineers and scientists with knowledge and skills in advanced automotive technologies. The UAB GATE focused on both the FCVT and GATE goals in the following manner: (1) Train and produce graduates in lightweight automotive materials technologies; (2) Structure the engineering curricula to produce specialists in the automotive area; (3) Leverage automotive related industry in the State of Alabama; (4) Expose minority students to advanced technologies early in their career; (5) Develop innovative virtual classroom capabilities tied to real manufacturing operations; and (6) Integrate synergistic, multi-departmental activities to produce new product and manufacturing technologies for more damage tolerant, cost-effective, and lighter automotive structures.

None

2011-07-31T23:59:59.000Z

436

Magic State Distillation and Gate Compilation in Quantum Algorithms for Quantum Chemistry  

E-Print Network [OSTI]

Quantum algorithms for quantum chemistry map the dynamics of electrons in a molecule to the dynamics of a coupled spin system. To reach chemical accuracy for interesting molecules, a large number of quantum gates must be applied which implies the need for quantum error correction and fault-tolerant quantum computation. Arbitrary fault-tolerant operations can be constructed from a small, universal set of fault-tolerant operations by gate compilation. Quantum chemistry algorithms are compiled by decomposing the dynamics of the coupled spin-system using a Trotter formula, synthesizing the decomposed dynamics using Clifford operations and single-qubit rotations, and finally approximating the single-qubit rotations by a sequence of fault-tolerant single-qubit gates. Certain fault-tolerant gates rely on the preparation of specific single-qubit states referred to as magic states. As a result, gate compilation and magic state distillation are critical for solving quantum chemistry problems on a quantum computer. We review recent progress that has improved the efficiency of gate compilation and magic state distillation by orders of magnitude.

Colin J. Trout; Kenneth R. Brown

2015-01-29T23:59:59.000Z

437

Correlation of gross tumor volume excursion with potential benefits of respiratory gating  

SciTech Connect (OSTI)

Purpose: To test the hypothesis that the magnitude of thoracic tumor motion can be used to determine the desirability of respiratory gating. Methods and materials: Twenty patients to be treated for lung tumors had computed tomography image data sets acquired under assisted breath hold at normal inspiration (100% tidal volume), at full expiration (0% tidal volume), and under free breathing. A radiation oncologist outlined gross tumor volumes (GTVs) on the breath-hold computed tomographic images. These data sets were registered to the free-breathing image data set. Two sets of treatment plans were generated: one based on an internal target volume explicitly formed from assessment of the excursion of the clinical target volume (CTV) through the respiratory cycle, representing an ungated treatment, and the other based on the 0% tidal volume CTV, representing a gated treatment with little margin for residual motion. Dose-volume statistics were correlated to the magnitude of the motion of the center of the GTV during respiration. Results: Patients whose GTVs were >100 cm{sup 3} showed little decrease in lung dose under gating. The other patients showed a correlation between the excursion of the center of the GTV and a reduction in potential lung toxicity. As residual motion increased, the benefits of respiratory gating increased. Conclusion: Gating seems to be advantageous for patients whose GTVs are <100 cm{sup 3} and for whom the center of the GTV exhibits significant motion, provided residual motion under gating is kept small.

Starkschall, George [Department of Radiation Physics, University of Texas M.D. Anderson Cancer Center, Houston, TX (United States)]. E-mail: gstarksc@mdanderson.org; Forster, Kenneth M. [Department of Radiation Physics, University of Texas M.D. Anderson Cancer Center, Houston, TX (United States); Kitamura, Kei [Department of Radiation Physics, University of Texas M.D. Anderson Cancer Center, Houston, TX (United States); Department of Radiology, Hokkaido University, Graduate School of Medicine, Sapporo (Japan); Cardenas, Alex [Department of Radiation Physics, University of Texas M.D. Anderson Cancer Center, Houston, TX (United States); Tucker, Susan L. [Department of Biomathematics, University of Texas M.D. Anderson Cancer Center, Houston, TX (United States); Stevens, Craig W. [Department of Radiation Oncology, University of Texas M.D. Anderson Cancer Center, Houston, TX (United States)

2004-11-15T23:59:59.000Z

438

Magic State Distillation and Gate Compilation in Quantum Algorithms for Quantum Chemistry  

E-Print Network [OSTI]

Quantum algorithms for quantum chemistry map the dynamics of electrons in a molecule to the dynamics of a coupled spin system. To reach chemical accuracy for interesting molecules, a large number of quantum gates must be applied which implies the need for quantum error correction and fault-tolerant quantum computation. Arbitrary fault-tolerant operations can be constructed from a small, universal set of fault-tolerant operations by gate compilation. Quantum chemistry algorithms are compiled by decomposing the dynamics of the coupled spin-system using a Trotter formula, synthesizing the decomposed dynamics using Clifford operations and single-qubit rotations, and finally approximating the single-qubit rotations by a sequence of fault-tolerant single-qubit gates. Certain fault-tolerant gates rely on the preparation of specific single-qubit states referred to as magic states. As a result, gate compilation and magic state distillation are critical for solving quantum chemistry problems on a quantum computer. We review recent progress that has improved the efficiency of gate compilation and magic state distillation by orders of magnitude.

Colin J. Trout; Kenneth R. Brown

2015-01-07T23:59:59.000Z

439

New VLSI complexity results for threshold gate comparison  

SciTech Connect (OSTI)

The paper overviews recent developments concerning optimal (from the point of view of size and depth) implementations of COMPARISON using threshold gates. We detail a class of solutions which also covers another particular solution, and spans from constant to logarithmic depths. These circuit complexity results are supplemented by fresh VLSI complexity results having applications to hardware implementations of neural networks and to VLSI-friendly learning algorithms. In order to estimate the area (A) and the delay (T), as well as the classical AT{sup 2}, we shall use the following {open_quote}cost functions{close_quote}: (i) the connectivity (i.e., sum of fan-ins) and the number-of-bits for representing the weights and thresholds are used as closer approximations of the area; while (ii) the fan-ins and the length of the wires are used for closer estimates of the delay. Such approximations allow us to compare the different solutions-which present very interesting fan-in dependent depth-size and area-delay tradeoffs - with respect to AT{sup 2}.

Beiu, V.

1996-12-31T23:59:59.000Z

440

Atomic layer deposition of Hf{sub x}Al{sub y}C{sub z} as a work function material in metal gate MOS devices  

SciTech Connect (OSTI)

As advanced silicon semiconductor devices are transitioning from planar to 3D structures, new materials and processes are needed to control the device characteristics. Atomic layer deposition (ALD) of Hf{sub x}Al{sub y}C{sub z} films using hafnium chloride and trimethylaluminum precursors was combined with postdeposition anneals and ALD liners to control the device characteristics in high-k metal-gate devices. Combinatorial process methods and technologies were employed for rapid electrical and materials characterization of various materials stacks. The effective work function in metal–oxide–semiconductor capacitor devices with the Hf{sub x}Al{sub y}C{sub z} layer coupled with an ALD HfO{sub 2} dielectric was quantified to be mid-gap at ?4.6?eV. Thus, Hf{sub x}Al{sub y}C{sub z} is a promising metal gate work function material that allows for the tuning of device threshold voltages (V{sub th}) for anticipated multi-V{sub th} integrated circuit devices.

Lee, Albert, E-mail: alee@intermolecular.com; Fuchigami, Nobi; Pisharoty, Divya; Hong, Zhendong; Haywood, Ed; Joshi, Amol; Mujumdar, Salil; Bodke, Ashish; Karlsson, Olov [Intermolecular, 3011 North First Street, San Jose, California 95134 (United States); Kim, Hoon; Choi, Kisik [GLOBALFOUNDRIES Technology Research Group, 257 Fuller Road, Albany, New York 12309 (United States); Besser, Paul [GLOBALFOUNDRIES, 1050 East Arques, Sunnyvale, California 94085 (United States)

2014-01-15T23:59:59.000Z

Note: This page contains sample records for the topic "transistor gate oxide" from the National Library of EnergyBeta (NLEBeta).
While these samples are representative of the content of NLEBeta,
they are not comprehensive nor are they the most current set.
We encourage you to perform a real-time search of NLEBeta
to obtain the most current and comprehensive results.


441

Silicon field-effect transistor based on quantum tunneling J. FL Tucker, Chinlee Wang, and P. Scott Carney  

E-Print Network [OSTI]

configuration, the gate could be offset in order to permit a shallow implant of the finished device to convert a commercial package, SEMICAD,' together with our own cal- culation of tunneling and thermionic emission

Bhargava, Rohit

442

Barium oxide, calcium oxide, magnesia, and alkali oxide free glass  

DOE Patents [OSTI]

A glass composition consisting essentially of about 10-45 mole percent of SrO; about 35-75 mole percent SiO.sub.2; one or more compounds from the group of compounds consisting of La.sub.2O.sub.3, Al.sub.2O.sub.3, B.sub.2O.sub.3, and Ni; the La.sub.2O.sub.3 less than about 20 mole percent; the Al.sub.2O.sub.3 less than about 25 mole percent; the B.sub.2O.sub.3 less than about 15 mole percent; and the Ni less than about 5 mole percent. Preferably, the glass is substantially free of barium oxide, calcium oxide, magnesia, and alkali oxide. Preferably, the glass is used as a seal in a solid oxide fuel/electrolyzer cell (SOFC) stack. The SOFC stack comprises a plurality of SOFCs connected by one or more interconnect and manifold materials and sealed by the glass. Preferably, each SOFC comprises an anode, a cathode, and a solid electrolyte.

Lu, Peizhen Kathy; Mahapatra, Manoj Kumar

2013-09-24T23:59:59.000Z

443

METAL OXIDE NANOPARTICLES  

SciTech Connect (OSTI)

This chapter covers the fundamental science, synthesis, characterization, physicochemical properties and applications of oxide nanomaterials. Explains fundamental aspects that determine the growth and behavior of these systems, briefly examines synthetic procedures using bottom-up and top-down fabrication technologies, discusses the sophisticated experimental techniques and state of the art theory results used to characterize the physico-chemical properties of oxide solids and describe the current knowledge concerning key oxide materials with important technological applications.

FERNANDEZ-GARCIA,M.; RODGRIGUEZ, J.A.

2007-10-01T23:59:59.000Z

444

Mixed oxide solid solutions  

DOE Patents [OSTI]

The present invention is a mixed oxide solid solution containing a tetravalent and a pentavalent cation that can be used as a support for a metal combustion catalyst. The invention is furthermore a combustion catalyst containing the mixed oxide solid solution and a method of making the mixed oxide solid solution. The tetravalent cation is zirconium(+4), hafnium(+4) or thorium(+4). In one embodiment, the pentavalent cation is tantalum(+5), niobium(+5) or bismuth(+5). Mixed oxide solid solutions of the present invention exhibit enhanced thermal stability, maintaining relatively high surface areas at high temperatures in the presence of water vapor.

Magno, Scott (Dublin, CA); Wang, Ruiping (Fremont, CA); Derouane, Eric (Liverpool, GB)

2003-01-01T23:59:59.000Z

445

positions): transistor,  

E-Print Network [OSTI]

, Hubble) . Anthropology ­ 1 (The Leakeys) . Economy ­ 1 (Keynes) . Environment ­ 1 (Rachel Carson & Astronomy ­ 3 (Einstein, Fermi, Hubble) . Anthropology ­ 1 (The Leakeys) . Economy ­ 1 (Keynes). Downside: Relatively slow. Later refinements improved its e#­ ciency but the logical purity has been lost

Artemov, Sergei N.

446

Influence of electron–phonon interactions in single dopant nanowire transistors  

SciTech Connect (OSTI)

Single dopant nanowire transistors can be viewed as the ultimate miniaturization of nano electronic devices. In this work, we theoretically investigate the influence of the electron-phonon coupling on their transport properties using a non-equilibrium Green's function approach in the self-consistent Born approximation. For an impurity located at the center of the wire we find that, at room temperature, acoustic phonons broaden the impurity level so that the bistability predicted in the ballistic regime is suppressed. Optical phonons are found to have a beneficial impact on carrier transport via a phonon-assisted tunneling effect. We discuss the position and temperature dependence of these effects, showing that such systems might be very promising for engineering of ultimate devices.

Carrillo-Nuñez, H., E-mail: carrillh@iis.ee.ethz.ch; Bescond, M., E-mail: marc.bescond@im2np.fr; Cavassilas, N.; Dib, E.; Lannoo, M. [IM2NP, UMR CNRS 6242, Bât. IRPHE, Technopôle de Château-Gombert, 13384 Marseille, Cedex 13 (France)

2014-10-28T23:59:59.000Z

447

Influence of curvature on the device physics of thin film transistors on flexible substrates  

SciTech Connect (OSTI)

Thin film transistors (TFTs) on elastomers promise flexible electronics with stretching and bending. Recently, there have been several experimental studies reporting the behavior of TFTs under bending and buckling. In the presence of stress, the insulator capacitance is influenced due to two reasons. The first is the variation in insulator thickness depending on the Poisson ratio and strain. The second is the geometric influence of the curvature of the insulator-semiconductor interface during bending or buckling. This paper models the role of curvature on TFT performance and brings to light an elegant result wherein the TFT characteristics is dependent on the area under the capacitance-distance curve. The paper compares models with simulations and explains several experimental findings reported in literature.

Amalraj, Rex; Sambandan, Sanjiv, E-mail: sanjiv@iap.iisc.ernet.in [Flexible Electronics Lab, Department of Instrumentation and Applied Physics, Indian Institute of Science, Bangalore 560012 (India)

2014-10-28T23:59:59.000Z

448

Detection of nanosecond-scale, high power THz pulses with a field effect transistor  

SciTech Connect (OSTI)

We demonstrate detection and resolution of high power, 34 ns free electron laser pulses using a rectifying field effect transistor. The detector remains linear up to an input power of 11 {+-} 0.5 W at a pulse energy of 20 {+-} 1 {mu}J at 240 GHz. We compare its performance to a protected Schottky diode, finding a shorter intrinsic time constant. The damage threshold is estimated to be a few 100 W. The detector is, therefore, well-suited for characterizing high power THz pulses. We further demonstrate that the same detector can be used to detect low power continuous-wave THz signals with a post detection limited noise floor of 3.1 {mu}W/{radical}(Hz). Such ultrafast, high power detectors are important tools for high power and high energy THz facilities such as free electron lasers.

Preu, S. [Physics Department and Institute for Terahertz Science and Technology, University of California, Santa Barbara, California 93106 (United States); Materials Department, University of California, Santa Barbara, California 93106 (United States); Chair for Applied Physics, University of Erlangen-Nuremberg, 91058 Erlangen (Germany); Lu, H.; Gossard, A. C. [Materials Department, University of California, Santa Barbara, California 93106 (United States); Sherwin, M. S. [Physics Department and Institute for Terahertz Science and Technology, University of California, Santa Barbara, California 93106 (United States)

2012-05-15T23:59:59.000Z

449

Atomically flat La-silicate/Si interface using tungsten carbide gate electrode with nano-sized grain  

SciTech Connect (OSTI)

Interface properties of La-silicate gate dielectrics on Si substrates with W or nano-sized grain W{sub 2}C gate electrodes have been investigated. A low interface state density of 2.5?×?10{sup 11}?cm{sup ?2}/eV has been achieved with W{sub 2}C gate electrodes, which is one third of those with W gate electrode. An interface roughness of 0.33?nm with spatial frequency comparable to the grain size of W gate electrode has been observed. Besides, an atomically flat interface of 0.12?nm has been obtained with W{sub 2}C gate electrode. The origin of flat interface may be attributed to the elimination of inhomogeneous stress by grains in metal electrode.

Tuokedaerhan, K.; Natori, K.; Iwai, H. [Frontier Research Center, Tokyo Institute of Technology, 4259 Nagatsuta, Midori-ku, Yokohama 226-8503 (Japan); Kakushima, K., E-mail: kakushima@ep.titech.ac.jp; Kataoka, Y.; Nishiyama, A.; Sugii, N.; Wakabayashi, H.; Tsutsui, K. [Interdisciplinary Graduate School of Science and Engineering, Tokyo Institute of Technology, 4259 Nagatsuta, Midori-ku, Yokohama 226-8502 (Japan)

2014-01-13T23:59:59.000Z

450

Stabilized chromium oxide film  

DOE Patents [OSTI]

Stabilized air-oxidized chromium films deposited on high-power klystron ceramic windows and sleeves having a thickness between 20 and 150A are useful in lowering secondary electron emission yield and in avoiding multipactoring and window failure due to overheating. The ceramic substrate for the film is chosen from alumina, sapphire or beryllium oxide.

Nyaiesh, A.R.; Garwin, E.L.

1986-08-04T23:59:59.000Z

451

Stabilized chromium oxide film  

DOE Patents [OSTI]

Stabilized air-oxidized chromium films deposited on high-power klystron ceramic windows and sleeves having a thickness between 20 and 150.ANG. are useful in lowering secondary electron emission yield and in avoiding multipactoring and window failure due to overheating. The ceramic substrate for the film is chosen from alumina, sapphire or beryllium oxide.

Garwin, Edward L. (Los Altos, CA); Nyaiesh, Ali R. (Palo Alto, CA)

1988-01-01T23:59:59.000Z

452

Reducible oxide based catalysts  

DOE Patents [OSTI]

A catalyst is disclosed herein. The catalyst includes a reducible oxide support and at least one noble metal fixed on the reducible oxide support. The noble metal(s) is loaded on the support at a substantially constant temperature and pH.

Thompson, Levi T.; Kim, Chang Hwan; Bej, Shyamal K.

2010-04-06T23:59:59.000Z

453

Exact solutions for a universal set of quantum gates on a family of iso-spectral spin chains  

E-Print Network [OSTI]

We find exact solutions for a universal set of quantum gates on a scalable candidate for quantum computers, namely an array of two level systems. The gates are constructed by a combination of dynamical and geometrical (non-Abelian) phases. Previously these gates have been constructed mostly on non-scalable systems and by numerical searches among the loops in the manifold of control parameters of the Hamiltonian.

V. Karimipour; N. Majd

2005-09-25T23:59:59.000Z

454

Modelling of silicon oxynitridation by nitrous oxide using the reaction rate approach  

SciTech Connect (OSTI)

Large technological progress in oxynitridation processing leads to the introduction of silicon oxynitride as ultra-thin gate oxide. On the theoretical side, few studies have been dedicated to the process modelling of oxynitridation. Such an objective is a considerable challenge regarding the various atomistic mechanisms occurring during this fabrication step. In this article, some progress performed to adapt the reaction rate approach for the modelling of oxynitride growth by a nitrous ambient are reported. The Ellis and Buhrman's approach is used for the gas phase decomposition modelling. Taking into account the mass balance of the species at the interface between the oxynitride and silicon, a minimal kinetic model describing the oxide growth has been calibrated and implemented. The influence of nitrogen on the reaction rate has been introduced in an empirical way. The oxidation kinetics predicted with this minimal model compares well with several experiments.

Dominique Krzeminski, Christophe, E-mail: christophe.krzeminski@isen.fr [Départment ISEN, IEMN-UMR-8520, 41 Boulevard Vauban, 59046 Lille Cedex (France)

2013-12-14T23:59:59.000Z

455

Single-Phase Self-Oscillating Jets for Enhanced Heat Transfer: Preprint  

SciTech Connect (OSTI)

Self-oscillating jets have potential to cool insulated gate bipolar transistors in vehicle power electronics modules.

Narumanchi, S.; Kelly, K.; Mihalic, M.; Gopalan, S.; Hester, R.; Vlahinos, A.

2008-06-01T23:59:59.000Z

456

The fabrication and characteristics of a Vertical V-grove Field-Effect Transistor  

E-Print Network [OSTI]

SOURCE + n DRAIN X n + n GATE Figure 7. Ideal JFET showing model parameters. P 12 Applying this condition to (2) it can be seen that qN a 2 W 0 2C where W is the pinch off potential for the JFET. The dotted line 0 in Figure 8 represents..., can then be obtained from the definition dI g dV (11) Taking the derivative of (10) with respect to the drain voltage, the conductance in the linear region is 2s(y -v ) , s = ~, L' ? (~~) I. qN a (12) The transconductance, g , is defined...

Simpson, Dale Alan

1980-01-01T23:59:59.000Z

457

Water gate array for current flow or tidal movement pneumatic harnessing system  

DOE Patents [OSTI]

The invention, which provides a system for harnessing power from current flow or tidal movement in a body of water, comprises first and second hydro-pneumatic chambers each having ingress and egress below the water surface near the river or ocean floor and water gates operative to open or seal the ports to the passage of water. In an exemplary embodiment, the gates are sychronized by shafts so that the ingress ports of each chamber are connected to the egress ports of each other chamber. Thus, one set of gates is closed, while the other is open, thereby allowing water to flow into one chamber and build air pressure therein and allowing water to flow out of the other chamber and create a partial vacuum therein. A pipe connects the chambers, and an air turbine harnesses the air movement within the pipe. When water levels are equilibrated, the open set of gates is closed by a counterweight, and the other set is allowed to open by natural force of the water differential. The water gates may be comprised of a plurality of louvers which are ganged for simultaneous opening and closing. The system is designed to operate with air turbines or other pneumatic devices. Its design minimizes construction cost and environmental impact, yet provides a clean renewable energy source.

Gorlov, Alexander M. (Brookline, MA)

1991-01-01T23:59:59.000Z

458

UC Davis Fuel Cell, Hydrogen, and Hybrid Vehicle (FCH2V) GATE Center of Excellence  

SciTech Connect (OSTI)

This is the final report of the UC Davis Fuel Cell, Hydrogen, and Hybrid Vehicle (FCH2V) GATE Center of Excellence which spanned from 2005-2012. The U.S. Department of Energy (DOE) established the Graduate Automotive Technology Education (GATE) Program, to provide a new generation of engineers and scientists with knowledge and skills to create advanced automotive technologies. The UC Davis Fuel Cell, Hydrogen, and Hybrid Vehicle (FCH2V) GATE Center of Excellence established in 2005 is focused on research, education, industrial collaboration and outreach within automotive technology. UC Davis has had two independent GATE centers with separate well-defined objectives and research programs from 1998. The Fuel Cell Center, administered by ITS-Davis, has focused on fuel cell technology. The Hybrid-Electric Vehicle Design Center (HEV Center), administered by the Department of Mechanical and Aeronautical Engineering, has focused on the development of plug-in hybrid technology using internal combustion engines. The merger of these two centers in 2005 has broadened the scope of research and lead to higher visibility of the activity. UC Davisâ??s existing GATE centers have become the campusâ??s research focal points on fuel cells and hybrid-electric vehicles, and the home for graduate students who are studying advanced automotive technologies. The centers have been highly successful in attracting, training, and placing top-notch students into fuel cell and hybrid programs in both industry and government.

Erickson, Paul

2012-05-31T23:59:59.000Z

459

High performance double pulse doped pseudomorphic AlGaAs/InGaAs transistors grown by molecular-beam epitaxy  

SciTech Connect (OSTI)

Double pulse doped AlGaAs/InGaAs pseudomorphic high electron mobility transistors have been grown by molecular-beam epitaxy on GaAs substrates. Hall mobilities in excess of 7100 cm{sup 2}/V s at 300 K and 25000 cm{sup 2}/V s at 77 K are obtained with a sheet density of 3 x 10{sup 12} cm{sup {minus}2}. Photoluminescence measurements indicate that two electronic subbands are occupied, and the subband energies are determined. The doping pulses are resolved in secondary ion mass spectrometry measurements. Using a double recess process, transistors have been fabricated that have produced state of the art microwave performance. At 10 GHz a 1.2 mm device has simultaneously achieved a power added efficiency of 70%, output power of 0.97 W, and gain of 10 dB. 17 refs., 5 figs., 1 tab.

Hoke, W.E.; Lyman, P.S.; Labossier, W.H.; Brierley, S.K.; Hendriks, H.T.; Shanfield, S.R.; Aucoin, L.M.; Kazior, T.E. [Raytheon Research Division, Lexington, MA (United States)] [Raytheon Research Division, Lexington, MA (United States)

1992-05-01T23:59:59.000Z

460

Optical imaging through turbid media with a degenerate four-wave mixing correlation time gate  

DOE Patents [OSTI]

Optical imaging through turbid media is demonstrated using a degenerate four-wave mixing correlation time gate. An apparatus and method for detecting ballistic and/or snake light while rejecting unwanted diffusive light for imaging structures within highly scattering media are described. Degenerate four-wave mixing (DFWM) of a doubled YAG laser in rhodamine 590 is used to provide an ultrafast correlation time gate to discriminate against light that has undergone multiple scattering and therefore has lost memory of the structures within the scattering medium. Images have been obtained of a test cross-hair pattern through highly turbid suspensions of whole milk in water that are opaque to the naked eye, which demonstrates the utility of DFWM for imaging through turbid media. Use of DFWM as an ultrafast time gate for the detection of ballistic and/or snake light in optical mammography is discussed.

Sappey, Andrew D. (Golden, CO)

1998-04-14T23:59:59.000Z

Note: This page contains sample records for the topic "transistor gate oxide" from the National Library of EnergyBeta (NLEBeta).
While these samples are representative of the content of NLEBeta,
they are not comprehensive nor are they the most current set.
We encourage you to perform a real-time search of NLEBeta
to obtain the most current and comprehensive results.


461

Coherent motion of stereocilia assures the concerted gating of hair-cell transduction channels  

E-Print Network [OSTI]

The hair cell's mechanoreceptive organelle, the hair bundle, is highly sensitive because its transduction channels open over a very narrow range of displacements. The synchronous gating of transduction channels also underlies the active hair-bundle motility that amplifies and tunes responsiveness. The extent to which the gating of independent transduction channels is coordinated depends on how tightly individual stereocilia are constrained to move as a unit. Using dual-beam interferometry in the bullfrog's sacculus, we found that thermal movements of stereocilia located as far apart as a bundle's opposite edges display high coherence and negligible phase lag. Because the mechanical degrees of freedom of stereocilia are strongly constrained, a force applied anywhere in the hair bundle deflects the structure as a unit. This feature assures the concerted gating of transduction channels that maximizes the sensitivity of mechanoelectrical transduction and enhances the hair bundle's capacity to amplify its inputs.

Andrei S. Kozlov; Thomas Risler; A. J. Hudspeth

2009-02-16T23:59:59.000Z

462

Oxidative Tritium Decontamination System  

DOE Patents [OSTI]

The Oxidative Tritium Decontamination System, OTDS, provides a method and apparatus for reduction of tritium surface contamination on various items. The OTDS employs ozone gas as oxidizing agent to convert elemental tritium to tritium oxide. Tritium oxide vapor and excess ozone gas is purged from the OTDS, for discharge to atmosphere or transport to further process. An effluent stream is subjected to a catalytic process for the decomposition of excess ozone to diatomic oxygen. One of two configurations of the OTDS is employed: dynamic apparatus equipped with agitation mechanism and large volumetric capacity for decontamination of light items, or static apparatus equipped with pressurization and evacuation capability for decontamination of heavier, delicate, and/or valuable items.

Gentile, Charles A. (Plainsboro, NJ), Guttadora, Gregory L. (Highland Park, NJ), Parker, John J. (Medford, NJ)

2006-02-07T23:59:59.000Z

463

Controlled CO preferential oxidation  

DOE Patents [OSTI]

Method is described for controlling the supply of air to a PROX (PReferential OXidation for CO cleanup) reactor for the preferential oxidation in the presence of hydrogen wherein the concentration of the hydrogen entering and exiting the PROX reactor is monitored, the difference there between correlated to the amount of air needed to minimize such difference, and based thereon the air supply to the PROX reactor adjusted to provide such amount and minimize such difference. 2 figs.

Meltser, M.A.; Hoch, M.M.

1997-06-10T23:59:59.000Z

464

Resilience of gated avalanche photodiodes against bright illumination attacks in quantum cryptography  

E-Print Network [OSTI]

Semiconductor avalanche photodiodes (APDs) are commonly used for single photon detection in quantum key distribution. Recently, many attacks using bright illumination have been proposed to manipulate gated InGaAs APDs. In order to devise effective counter-measures, careful analysis of these attacks must be carried out to distinguish between incorrect operation and genuine loopholes. Here, we show that correctly-operated, gated APDs are immune to continuous-wave illumination attacks, while monitoring the photocurrent for anomalously high values is a straightforward counter-measure against attacks using temporally tailored light.

Z. L. Yuan; J. F. Dynes; A. J. Shields

2011-06-14T23:59:59.000Z

465

A proposal for the implementation of quantum gates with photonic-crystal coupled cavity waveguides  

E-Print Network [OSTI]

Quantum computers require technologies that offer both sufficient control over coherent quantum phenomena and minimal spurious interactions with the environment. We show, that photons confined to photonic crystals, and in particular to highly efficient waveguides formed from linear chains of defects doped with atoms can generate strong non-linear interactions which allow to implement both single and two qubit quantum gates. The simplicity of the gate switching mechanism, the experimental feasibility of fabricating two dimensional photonic crystal structures and integrability of this device with optoelectronics offers new interesting possibilities for optical quantum information processing networks.

Dimitris G. Angelakis; Marcelo Franca Santos; Vassilis Yannopapas; Artur Ekert

2007-04-12T23:59:59.000Z

466

Noise-Protected Gate for Six-Electron Double-Dot Qubits  

E-Print Network [OSTI]

Singlet-triplet spin qubits in six-electron double quantum dots, in moderate magnetic fields, can show superior immunity to charge noise. This immunity results from the symmetry of orbitals in the second energy shell of circular quantum dots: singlet and triplet states in this shell have identical charge distributions. Our phase-gate simulations, which include $1/f$ charge noise from fluctuating traps, show that this symmetry is most effectively exploited if the gate operation switches rapidly between sweet spots deep in the (3,3) and (4,2) charge stability regions; fidelities very close to one are predicted if subnanosecond switching can be performed.

Sebastian Mehl; David P. DiVincenzo

2014-08-05T23:59:59.000Z

467

Engineering a C-Phase quantum gate: optical design and experimental realization  

E-Print Network [OSTI]

A two qubit quantum gate, namely the C-Phase, has been realized by exploiting the longitudinal momentum (i.e. the optical path) degree of freedom of a single photon. The experimental setup used to engineer this quantum gate represents an advanced version of the high stability closed-loop interferometric setup adopted to generate and characterize 2-photon 4-qubit Phased Dicke states. Some experimental results, dealing with the characterization of multipartite entanglement of the Phased Dicke states are also discussed in detail.

Andrea Chiuri; Chiara Greganti; Paolo Mataloni

2012-04-12T23:59:59.000Z

468

ADVANCED OXIDATION PROCESS  

SciTech Connect (OSTI)

The removal of recalcitrant sulfur species, dibenzothiophene and its derivatives, from automotive fuels is an integral component in the development of cleaner burning and more efficient automobile engines. Oxidative desulfurization (ODS) wherein the dibenzothiophene derivative is converted to its corresponding sulfoxide and sulfone is an attractive approach to sulfur removal because the oxidized species are easily extracted or precipitated and filtered from the hydrocarbon phase. Fe-TAML{reg_sign} activators of hydrogen peroxide (TAML is Tetra-Amido-Macrocyclic-Ligand) catalytically convert dibenzothiophene and its derivatives rapidly and effectively at moderate temperatures (50-60 C) and ambient pressure to the corresponding sulfoxides and sulfones. The oxidation process can be performed in both aqueous systems containing alcohols such as methanol, ethanol, or t-butanol, and in a two-phase hydrocarbon/aqueous system containing tert-butanol or acetonitrile. In the biphasic system, essentially complete conversion of the DBT to its oxidized products can be achieved using slightly longer reaction times than in homogeneous solution. Among the key features of the technology are the mild reaction conditions, the very high selectivity where no over oxidation of the sulfur compounds occurs, the near stoichiometric use of hydrogen peroxide, the apparent lack of degradation of sensitive fuel components, and the ease of separation of oxidized products.

Dr. Colin P. Horwitz; Dr. Terrence J. Collins

2003-11-04T23:59:59.000Z

469

Crystal Structure of the Mammalian GIRK2 KplusChannel and Gating Regulation by G Proteins PIP2 and Sodium  

SciTech Connect (OSTI)

G protein-gated K{sup +} channels (Kir3.1--Kir3.4) control electrical excitability in many different cells. Among their functions relevant to human physiology and disease, they regulate the heart rate and govern a wide range of neuronal activities. Here, we present the first crystal structures of a G protein-gated K{sup +} channel. By comparing the wild-type structure to that of a constitutively active mutant, we identify a global conformational change through which G proteins could open a G loop gate in the cytoplasmic domain. The structures of both channels in the absence and presence of PIP{sub 2} suggest that G proteins open only the G loop gate in the absence of PIP{sub 2}, but in the presence of PIP{sub 2} the G loop gate and a second inner helix gate become coupled, so that both gates open. We also identify a strategically located Na{sup +} ion-binding site, which would allow intracellular Na{sup +} to modulate GIRK channel activity. These data provide a structural basis for understanding multiligand regulation of GIRK channel gating.

M Whorton; R MacKinnon

2011-12-31T23:59:59.000Z

470

Dominant-Negative Synthesis Suppression of Voltage-Gated Calcium Channel Cav2.2 Induced by Truncated Constructs  

E-Print Network [OSTI]

Dominant-Negative Synthesis Suppression of Voltage-Gated Calcium Channel Cav2.2 Induced, United Kingdom Voltage-gated calcium channel 1 subunits consist of four domains (I­IV), each with six by the cytoplasmic I-II loop of Cav2.2. It requires transmembrane seg- ments, because the isolated Cav2.2 N terminus

Dolphin, Annette C.

471

Trapping in deep defects under substrate hot electron stress in TiN/Hf-silicate based gate stacks  

E-Print Network [OSTI]

Trapping in deep defects under substrate hot electron stress in TiN/Hf-silicate based gate stacks N. Zaslavsky Abstract Substrate hot electron stress was applied on n+ -ringed n-channel MOS capacitors with TiN/Hf-silicate. Introduction Hafnium silicate based high-j gate dielectrics have been put forth as the leading candidates

Misra, Durgamadhab "Durga"

472

ECG-GATED C-ARM COMPUTED TOMOGRAPHY USING L1 REGULARIZATION Cyril Mory 1,3  

E-Print Network [OSTI]

ECG-GATED C-ARM COMPUTED TOMOGRAPHY USING L1 REGULARIZATION Cyril Mory 1,3 , Bo Zhang 3 , Vincent of the algorithm used for the minimization. Index Terms -- C-Arm, computed tomography, ECG- gating, augmented arises from the synchronization with the patient's electrocardiogram (ECG), which is necessary to avoid

Paris-Sud XI, Université de

473

An energy relaxation tolerant approach to quantum entanglement, information transfer, and gates with superconducting-quantum-interference-device qubits in cavity QED  

E-Print Network [OSTI]

A scheme is proposed for realizing quantum entanglement, information transfer, CNOT gates, and SWAP gates with supercoiiducting-quantum-interference-device (SQUID) qubits in cavity QED. In the scheme, the two logical states ...

Yang, Chuiping; Chu, Shih-I; Han, Siyuan

2004-03-31T23:59:59.000Z

474

Possible realization of entanglement, logical gates, and quantum-information transfer with superconducting-quantum-interference-device qubits in cavity QED  

E-Print Network [OSTI]

We present a scheme to achieve maximally entangled states, controlled phase-shift gate, and SWAP gate for two superconducting-quantum-interference-device (SQUID) qubits, by placing SQUIDs in a microwave cavity. We also ...

Yang, Chui-Ping; Chu, Shih-I; Han, Siyuan

2003-04-17T23:59:59.000Z

475

Advantages of flattened electrode in bottom contact single-walled carbon nanotube field-effect transistor  

SciTech Connect (OSTI)

We fabricated single-walled carbon nanotube (SWNT) field-effect transistor (FET) devices on flattened electrodes, in which there are no height difference between metal electrodes and the substrate. SWNT-FET fabricated using bottom contact technique have some advantages, such that the SWNTs are free from electron irradiation, have direct contact with the desired metal electrodes, and can be functionalized before or after deposition. However, the SWNTs can be bent at the contact point with the metal electrodes leading to a different electrical characteristic of the devices. The number of SWNT direct junctions in short channel length devices is drastically increased by the use of flattened electrodes due to strong attractive interaction between SWNT and the substrate. The flattened electrodes show a better balance between their hole and electron mobility compared to that of the non-flattened electrodes, that is, ambipolar FET characteristic. It is considered that bending of the SWNTs in the non-flattened electrode devices results in a higher Schottky barrier for the electrons.

Setiadi, Agung; Akai-Kasaya, Megumi, E-mail: kasaya@prec.eng.osaka-u.ac.jp; Saito, Akira; Kuwahara, Yuji [Department of Precision Science and Technology, Graduate School of Engineering, Osaka University, 565-0871 Suita (Japan)

2014-09-01T23:59:59.000Z

476

Improvement of graphene field-effect transistors by hexamethyldisilazane surface treatment  

SciTech Connect (OSTI)

We report the improvement of the electrical characteristics of graphene field-effect transistors (FETs) by hexamethyldisilazane (HMDS) treatment. Both electron and hole field-effect mobilities are increased by 1.5?×?–2×, accompanied by effective residual carrier concentration reduction. Dirac point also moves closer to zero Volt. Time evolution of mobility data shows that mobility improvement saturates after a few hours of HMDS treatment. Temperature-dependent transport measurements show small mobility variation between 77 K and room temperature (295?K) before HMDS application. But mobility at 77 K is almost 2 times higher than mobility at 295?K after HMDS application, indicating reduced carrier scattering. Performance improvement is also observed for FETs made on hydrophobic substrate–an HMDS-graphene-HMDS sandwich structure. Raman spectroscopic analysis shows that G peak width is increased, G peak position is down shifted, and intensity ratio between 2D and G peaks is increased after HMDS application. We attribute the improvements in electronic transport mainly to enhanced screening and mitigation of adsorbed impurities from graphene surface upon HMDS treatment.

Chowdhury, Sk. Fahad; Sonde, Sushant; Rahimi, Somayyeh; Tao, Li; Banerjee, Sanjay; Akinwande, Deji, E-mail: deji@ece.utexas.edu [Microelectronics Research Center, The University of Texas at Austin, Austin, Texas 78758 (United States)

2014-07-21T23:59:59.000Z

477

Cerium Oxide Coating for Oxidation Reduction  

Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

AFDC Printable Version Share this resource Send a link to EERE: Alternative Fuels Data Center Home Page to someone by E-mail Share EERE: Alternative Fuels Data Center Home Page on Facebook Tweet about EERE: Alternative Fuels Data Center Home Page on Twitter Bookmark EERE:1 First Use of Energy for All Purposes (Fuel and Nonfuel),Feet) Year Jan Feb Mar Apr MayAtmospheric Optical Depth7-1D: Vegetation Proposed New Substation SitesStanding Friedel Waves,TheoryParliament'v0,MixturesCerium Oxide

478

Circadian gating of the psbAIII high light response in Synechococcus sp. strain PCC 7942  

E-Print Network [OSTI]

(1-5 fold) during the peaks of the cycle. We also found that in a clock null strain the lack of an oscillator does not entirely negate the light response of PpsbAIII::luxAB; however, this response does not demonstrate gating. In contrast...

Shelton, Jeffrey Lyn

2000-01-01T23:59:59.000Z

479

Elsevier Science 1 Use of the GATE Monte Carlo package for dosimetry  

E-Print Network [OSTI]

Elsevier Science 1 Use of the GATE Monte Carlo package for dosimetry applications D. Visvikis, a* M Angeles, USA Abstract One of the roles for MC simulation studies is in the area of dosimetry. A number of different codes dedicated to dosimetry applications are available and widely used today, such as MCNP

Paris-Sud XI, Université de

480

How to Successfully Implement a Knowledge Management System for the Mechanical Engineering Department at Gating Incorporated  

E-Print Network [OSTI]

. With this explosive growth, it has become imperative that Gating Incorporated instill a Knowledge Management System to retain the vast amount of tacit knowledge. New products are critical for consumer product companies, so finding ways to capture the knowledge of a...

Mudd, John

2009-05-15T23:59:59.000Z

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481

Performance of a 512 x 512 Gated CMOS Imager with a 250 ps Exposure Time  

SciTech Connect (OSTI)

We describe the performance of a 512x512 gated CMOS read out integrated circuit (ROIC) with a 250 ps exposure time. A low-skew, H-tree trigger distribution system is used to locally generate individual pixel gates in each 8x8 neighborhood of the ROIC. The temporal width of the gate is voltage controlled and user selectable via a precision potentiometer. The gating implementation was first validated in optical tests of a 64x64 pixel prototype ROIC developed as a proof-of-concept during the early phases of the development program. The layout of the H-Tree addresses each quadrant of the ROIC independently and admits operation of the ROIC in two modes. If “common mode” triggering is used, the camera provides a single 512x512 image. If independent triggers are used, the camera can provide up to four 256x256 images with a frame separation set by the trigger intervals. The ROIC design includes small (sub-pixel) optical photodiode structures to allow test and characterization of the ROIC using optical sources prior to bump bonding. Reported test results were obtained using short pulse, second harmonic Ti:Sapphire laser systems operating at ?~ 400 nm at sub-ps pulse widths.

Teruya, A T; Moody, J D; Hsing, W W; Brown, C G; Griffin, M; Mead, A S

2012-10-01T23:59:59.000Z

482

Needle-based reflection refractometry of scattering samples using coherence-gated  

E-Print Network [OSTI]

effects of internal refractive index variation in near-infrared optical tomography: a finite element, and K. D. Paulsen, "Effects of refractive index on near- infrared tomography of the breast," Appl. OptNeedle-based reflection refractometry of scattering samples using coherence-gated detection Adam M

Boppart, Stephen

483

Unique Functional Properties of a Sensory Neuronal P2X ATP-Gated Channel from Zebrafish  

E-Print Network [OSTI]

of native P2X receptor channels evokes a fast inward current carried by mono- valent and calcium ions in a broad range of calcium- dependent signaling events from the neurogenic control of smooth muscle, and a cysteine-rich extracellular loop resembles that of recently discovered proton-gated channels (Wald- mann

Séguéla, Philippe

484

Ligand Gated Ion Channel Functionality Assays Robert P. Hayes, Kumud Raj Poudel and James A. Brozik  

E-Print Network [OSTI]

was to devise a method suitable to test the functionality of the entire family of cysteine-loop ligand gated ion substrate was infused with calcium ions that were trapped by the POPC bilayer. Once the assembly was formed. Electrochemical measurements were taken using a calcium ion sensitive electrode. The assemblies were interrogated

Collins, Gary S.

485

International Agriculture Fellowship: A Gates Foundation Grand Challenges Exploration in Endophytic Biological Control  

E-Print Network [OSTI]

International Agriculture Fellowship: A Gates Foundation Grand Challenges Exploration in Endophytic Biological Control Who we are: The International Center for Tropical Agriculture (CIAT) is a member institute of the Consultative Group on International Agricultural Research (CIAR). Based in Cali, Colombia, we focus

Ferrara, Katherine W.

486

Accuracy of gates in a quantum computer based on vibrational eigenstates Dmitri Babikov  

E-Print Network [OSTI]

of quantum gates in such a system. Optimal control theory and numerical time-propagation of vibrational wave the computational sciences:2 ``Quantum computing would be to ordinary com- puting what nuclear energy is to fire'' consisting of two states 0 and 1 that have been harnessed for running quantum computing algorithms, setting

Reid, Scott A.

487

7-Gate Kinetic AMPA Model Kinetics to match EPSCs from calyx of Held  

E-Print Network [OSTI]

7-Gate Kinetic AMPA Model · Kinetics to match EPSCs from calyx of Held · Multiple closed, open and EPSC amplitude Bruce Graham Department of Computing Science and Mathematics, University of Stirling, U, including the calyx of Held in the mammalian auditory system. Such depression may be mediated

Graham, Bruce

488

REAL-TIME DUAL-MICROPHONE SPEECH ENHANCEMENT USING FIELD PROGRAMMABLE GATE ARRAYS  

E-Print Network [OSTI]

REAL-TIME DUAL-MICROPHONE SPEECH ENHANCEMENT USING FIELD PROGRAMMABLE GATE ARRAYS David Halupka@eecg}.toronto.edu ABSTRACT This paper discusses an implementation of a dual- microphone phase-based speech enhancement or irrelevant conversations, are present has fueled research interest in the areas of speech enhancement

Sheikholeslami, Ali

489

Method and system for measuring gate valve clearances and seating force  

DOE Patents [OSTI]

Valve clearances and seating force, as well as other valve operational parameters, are determined by measuring valve stem rotation during opening and closing operations of a translatable gate valve. The magnitude of the stem rotation, and the relative difference between the stem rotation on opening and closing provides valuable data on the valve internals in a non-intrusive manner.

Casada, Donald A. (Knoxville, TN); Haynes, Howard D. (Knoxville, TN); Moyers, John C. (Oak Ridge, TN); Stewart, Brian K. (Burns, TN)

1996-01-01T23:59:59.000Z

490

Gate Voltage Control of Oxygen Diffusion on Graphene Dr. Jorge O. Sofo  

E-Print Network [OSTI]

Gate Voltage Control of Oxygen Diffusion on Graphene Dr. Jorge O. Sofo Associate Professor conductivity (twice that of diamond). Due to Carbon's affinity for tetrahedral bonding, its surface is amenable atoms. Our research focuses on the attachment and diffusion of different atomic species to the surface

Bjørnstad, Ottar Nordal

491

Economic Congestion Relief Across Multiple Regions Requires Tradable Physical Flow-gate Rights  

E-Print Network [OSTI]

PWP-076 Economic Congestion Relief Across Multiple Regions Requires Tradable Physical Flow.ucei.berkeley.edu/ucei #12;Economic Congestion Relief Across Multiple Regions Requires Tradable Physical Flow-gate Rights- mission use. The North American Electric Reliability Council NERC is in the process of implementing

California at Berkeley. University of

492

Effects of Magnesium on Inactivation of the Voltage-gated Calcium Current in  

E-Print Network [OSTI]

Effects of Magnesium on Inactivation of the Voltage-gated Calcium Current in Cardiac Myocytes H-dependent inactivation can be modulated by changes in cytoplasmic Mg~+. INTRODUCTION Magnesium is an important constituent of the intracellular milieu. Despite the importance of magnesium as an essential cofactor

493

Photothermal Response in Dual-Gated Bilayer Graphene M.-H. Kim,1  

E-Print Network [OSTI]

Photothermal Response in Dual-Gated Bilayer Graphene M.-H. Kim,1 J. Yan,1,2 R. J. Suess,3 T. E photoresponse in gapped bilayer graphene was investigated by optical and transport measurements. A pulse There is growing recognition that graphene has excep- tional potential as a new optoelectronic material, which has

Murphy, Thomas E.

494

Current transport, gate dielectrics and band gap engineering in graphene devices  

E-Print Network [OSTI]

Current transport, gate dielectrics and band gap engineering in graphene devices Wenjuan Zhu In this work, we studied current transport in mono-, bi- and tri-layer graphene. We find that both of the electrical field of the substrate surface polar phonons in bi-layer/tri-layer graphenes. We also find

Perebeinos, Vasili

495

Gate-modulated thermoelectric conversion in disordered nanowires: I. Low temperature coherent regime  

E-Print Network [OSTI]

Gate-modulated thermoelectric conversion in disordered nanowires: I. Low temperature coherent as promising thermoelectric devices1 . In comparison to their bulk counterparts, they provide opportunities of thermoelectric conversion at a given temperature T . Indeed, they allow to reduce the phonon contribution ph

Recanati, Catherine

496

Title: Hydraulic modeling of a mixed water level control hydro-mechanical gate  

E-Print Network [OSTI]

Title: Hydraulic modeling of a mixed water level control hydro-mechanical gate Ludovic Cassan1 Abstract: The article describes the hydraulic functioning of a mixed water level control hydro- mechanical of the model to reproduce the functioning of this complex hydro-mechanical system. CE database Subject headings

Paris-Sud XI, Université de

497

Finding the Energy Efficient Curve: Gate Sizing for Minimum Power under Delay Constraints  

E-Print Network [OSTI]

Finding the Energy Efficient Curve: Gate Sizing for Minimum Power under Delay Constraints Yoni in a fast circuit by the same factor does not yield an energy-efficient design, and we characterize efficient. A design implementation is considered to be energy efficient when it has the highest performance

Kolodny, Avinoam

498

Transport in carbon nanotube field-effect transistors tuned using low energy electron beam This article has been downloaded from IOPscience. Please scroll down to see the full text article.  

E-Print Network [OSTI]

Transport in carbon nanotube field-effect transistors tuned using low energy electron beam exposure nanotube field-effect transistors tuned using low energy electron beam exposure Jack Chan1 , Brian Burke1/334212 Abstract We have studied the effect of low energy (30 keV) electron beam exposure on carbon nanotube field

Harriott, Lloyd R.

499

Methanol partial oxidation reformer  

DOE Patents [OSTI]

A partial oxidation reformer comprising a longitudinally extending chamber having a methanol, water and an air inlet and an outlet. An igniter mechanism is near the inlets for igniting a mixture of methanol and air, while a partial oxidation catalyst in the chamber is spaced from the inlets and converts methanol and oxygen to carbon dioxide and hydrogen. Controlling the oxygen to methanol mole ratio provides continuous slightly exothermic partial oxidation reactions of methanol and air producing hydrogen gas. The liquid is preferably injected in droplets having diameters less than 100 micrometers. The reformer is useful in a propulsion system for a vehicle which supplies a hydrogen-containing gas to the negative electrode of a fuel cell.

Ahmed, Shabbir (Bolingbrook, IL); Kumar, Romesh (Naperville, IL); Krumpelt, Michael (Naperville, IL)

1999-01-01T23:59:59.000Z

500

Methanol partial oxidation reformer  

DOE Patents [OSTI]

A partial oxidation reformer comprising a longitudinally extending chamber having a methanol, water and an air inlet and an outlet. An igniter mechanism is near the inlets for igniting a mixture of methanol and air, while a partial oxidation catalyst in the chamber is spaced from the inlets and converts methanol and oxygen to carbon dioxide and hydrogen. Controlling the oxygen to methanol mole ratio provides continuous slightly exothermic partial oxidation reactions of methanol and air producing hydrogen gas. The liquid is preferably injected in droplets having diameters less than 100 micrometers. The reformer is useful in a propulsion system for a vehicle which supplies a hydrogen-containing gas to the negative electrode of a fuel cell.

Ahmed, Shabbir (Bolingbrook, IL); Kumar, Romesh (Naperville, IL); Krumpelt, Michael (Naperville, IL)

2001-01-01T23:59:59.000Z