National Library of Energy BETA

Sample records for random access memory

  1. Paging memory from random access memory to backing storage in a parallel computer

    DOE Patents [OSTI]

    Archer, Charles J; Blocksome, Michael A; Inglett, Todd A; Ratterman, Joseph D; Smith, Brian E

    2013-05-21

    Paging memory from random access memory (`RAM`) to backing storage in a parallel computer that includes a plurality of compute nodes, including: executing a data processing application on a virtual machine operating system in a virtual machine on a first compute node; providing, by a second compute node, backing storage for the contents of RAM on the first compute node; and swapping, by the virtual machine operating system in the virtual machine on the first compute node, a page of memory from RAM on the first compute node to the backing storage on the second compute node.

  2. Phase-change Random Access Memory: A Scalable Technology

    SciTech Connect (OSTI)

    Raoux, S.; Burr, G; Breitwisch, M; Rettner, C; Chen, Y; Shelby, R; Salinga, M; Krebs, D; Chen, S; Lung, H

    2008-01-01

    Nonvolatile RAM using resistance contrast in phase-change materials [or phase-change RAM (PCRAM)] is a promising technology for future storage-class memory. However, such a technology can succeed only if it can scale smaller in size, given the increasingly tiny memory cells that are projected for future technology nodes (i.e., generations). We first discuss the critical aspects that may affect the scaling of PCRAM, including materials properties, power consumption during programming and read operations, thermal cross-talk between memory cells, and failure mechanisms. We then discuss experiments that directly address the scaling properties of the phase-change materials themselves, including studies of phase transitions in both nanoparticles and ultrathin films as a function of particle size and film thickness. This work in materials directly motivated the successful creation of a series of prototype PCRAM devices, which have been fabricated and tested at phase-change material cross-sections with extremely small dimensions as low as 3 nm x 20 nm. These device measurements provide a clear demonstration of the excellent scaling potential offered by this technology, and they are also consistent with the scaling behavior predicted by extensive device simulations. Finally, we discuss issues of device integration and cell design, manufacturability, and reliability.

  3. Spin-transfer torque magnetoresistive random-access memory technologies for normally off computing (invited)

    SciTech Connect (OSTI)

    Ando, K. Yuasa, S.; Fujita, S.; Ito, J.; Yoda, H.; Suzuki, Y.; Nakatani, Y.; Miyazaki, T.

    2014-05-07

    Most parts of present computer systems are made of volatile devices, and the power to supply them to avoid information loss causes huge energy losses. We can eliminate this meaningless energy loss by utilizing the non-volatile function of advanced spin-transfer torque magnetoresistive random-access memory (STT-MRAM) technology and create a new type of computer, i.e., normally off computers. Critical tasks to achieve normally off computers are implementations of STT-MRAM technologies in the main memory and low-level cache memories. STT-MRAM technology for applications to the main memory has been successfully developed by using perpendicular STT-MRAMs, and faster STT-MRAM technologies for applications to the cache memory are now being developed. The present status of STT-MRAMs and challenges that remain for normally off computers are discussed.

  4. A random access memory immune to single event upset using a T-Resistor

    DOE Patents [OSTI]

    Ochoa, A. Jr.

    1987-10-28

    In a random access memory cell, a resistance ''T'' decoupling network in each leg of the cell reduces random errors caused by the interaction of energetic ions with the semiconductor material forming the cell. The cell comprises two parallel legs each containing a series pair of complementary MOS transistors having a common gate connected to the node between the transistors of the opposite leg. The decoupling network in each leg is formed by a series pair of resistors between the transistors together with a third resistor interconnecting the junction between the pair of resistors and the gate of the transistor pair forming the opposite leg of the cell. 4 figs.

  5. Random access memory immune to single event upset using a T-resistor

    DOE Patents [OSTI]

    Ochoa, Jr., Agustin

    1989-01-01

    In a random access memory cell, a resistance "T" decoupling network in each leg of the cell reduces random errors caused by the interaction of energetic ions with the semiconductor material forming the cell. The cell comprises two parallel legs each containing a series pair of complementary MOS transistors having a common gate connected to the node between the transistors of the opposite leg. The decoupling network in each leg is formed by a series pair of resistors between the transistors together with a third resistor interconnecting the junction between the pair of resistors and the gate of the transistor pair forming the opposite leg of the cell.

  6. Spin-transfer-torque efficiency enhanced by edge-damage of perpendicular magnetic random access memories

    SciTech Connect (OSTI)

    Song, Kyungmi; Lee, Kyung-Jin

    2015-08-07

    We numerically investigate the effect of magnetic and electrical damages at the edge of a perpendicular magnetic random access memory (MRAM) cell on the spin-transfer-torque (STT) efficiency that is defined by the ratio of thermal stability factor to switching current. We find that the switching mode of an edge-damaged cell is different from that of an undamaged cell, which results in a sizable reduction in the switching current. Together with a marginal reduction of the thermal stability factor of an edge-damaged cell, this feature makes the STT efficiency large. Our results suggest that a precise edge control is viable for the optimization of STT-MRAM.

  7. A stochastic simulation method for the assessment of resistive random access memory retention reliability

    SciTech Connect (OSTI)

    Berco, Dan Tseng, Tseung-Yuen

    2015-12-21

    This study presents an evaluation method for resistive random access memory retention reliability based on the Metropolis Monte Carlo algorithm and Gibbs free energy. The method, which does not rely on a time evolution, provides an extremely efficient way to compare the relative retention properties of metal-insulator-metal structures. It requires a small number of iterations and may be used for statistical analysis. The presented approach is used to compare the relative robustness of a single layer ZrO{sub 2} device with a double layer ZnO/ZrO{sub 2} one, and obtain results which are in good agreement with experimental data.

  8. Voltage induced magnetostrictive switching of nanomagnets: Strain assisted strain transfer torque random access memory

    SciTech Connect (OSTI)

    Khan, Asif Nikonov, Dmitri E.; Manipatruni, Sasikanth; Ghani, Tahir; Young, Ian A.

    2014-06-30

    A spintronic device, called the “strain assisted spin transfer torque (STT) random access memory (RAM),” is proposed by combining the magnetostriction effect and the spin transfer torque effect which can result in a dramatic improvement in the energy dissipation relative to a conventional STT-RAM. Magnetization switching in the device which is a piezoelectric-ferromagnetic heterostructure via the combined magnetostriction and STT effect is simulated by solving the Landau-Lifshitz-Gilbert equation incorporating the influence of thermal noise. The simulations show that, in such a device, each of these two mechanisms (magnetostriction and spin transfer torque) provides in a 90° rotation of the magnetization leading a deterministic 180° switching with a critical current significantly smaller than that required for spin torque alone. Such a scheme is an attractive option for writing magnetic RAM cells.

  9. Performance improvement of gadolinium oxide resistive random access memory treated by hydrogen plasma immersion ion implantation

    SciTech Connect (OSTI)

    Wang, Jer-Chyi Hsu, Chih-Hsien; Ye, Yu-Ren; Ai, Chi-Fong; Tsai, Wen-Fa

    2014-03-15

    Characteristics improvement of gadolinium oxide (Gd{sub x}O{sub y}) resistive random access memories (RRAMs) treated by hydrogen plasma immersion ion implantation (PIII) was investigated. With the hydrogen PIII treatment, the Gd{sub x}O{sub y} RRAMs exhibited low set/reset voltages and a high resistance ratio, which were attributed to the enhanced movement of oxygen ions within the Gd{sub x}O{sub y} films and the increased Schottky barrier height at Pt/Gd{sub x}O{sub y} interface, respectively. The resistive switching mechanism of Gd{sub x}O{sub y} RRAMs was dominated by Schottky emission, as proved by the area dependence of the resistance in the low resistance state. After the hydrogen PIII treatment, a retention time of more than 10{sup 4} s was achieved at an elevated measurement temperature. In addition, a stable cycling endurance with the resistance ratio of more than three orders of magnitude of the Gd{sub x}O{sub y} RRAMs can be obtained.

  10. Set statistics in conductive bridge random access memory device with Cu/HfO{sub 2}/Pt structure

    SciTech Connect (OSTI)

    Zhang, Meiyun; Long, Shibing Wang, Guoming; Xu, Xiaoxin; Li, Yang; Liu, Qi; Lv, Hangbing; Liu, Ming; Lian, Xiaojuan; Miranda, Enrique; Su, Jordi

    2014-11-10

    The switching parameter variation of resistive switching memory is one of the most important challenges in its application. In this letter, we have studied the set statistics of conductive bridge random access memory with a Cu/HfO{sub 2}/Pt structure. The experimental distributions of the set parameters in several off resistance ranges are shown to nicely fit a Weibull model. The Weibull slopes of the set voltage and current increase and decrease logarithmically with off resistance, respectively. This experimental behavior is perfectly captured by a Monte Carlo simulator based on the cell-based set voltage statistics model and the Quantum Point Contact electron transport model. Our work provides indications for the improvement of the switching uniformity.

  11. In situ observation of nickel as an oxidizable electrode material for the solid-electrolyte-based resistive random access memory

    SciTech Connect (OSTI)

    Sun, Jun; Wu, Xing; Xu, Feng; Xu, Tao; Sun, Litao; Liu, Qi; Xie, Hongwei; Long, Shibing; Lv, Hangbing; Li, Yingtao; Liu, Ming

    2013-02-04

    In this letter, we dynamically investigate the resistive switching characteristics and physical mechanism of the Ni/ZrO{sub 2}/Pt device. The device shows stable bipolar resistive switching behaviors after forming process, which is similar to the Ag/ZrO{sub 2}/Pt and Cu/ZrO{sub 2}/Pt devices. Using in situ transmission electron microscopy, we observe in real time that several conductive filaments are formed across the ZrO{sub 2} layer between Ni and Pt electrodes after forming. Energy-dispersive X-ray spectroscopy results confirm that Ni is the main composition of the conductive filaments. The ON-state resistance increases with increasing temperature, exhibiting the feature of metallic conduction. In addition, the calculated resistance temperature coefficient is equal to that of the 10-30 nm diameter Ni nanowire, further indicating that the nanoscale Ni conductive bridge is the physical origin of the observed conductive filaments. The resistive switching characteristics and the conductive filament's component of Ni/ZrO{sub 2}/Pt device are consistent with the characteristics of the typical solid-electrolyte-based resistive random access memory. Therefore, aside from Cu and Ag, Ni can also be used as an oxidizable electrode material for resistive random access memory applications.

  12. Effect of embedded metal nanocrystals on the resistive switching characteristics in NiN-based resistive random access memory cells

    SciTech Connect (OSTI)

    Yun, Min Ju; Kim, Hee-Dong; Man Hong, Seok; Hyun Park, Ju; Su Jeon, Dong; Geun Kim, Tae

    2014-03-07

    The metal nanocrystals (NCs) embedded-NiN-based resistive random access memory cells are demonstrated using several metal NCs (i.e., Pt, Ni, and Ti) with different physical parameters in order to investigate the metal NC's dependence on resistive switching (RS) characteristics. First, depending on the electronegativity of metal, the size of metal NCs is determined and this affects the operating current of memory cells. If metal NCs with high electronegativity are incorporated, the size of the NCs is reduced; hence, the operating current is reduced owing to the reduced density of the electric field around the metal NCs. Second, the potential wells are formed by the difference of work function between the metal NCs and active layer, and the barrier height of the potential wells affects the level of operating voltage as well as the conduction mechanism of metal NCs embedded memory cells. Therefore, by understanding these correlations between the active layer and embedded metal NCs, we can optimize the RS properties of metal NCs embedded memory cells as well as predict their conduction mechanisms.

  13. Perpendicular spin transfer torque magnetic random access memories with high spin torque efficiency and thermal stability for embedded applications (invited)

    SciTech Connect (OSTI)

    Thomas, Luc Jan, Guenole; Zhu, Jian; Liu, Huanlong; Lee, Yuan-Jen; Le, Son; Tong, Ru-Ying; Pi, Keyu; Wang, Yu-Jen; Shen, Dongna; He, Renren; Haq, Jesmin; Teng, Jeffrey; Lam, Vinh; Huang, Kenlin; Zhong, Tom; Torng, Terry; Wang, Po-Kang

    2014-05-07

    Magnetic random access memories based on the spin transfer torque phenomenon (STT-MRAMs) have become one of the leading candidates for next generation memory applications. Among the many attractive features of this technology are its potential for high speed and endurance, read signal margin, low power consumption, scalability, and non-volatility. In this paper, we discuss our recent results on perpendicular STT-MRAM stack designs that show STT efficiency higher than 5?k{sub B}T/?A, energy barriers higher than 100?k{sub B}T at room temperature for sub-40?nm diameter devices, and tunnel magnetoresistance higher than 150%. We use both single device data and results from 8?Mb array to demonstrate data retention sufficient for automotive applications. Moreover, we also demonstrate for the first time thermal stability up to 400?C exceeding the requirement of Si CMOS back-end processing, thus opening the realm of non-volatile embedded memory to STT-MRAM technology.

  14. Atomic memory access hardware implementations

    SciTech Connect (OSTI)

    Ahn, Jung Ho; Erez, Mattan; Dally, William J

    2015-02-17

    Atomic memory access requests are handled using a variety of systems and methods. According to one example method, a data-processing circuit having an address-request generator that issues requests to a common memory implements a method of processing the requests using a memory-access intervention circuit coupled between the generator and the common memory. The method identifies a current atomic-memory access request from a plurality of memory access requests. A data set is stored that corresponds to the current atomic-memory access request in a data storage circuit within the intervention circuit. It is determined whether the current atomic-memory access request corresponds to at least one previously-stored atomic-memory access request. In response to determining correspondence, the current request is implemented by retrieving data from the common memory. The data is modified in response to the current request and at least one other access request in the memory-access intervention circuit.

  15. Total ionizing dose effect of γ-ray radiation on the switching characteristics and filament stability of HfOx resistive random access memory

    SciTech Connect (OSTI)

    Fang, Runchen; Yu, Shimeng; Gonzalez Velo, Yago; Chen, Wenhao; Holbert, Keith E.; Kozicki, Michael N.; Barnaby, Hugh

    2014-05-05

    The total ionizing dose (TID) effect of gamma-ray (γ-ray) irradiation on HfOx based resistive random access memory was investigated by electrical and material characterizations. The memory states can sustain TID level ∼5.2 Mrad (HfO{sub 2}) without significant change in the functionality or the switching characteristics under pulse cycling. However, the stability of the filament is weakened after irradiation as memory states are more vulnerable to flipping under the electrical stress. X-ray photoelectron spectroscopy was performed to ascertain the physical mechanism of the stability degradation, which is attributed to the Hf-O bond breaking by the high-energy γ-ray exposure.

  16. Implementation of nitrogen-doped titanium-tungsten tunable heater in phase change random access memory and its effects on device performance

    SciTech Connect (OSTI)

    Tan, Chun Chia; Zhao, Rong Chong, Tow Chong; Shi, Luping

    2014-10-13

    Nitrogen-doped titanium-tungsten (N-TiW) was proposed as a tunable heater in Phase Change Random Access Memory (PCRAM). By tuning N-TiW's material properties through doping, the heater can be tailored to optimize the access speed and programming current of PCRAM. Experiments reveal that N-TiW's resistivity increases and thermal conductivity decreases with increasing nitrogen-doping ratio, and N-TiW devices displayed (∼33% to ∼55%) reduced programming currents. However, there is a tradeoff between the current and speed for heater-based PCRAM. Analysis of devices with different N-TiW heaters shows that N-TiW doping levels could be optimized to enable low RESET currents and fast access speeds.

  17. Remote direct memory access

    DOE Patents [OSTI]

    Archer, Charles J.; Blocksome, Michael A.

    2012-12-11

    Methods, parallel computers, and computer program products are disclosed for remote direct memory access. Embodiments include transmitting, from an origin DMA engine on an origin compute node to a plurality target DMA engines on target compute nodes, a request to send message, the request to send message specifying a data to be transferred from the origin DMA engine to data storage on each target compute node; receiving, by each target DMA engine on each target compute node, the request to send message; preparing, by each target DMA engine, to store data according to the data storage reference and the data length, including assigning a base storage address for the data storage reference; sending, by one or more of the target DMA engines, an acknowledgment message acknowledging that all the target DMA engines are prepared to receive a data transmission from the origin DMA engine; receiving, by the origin DMA engine, the acknowledgement message from the one or more of the target DMA engines; and transferring, by the origin DMA engine, data to data storage on each of the target compute nodes according to the data storage reference using a single direct put operation.

  18. Low leakage Ru-strontium titanate-Ru metal-insulator-metal capacitors for sub-20 nm technology node in dynamic random access memory

    SciTech Connect (OSTI)

    Popovici, M. Swerts, J.; Redolfi, A.; Kaczer, B.; Aoulaiche, M.; Radu, I.; Clima, S.; Everaert, J.-L.; Van Elshocht, S.; Jurczak, M.

    2014-02-24

    Improved metal-insulator-metal capacitor (MIMCAP) stacks with strontium titanate (STO) as dielectric sandwiched between Ru as top and bottom electrode are shown. The Ru/STO/Ru stack demonstrates clearly its potential to reach sub-20 nm technology nodes for dynamic random access memory. Downscaling of the equivalent oxide thickness, leakage current density (J{sub g}) of the MIMCAPs, and physical thickness of the STO have been realized by control of the Sr/Ti ratio and grain size using a heterogeneous TiO{sub 2}/STO based nanolaminate stack deposition and a two-step crystallization anneal. Replacement of TiN with Ru as both top and bottom electrodes reduces the amount of electrically active defects and is essential to achieve a low leakage current in the MIM capacitor.

  19. Detrimental effect of interfacial Dzyaloshinskii-Moriya interaction on perpendicular spin-transfer-torque magnetic random access memory

    SciTech Connect (OSTI)

    Jang, Peong-Hwa; Lee, Seo-Won E-mail: kj-lee@korea.ac.kr; Song, Kyungmi; Lee, Seung-Jae; Lee, Kyung-Jin E-mail: kj-lee@korea.ac.kr

    2015-11-16

    Interfacial Dzyaloshinskii-Moriya interaction in ferromagnet/heavy metal bilayers is recently of considerable interest as it offers an efficient control of domain walls and the stabilization of magnetic skyrmions. However, its effect on the performance of perpendicular spin transfer torque memory has not been explored yet. We show based on numerical studies that the interfacial Dzyaloshinskii-Moriya interaction decreases the thermal energy barrier while increases the switching current. As high thermal energy barrier as well as low switching current is required for the commercialization of spin torque memory, our results suggest that the interfacial Dzyaloshinskii-Moriya interaction should be minimized for spin torque memory applications.

  20. Correlative transmission electron microscopy and electrical properties study of switchable phase-change random access memory line cells

    SciTech Connect (OSTI)

    Oosthoek, J. L. M.; Kooi, B. J.; Voogt, F. C.; Attenborough, K.; Verheijen, M. A.; Hurkx, G. A. M.; Gravesteijn, D. J.

    2015-02-14

    Phase-change memory line cells, where the active material has a thickness of 15 nm, were prepared for transmission electron microscopy (TEM) observation such that they still could be switched and characterized electrically after the preparation. The result of these observations in comparison with detailed electrical characterization showed (i) normal behavior for relatively long amorphous marks, resulting in a hyperbolic dependence between SET resistance and SET current, indicating a switching mechanism based on initially long and thin nanoscale crystalline filaments which thicken gradually, and (ii) anomalous behavior, which holds for relatively short amorphous marks, where initially directly a massive crystalline filament is formed that consumes most of the width of the amorphous mark only leaving minor residual amorphous regions at its edges. The present results demonstrate that even in (purposely) thick TEM samples, the TEM sample preparation hampers the probability to observe normal behavior and it can be debated whether it is possible to produce electrically switchable TEM specimen in which the memory cells behave the same as in their original bulk embedded state.

  1. Correlation of anomalous write error rates and ferromagnetic resonance spectrum in spin-transfer-torque-magnetic-random-access-memory devices containing in-plane free layers

    SciTech Connect (OSTI)

    Evarts, Eric R.; Rippard, William H.; Pufall, Matthew R.; Heindl, Ranko

    2014-05-26

    In a small fraction of magnetic-tunnel-junction-based magnetic random-access memory devices with in-plane free layers, the write-error rates (WERs) are higher than expected on the basis of the macrospin or quasi-uniform magnetization reversal models. In devices with increased WERs, the product of effective resistance and area, tunneling magnetoresistance, and coercivity do not deviate from typical device properties. However, the field-swept, spin-torque, ferromagnetic resonance (FS-ST-FMR) spectra with an applied DC bias current deviate significantly for such devices. With a DC bias of 300 mV (producing 9.9 × 10{sup 6} A/cm{sup 2}) or greater, these anomalous devices show an increase in the fraction of the power present in FS-ST-FMR modes corresponding to higher-order excitations of the free-layer magnetization. As much as 70% of the power is contained in higher-order modes compared to ≈20% in typical devices. Additionally, a shift in the uniform-mode resonant field that is correlated with the magnitude of the WER anomaly is detected at DC biases greater than 300 mV. These differences in the anomalous devices indicate a change in the micromagnetic resonant mode structure at high applied bias.

  2. Low latency memory access and synchronization

    DOE Patents [OSTI]

    Blumrich, Matthias A.; Chen, Dong; Coteus, Paul W.; Gara, Alan G.; Giampapa, Mark E.; Heidelberger, Philip; Hoenicke, Dirk; Ohmacht, Martin; Steinmacher-Burow, Burkhard D.; Takken, Todd E. , Vranas; Pavlos M.

    2010-10-19

    A low latency memory system access is provided in association with a weakly-ordered multiprocessor system. Bach processor in the multiprocessor shares resources, and each shared resource has an associated lock within a locking device that provides support for synchronization between the multiple processors in the multiprocessor and the orderly sharing of the resources. A processor only has permission to access a resource when it owns the lock associated with that resource, and an attempt by a processor to own a lock requires only a single load operation, rather than a traditional atomic load followed by store, such that the processor only performs a read operation and the hardware locking device performs a subsequent write operation rather than the processor. A simple prefetching for non-contiguous data structures is also disclosed. A memory line is redefined so that in addition to the normal physical memory data, every line includes a pointer that is large enough to point to any other line in the memory, wherein the pointers to determine which memory line to prefetch rather than some other predictive algorithm. This enables hardware to effectively prefetch memory access patterns that are non-contiguous, but repetitive.

  3. Low latency memory access and synchronization

    DOE Patents [OSTI]

    Blumrich, Matthias A.; Chen, Dong; Coteus, Paul W.; Gara, Alan G.; Giampapa, Mark E.; Heidelberger, Philip; Hoenicke, Dirk; Ohmacht, Martin; Steinmacher-Burow, Burkhard D.; Takken, Todd E.; Vranas, Pavlos M.

    2007-02-06

    A low latency memory system access is provided in association with a weakly-ordered multiprocessor system. Each processor in the multiprocessor shares resources, and each shared resource has an associated lock within a locking device that provides support for synchronization between the multiple processors in the multiprocessor and the orderly sharing of the resources. A processor only has permission to access a resource when it owns the lock associated with that resource, and an attempt by a processor to own a lock requires only a single load operation, rather than a traditional atomic load followed by store, such that the processor only performs a read operation and the hardware locking device performs a subsequent write operation rather than the processor. A simple prefetching for non-contiguous data structures is also disclosed. A memory line is redefined so that in addition to the normal physical memory data, every line includes a pointer that is large enough to point to any other line in the memory, wherein the pointers to determine which memory line to prefetch rather than some other predictive algorithm. This enables hardware to effectively prefetch memory access patterns that are non-contiguous, but repetitive.

  4. Influence of carbon content on the copper-telluride phase formation and on the resistive switching behavior of carbon alloyed Cu-Te conductive bridge random access memory cells

    SciTech Connect (OSTI)

    Devulder, Wouter De Schutter, Bob; Detavernier, Christophe; Opsomer, Karl; Franquet, Alexis; Meersschaut, Johan; Muller, Robert; Van Elshocht, Sven; Jurczak, Malgorzata; Goux, Ludovic; Belmonte, Attilio

    2014-02-07

    In this paper, we investigate the influence of the carbon content on the Cu-Te phase formation and on the resistive switching behavior in carbon alloyed Cu{sub 0.6}Te{sub 0.4} based conductive bridge random access memory (CBRAM) cells. Carbon alloying of copper-tellurium inhibits the crystallization, while attractive switching behavior is preserved when using the material as Cu-supply layer in CBRAM cells. The phase formation is first investigated in a combinatorial way. With increasing carbon content, an enlargement of the temperature window in which the material stays amorphous was observed. Moreover, if crystalline phases are formed, subsequent phase transformations are inhibited. The electrical switching behavior of memory cells with different carbon contents is then investigated by implementing them in 580 μm diameter dot TiN/Cu{sub 0.6}Te{sub 0.4}-C/Al{sub 2}O{sub 3}/Si memory cells. Reliable switching behavior is observed for carbon contents up to 40 at. %, with a resistive window of more than 2 orders of magnitude, whereas for 50 at. % carbon, a higher current in the off state and only a small resistive window are present after repeated cycling. This degradation can be ascribed to the higher thermal and lower drift contribution to the reset operation due to a lower Cu affinity towards the supply layer, leading cycle-after-cycle to an increasing amount of Cu in the switching layer, which contributes to the current. The thermal diffusion of Cu into Al{sub 2}O{sub 3} under annealing also gives an indication of the Cu affinity of the source layer. Time of flight secondary ion mass spectroscopy was used to investigate this migration depth in Al{sub 2}O{sub 3} before and after annealing, showing a higher Cu, Te, and C migration for high carbon contents.

  5. Effect of annealing treatment on the electrical characteristics of Pt/Cr-embedded ZnO/Pt resistance random access memory devices

    SciTech Connect (OSTI)

    Chang, Li-Chun; Kao, Hsuan-Ling; Liu, Keng-Hao

    2014-03-15

    ZnO/Cr/ZnO trilayer films sandwiched with Pt electrodes were prepared for nonvolatile resistive memory applications. The threshold voltage of a ZnO device embedded with a 3-nm Cr interlayer was approximately 50% lower than that of a ZnO monolayer device. This study investigated threshold voltage as a function of Cr thickness. Both the ZnO monolayer device and the Cr-embedded ZnO device structures exhibited resistance switching under electrical bias both before and after rapid thermal annealing (RTA) treatment, but resistive switching effects in the two cases exhibited distinct characteristics. Compared with the as-fabricated device, the memory cell after RTA demonstrated remarkable device parameter improvements, including a lower threshold voltage, a lower write current, and a higher R{sub off}/R{sub on} ratio. Both transmission electron microscope observations and Auger electron spectroscopy revealed that the Cr charge trapping layer in Cr-embedded ZnO dispersed uniformly into the storage medium after RTA, and x-ray diffraction and x-ray photoelectron spectroscopy analyses demonstrated that the Cr atoms lost electrons to become Cr{sup 3+} ions after dispersion. These results indicated that the altered status of Cr in ZnO/Cr/ZnO trilayer films during RTA treatment was responsible for the switching mechanism transition.

  6. Direct memory access transfer completion notification

    DOE Patents [OSTI]

    Chen, Dong; Giampapa, Mark E.; Heidelberger, Philip; Kumar, Sameer; Parker, Jeffrey J.; Steinmacher-Burow, Burkhard D.; Vranas, Pavlos

    2010-07-27

    Methods, compute nodes, and computer program products are provided for direct memory access (`DMA`) transfer completion notification. Embodiments include determining, by an origin DMA engine on an origin compute node, whether a data descriptor for an application message to be sent to a target compute node is currently in an injection first-in-first-out (`FIFO`) buffer in dependence upon a sequence number previously associated with the data descriptor, the total number of descriptors currently in the injection FIFO buffer, and the current sequence number for the newest data descriptor stored in the injection FIFO buffer; and notifying a processor core on the origin DMA engine that the message has been sent if the data descriptor for the message is not currently in the injection FIFO buffer.

  7. Remote direct memory access over datagrams

    SciTech Connect (OSTI)

    Grant, Ryan Eric; Rashti, Mohammad Javad; Balaji, Pavan; Afsahi, Ahmad

    2014-12-02

    A communication stack for providing remote direct memory access (RDMA) over a datagram network is disclosed. The communication stack has a user level interface configured to accept datagram related input and communicate with an RDMA enabled network interface card (NIC) via an NIC driver. The communication stack also has an RDMA protocol layer configured to supply one or more data transfer primitives for the datagram related input of the user level. The communication stack further has a direct data placement (DDP) layer configured to transfer the datagram related input from a user storage to a transport layer based on the one or more data transfer primitives by way of a lower layer protocol (LLP) over the datagram network.

  8. Generation-based memory synchronization in a multiprocessor system with weakly consistent memory accesses

    SciTech Connect (OSTI)

    Ohmacht, Martin

    2014-09-09

    In a multiprocessor system, a central memory synchronization module coordinates memory synchronization requests responsive to memory access requests in flight, a generation counter, and a reclaim pointer. The central module communicates via point-to-point communication. The module includes a global OR reduce tree for each memory access requesting device, for detecting memory access requests in flight. An interface unit is implemented associated with each processor requesting synchronization. The interface unit includes multiple generation completion detectors. The generation count and reclaim pointer do not pass one another.

  9. 2015 Salishan Random Access (Conference) | SciTech Connect

    Office of Scientific and Technical Information (OSTI)

    Title: 2015 Salishan Random Access Authors: Vigil, Benny Manuel 1 ; Mattson, Tim 2 ; Coteus, Paul 3 ; Lucas, Bob 4 ; Michalak, Sarah 1 ; Choi, Sung-Eun 5 ; Mountain, ...

  10. Direct access inter-process shared memory

    DOE Patents [OSTI]

    Brightwell, Ronald B; Pedretti, Kevin; Hudson, Trammell B

    2013-10-22

    A technique for directly sharing physical memory between processes executing on processor cores is described. The technique includes loading a plurality of processes into the physical memory for execution on a corresponding plurality of processor cores sharing the physical memory. An address space is mapped to each of the processes by populating a first entry in a top level virtual address table for each of the processes. The address space of each of the processes is cross-mapped into each of the processes by populating one or more subsequent entries of the top level virtual address table with the first entry in the top level virtual address table from other processes.

  11. Fencing direct memory access data transfers in a parallel active messaging interface of a parallel computer

    DOE Patents [OSTI]

    Blocksome, Michael A.; Mamidala, Amith R.

    2013-09-03

    Fencing direct memory access (`DMA`) data transfers in a parallel active messaging interface (`PAMI`) of a parallel computer, the PAMI including data communications endpoints, each endpoint including specifications of a client, a context, and a task, the endpoints coupled for data communications through the PAMI and through DMA controllers operatively coupled to segments of shared random access memory through which the DMA controllers deliver data communications deterministically, including initiating execution through the PAMI of an ordered sequence of active DMA instructions for DMA data transfers between two endpoints, effecting deterministic DMA data transfers through a DMA controller and a segment of shared memory; and executing through the PAMI, with no FENCE accounting for DMA data transfers, an active FENCE instruction, the FENCE instruction completing execution only after completion of all DMA instructions initiated prior to execution of the FENCE instruction for DMA data transfers between the two endpoints.

  12. Fencing direct memory access data transfers in a parallel active messaging interface of a parallel computer

    DOE Patents [OSTI]

    Blocksome, Michael A; Mamidala, Amith R

    2014-02-11

    Fencing direct memory access (`DMA`) data transfers in a parallel active messaging interface (`PAMI`) of a parallel computer, the PAMI including data communications endpoints, each endpoint including specifications of a client, a context, and a task, the endpoints coupled for data communications through the PAMI and through DMA controllers operatively coupled to segments of shared random access memory through which the DMA controllers deliver data communications deterministically, including initiating execution through the PAMI of an ordered sequence of active DMA instructions for DMA data transfers between two endpoints, effecting deterministic DMA data transfers through a DMA controller and a segment of shared memory; and executing through the PAMI, with no FENCE accounting for DMA data transfers, an active FENCE instruction, the FENCE instruction completing execution only after completion of all DMA instructions initiated prior to execution of the FENCE instruction for DMA data transfers between the two endpoints.

  13. Direct memory access transfer completion notification

    DOE Patents [OSTI]

    Archer, Charles J.; Blocksome, Michael A.; Parker, Jeffrey J.

    2011-02-15

    DMA transfer completion notification includes: inserting, by an origin DMA engine on an origin node in an injection first-in-first-out (`FIFO`) buffer, a data descriptor for an application message to be transferred to a target node on behalf of an application on the origin node; inserting, by the origin DMA engine, a completion notification descriptor in the injection FIFO buffer after the data descriptor for the message, the completion notification descriptor specifying a packet header for a completion notification packet; transferring, by the origin DMA engine to the target node, the message in dependence upon the data descriptor; sending, by the origin DMA engine, the completion notification packet to a local reception FIFO buffer using a local memory FIFO transfer operation; and notifying, by the origin DMA engine, the application that transfer of the message is complete in response to receiving the completion notification packet in the local reception FIFO buffer.

  14. Kokkos: Enabling manycore performance portability through polymorphic memory access patterns

    SciTech Connect (OSTI)

    Carter Edwards, H.; Trott, Christian R.; Sunderland, Daniel

    2014-07-22

    The manycore revolution can be characterized by increasing thread counts, decreasing memory per thread, and diversity of continually evolving manycore architectures. High performance computing (HPC) applications and libraries must exploit increasingly finer levels of parallelism within their codes to sustain scalability on these devices. We found that a major obstacle to performance portability is the diverse and conflicting set of constraints on memory access patterns across devices. Contemporary portable programming models address manycore parallelism (e.g., OpenMP, OpenACC, OpenCL) but fail to address memory access patterns. The Kokkos C++ library enables applications and domain libraries to achieve performance portability on diverse manycore architectures by unifying abstractions for both fine-grain data parallelism and memory access patterns. In this paper we describe Kokkos’ abstractions, summarize its application programmer interface (API), present performance results for unit-test kernels and mini-applications, and outline an incremental strategy for migrating legacy C++ codes to Kokkos. Furthermore, the Kokkos library is under active research and development to incorporate capabilities from new generations of manycore architectures, and to address a growing list of applications and domain libraries.

  15. Kokkos: Enabling manycore performance portability through polymorphic memory access patterns

    DOE Public Access Gateway for Energy & Science Beta (PAGES Beta)

    Carter Edwards, H.; Trott, Christian R.; Sunderland, Daniel

    2014-07-22

    The manycore revolution can be characterized by increasing thread counts, decreasing memory per thread, and diversity of continually evolving manycore architectures. High performance computing (HPC) applications and libraries must exploit increasingly finer levels of parallelism within their codes to sustain scalability on these devices. We found that a major obstacle to performance portability is the diverse and conflicting set of constraints on memory access patterns across devices. Contemporary portable programming models address manycore parallelism (e.g., OpenMP, OpenACC, OpenCL) but fail to address memory access patterns. The Kokkos C++ library enables applications and domain libraries to achieve performance portability on diversemore » manycore architectures by unifying abstractions for both fine-grain data parallelism and memory access patterns. In this paper we describe Kokkos’ abstractions, summarize its application programmer interface (API), present performance results for unit-test kernels and mini-applications, and outline an incremental strategy for migrating legacy C++ codes to Kokkos. Furthermore, the Kokkos library is under active research and development to incorporate capabilities from new generations of manycore architectures, and to address a growing list of applications and domain libraries.« less

  16. Administering an epoch initiated for remote memory access

    DOE Patents [OSTI]

    Blocksome, Michael A.; Miller, Douglas R.

    2013-01-01

    Methods, systems, and products are disclosed for administering an epoch initiated for remote memory access that include: initiating, by an origin application messaging module on an origin compute node, one or more data transfers to a target compute node for the epoch; initiating, by the origin application messaging module after initiating the data transfers, a closing stage for the epoch, including rejecting any new data transfers after initiating the closing stage for the epoch; determining, by the origin application messaging module, whether the data transfers have completed; and closing, by the origin application messaging module, the epoch if the data transfers have completed.

  17. Administering an epoch initiated for remote memory access

    DOE Patents [OSTI]

    Blocksome, Michael A; Miller, Douglas R

    2012-10-23

    Methods, systems, and products are disclosed for administering an epoch initiated for remote memory access that include: initiating, by an origin application messaging module on an origin compute node, one or more data transfers to a target compute node for the epoch; initiating, by the origin application messaging module after initiating the data transfers, a closing stage for the epoch, including rejecting any new data transfers after initiating the closing stage for the epoch; determining, by the origin application messaging module, whether the data transfers have completed; and closing, by the origin application messaging module, the epoch if the data transfers have completed.

  18. Administering an epoch initiated for remote memory access

    SciTech Connect (OSTI)

    Blocksome, Michael A; Miller, Douglas R

    2014-03-18

    Methods, systems, and products are disclosed for administering an epoch initiated for remote memory access that include: initiating, by an origin application messaging module on an origin compute node, one or more data transfers to a target compute node for the epoch; initiating, by the origin application messaging module after initiating the data transfers, a closing stage for the epoch, including rejecting any new data transfers after initiating the closing stage for the epoch; determining, by the origin application messaging module, whether the data transfers have completed; and closing, by the origin application messaging module, the epoch if the data transfers have completed.

  19. Efficient Memory Access with NumPy Global Arrays using Local Memory Access

    SciTech Connect (OSTI)

    Daily, Jeffrey A.; Berghofer, Dan C.

    2013-08-03

    This paper discusses the work completed working with Global Arrays of data on distributed multi-computer systems and improving their performance. The tasks completed were done at Pacific Northwest National Laboratory in the Science Undergrad Laboratory Internship program in the summer of 2013 for the Data Intensive Computing Group in the Fundamental and Computational Sciences DIrectorate. This work was done on the Global Arrays Toolkit developed by this group. This toolkit is an interface for programmers to more easily create arrays of data on networks of computers. This is useful because scientific computation is often done on large amounts of data sometimes so large that individual computers cannot hold all of it. This data is held in array form and can best be processed on supercomputers which often consist of a network of individual computers doing their computation in parallel. One major challenge for this sort of programming is that operations on arrays on multiple computers is very complex and an interface is needed so that these arrays seem like they are on a single computer. This is what global arrays does. The work done here is to use more efficient operations on that data that requires less copying of data to be completed. This saves a lot of time because copying data on many different computers is time intensive. The way this challenge was solved is when data to be operated on with binary operations are on the same computer, they are not copied when they are accessed. When they are on separate computers, only one set is copied when accessed. This saves time because of less copying done although more data access operations were done.

  20. Mapping virtual addresses to different physical addresses for value disambiguation for thread memory access requests

    SciTech Connect (OSTI)

    Gala, Alan; Ohmacht, Martin

    2014-09-02

    A multiprocessor system includes nodes. Each node includes a data path that includes a core, a TLB, and a first level cache implementing disambiguation. The system also includes at least one second level cache and a main memory. For thread memory access requests, the core uses an address associated with an instruction format of the core. The first level cache uses an address format related to the size of the main memory plus an offset corresponding to hardware thread meta data. The second level cache uses a physical main memory address plus software thread meta data to store the memory access request. The second level cache accesses the main memory using the physical address with neither the offset nor the thread meta data after resolving speculation. In short, this system includes mapping of a virtual address to a different physical addresses for value disambiguation for different threads.

  1. Spin-Hall-assisted magnetic random access memory (Journal Article...

    Office of Scientific and Technical Information (OSTI)

    OSTI Identifier: 22257135 Resource Type: Journal Article Resource Relation: Journal Name: Applied Physics Letters; Journal Volume: 104; Journal Issue: 1; Other Information: (c) ...

  2. Accessibility

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Web Policies Accessibility Accessibility LANL places a high degree of emphasis on user ... Contact Web Team Email Reaching the broadest possible audience Los Alamos National ...

  3. Accessibility

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    is committed to providing access to our Web pages for individuals with disabilities. To meet this commitment, this site is built to comply with the requirements of...

  4. Fencing network direct memory access data transfers in a parallel active messaging interface of a parallel computer

    DOE Patents [OSTI]

    Blocksome, Michael A.; Mamidala, Amith R.

    2015-07-07

    Fencing direct memory access (`DMA`) data transfers in a parallel active messaging interface (`PAMI`) of a parallel computer, the PAMI including data communications endpoints, each endpoint including specifications of a client, a context, and a task, the endpoints coupled for data communications through the PAMI and through DMA controllers operatively coupled to a deterministic data communications network through which the DMA controllers deliver data communications deterministically, including initiating execution through the PAMI of an ordered sequence of active DMA instructions for DMA data transfers between two endpoints, effecting deterministic DMA data transfers through a DMA controller and the deterministic data communications network; and executing through the PAMI, with no FENCE accounting for DMA data transfers, an active FENCE instruction, the FENCE instruction completing execution only after completion of all DMA instructions initiated prior to execution of the FENCE instruction for DMA data transfers between the two endpoints.

  5. Fencing network direct memory access data transfers in a parallel active messaging interface of a parallel computer

    DOE Patents [OSTI]

    Blocksome, Michael A.; Mamidala, Amith R.

    2015-07-14

    Fencing direct memory access (`DMA`) data transfers in a parallel active messaging interface (`PAMI`) of a parallel computer, the PAMI including data communications endpoints, each endpoint including specifications of a client, a context, and a task, the endpoints coupled for data communications through the PAMI and through DMA controllers operatively coupled to a deterministic data communications network through which the DMA controllers deliver data communications deterministically, including initiating execution through the PAMI of an ordered sequence of active DMA instructions for DMA data transfers between two endpoints, effecting deterministic DMA data transfers through a DMA controller and the deterministic data communications network; and executing through the PAMI, with no FENCE accounting for DMA data transfers, an active FENCE instruction, the FENCE instruction completing execution only after completion of all DMA instructions initiated prior to execution of the FENCE instruction for DMA data transfers between the two endpoints.

  6. Livermore Random I/O Testbench

    Energy Science and Technology Software Center (OSTI)

    2012-09-01

    LRIOT is a test bench framework that is designed to generate sophisticated I/O rates that can stress high-performance memory and storage systems, such as non-volatile random access memories (NVRAM)and storage class memory. Furthermore, LRIOT provides the capabilities to mix multiple types of concurrency, namely threading and task parallelism, as well as distributed execution using Message Passing Interface (MPI) libraries. It will be used by algorithm designers to generate access patterns that mimic their application's behavior,more » and by system designers to test high-performance NVRAM storage.« less

  7. Data-Intensive Memory-Map simulator and runtime

    Energy Science and Technology Software Center (OSTI)

    2012-05-01

    DI-MMAP is a simulator for modeling the performance of next generation non-volatile random access memory technologies (NVRAM) and a high-perfromance memory-map runtime for the Linux operating system. It is implemented as a device driver for the Linux operating system. It will be used by algorithm designers to unserstand the impact of future NVRAM on their algorithms and will be used by application developers for high-performance access to NVRAM storage.

  8. Magnetic Random Access Memory based non-volatile asynchronous Muller cell for ultra-low power autonomous applications

    SciTech Connect (OSTI)

    Di Pendina, G. E-mail: eldar.zianbetov@cea.fr Zianbetov, E. E-mail: eldar.zianbetov@cea.fr; Beigne, E. E-mail: eldar.zianbetov@cea.fr

    2015-05-07

    Micro and nano electronic integrated circuit domain is today mainly driven by the advent of the Internet of Things for which the constraints are strong, especially in terms of power consumption and autonomy, not only during the computing phases but also during the standby or idle phases. In such ultra-low power applications, the circuit has to meet new constraints mainly linked to its changing energetic environment: long idle phases, automatic wake up, data back-up when the circuit is sporadically turned off, and ultra-low voltage power supply operation. Such circuits have to be completely autonomous regarding their unstable environment, while remaining in an optimum energetic configuration. Therefore, we propose in this paper the first MRAM-based non-volatile asynchronous Muller cell. This cell has been simulated and characterized in a very advanced 28?nm CMOS fully depleted silicon-on-insulator technology, presenting good power performance results due to an extremely efficient body biasing control together with ultra-wide supply voltage range from 160?mV up to 920?mV. The leakage current can be reduced to 154?pA thanks to reverse body biasing. We also propose an efficient standard CMOS bulk version of this cell in order to be compatible with different fabrication processes.

  9. Structural changes and conductance thresholds in metal-free intrinsic SiO{sub x} resistive random access memory

    SciTech Connect (OSTI)

    Mehonic, Adnan E-mail: t.kenyon@ucl.ac.uk; Buckwell, Mark; Montesi, Luca; Garnett, Leon; Hudziak, Stephen; Kenyon, Anthony J. E-mail: t.kenyon@ucl.ac.uk; Fearn, Sarah; Chater, Richard; McPhail, David

    2015-03-28

    We present an investigation of structural changes in silicon-rich silicon oxide metal-insulator-metal resistive RAM devices. The observed unipolar switching, which is intrinsic to the bulk oxide material and does not involve movement of metal ions, correlates with changes in the structure of the oxide. We use atomic force microscopy, conductive atomic force microscopy, x-ray photoelectron spectroscopy, and secondary ion mass spectroscopy to examine the structural changes occurring as a result of switching. We confirm that protrusions formed at the surface of samples during switching are bubbles, which are likely to be related to the outdiffusion of oxygen. This supports existing models for valence-change based resistive switching in oxides. In addition, we describe parallel linear and nonlinear conduction pathways and suggest that the conductance quantum, G{sub 0}, is a natural boundary between the high and low resistance states of our devices.

  10. Memory Considerations

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Memory Considerations Memory Considerations Memory Usage Considerations on Franklin Each Franklin compute node has 8 GB (8192 MB) of physical memory, but, not all that memory is...

  11. Memory Considerations

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Memory Considerations Memory Considerations Memory Usage Considerations on Hopper Most Hopper compute nodes have 32 GB of physical memory, but, not all that memory is available to...

  12. System for loading executable code into volatile memory in a downhole tool

    DOE Patents [OSTI]

    Hall, David R.; Bartholomew, David B.; Johnson, Monte L.

    2007-09-25

    A system for loading an executable code into volatile memory in a downhole tool string component comprises a surface control unit comprising executable code. An integrated downhole network comprises data transmission elements in communication with the surface control unit and the volatile memory. The executable code, stored in the surface control unit, is not permanently stored in the downhole tool string component. In a preferred embodiment of the present invention, the downhole tool string component comprises boot memory. In another embodiment, the executable code is an operating system executable code. Preferably, the volatile memory comprises random access memory (RAM). A method for loading executable code to volatile memory in a downhole tool string component comprises sending the code from the surface control unit to a processor in the downhole tool string component over the network. A central processing unit writes the executable code in the volatile memory.

  13. Shape memory polymers (Patent) | DOEPatents

    Office of Scientific and Technical Information (OSTI)

    polymers Title: Shape memory polymers You are accessing a document from the Department ... Sponsoring Org: USDOE Country of Publication: United States Language: English Subject: 36 ...

  14. Post-Polymerization Crosslinked Polyurethane Shape-Memory Polymers...

    Office of Scientific and Technical Information (OSTI)

    Crosslinked Polyurethane Shape-Memory Polymers Citation Details In-Document Search Title: Post-Polymerization Crosslinked Polyurethane Shape-Memory Polymers You are accessing a ...

  15. Ultra Low Density Amorphous Shape Memory polymer Foams. (Conference...

    Office of Scientific and Technical Information (OSTI)

    Ultra Low Density Amorphous Shape Memory polymer Foams. Citation Details In-Document Search Title: Ultra Low Density Amorphous Shape Memory polymer Foams. You are accessing a ...

  16. Shape Memory Polymer Therapeutic Devices for Stroke (Conference...

    Office of Scientific and Technical Information (OSTI)

    Shape Memory Polymer Therapeutic Devices for Stroke Citation Details In-Document Search Title: Shape Memory Polymer Therapeutic Devices for Stroke You are accessing a document ...

  17. Ferroelectric tunneling element and memory applications which utilize the tunneling element

    DOE Patents [OSTI]

    Kalinin, Sergei V. [Knoxville, TN; Christen, Hans M. [Knoxville, TN; Baddorf, Arthur P. [Knoxville, TN; Meunier, Vincent [Knoxville, TN; Lee, Ho Nyung [Oak Ridge, TN

    2010-07-20

    A tunneling element includes a thin film layer of ferroelectric material and a pair of dissimilar electrically-conductive layers disposed on opposite sides of the ferroelectric layer. Because of the dissimilarity in composition or construction between the electrically-conductive layers, the electron transport behavior of the electrically-conductive layers is polarization dependent when the tunneling element is below the Curie temperature of the layer of ferroelectric material. The element can be used as a basis of compact 1R type non-volatile random access memory (RAM). The advantages include extremely simple architecture, ultimate scalability and fast access times generic for all ferroelectric memories.

  18. RTDB: A memory resident real-time object database

    SciTech Connect (OSTI)

    Jerzy M. Nogiec; Eugene Desavouret

    2003-06-04

    RTDB is a fast, memory-resident object database with built-in support for distribution. It constitutes an attractive alternative for architecting real-time solutions with multiple, possibly distributed, processes or agents sharing data. RTDB offers both direct and navigational access to stored objects, with local and remote random access by object identifiers, and immediate direct access via object indices. The database supports transparent access to objects stored in multiple collaborating dispersed databases and includes a built-in cache mechanism that allows for keeping local copies of remote objects, with specifiable invalidation deadlines. Additional features of RTDB include a trigger mechanism on objects that allows for issuing events or activating handlers when objects are accessed or modified and a very fast, attribute based search/query mechanism. The overall architecture and application of RTDB in a control and monitoring system is presented.

  19. Memory Considerations

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Memory Considerations Memory Considerations Memory Usage Considerations on Edison Edison compute nodes have 64 GB of physical memory (2.67GB per core), but not all the memory is available to user programs. Compute Node Linux (the kernel), the Lustre file system software, and message passing library buffers all consume memory, as does loading the executable into the memory. Thus the precise memory available to an application varies. Approximately 61 GB of memory can be allocated from within an

  20. Memory Considerations

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Memory Considerations Memory Considerations Memory Usage Considerations on Franklin Each Franklin compute node has 8 GB (8192 MB) of physical memory, but, not all that memory is available to user programs. Compute Node Linux (the kernel), the Lustre file system software, and message passing library buffers all consume memory, as does loading the executable into memory. Thus the precise memory available to an application varies, approximately 7566 MB (7.38 GB) of memory can be allocated from

  1. Memory Considerations

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Memory Considerations Memory Considerations Memory Usage Considerations on Hopper Most Hopper compute nodes have 32 GB of physical memory, but, not all that memory is available to user programs. Compute Node Linux (the kernel), the Lustre file system software, and message passing library buffers all consume memory, as does loading the executable into memory. Thus the precise memory available to an application varies. Approximately 31 GB of memory can be allocated from within an MPI program using

  2. Mechanical memory

    DOE Patents [OSTI]

    Gilkey, Jeffrey C.; Duesterhaus, Michelle A.; Peter, Frank J.; Renn, Rosemarie A.; Baker, Michael S.

    2006-08-15

    A first-in-first-out (FIFO) microelectromechanical memory apparatus (also termed a mechanical memory) is disclosed. The mechanical memory utilizes a plurality of memory cells, with each memory cell having a beam which can be bowed in either of two directions of curvature to indicate two different logic states for that memory cell. The memory cells can be arranged around a wheel which operates as a clocking actuator to serially shift data from one memory cell to the next. The mechanical memory can be formed using conventional surface micromachining, and can be formed as either a nonvolatile memory or as a volatile memory.

  3. Mechanical memory

    DOE Patents [OSTI]

    Gilkey, Jeffrey C.; Duesterhaus, Michelle A.; Peter, Frank J.; Renn, Rosemarie A.; Baker, Michael S.

    2006-05-16

    A first-in-first-out (FIFO) microelectromechanical memory apparatus (also termed a mechanical memory) is disclosed. The mechanical memory utilizes a plurality of memory cells, with each memory cell having a beam which can be bowed in either of two directions of curvature to indicate two different logic states for that memory cell. The memory cells can be arranged around a wheel which operates as a clocking actuator to serially shift data from one memory cell to the next. The mechanical memory can be formed using conventional surface micromachining, and can be formed as either a nonvolatile memory or as a volatile memory.

  4. Memory Considerations

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Memory Considerations Memory Considerations Overview Carver login nodes each have 48GB of ... Furthermore, since Carver nodes have no disk, the "root" file system (including tmp) is ...

  5. Memory Considerations

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Memory Considerations Memory Considerations Overview Carver login nodes each have 48GB of physical memory. Most compute nodes have 24GB; however, 80 compute nodes have 48GB. Not all of this memory is available to user processes. Some memory is reserved for the Linux kernel. Furthermore, since Carver nodes have no disk, the "root" file system (including /tmp) is kept in memory ("ramdisk"). The kernel and root file system combined occupy about 4GB of memory. Therefore users

  6. Controlling the Actuation Rate of Low Density Shape Memory Polymer...

    Office of Scientific and Technical Information (OSTI)

    Memory Polymer Foams in Water Citation Details In-Document Search Title: Controlling the Actuation Rate of Low Density Shape Memory Polymer Foams in Water You are accessing a ...

  7. Open Access

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    access, is a type of unrestricted access to scholarly publications that is online, free of charge to everyone and free of most copyright and licensing restrictions. Open...

  8. Direct memory access transfer completion notification

    DOE Patents [OSTI]

    Archer, Charles J. , Blocksome; Michael A. , Parker; Jeffrey J.

    2011-02-15

    Methods, systems, and products are disclosed for DMA transfer completion notification that include: inserting, by an origin DMA on an origin node in an origin injection FIFO, a data descriptor for an application message; inserting, by the origin DMA, a reflection descriptor in the origin injection FIFO, the reflection descriptor specifying a remote get operation for injecting a completion notification descriptor in a reflection injection FIFO on a reflection node; transferring, by the origin DMA to a target node, the message in dependence upon the data descriptor; in response to completing the message transfer, transferring, by the origin DMA to the reflection node, the completion notification descriptor in dependence upon the reflection descriptor; receiving, by the origin DMA from the reflection node, a completion packet; and notifying, by the origin DMA in response to receiving the completion packet, the origin node's processing core that the message transfer is complete.

  9. Direct memory access transfer completion notification

    DOE Patents [OSTI]

    Archer, Charles J.; Blocksome, Michael A.; Parker, Jeffrey J.

    2010-08-17

    Methods, apparatus, and products are disclosed for DMA transfer completion notification that include: inserting, by an origin DMA engine on an origin compute node in an injection FIFO buffer, a data descriptor for an application message to be transferred to a target compute node on behalf of an application on the origin compute node; inserting, by the origin DMA engine, a completion notification descriptor in the injection FIFO buffer after the data descriptor for the message, the completion notification descriptor specifying an address of a completion notification field in application storage for the application; transferring, by the origin DMA engine to the target compute node, the message in dependence upon the data descriptor; and notifying, by the origin DMA engine, the application that the transfer of the message is complete, including performing a local direct put operation to store predesignated notification data at the address of the completion notification field.

  10. Remote Access

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Remote Access Remote Access Laboratory employees can access Research Library databases and products from offsite using our EZproxy service. This service is limited to LANL employees with active Z numbers and cryptocards. Access Electronic Collections with EZproxy Remote Access Journals - Books - Standards - Databases (WOK, etc) How to use EZproxy: From this page: Click on the icon above. From external site: Select "OFFSITE LANL Employee". Enter your Z number and Cryptocard passcode.

  11. RandomAccessECI_Final.pptx

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Impact o f E CI o n D OE C o---design S trategies James A . A ng, P h.D., M anager Scalable C omputer A rchitectures The S alishan C onference o n H igh S peed C ompuCng Gleneden B...

  12. Memory-bit selection and recording by rotating fields in vortex-core cross-point architecture

    SciTech Connect (OSTI)

    Yu, Y. -S.; Jung, H.; Lee, K. -S.; Fischer, P.; Kim, S. -K.

    2010-10-21

    In one of our earlier studies [Appl. Phys. Lett. 92, 022509 (2008)], we proposed a concept of robust information storage, recording and readout, which can be implementaed in nonvolatile magnetic random-access memories and is based on the energetically degenerated twofold ground states of vortex-core magnetizations. In the present study, we experimentally demonstrate reliable memory-bit selection and information recording in vortex-core cross-point architecture, specifically using a two-by-two vortex-state disk array. In order to efficiently switch a vortex core positioned at the intersection of crossed electrodes, two orthogonal addressing electrodes are selected, and then two Gaussian pulse currents of optimal pulse width and time delay are applied. Such tailored pulse-type rotating magnetic fields which occurs only at the selected intersection is prerequisite for a reliable memory-bit selection and low-power-consumption recording of information in the existing cross-point architecture.

  13. System and method for programmable bank selection for banked memory subsystems

    DOE Patents [OSTI]

    Blumrich, Matthias A.; Chen, Dong; Gara, Alan G.; Giampapa, Mark E.; Hoenicke, Dirk; Ohmacht, Martin; Salapura, Valentina; Sugavanam, Krishnan

    2010-09-07

    A programmable memory system and method for enabling one or more processor devices access to shared memory in a computing environment, the shared memory including one or more memory storage structures having addressable locations for storing data. The system comprises: one or more first logic devices associated with a respective one or more processor devices, each first logic device for receiving physical memory address signals and programmable for generating a respective memory storage structure select signal upon receipt of pre-determined address bit values at selected physical memory address bit locations; and, a second logic device responsive to each of the respective select signal for generating an address signal used for selecting a memory storage structure for processor access. The system thus enables each processor device of a computing environment memory storage access distributed across the one or more memory storage structures.

  14. V-194: Citrix XenServer Memory Management Error Lets Local Administrat...

    Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

    XenServer Memory Management Error Lets Local Administrative Users on the Guest Gain Access on the Host V-194: Citrix XenServer Memory Management Error Lets Local Administrative...

  15. Accessibility | NREL

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    making its electronic and information technologies accessible to individuals with disabilities in accordance with Section 508 of the Rehabilitation Act (29 U.S.C. 794d), as...

  16. Accessing HPSS

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Accessing HPSS Accessing HPSS Once you have successfully generated an HPSS token you can access NERSC's HPSS in the different ways listed below. HSI and HTAR are usually the best ways to transfer data in and out of HPSS but other methods are also included. Access Method When to use this method Features Limitations HSI When a full-featured unix-like interface is desired high performance (parallel); unix-like user interface; firewall mode client is specific to HPSS version and might not work at

  17. Accessing PDSF

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Accessing PDSF Accessing PDSF All the linux interactive nodes are known under the name of pdsf.nersc.gov and should be accessed via that name. To access them the ssh protocol should be used and you should make sure that a Keyboard Interactive method is available in your ssh client. You will probably also want to enable X11 forwarding with the -X or -Y option, i.e., ssh -Y pdsf.nersc.gov For more information see Interactive (login) Nodes. If you are in STAR your default unix group is rhstar (just

  18. Gate Access

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Gate Access Gate Access Print When you first arrive at the ALS, gate clearance will have been arranged for you by the User Office. Berkeley Lab employees and visiting researchers (participating guests) may arrange for gate clearance for their visitors through the Lab's Site Access Office . Please notify the Site Office by submitting a Visitor Pass Request before 3:00 p.m. on the day before the expected visit. Include the name(s) of any visitors, the time you expect them, and your name and

  19. Disorder-Induced Microscopic Magnetic Memory

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Disorder-Induced Microscopic Magnetic Memory Disorder-Induced Microscopic Magnetic Memory Print Wednesday, 26 October 2005 00:00 The magnetic-recording industry deliberately introduces carefully controlled disorder into its materials to obtain the desired magnetic properties. But as the density of magnetic disks climbs, the size of the magnetic domains responsible for storage must decrease, posing new challenges. Beautiful theories based on random microscopic disorder have been developed over

  20. Adiabatic quantum optimization for associative memory recall

    SciTech Connect (OSTI)

    Seddiqi, Hadayat; Humble, Travis S.

    2014-12-22

    Hopfield networks are a variant of associative memory that recall patterns stored in the couplings of an Ising model. Stored memories are conventionally accessed as fixed points in the network dynamics that correspond to energetic minima of the spin state. We show that memories stored in a Hopfield network may also be recalled by energy minimization using adiabatic quantum optimization (AQO). Numerical simulations of the underlying quantum dynamics allow us to quantify AQO recall accuracy with respect to the number of stored memories and noise in the input key. We investigate AQO performance with respect to how memories are stored in the Ising model according to different learning rules. Our results demonstrate that AQO recall accuracy varies strongly with learning rule, a behavior that is attributed to differences in energy landscapes. Consequently, learning rules offer a family of methods for programming adiabatic quantum optimization that we expect to be useful for characterizing AQO performance.

  1. Adiabatic quantum optimization for associative memory recall

    DOE Public Access Gateway for Energy & Science Beta (PAGES Beta)

    Seddiqi, Hadayat; Humble, Travis S.

    2014-12-22

    Hopfield networks are a variant of associative memory that recall patterns stored in the couplings of an Ising model. Stored memories are conventionally accessed as fixed points in the network dynamics that correspond to energetic minima of the spin state. We show that memories stored in a Hopfield network may also be recalled by energy minimization using adiabatic quantum optimization (AQO). Numerical simulations of the underlying quantum dynamics allow us to quantify AQO recall accuracy with respect to the number of stored memories and noise in the input key. We investigate AQO performance with respect to how memories are storedmore » in the Ising model according to different learning rules. Our results demonstrate that AQO recall accuracy varies strongly with learning rule, a behavior that is attributed to differences in energy landscapes. Consequently, learning rules offer a family of methods for programming adiabatic quantum optimization that we expect to be useful for characterizing AQO performance.« less

  2. Gate Access

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    to the laboratory. Visitors from outside the U.S. should be prepared to show a valid passport. See Access to the ALS for additional information about visitor procedures at the...

  3. Genepool Memory Heatmaps

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Genepool Memory Heatmaps Heatmap of Memory and Slots Requested vs Time Waited (in hours) | Queue: All | Last 7 Days Memory Requested Slots <5GB 5-10GB 10-20GB 20-30GB 30-40GB...

  4. Large N (=3) Neutrinos and Random Matrix Theory (Journal Article...

    Office of Scientific and Technical Information (OSTI)

    Journal Article: Large N (3) Neutrinos and Random Matrix Theory Citation Details In-Document Search Title: Large N (3) Neutrinos and Random Matrix Theory You are accessing a ...

  5. Optical memory

    DOE Patents [OSTI]

    Mao, Samuel S; Zhang, Yanfeng

    2013-07-02

    Optical memory comprising: a semiconductor wire, a first electrode, a second electrode, a light source, a means for producing a first voltage at the first electrode, a means for producing a second voltage at the second electrode, and a means for determining the presence of an electrical voltage across the first electrode and the second electrode exceeding a predefined voltage. The first voltage, preferably less than 0 volts, different from said second voltage. The semiconductor wire is optically transparent and has a bandgap less than the energy produced by the light source. The light source is optically connected to the semiconductor wire. The first electrode and the second electrode are electrically insulated from each other and said semiconductor wire.

  6. Conditional load and store in a shared memory

    SciTech Connect (OSTI)

    Blumrich, Matthias A; Ohmacht, Martin

    2015-02-03

    A method, system and computer program product for implementing load-reserve and store-conditional instructions in a multi-processor computing system. The computing system includes a multitude of processor units and a shared memory cache, and each of the processor units has access to the memory cache. In one embodiment, the method comprises providing the memory cache with a series of reservation registers, and storing in these registers addresses reserved in the memory cache for the processor units as a result of issuing load-reserve requests. In this embodiment, when one of the processor units makes a request to store data in the memory cache using a store-conditional request, the reservation registers are checked to determine if an address in the memory cache is reserved for that processor unit. If an address in the memory cache is reserved for that processor, the data are stored at this address.

  7. Nanopatterned ferroelectrics for ultrahigh density rad-hard nonvolatile memories.

    SciTech Connect (OSTI)

    Brennecka, Geoffrey L.; Stevens, Jeffrey; Scrymgeour, David; Gin, Aaron V.; Tuttle, Bruce Andrew

    2010-09-01

    Radiation hard nonvolatile random access memory (NVRAM) is a crucial component for DOE and DOD surveillance and defense applications. NVRAMs based upon ferroelectric materials (also known as FERAMs) are proven to work in radiation-rich environments and inherently require less power than many other NVRAM technologies. However, fabrication and integration challenges have led to state-of-the-art FERAMs still being fabricated using a 130nm process while competing phase-change memory (PRAM) has been demonstrated with a 20nm process. Use of block copolymer lithography is a promising approach to patterning at the sub-32nm scale, but is currently limited to self-assembly directly on Si or SiO{sub 2} layers. Successful integration of ferroelectrics with discrete and addressable features of {approx}15-20nm would represent a 100-fold improvement in areal memory density and would enable more highly integrated electronic devices required for systems advances. Towards this end, we have developed a technique that allows us to carry out block copolymer self-assembly directly on a huge variety of different materials and have investigated the fabrication, integration, and characterization of electroceramic materials - primarily focused on solution-derived ferroelectrics - with discrete features of {approx}20nm and below. Significant challenges remain before such techniques will be capable of fabricating fully integrated NVRAM devices, but the tools developed for this effort are already finding broader use. This report introduces the nanopatterned NVRAM device concept as a mechanism for motivating the subsequent studies, but the bulk of the document will focus on the platform and technology development.

  8. An optical simulation of shared memory

    SciTech Connect (OSTI)

    Goldberg, L.A.; Matias, Y.; Rao, S.

    1994-06-01

    We present a work-optimal randomized algorithm for simulating a shared memory machine (PRAM) on an optical communication parallel computer (OCPC). The OCPC model is motivated by the potential of optical communication for parallel computation. The memory of an OCPC is divided into modules, one module per processor. Each memory module only services a request on a timestep if it receives exactly one memory request. Our algorithm simulates each step of an n lg lg n-processor EREW PRAM on an n-processor OCPC in O(lg lg n) expected delay. (The probability that the delay is longer than this is at most n{sup {minus}{alpha}} for any constant {alpha}). The best previous simulation, due to Valiant, required {Theta}(lg n) expected delay.

  9. Aggregate Remote Memory Copy Interface

    Energy Science and Technology Software Center (OSTI)

    2006-02-23

    The purpose of the Aggregate Remote Memory Copy (ARMCI) library is to provide a general- purpose, efficient, and Widely portable remote memory access (RMA) operations (one-sided communication) optimized for Contiguous and noncontiguous (strided, scatter/gather, I/O vector) data transfers. In addition, ARMCI includes a set of atomic and mutual exclusion operations. The development ARMCI is driven by the need to support the global-addres space communication model in context of distributed regular or irregular distributed data structures,more » communication libraries, and compilers. ARMCI is a standalone system that could be used to support user-level libraries and applications that use MPI or PVM.« less

  10. Resistance controllability and variability improvement in a TaO{sub x}-based resistive memory for multilevel storage application

    SciTech Connect (OSTI)

    Prakash, A. E-mail: amit.knp02@gmail.com Song, J.; Hwang, H. E-mail: amit.knp02@gmail.com; Deleruyelle, D.; Bocquet, M.

    2015-06-08

    In order to obtain reliable multilevel cell (MLC) characteristics, resistance controllability between the different resistance levels is required especially in resistive random access memory (RRAM), which is prone to resistance variability mainly due to its intrinsic random nature of defect generation and filament formation. In this study, we have thoroughly investigated the multilevel resistance variability in a TaO{sub x}-based nanoscale (<30 nm) RRAM operated in MLC mode. It is found that the resistance variability not only depends on the conductive filament size but also is a strong function of oxygen vacancy concentration in it. Based on the gained insights through experimental observations and simulation, it is suggested that forming thinner but denser conductive filament may greatly improve the temporal resistance variability even at low operation current despite the inherent stochastic nature of resistance switching process.

  11. Extra-Large Memory Nodes

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Extra-Large Memory Nodes Extra-Large Memory Nodes Extra-Large Memory Nodes Overview Carver has two "extra-large" memory nodes; each node has four 8-core Intel X7550 ("Nehalem EX")...

  12. A Monte Carlo simulation for bipolar resistive memory switching in large band-gap oxides

    SciTech Connect (OSTI)

    Hur, Ji-Hyun E-mail: jeonsh@korea.ac.kr; Lee, Dongsoo; Jeon, Sanghun E-mail: jeonsh@korea.ac.kr

    2015-11-16

    A model that describes bilayered bipolar resistive random access memory (BL-ReRAM) switching in oxide with a large band gap is presented. It is shown that, owing to the large energy barrier between the electrode and thin oxide layer, the electronic conduction is dominated by trap-assisted tunneling. The model is composed of an atomic oxygen vacancy migration model and an electronic tunneling conduction model. We also show experimentally observed three-resistance-level switching in Ru/ZrO{sub 2}/TaO{sub x} BL-ReRAM that can be explained by the two types of traps, i.e., shallow and deep traps in ZrO{sub 2}.

  13. Measuring and Understanding Memory Bandwidth

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Measuring and Understanding Memory Bandwidth Measuring and Understanding Memory Bandwidth Measuring Bandwidth Usage Measuring memory bandwidth is a good way of understanding how well your application uses cache memory. Today's processors are constructed under the assumption that a small amount of (expensive) fast memory - called "cache" - is used more often than a larger amount of slower memory (DRAM). The extent to which this assumption applies to your code is referred to as memory

  14. zorder-lib: Library API for Z-Order Memory Layout

    SciTech Connect (OSTI)

    Nowell, Lucy; Edward W. Bethel

    2015-04-01

    This document describes the motivation for, elements of, and use of the zorder-lib, a library API that implements organization of and access to data in memory using either a-order (also known as "row-major" order) or z-order memory layouts. The primary motivation for this work is to improve the performance of many types of data- intensive codes by increasing both spatial and temporal locality of memory accesses. The basic idea is that the cost associated with accessing a datum is less when it is nearby in either space or time.

  15. Using DMA for copying performance counter data to memory

    DOE Patents [OSTI]

    Gara, Alan; Salapura, Valentina; Wisniewski, Robert W.

    2012-09-25

    A device for copying performance counter data includes hardware path that connects a direct memory access (DMA) unit to a plurality of hardware performance counters and a memory device. Software prepares an injection packet for the DMA unit to perform copying, while the software can perform other tasks. In one aspect, the software that prepares the injection packet runs on a processing core other than the core that gathers the hardware performance counter data.

  16. Using DMA for copying performance counter data to memory

    DOE Patents [OSTI]

    Gara, Alan; Salapura, Valentina; Wisniewski, Robert W

    2013-12-31

    A device for copying performance counter data includes hardware path that connects a direct memory access (DMA) unit to a plurality of hardware performance counters and a memory device. Software prepares an injection packet for the DMA unit to perform copying, while the software can perform other tasks. In one aspect, the software that prepares the injection packet runs on a processing core other than the core that gathers the hardware performance data.

  17. Disorder-Induced Microscopic Magnetic Memory

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Disorder-Induced Microscopic Magnetic Memory Print The magnetic-recording industry deliberately introduces carefully controlled disorder into its materials to obtain the desired magnetic properties. But as the density of magnetic disks climbs, the size of the magnetic domains responsible for storage must decrease, posing new challenges. Beautiful theories based on random microscopic disorder have been developed over the past ten years. To directly compare these theories with precise experiments,

  18. Disorder-Induced Microscopic Magnetic Memory

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Disorder-Induced Microscopic Magnetic Memory Print The magnetic-recording industry deliberately introduces carefully controlled disorder into its materials to obtain the desired magnetic properties. But as the density of magnetic disks climbs, the size of the magnetic domains responsible for storage must decrease, posing new challenges. Beautiful theories based on random microscopic disorder have been developed over the past ten years. To directly compare these theories with precise experiments,

  19. Disorder-Induced Microscopic Magnetic Memory

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Disorder-Induced Microscopic Magnetic Memory Print The magnetic-recording industry deliberately introduces carefully controlled disorder into its materials to obtain the desired magnetic properties. But as the density of magnetic disks climbs, the size of the magnetic domains responsible for storage must decrease, posing new challenges. Beautiful theories based on random microscopic disorder have been developed over the past ten years. To directly compare these theories with precise experiments,

  20. Disorder-Induced Microscopic Magnetic Memory

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Disorder-Induced Microscopic Magnetic Memory Print The magnetic-recording industry deliberately introduces carefully controlled disorder into its materials to obtain the desired magnetic properties. But as the density of magnetic disks climbs, the size of the magnetic domains responsible for storage must decrease, posing new challenges. Beautiful theories based on random microscopic disorder have been developed over the past ten years. To directly compare these theories with precise experiments,

  1. Parallel garbage collection on a virtual memory system

    SciTech Connect (OSTI)

    Abraham, S.G.; Patel, J.H.

    1987-01-01

    Since most artificial intelligence applications are programmed in list processing languages, it is important to design architectures to support efficient garbage collection. This paper presents an architecture and an associated algorithm for parallel garbage collection on a virtual memory system. All the previously proposed parallel algorithms attempt to collect cells released by the list processor during the garbage collection cycle. We do not attempt to collect such cells. As a consequence, the list processor incurs little overhead in the proposed scheme, since it need not synchronize with the collector. Most parallel algorithms are designed for shared memory machines which have certain implicit synchronization functions on variable access. The proposed algorithm is designed for virtual memory systems where both the list processor and the garbage collector have private memories. The enforcement of coherence between the two private memories can be expensive and is not necessary in our scheme. 15 refs., 3 figs.

  2. Shape memory polymers

    DOE Patents [OSTI]

    Wilson, Thomas S.; Bearinger, Jane P.

    2015-06-09

    New shape memory polymer compositions, methods for synthesizing new shape memory polymers, and apparatus comprising an actuator and a shape memory polymer wherein the shape memory polymer comprises at least a portion of the actuator. A shape memory polymer comprising a polymer composition which physically forms a network structure wherein the polymer composition has shape-memory behavior and can be formed into a permanent primary shape, re-formed into a stable secondary shape, and controllably actuated to recover the permanent primary shape. Polymers have optimal aliphatic network structures due to minimization of dangling chains by using monomers that are symmetrical and that have matching amine and hydroxyl groups providing polymers and polymer foams with clarity, tight (narrow temperature range) single transitions, and high shape recovery and recovery force that are especially useful for implanting in the human body.

  3. Myrmics Memory Allocator

    Energy Science and Technology Software Center (OSTI)

    2011-09-23

    MMA is a stand-alone memory management system for MPI clusters. It implements a shared Partitioned Global Address Space, where multiple MPI processes request objects from the allocator and the latter provides them with system-wide unique memory addresses for each object. It provides applications with an intuitive way of managing the memory system in a unified way, thus enabling easier writing of irregular application code.

  4. A hybrid magnetic/complementary metal oxide semiconductor three-context memory bit cell for non-volatile circuit design

    SciTech Connect (OSTI)

    Jovanović, B. E-mail: lionel.torres@lirmm.fr; Brum, R. M.; Torres, L.

    2014-04-07

    After decades of continued scaling to the beat of Moore's law, it now appears that conventional silicon based devices are approaching their physical limits. In today's deep-submicron nodes, a number of short-channel and quantum effects are emerging that affect the manufacturing process, as well as, the functionality of the microelectronic systems-on-chip. Spintronics devices that exploit both the intrinsic spin of the electron and its associated magnetic moment, in addition to its fundamental electronic charge, are promising solutions to circumvent these scaling threats. Being compatible with the CMOS technology, such devices offer a promising synergy of radiation immunity, infinite endurance, non-volatility, increased density, etc. In this paper, we present a hybrid (magnetic/CMOS) cell that is able to store and process data both electrically and magnetically. The cell is based on perpendicular spin-transfer torque magnetic tunnel junctions (STT-MTJs) and is suitable for use in magnetic random access memories and reprogrammable computing (non-volatile registers, processor cache memories, magnetic field-programmable gate arrays, etc). To demonstrate the potential our hybrid cell, we physically implemented a small hybrid memory block using 45 nm × 45 nm round MTJs for the magnetic part and 28 nm fully depleted silicon on insulator (FD-SOI) technology for the CMOS part. We also report the cells measured performances in terms of area, robustness, read/write speed and energy consumption.

  5. ACCESSING SUBCONTRACTOR EMPLOYMENT RECORDS

    Broader source: Energy.gov [DOE]

    Federal officials, on occasion, may seek access to contractor or subcontractor employment and personnel records. There are circumstances in which such access is appropriate and permissible. But...

  6. Using on-package memory

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    on-package memory Using on-package memory Introduction The NERSC-8 system will include a novel feature on its node architecture: 16 GB of high-bandwidth 3D stacked memory...

  7. Shape memory polymers (Patent) | DOEPatents

    Office of Scientific and Technical Information (OSTI)

    polymers Title: Shape memory polymers New shape memory polymer compositions, methods for ... Sponsoring Org: USDOE Country of Publication: United States Language: English Subject: 36 ...

  8. Computer memory management system

    DOE Patents [OSTI]

    Kirk, III, Whitson John

    2002-01-01

    A computer memory management system utilizing a memory structure system of "intelligent" pointers in which information related to the use status of the memory structure is designed into the pointer. Through this pointer system, The present invention provides essentially automatic memory management (often referred to as garbage collection) by allowing relationships between objects to have definite memory management behavior by use of coding protocol which describes when relationships should be maintained and when the relationships should be broken. In one aspect, the present invention system allows automatic breaking of strong links to facilitate object garbage collection, coupled with relationship adjectives which define deletion of associated objects. In another aspect, The present invention includes simple-to-use infinite undo/redo functionality in that it has the capability, through a simple function call, to undo all of the changes made to a data model since the previous `valid state` was noted.

  9. Cache directory look-up re-use as conflict check mechanism for speculative memory requests

    DOE Patents [OSTI]

    Ohmacht, Martin

    2013-09-10

    In a cache memory, energy and other efficiencies can be realized by saving a result of a cache directory lookup for sequential accesses to a same memory address. Where the cache is a point of coherence for speculative execution in a multiprocessor system, with directory lookups serving as the point of conflict detection, such saving becomes particularly advantageous.

  10. Effcient Shared-array Accesses in Ab Initio Nuclear Structure Calculations

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    on Multicore Architectures | Argonne Leadership Computing Facility Effcient Shared-array Accesses in Ab Initio Nuclear Structure Calculations on Multicore Architectures Authors: Srinivasa, A., Sosonkina, M., Maris, P., Vary, J.P. With the increase in the processing core counts on modern computing platforms, the main memory accesses present a considerable execution bottleneck, leading to poor scalability in multithreaded applications. Even when the memory is physically divided into separate

  11. Sarkar-Salishan-RandomAccess-April-2014.pptx

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    6 Replacing Shuffle by Collective Communications for Iterative MapReduce . . . . . . "Harp Collective Collection", Bingjing Zhang, Judy Qiu, Geoffrey Fox. 7 K-Means Clustering...

  12. choi_salishan15_random_access.pptx

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    upper-layer protocols and applications needs for high-performance fabric services. 2 Translation The only network API you'll ever need (we hope) 3 Why? * Today middleware needs to...

  13. 2015 Salishan Random Access (Conference) | SciTech Connect

    Office of Scientific and Technical Information (OSTI)

    Authors: Vigil, Benny Manuel 1 ; Mattson, Tim 2 ; Coteus, Paul 3 ; Lucas, Bob 4 ; Michalak, Sarah 1 ; Choi, Sung-Eun 5 ; Mountain, Dave 6 ; Levesque, John 5 ; Ang, ...

  14. The Unobtrusive Memory Allocator

    Energy Science and Technology Software Center (OSTI)

    2003-03-31

    This library implements a memory allocator/manager which ask its host program or library for memory refions to manage rather than requesting them from the operating system. This allocator supports multiple distinct heaps within a single executable, each of which may grow either upward or downward in memory. The GNU mmalloc library has been modified in such a way that its allocation algorithms have been preserved, but the manner in which it obtains regions to managemore » has been changed to request memory from the host program or library. Additional modifications allow the allocator to manage each heap as either upward or downward-growing. By allowing the hosting program or library to determine what memory is managed, this package allows a greater degree of control than other memory allocation/management libraries. Additional distinguishing features include the ability to manage multiple distinct heaps with in a single executable, each of which may grow either upward or downward in memory. The most common use of this library is in conjunction with the Berkeley Unified Parallel C (UPC) Runtime Library. This package is a modified version of the LGPL-licensed "mmalloc" allocator from release 5.2 of the "gdb" debugger's source code.« less

  15. Using on-package memory

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    on-package memory Using on-package memory Introduction The NERSC-8 system will include a novel feature on its node architecture: 16 GB of high-bandwidth 3D stacked memory interposed between the KNL chip and the slower off-package DDR memory. Compared to the on-node DDR4 memory, the high-bandwidth memory (HBM) has approximately 5x the bandwidth but has similar latency. This new feature has the potential to accelerate those applications which are particularly sensitive to memory bandwidth limits.

  16. Library API for Z-Order Memory Layout

    Energy Science and Technology Software Center (OSTI)

    2015-02-01

    This library provides a simple-to-use API for implementing an altnerative to traditional row-major order in-memory layout, one based on a Morton- order space filling curve (SFC) , specifically, a Z-order variant of the Morton order curve. The library enables programmers to, after a simple initialization step, to convert a multidimensional array from row-major to Z- order layouts, then use a single, generic API call to access data from any arbitrary (i,j,k) location from within themore » array, whether it it be stored in row- major or z-order format. The motivation for using a SFC in-memory layout is for improved spatial locality, which results in increased use of local high speed cache memory. The basic idea is that with row-major order layouts, a data access to some location that is nearby in index space is likely far away in physical memory, resulting in poor spatial locality and slow runtime. On the other hand, with a SFC-based layout, accesses that are nearby in index space are much more likely to also be nearby in physical memory, resulting in much better spatial locality, and better runtime performance. Numerous studies over the years have shown significant runtime performance gains are realized by using a SFC-based memory layout compared to a row-major layout, sometimes by as much as 50%, which result from the better use of the memory and cache hierarchy that are attendant with a SFC-based layout (see, for example, [Beth2012]). This library implementation is intended for use with codes that work with structured, array-based data in 2 or 3 dimensions. It is not appropriate for use with unstructured or point-based data.« less

  17. Collective Memory Transfers for Multi-Core Chips

    SciTech Connect (OSTI)

    Michelogiannakis, George; Williams, Alexander; Shalf, John

    2013-11-13

    Future performance improvements for microprocessors have shifted from clock frequency scaling towards increases in on-chip parallelism. Performance improvements for a wide variety of parallel applications require domain-decomposition of data arrays from a contiguous arrangement in memory to a tiled layout for on-chip L1 data caches and scratchpads. How- ever, DRAM performance suffers under the non-streaming access patterns generated by many independent cores. We propose collective memory scheduling (CMS) that actively takes control of collective memory transfers such that requests arrive in a sequential and predictable fashion to the memory controller. CMS uses the hierarchically tiled arrays formal- ism to compactly express collective operations, which greatly improves programmability over conventional prefetch or list- DMA approaches. CMS reduces application execution time by up to 32% and DRAM read power by 2.2×, compared to a baseline DMA architecture such as STI Cell.

  18. LANL access restrictions lifted

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    lifted LANL access restrictions lifted Vehicle access points on West Jemez Road will be open to non-badge holders. August 6, 2012 Los Alamos National Laboratory sits on top of a...

  19. Accessing Online COR Training

    Office of Energy Efficiency and Renewable Energy (EERE)

    Contracting Officer’s Representative (COR) training is now be available in an online format. "Accessing Online COR Training" provides a step-by-step guide to access the online COR course. 

  20. A fast and memory-sparing probabilistic selection algorithm for the GPU

    SciTech Connect (OSTI)

    Monroe, Laura M; Wendelberger, Joanne; Michalak, Sarah

    2010-09-29

    A fast and memory-sparing probabilistic top-N selection algorithm is implemented on the GPU. This probabilistic algorithm gives a deterministic result and always terminates. The use of randomization reduces the amount of data that needs heavy processing, and so reduces both the memory requirements and the average time required for the algorithm. This algorithm is well-suited to more general parallel processors with multiple layers of memory hierarchy. Probabilistic Las Vegas algorithms of this kind are a form of stochastic optimization and can be especially useful for processors having a limited amount of fast memory available.

  1. Access to the ALS

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Gate Access Access to the ALS Print User Access The ALS experiment floor (Building 6) is a Controlled Access Area for radiation protection. All ALS users are required to register with the ALS User Services Office and take safety training (see Complete Safety Training ) before they are issued a Berkeley Lab ID badge and granted access to the facility. Note: Users arriving at the ALS outside registration business hours (Monday-Friday 8:00 a.m.-4:00 p.m.) must notify the User Office in advance and

  2. Extra-Large Memory Nodes

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Extra-Large Memory Nodes Extra-Large Memory Nodes Extra-Large Memory Nodes Overview Carver has two "extra-large" memory nodes; each node has four 8-core Intel X7550 ("Nehalem EX") 2.0 GHz processors (32 cores total) and 1TB memory. These nodes are available through the queue "reg_xlmem". They can be used for interactive and batch jobs that require large amount of memory (16GB per core or more). reg_xlmem queue Please refer to the "Queues and Policies" page

  3. Quantum random number generation

    DOE Public Access Gateway for Energy & Science Beta (PAGES Beta)

    Ma, Xiongfeng; Yuan, Xiao; Cao, Zhu; Zhang, Zhen; Qi, Bing

    2016-06-28

    Here, quantum physics can be exploited to generate true random numbers, which play important roles in many applications, especially in cryptography. Genuine randomness from the measurement of a quantum system reveals the inherent nature of quantumness -- coherence, an important feature that differentiates quantum mechanics from classical physics. The generation of genuine randomness is generally considered impossible with only classical means. Based on the degree of trustworthiness on devices, quantum random number generators (QRNGs) can be grouped into three categories. The first category, practical QRNG, is built on fully trusted and calibrated devices and typically can generate randomness at amore » high speed by properly modeling the devices. The second category is self-testing QRNG, where verifiable randomness can be generated without trusting the actual implementation. The third category, semi-self-testing QRNG, is an intermediate category which provides a tradeoff between the trustworthiness on the device and the random number generation speed.« less

  4. Shape memory polymer medical device

    DOE Patents [OSTI]

    Maitland, Duncan; Benett, William J.; Bearinger, Jane P.; Wilson, Thomas S.; Small, IV, Ward; Schumann, Daniel L.; Jensen, Wayne A.; Ortega, Jason M.; Marion, III, John E.; Loge, Jeffrey M.

    2010-06-29

    A system for removing matter from a conduit. The system includes the steps of passing a transport vehicle and a shape memory polymer material through the conduit, transmitting energy to the shape memory polymer material for moving the shape memory polymer material from a first shape to a second and different shape, and withdrawing the transport vehicle and the shape memory polymer material through the conduit carrying the matter.

  5. Access to Capital Roundtable

    Broader source: Energy.gov (indexed) [DOE]

    ... State of Washington Chahalis and Great Wolf Lodge Streamlined environmental approval and process Price advantages due to tax preference Access to NMTC, USDA, DOE, ...

  6. Energy Data Access

    Broader source: Energy.gov [DOE]

    Access to energy data presents a significant opportunity for many organizations interested in energy management, benchmarking, disclosure, and energy efficiency services.

  7. Access to Capital

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    IPR 2008 Capital Investment Review CIR 2012 Quarterly Business Review Focus 2028 2011 Strategic Capital Discussions Access to Capital Debt Optimization Asset Management Cost...

  8. New 1 Terabyte Memory Node

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    New 1 Terabyte Memory Node New 1 Terabyte Memory Node June 17, 2011 by Francesca Verdier A new "extra large" memory node that has four 8-core Nehalem EX processors (32 cores total) and 1TB memory has been deployed in the Carver/Magellan complex. See Memory Considerations on Carver. Subscribe via RSS Subscribe Browse by Date August 2016 June 2016 May 2016 April 2016 January 2016 December 2015 November 2015 October 2015 September 2015 August 2015 July 2015 April 2015 March 2015 January

  9. Quantum random number generator

    DOE Patents [OSTI]

    Pooser, Raphael C.

    2016-05-10

    A quantum random number generator (QRNG) and a photon generator for a QRNG are provided. The photon generator may be operated in a spontaneous mode below a lasing threshold to emit photons. Photons emitted from the photon generator may have at least one random characteristic, which may be monitored by the QRNG to generate a random number. In one embodiment, the photon generator may include a photon emitter and an amplifier coupled to the photon emitter. The amplifier may enable the photon generator to be used in the QRNG without introducing significant bias in the random number and may enable multiplexing of multiple random numbers. The amplifier may also desensitize the photon generator to fluctuations in power supplied thereto while operating in the spontaneous mode. In one embodiment, the photon emitter and amplifier may be a tapered diode amplifier.

  10. Method and apparatus for faulty memory utilization

    DOE Patents [OSTI]

    Cher, Chen-Yong; Andrade Costa, Carlos H.; Park, Yoonho; Rosenburg, Bryan S.; Ryu, Kyung D.

    2016-04-19

    A method for faulty memory utilization in a memory system includes: obtaining information regarding memory health status of at least one memory page in the memory system; determining an error tolerance of the memory page when the information regarding memory health status indicates that a failure is predicted to occur in an area of the memory system affecting the memory page; initiating a migration of data stored in the memory page when it is determined that the data stored in the memory page is non-error-tolerant; notifying at least one application regarding a predicted operating system failure and/or a predicted application failure when it is determined that data stored in the memory page is non-error-tolerant and cannot be migrated; and notifying at least one application regarding the memory failure predicted to occur when it is determined that data stored in the memory page is error-tolerant.

  11. Shape memory alloy actuator

    DOE Patents [OSTI]

    Varma, Venugopal K.

    2001-01-01

    An actuator for cycling between first and second positions includes a first shaped memory alloy (SMA) leg, a second SMA leg. At least one heating/cooling device is thermally connected to at least one of the legs, each heating/cooling device capable of simultaneously heating one leg while cooling the other leg. The heating/cooling devices can include thermoelectric and/or thermoionic elements.

  12. Genepool Memory Heatmaps

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Genepool Memory Heatmaps Heatmap of Memory and Slots Requested vs Time Waited (in hours) | Queue: All | Last 7 Days Memory Requested Slots <5GB 5-10GB 10-20GB 20-30GB 30-40GB 40-50GB 50-100GB 100-150GB 150-200GB 200-256GB 256-512GB 512+GB Job Count Longest Wait 1 2.26 (2693) 10.5 (201167) 3.2 (11650) 0 1.75 (282) 1.49 (1627) 0.03 (1) 0 0 0 0 0 217420 538.96 2 0.26 (103) 1.02 (2817) 0 0 0 0 0 0 0 0 0 0 2920 9.1 4 1.55 (198) 1.48 (104) 0.34 (8) 0 0 0 1.86 (3) 0 0 0 0 0 313 20.48 6 0.01 (1) 0.09

  13. DOE Science Showcase - Shape-Memory Materials | OSTI, US Dept...

    Office of Scientific and Technical Information (OSTI)

    Shape-memory Materials, explainthatstuff.com Shape-memory Alloys, Wikipedia Shape-memory Polymers, Wikipedia Shape Memory Alloy demonstration, University of Birmingham, YouTube ...

  14. Accessibility - Hanford Site

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    of Energy is committed to providing access to our Web pages for individuals with disabilities. To meet this committment, this site is built to comply with the requirements of...

  15. Remote Access Options

    Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

    ... Applications Features Blackberry (if applicable) Outlook Web Access (OWA) Citrix Workplace WebVPN AnyConnect VPN All methods other than Blackberry require a RSA Token Email 1 ...

  16. VEHICLE ACCESS PORTALS

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    ACCESS PORTALS Changes Effective January 11, 2010 Traffic Lane 1: No stop required. Drivers must slow down to 15 MPH while nearing and driving through the lane Traffic Lane 2:...

  17. Compiler-Assisted Detection of Transient Memory Errors

    SciTech Connect (OSTI)

    Tavarageri, Sanket; Krishnamoorthy, Sriram; Sadayappan, Ponnuswamy

    2014-06-09

    The probability of bit flips in hardware memory systems is projected to increase significantly as memory systems continue to scale in size and complexity. Effective hardware-based error detection and correction requires that the complete data path, involving all parts of the memory system, be protected with sufficient redundancy. First, this may be costly to employ on commodity computing platforms and second, even on high-end systems, protection against multi-bit errors may be lacking. Therefore, augmenting hardware error detection schemes with software techniques is of consider- able interest. In this paper, we consider software-level mechanisms to comprehensively detect transient memory faults. We develop novel compile-time algorithms to instrument application programs with checksum computation codes so as to detect memory errors. Unlike prior approaches that employ checksums on computational and architectural state, our scheme verifies every data access and works by tracking variables as they are produced and consumed. Experimental evaluation demonstrates that the proposed comprehensive error detection solution is viable as a completely software-only scheme. We also demonstrate that with limited hardware support, overheads of error detection can be further reduced.

  18. Random array grid collimator

    DOE Patents [OSTI]

    Fenimore, E.E.

    1980-08-22

    A hexagonally shaped quasi-random no-two-holes touching grid collimator. The quasi-random array grid collimator eliminates contamination from small angle off-axis rays by using a no-two-holes-touching pattern which simultaneously provides for a self-supporting array increasng throughput by elimination of a substrate. The presentation invention also provides maximum throughput using hexagonally shaped holes in a hexagonal lattice pattern for diffraction limited applications. Mosaicking is also disclosed for reducing fabrication effort.

  19. Memory-2014-salishan.key

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    WHAT'S NEXT? Bruce Jacob University of Maryland SLIDE Your Next Memory System Bruce Jacob University of Maryland PERSPECTIVE: 1 Cost for 10 GB Power for 10 GB...

  20. Carlsbad employees fund veteran memorial

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    regional veterans by purchasing and placing their own remembrance. On November 12, a dedication ceremony will recognize newly placed memorials in the Park, including one from LANL...

  1. Nanoparticle shuttle memory

    DOE Patents [OSTI]

    Zettl, Alex Karlwalter

    2012-03-06

    A device for storing data using nanoparticle shuttle memory having a nanotube. The nanotube has a first end and a second end. A first electrode is electrically connected to the first end of the nanotube. A second electrode is electrically connected to the second end of the nanotube. The nanotube has an enclosed nanoparticle shuttle. A switched voltage source is electrically connected to the first electrode and the second electrode, whereby a voltage may be controllably applied across the nanotube. A resistance meter is also connected to the first electrode and the second electrode, whereby the electrical resistance across the nanotube can be determined.

  2. Caf Systems Express Access Form

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Cognos Report Access checkboxes (as applicable). Access to Monthly Financials & Supply Chain folders is included with any selections below. BudgetCOA - Capital project,...

  3. Shape memory alloy thaw sensors

    DOE Patents [OSTI]

    Shahinpoor, Mohsen; Martinez, David R.

    1998-01-01

    A sensor permanently indicates that it has been exposed to temperatures exceeding a critical temperature for a predetermined time period. An element of the sensor made from shape memory alloy changes shape when exposed, even temporarily, to temperatures above the Austenitic temperature of the shape memory alloy. The shape change of the SMA element causes the sensor to change between two readily distinguishable states.

  4. Shape memory polymer medical device (Patent) | DOEPatents

    Office of Scientific and Technical Information (OSTI)

    Shape memory polymer medical device Title: Shape memory polymer medical device A system for removing matter from a conduit. The system includes the steps of passing a transport ...

  5. Disorder-Induced Microscopic Magnetic Memory

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Disorder-Induced Microscopic Magnetic Memory Disorder-Induced Microscopic Magnetic Memory Print Wednesday, 26 October 2005 00:00 The magnetic-recording industry deliberately...

  6. Memorandum Memorializing Ex Parte Communication | Department...

    Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

    Memorandum Memorializing Ex Parte Communication Memorandum Memorializing Ex Parte Communication On March 31, 2011, a call was held between the Department of Energy and...

  7. Memorandum Memorializing Ex Parte Communication | Department...

    Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

    Memorandum Memorializing Ex Parte Communication More Documents & Publications Exelon response Memorandum Memorializing Ex Parte Communication CSC Workshop Transcript 02-20-2105

  8. Memorandum Memorializing Ex Parte Communication | Department...

    Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

    PDF icon Memorandum Memorializing Ex Parte Communication More Documents & Publications Memorandum Memorializing Ex Parte Communication Public Comment re NOI on Convention on ...

  9. Public Access Policy and Communications | DOE PAGES

    Office of Scientific and Technical Information (OSTI)

    Public Access Policy and Communications Public Access Policy and Communications 72414 Department of Energy Public Access Plan DOE Public Access Plan 22213 White House Office of ...

  10. Public Access Policy and Communications | DOE PAGES

    Office of Scientific and Technical Information (OSTI)

    DOE PAGES Public Access Policy and Communications Public Access Policy and Communications 72414 Department of Energy Public Access Plan DOE Public Access Plan 22213 White House ...

  11. REMOTE ACCESS SERVICES | Department of Energy

    Office of Environmental Management (EM)

    Energy IT Services (EITS) Remote Access Services: Outlook Web Access RSA Token Login RSA ... Energy Information Administration (EIA) Remote Access Services Outlook Web Access EIA VPN ...

  12. ACCESS Project: Final Report

    SciTech Connect (OSTI)

    Weller, Heiko

    2015-04-01

    The ACCESS project addressed the development, testing, and demonstration of the proposed advanced technologies and the associated emission and fuel economy improvement at an engine dynamometer and on a full-scale vehicle. Improve fuel economy by 25% with minimum performance penalties Achieve SULEV level emissions with gasoline Demonstrate multi-mode combustion engine management system

  13. Special Access Programs

    Broader source: Directives, Delegations, and Requirements [Office of Management (MA)]

    2011-03-29

    This Order is for OFFICIAL USE ONLY and will not be distributed on the Directives' Portal. For distribution, please contact the Executive Secretary of the Special Access Program Oversight Committee at (202) 586-3345. Does not cancel/supersede other directives.

  14. ELECTROSTATIC MEMORY SYSTEM

    DOE Patents [OSTI]

    Chu, J.C.

    1958-09-23

    An improved electrostatic memory system is de scribed fer a digital computer wherein a plarality of storage tubes are adapted to operate in either of two possible modes. According to the present irvention, duplicate storage tubes are provided fur each denominational order of the several binary digits. A single discriminator system is provided between corresponding duplicate tubes to determine the character of the infurmation stored in each. If either tube produces the selected type signal, corresponding to binazy "1" in the preferred embodiment, a "1" is regenerated in both tubes. In one mode of operation each bit of information is stored in two corresponding tubes, while in the other mode of operation each bit is stored in only one tube in the conventional manner.

  15. Template Discontinuation Access

    Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

    FOR SUBJECT FROM: Personnel Security Program Manager SUBJECT: Discontinuation of Access Eligibility Determination Reference is made to your Questionnaire for National Security Positions signed on [insert date], which was forwarded to this office in connection with a Department of Energy security clearance request. A review of that form disclosed recent use of illegal drugs. [Insert a brief description of the circumstances such as: Specifically, you listed marijuana use 1 time in 5/02; 1 time in

  16. Earthquake 'memory' could spur aftershocks

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    applied. More surprising still, the team found that the granular beads could store a "memory" even after the system had undergone a quake and the beads had rearranged themselves....

  17. Shape memory alloy thaw sensors

    DOE Patents [OSTI]

    Shahinpoor, M.; Martinez, D.R.

    1998-04-07

    A sensor permanently indicates that it has been exposed to temperatures exceeding a critical temperature for a predetermined time period. An element of the sensor made from shape memory alloy changes shape when exposed, even temporarily, to temperatures above the austenitic temperature of the shape memory alloy. The shape change of the SMA element causes the sensor to change between two readily distinguishable states. 16 figs.

  18. Multi-Level Bitmap Indexes for Flash Memory Storage

    SciTech Connect (OSTI)

    Wu, Kesheng; Madduri, Kamesh; Canon, Shane

    2010-07-23

    Due to their low access latency, high read speed, and power-efficient operation, flash memory storage devices are rapidly emerging as an attractive alternative to traditional magnetic storage devices. However, tests show that the most efficient indexing methods are not able to take advantage of the flash memory storage devices. In this paper, we present a set of multi-level bitmap indexes that can effectively take advantage of flash storage devices. These indexing methods use coarsely binned indexes to answer queries approximately, and then use finely binned indexes to refine the answers. Our new methods read significantly lower volumes of data at the expense of an increased disk access count, thus taking full advantage of the improved read speed and low access latency of flash devices. To demonstrate the advantage of these new indexes, we measure their performance on a number of storage systems using a standard data warehousing benchmark called the Set Query Benchmark. We observe that multi-level strategies on flash drives are up to 3 times faster than traditional indexing strategies on magnetic disk drives.

  19. Improving Memory Subsystem Performance Using ViVA: Virtual Vector Architecture

    SciTech Connect (OSTI)

    Gebis, Joseph; Oliker, Leonid; Shalf, John; Williams, Samuel; Yelick, Katherine

    2009-01-12

    The disparity between microprocessor clock frequencies and memory latency is a primary reason why many demanding applications run well below peak achievable performance. Software controlled scratchpad memories, such as the Cell local store, attempt to ameliorate this discrepancy by enabling precise control over memory movement; however, scratchpad technology confronts the programmer and compiler with an unfamiliar and difficult programming model. In this work, we present the Virtual Vector Architecture (ViVA), which combines the memory semantics of vector computers with a software-controlled scratchpad memory in order to provide a more effective and practical approach to latency hiding. ViVA requires minimal changes to the core design and could thus be easily integrated with conventional processor cores. To validate our approach, we implemented ViVA on the Mambo cycle-accurate full system simulator, which was carefully calibrated to match the performance on our underlying PowerPC Apple G5 architecture. Results show that ViVA is able to deliver significant performance benefits over scalar techniques for a variety of memory access patterns as well as two important memory-bound compact kernels, corner turn and sparse matrix-vector multiplication -- achieving 2x-13x improvement compared the scalar version. Overall, our preliminary ViVA exploration points to a promising approach for improving application performance on leading microprocessors with minimal design and complexity costs, in a power efficient manner.

  20. Shape memory system with integrated actuation using embedded...

    Office of Scientific and Technical Information (OSTI)

    Shape memory system with integrated actuation using embedded particles Title: Shape memory system with integrated actuation using embedded particles A shape memory material with ...

  1. Shape memory system with integrated actuation using embedded...

    Office of Scientific and Technical Information (OSTI)

    One embodiment provides a shape memory material apparatus comprising a shape memory material body and magnetic pieces in the shape memory material body. Another embodiment provides ...

  2. Shape memory polymers (Patent) | SciTech Connect

    Office of Scientific and Technical Information (OSTI)

    Citation Details In-Document Search Title: Shape memory polymers New shape memory polymer compositions, methods for synthesizing new shape memory polymers, and apparatus comprising ...

  3. Random Selection for Drug Screening

    SciTech Connect (OSTI)

    Center for Human Reliability Studies

    2007-05-01

    Simple random sampling is generally the starting point for a random sampling process. This sampling technique ensures that each individual within a group (population) has an equal chance of being selected. There are a variety of ways to implement random sampling in a practical situation.

  4. System and method for memory allocation in a multiclass memory system

    DOE Patents [OSTI]

    Loh, Gabriel; Meswani, Mitesh; Ignatowski, Michael; Nutter, Mark

    2016-06-28

    A system for memory allocation in a multiclass memory system includes a processor coupleable to a plurality of memories sharing a unified memory address space, and a library store to store a library of software functions. The processor identifies a type of a data structure in response to a memory allocation function call to the library for allocating memory to the data structure. Using the library, the processor allocates portions of the data structure among multiple memories of the multiclass memory system based on the type of the data structure.

  5. Optimizing TLB entries for mixed page size storage in contiguous memory

    DOE Patents [OSTI]

    Chen, Dong; Gara, Alan; Giampapa, Mark E.; Heidelberger, Philip; Kriegel, Jon K.; Ohmacht, Martin; Steinmacher-Burow, Burkhard

    2013-04-30

    A system and method for accessing memory are provided. The system comprises a lookup buffer for storing one or more page table entries, wherein each of the one or more page table entries comprises at least a virtual page number and a physical page number; a logic circuit for receiving a virtual address from said processor, said logic circuit for matching the virtual address to the virtual page number in one of the page table entries to select the physical page number in the same page table entry, said page table entry having one or more bits set to exclude a memory range from a page.

  6. Reader set encoding for directory of shared cache memory in multiprocessor system

    SciTech Connect (OSTI)

    Ahn, Dnaiel; Ceze, Luis H.; Gara, Alan; Ohmacht, Martin; Xiaotong, Zhuang

    2014-06-10

    In a parallel processing system with speculative execution, conflict checking occurs in a directory lookup of a cache memory that is shared by all processors. In each case, the same physical memory address will map to the same set of that cache, no matter which processor originated that access. The directory includes a dynamic reader set encoding, indicating what speculative threads have read a particular line. This reader set encoding is used in conflict checking. A bitset encoding is used to specify particular threads that have read the line.

  7. Shape memory polymers (Patent) | SciTech Connect

    Office of Scientific and Technical Information (OSTI)

    Shape memory polymers Citation Details In-Document Search Title: Shape memory polymers New shape memory polymer compositions, methods for synthesizing new shape memory polymers, and apparatus comprising an actuator and a shape memory polymer wherein the shape memory polymer comprises at least a portion of the actuator. A shape memory polymer comprising a polymer composition which physically forms a network structure wherein the polymer composition has shape-memory behavior and can be formed into

  8. Remote Access | The Ames Laboratory

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Ames Laboratory Information Systems supports VPN for remotely accessing internal computers and network services. These are: Once connected remotely to Ames Laboratory,...

  9. Vehicle barrier with access delay

    DOE Patents [OSTI]

    Swahlan, David J; Wilke, Jason

    2013-09-03

    An access delay vehicle barrier for stopping unauthorized entry into secure areas by a vehicle ramming attack includes access delay features for preventing and/or delaying an adversary from defeating or compromising the barrier. A horizontally deployed barrier member can include an exterior steel casing, an interior steel reinforcing member and access delay members disposed within the casing and between the casing and the interior reinforcing member. Access delay members can include wooden structural lumber, concrete and/or polymeric members that in combination with the exterior casing and interior reinforcing member act cooperatively to impair an adversarial attach by thermal, mechanical and/or explosive tools.

  10. Access, Compiling and Running Jobs

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Access Compiling and Running Jobs Access, Compiling and Running Jobs Access Dirac Dirac can be accessed by logging into carver.nersc.gov. Compile To compile your code, you need to land on a dirac compute node 1st: qsub -q dirac_reg -l nodes=1 -l walltime=00:30:00 -I After you are inside the job, you can load the necessary module for compile: module unload pgi module unload openmpi module unload cuda module load gcc-sl6 module load openmpi-gcc-sl6 module load cuda Now you can compile your code.

  11. Shape memory polymer foams for endovascular therapies

    DOE Patents [OSTI]

    Wilson, Thomas S.; Maitland, Duncan J.

    2015-05-26

    A system for occluding a physical anomaly. One embodiment comprises a shape memory material body wherein the shape memory material body fits within the physical anomaly occluding the physical anomaly. The shape memory material body has a primary shape for occluding the physical anomaly and a secondary shape for being positioned in the physical anomaly.

  12. Shape memory polymer foams for endovascular therapies

    DOE Patents [OSTI]

    Wilson, Thomas S.; Maitland, Duncan J.

    2012-03-13

    A system for occluding a physical anomaly. One embodiment comprises a shape memory material body wherein the shape memory material body fits within the physical anomaly occluding the physical anomaly. The shape memory material body has a primary shape for occluding the physical anomaly and a secondary shape for being positioned in the physical anomaly.

  13. Configurable memory system and method for providing atomic counting operations in a memory device

    DOE Patents [OSTI]

    Bellofatto, Ralph E.; Gara, Alan G.; Giampapa, Mark E.; Ohmacht, Martin

    2010-09-14

    A memory system and method for providing atomic memory-based counter operations to operating systems and applications that make most efficient use of counter-backing memory and virtual and physical address space, while simplifying operating system memory management, and enabling the counter-backing memory to be used for purposes other than counter-backing storage when desired. The encoding and address decoding enabled by the invention provides all this functionality through a combination of software and hardware.

  14. Memory Optimization for Phase-field Simulations

    SciTech Connect (OSTI)

    Derek Gaston; John Peterson; Andrew Slaughter; Cody Permann; David Andrs

    2014-08-01

    Phase-field simulations are computationally and memory intensive applications. Many of the phase-field simulations being conducted in support of NEAMS were not capable of running on “normal clusters” with 2-4GB of RAM per core, and instead required specialized “big-memory” clusters with 64GB per core. To address this issue, the MOOSE team developed a new Python-based utility called MemoryLogger, and applied it to locate, diagnose, and eradicate memory bottlenecks within the MOOSE framework. MemoryLogger allows for a better understanding of the memory usage of an application being run in parallel across a cluster. Memory usage information is captured for every individual process in a parallel job, and communicated to the head node of the cluster. Console text output from the application itself is automatically matched with this memory usage information to produce a detailed picture of memory usage over time, making it straightforward to identify the subroutines which contribute most to the application’s peak memory usage. The information produced by the MemoryLogger quickly and effectively narrows the search for memory optimizations to the most data-intensive parts of the simulation.

  15. Shape memory alloy/shape memory polymer tools

    DOE Patents [OSTI]

    Seward, Kirk P.; Krulevitch, Peter A.

    2005-03-29

    Micro-electromechanical tools for minimally invasive techniques including microsurgery. These tools utilize composite shape memory alloy (SMA), shape memory polymer (SMP) and combinations of SMA and SMP to produce catheter distal tips, actuators, etc., which are bistable. Applications for these structures include: 1) a method for reversible fine positioning of a catheter tip, 2) a method for reversible fine positioning of tools or therapeutic catheters by a guide catheter, 3) a method for bending articulation through the body's vasculature, 4) methods for controlled stent delivery, deployment, and repositioning, and 5) catheters with variable modulus, with vibration mode, with inchworm capability, and with articulated tips. These actuators and catheter tips are bistable and are opportune for in vivo usage because the materials are biocompatible and convenient for intravascular use as well as other minimal by invasive techniques.

  16. Targeting Atmospheric Simulation Algorithms for Large Distributed Memory GPU Accelerated Computers

    SciTech Connect (OSTI)

    Norman, Matthew R

    2013-01-01

    Computing platforms are increasingly moving to accelerated architectures, and here we deal particularly with GPUs. In [15], a method was developed for atmospheric simulation to improve efficiency on large distributed memory machines by reducing communication demand and increasing the time step. Here, we improve upon this method to further target GPU accelerated platforms by reducing GPU memory accesses, removing a synchronization point, and better clustering computations. The modification ran over two times faster in some cases even though more computations were required, demonstrating the merit of improving memory handling on the GPU. Furthermore, we discover that the modification also has a near 100% hit rate in fast on-chip L1 cache and discuss the reasons for this. In concluding, we remark on further potential improvements to GPU efficiency.

  17. Laboratory Access | Sample Preparation Laboratories

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Access Planning Ahead Planning Ahead Please complete the Beam Time Request (BTR) and Support Request forms thourgh the User Portal. Thorough chemical and sample information must be included in your BTR. Support Request forms include a list of collaborators that require laboratory access and your group's laboratory equipment requests. Researcher safety is taken seriously at SLAC. Please remember that radioactive materials, nanomaterials, and biohazardous materials have additional safety

  18. Determining Memory Use | Argonne Leadership Computing Facility

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Allinea DDT Core File Settings Determining Memory Use Using VNC with a Debugger bgq_stack gdb Coreprocessor Runjob termination TotalView Performance Tools & APIs Software & Libraries IBM References Cooley Policies Documentation Feedback Please provide feedback to help guide us as we continue to build documentation for our new computing resource. [Feedback Form] Determining Memory Use Determining the amount of memory available during the execution of the program requires the use of

  19. Improving Alloy Memory by Tuning Material Composition

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Improving Alloy Memory by Tuning Material Composition Improving Alloy Memory by Tuning Material Composition Print Wednesday, 10 August 2016 00:00 Upon deformation, some metal alloys can "remember" their original form and return to it repeatedly when heated. Called "shape memory alloys," these materials have emerging applications in medical devices (stents, artery guide wires, and heart valves) and microelectromechanical actuators and sensors. Usually, within a few cycles, the

  20. 2e Carbon Access | Open Energy Information

    Open Energy Info (EERE)

    e Carbon Access Jump to: navigation, search Name: 2e Carbon Access Place: New York, New York Zip: 10280 Sector: Carbon Product: 2E Carbon Access is an enterprise focused solely on...

  1. Biomass accessibility analysis using electron tomography

    DOE Public Access Gateway for Energy & Science Beta (PAGES Beta)

    Hinkle, Jacob D.; Ciesielski, Peter N.; Gruchalla, Kenny; Munch, Kristin R.; Donohoe, Bryon S.

    2015-12-25

    Substrate accessibility to catalysts has been a dominant theme in theories of biomass deconstruction. Furthermore, current methods of quantifying accessibility do not elucidate mechanisms for increased accessibility due to changes in microstructure following pretreatment.

  2. Sandia Cognitive Runtime Engine with Active Memory

    Energy Science and Technology Software Center (OSTI)

    2005-12-01

    The SCREAM (Sandia Cognitive Runtime Engine with Active memory) software implements a subset of a Cognitive Famework developed at Sandia National Laboratories. The software is implemented in the Umbra simulation and modular software framework, which is C++-based. SCREAM components include a Concept Instance Driver, Semantic Activation Network, Concept Database, Context Recognizer, Context Database, Episodic Memory, Egocentric Spatial Memory, Allocentric Spatial Memory, Comparator, and a Context to Abstract Action converter. At initialization, modules load the datamore » files that together specify all the components of a particular cognitive model, such as concept declarations, context declarations, spreading activation weights, and context/situation-cue-patterns.« less

  3. Exploiting Data Similarity to Reduce Memory Footprints

    SciTech Connect (OSTI)

    Biswas, S; de Supinski, B R; Schulz, M; Franklin, D; Sherwood, T; Chong, F T

    2011-01-28

    Memory size has long limited large-scale applications on high-performance computing (HPC) systems. Since compute nodes frequently do not have swap space, physical memory often limits problem sizes. Increasing core counts per chip and power density constraints, which limit the number of DIMMs per node, have exacerbated this problem. Further, DRAM constitutes a significant portion of overall HPC system cost. Therefore, instead of adding more DRAM to the nodes, mechanisms to manage memory usage more efficiently - preferably transparently - could increase effective DRAM capacity and thus the benefit of multicore nodes for HPC systems. MPI application processes often exhibit significant data similarity. These data regions occupy multiple physical locations across the individual rank processes within a multicore node and thus offer a potential savings in memory capacity. These regions, primarily residing in heap, are dynamic, which makes them difficult to manage statically. Our novel memory allocation library, SBLLmalloc, automatically identifies identical memory blocks and merges them into a single copy. SBLLmalloc does not require application or OS changes since we implement it as a user-level library. Overall, we demonstrate that SBLLmalloc reduces the memory footprint of a range of MPI applications by 32.03% on average and up to 60.87%. Further, SBLLmalloc supports problem sizes for IRS over 21.36% larger than using standard memory management techniques, thus significantly increasing effective system size. Similarly, SBLLmalloc requires 43.75% fewer nodes than standard memory management techniques to solve an AMG problem.

  4. Disorder-Induced Microscopic Magnetic Memory

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Disorder-Induced Microscopic Magnetic Memory Print The magnetic-recording industry deliberately introduces carefully controlled disorder into its materials to obtain the desired...

  5. Disorder-Induced Microscopic Magnetic Memory

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    point for future theories. The Persistence of Memory Magnets are not just for refrigerator doors-they are of paramount importance in today's digital information age. In the...

  6. Improving Memory Error Handling Using Linux

    SciTech Connect (OSTI)

    Carlton, Michael Andrew; Blanchard, Sean P.; Debardeleben, Nathan A.

    2014-07-25

    As supercomputers continue to get faster and more powerful in the future, they will also have more nodes. If nothing is done, then the amount of memory in supercomputer clusters will soon grow large enough that memory failures will be unmanageable to deal with by manually replacing memory DIMMs. "Improving Memory Error Handling Using Linux" is a process oriented method to solve this problem by using the Linux kernel to disable (offline) faulty memory pages containing bad addresses, preventing them from being used again by a process. The process of offlining memory pages simplifies error handling and results in reducing both hardware and manpower costs required to run Los Alamos National Laboratory (LANL) clusters. This process will be necessary for the future of supercomputing to allow the development of exascale computers. It will not be feasible without memory error handling to manually replace the number of DIMMs that will fail daily on a machine consisting of 32-128 petabytes of memory. Testing reveals the process of offlining memory pages works and is relatively simple to use. As more and more testing is conducted, the entire process will be automated within the high-performance computing (HPC) monitoring software, Zenoss, at LANL.

  7. Visitor Hanford Computer Access Request - Hanford Site

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Visitor Hanford Computer Access Request Visitor Hanford Computer Access Request Visitor Hanford Computer Access Request Visitor Hanford Computer Access Request Email Email Page | Print Print Page | Text Increase Font Size Decrease Font Size The U.S. Department of Energy (DOE), Richland Operations Office (RL), in compliance with the 'Tri-Party Agreement Databases, Access Mechanism and Procedures' document, DOE/RL-93-69, Revision 5; set forth the requirements for access to the Hanford Site

  8. Mitigation of cache memory using an embedded hard-core PPC440 processor in a Virtex-5 Field Programmable Gate Array.

    SciTech Connect (OSTI)

    Learn, Mark Walter

    2010-02-01

    Sandia National Laboratories is currently developing new processing and data communication architectures for use in future satellite payloads. These architectures will leverage the flexibility and performance of state-of-the-art static-random-access-memory-based Field Programmable Gate Arrays (FPGAs). One such FPGA is the radiation-hardened version of the Virtex-5 being developed by Xilinx. However, not all features of this FPGA are being radiation-hardened by design and could still be susceptible to on-orbit upsets. One such feature is the embedded hard-core PPC440 processor. Since this processor is implemented in the FPGA as a hard-core, traditional mitigation approaches such as Triple Modular Redundancy (TMR) are not available to improve the processor's on-orbit reliability. The goal of this work is to investigate techniques that can help mitigate the embedded hard-core PPC440 processor within the Virtex-5 FPGA other than TMR. Implementing various mitigation schemes reliably within the PPC440 offers a powerful reconfigurable computing resource to these node-based processing architectures. This document summarizes the work done on the cache mitigation scheme for the embedded hard-core PPC440 processor within the Virtex-5 FPGAs, and describes in detail the design of the cache mitigation scheme and the testing conducted at the radiation effects facility on the Texas A&M campus.

  9. U-205: RSA Access Manager Session Replay Flaw Lets Remote Users Access the System

    Broader source: Energy.gov [DOE]

    A vulnerability was reported in RSA Access Manager. A remote user can gain access to the target system.

  10. Access Venture Partners | Open Energy Information

    Open Energy Info (EERE)

    Venture Partners Jump to: navigation, search Logo: Access Venture Partners Name: Access Venture Partners Address: 8787 Turnpike Drive, Suite 260 Place: Westminster, Colorado Zip:...

  11. International Electricity Trade - Open Access | Department of...

    Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

    to provide non-discriminatory open access transmission services. This open access requirement would also be attached to the permit holder's authorization(s) to export electricity. ...

  12. Argonne Site Access | Advanced Photon Source

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Getting Started Users Home Introduction to APS New User Checklist Argonne Site Access My APS Portal My APS Portal Argonne Site Access Argonne National Laboratory is a...

  13. Testing Web Application Accessibility | Department of Energy

    Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

    Testing Web Application Accessibility Testing Web Application Accessibility Section 508 requires all federal agencies to make their electronic and information technologies ...

  14. Get Access to Work Onsite

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Get Access to Work Onsite Get Access to Work Onsite Print Monday, 31 August 2009 09:48 The following process MUST be completed online by new and returning users at least TWO WEEKS prior to arrival at the ALS. Not a U.S. citizen? Please look at Documents for Foreign Nationals well ahead of your visit. Bring all relevant documents to the ALS in order to complete your registration. NOTE: Users who are citizens of, or were born in, T4 countries (Cuba, Iran, Sudan, and Syria) need DOE permission to

  15. Shape memory system with integrated actuation using embedded particles

    Office of Scientific and Technical Information (OSTI)

    (Patent) | SciTech Connect Shape memory system with integrated actuation using embedded particles Citation Details In-Document Search Title: Shape memory system with integrated actuation using embedded particles A shape memory material with integrated actuation using embedded particles. One embodiment provides a shape memory material apparatus comprising a shape memory material body and magnetic pieces in the shape memory material body. Another embodiment provides a method of actuating a

  16. Shape memory polymer actuator and catheter

    DOE Patents [OSTI]

    Maitland, Duncan J.; Lee, Abraham P.; Schumann, Daniel L.; Matthews, Dennis L.; Decker, Derek E.; Jungreis, Charles A.

    2004-05-25

    An actuator system is provided for acting upon a material in a vessel. The system includes an optical fiber and a shape memory polymer material operatively connected to the optical fiber. The shape memory polymer material is adapted to move from a first shape for moving through said vessel to a second shape where it can act upon said material.

  17. Shape memory polymer actuator and catheter

    DOE Patents [OSTI]

    Maitland, Duncan J.; Lee, Abraham P.; Schumann, Daniel L.; Matthews, Dennis L.; Decker, Derek E.; Jungreis, Charles A.

    2007-11-06

    An actuator system is provided for acting upon a material in a vessel. The system includes an optical fiber and a shape memory polymer material operatively connected to the optical fiber. The shape memory polymer material is adapted to move from a first shape for moving through said vessel to a second shape where it can act upon said material.

  18. Tier identification (TID) for tiered memory characteristics

    SciTech Connect (OSTI)

    Chang, Jichuan; Lim, Kevin T; Ranganathan, Parthasarathy

    2014-03-25

    A tier identification (TID) is to indicate a characteristic of a memory region associated with a virtual address in a tiered memory system. A thread may be serviced according to a first path based on the TID indicating a first characteristic. The thread may be serviced according to a second path based on the TID indicating a second characteristic.

  19. Self-pacing direct memory access data transfer operations for compute nodes in a parallel computer

    SciTech Connect (OSTI)

    Blocksome, Michael A

    2015-02-17

    Methods, apparatus, and products are disclosed for self-pacing DMA data transfer operations for nodes in a parallel computer that include: transferring, by an origin DMA on an origin node, a RTS message to a target node, the RTS message specifying an message on the origin node for transfer to the target node; receiving, in an origin injection FIFO for the origin DMA from a target DMA on the target node in response to transferring the RTS message, a target RGET descriptor followed by a DMA transfer operation descriptor, the DMA descriptor for transmitting a message portion to the target node, the target RGET descriptor specifying an origin RGET descriptor on the origin node that specifies an additional DMA descriptor for transmitting an additional message portion to the target node; processing, by the origin DMA, the target RGET descriptor; and processing, by the origin DMA, the DMA transfer operation descriptor.

  20. Chaining direct memory access data transfer operations for compute nodes in a parallel computer

    DOE Patents [OSTI]

    Archer, Charles J.; Blocksome, Michael A.

    2010-09-28

    Methods, systems, and products are disclosed for chaining DMA data transfer operations for compute nodes in a parallel computer that include: receiving, by an origin DMA engine on an origin node in an origin injection FIFO buffer for the origin DMA engine, a RGET data descriptor specifying a DMA transfer operation data descriptor on the origin node and a second RGET data descriptor on the origin node, the second RGET data descriptor specifying a target RGET data descriptor on the target node, the target RGET data descriptor specifying an additional DMA transfer operation data descriptor on the origin node; creating, by the origin DMA engine, an RGET packet in dependence upon the RGET data descriptor, the RGET packet containing the DMA transfer operation data descriptor and the second RGET data descriptor; and transferring, by the origin DMA engine to a target DMA engine on the target node, the RGET packet.

  1. Controlling the Actuation Rate of Low Density Shape Memory Polymer...

    Office of Scientific and Technical Information (OSTI)

    Density Shape Memory Polymer Foams in Water Citation Details In-Document Search Title: Controlling the Actuation Rate of Low Density Shape Memory Polymer Foams in Water Authors: ...

  2. Aging and deaging effects in shape memory alloys (Journal Article...

    Office of Scientific and Technical Information (OSTI)

    Aging and deaging effects in shape memory alloys Citation Details In-Document Search Title: Aging and deaging effects in shape memory alloys Authors: Xue, Dezhen ; Zhou, Yumei ; ...

  3. Shape memory polymer foams for endovascular therapies (Patent...

    Office of Scientific and Technical Information (OSTI)

    Patent: Shape memory polymer foams for endovascular therapies Citation Details In-Document Search Title: Shape memory polymer foams for endovascular therapies A system for ...

  4. Modesto Memorial Hospital Space Heating Low Temperature Geothermal...

    Open Energy Info (EERE)

    Memorial Hospital Space Heating Low Temperature Geothermal Facility Jump to: navigation, search Name Modesto Memorial Hospital Space Heating Low Temperature Geothermal Facility...

  5. V-176: Adobe Flash Player Memory Corruption Flaw Lets Remote...

    Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

    6: Adobe Flash Player Memory Corruption Flaw Lets Remote Users Execute Arbitrary Code V-176: Adobe Flash Player Memory Corruption Flaw Lets Remote Users Execute Arbitrary Code June...

  6. Similarity Engine: Using Content Similarity to Improve Memory...

    Office of Scientific and Technical Information (OSTI)

    Similarity to Improve Memory Resilience. Citation Details In-Document Search Title: Similarity Engine: Using Content Similarity to Improve Memory Resilience. Abstract not provided. ...

  7. Aging and deaging effects in shape memory alloys (Journal Article...

    Office of Scientific and Technical Information (OSTI)

    Aging and deaging effects in shape memory alloys Title: Aging and deaging effects in shape memory alloys Authors: Xue, Dezhen ; Zhou, Yumei ; Ding, Xiangdong ; Lookman, Turab ; ...

  8. The Future of Memory. (Conference) | SciTech Connect

    Office of Scientific and Technical Information (OSTI)

    The Future of Memory. Citation Details In-Document Search Title: The Future of Memory. Authors: Marinella, Matthew Publication Date: 2013-01-01 OSTI Identifier: 1063520 Report ...

  9. Shape memory polymer (SMP) gripper with a release sensing system...

    Office of Scientific and Technical Information (OSTI)

    Shape memory polymer (SMP) gripper with a release sensing system Title: Shape memory polymer (SMP) gripper with a release sensing system A system for releasing a target material, ...

  10. Guide wire extension for shape memory polymer occlusion removal...

    Office of Scientific and Technical Information (OSTI)

    Guide wire extension for shape memory polymer occlusion removal devices Title: Guide wire extension for shape memory polymer occlusion removal devices A flexible extension for a ...

  11. A Shape Memory Polymer Dialysis Needle Adapter for the Reduction...

    Office of Scientific and Technical Information (OSTI)

    A Shape Memory Polymer Dialysis Needle Adapter for the Reduction of Hemodynamic Stress within Arteriovenous Grafts Citation Details In-Document Search Title: A Shape Memory Polymer ...

  12. Method for loading shape memory polymer gripper mechanisms (Patent...

    Office of Scientific and Technical Information (OSTI)

    Method for loading shape memory polymer gripper mechanisms Title: Method for loading shape memory polymer gripper mechanisms A method and apparatus for loading deposit material, ...

  13. Shape memory polymer actuator and catheter (Patent) | DOEPatents

    Office of Scientific and Technical Information (OSTI)

    Shape memory polymer actuator and catheter Title: Shape memory polymer actuator and catheter An actuator system is provided for acting upon a material in a vessel. The system ...

  14. Biomedical Applications of Thermally Activated Shape Memory Polymers...

    Office of Scientific and Technical Information (OSTI)

    Biomedical Applications of Thermally Activated Shape Memory Polymers Citation Details In-Document Search Title: Biomedical Applications of Thermally Activated Shape Memory Polymers ...

  15. Shape memory polymer foams for endovascular therapies (Patent...

    Office of Scientific and Technical Information (OSTI)

    Shape memory polymer foams for endovascular therapies Title: Shape memory polymer foams for endovascular therapies A system for occluding a physical anomaly. One embodiment ...

  16. Shape memory system with integrated actuation using embedded...

    Office of Scientific and Technical Information (OSTI)

    Patent: Shape memory system with integrated actuation using embedded particles Citation Details In-Document Search Title: Shape memory system with integrated actuation using ...

  17. Apparatus for loading shape memory gripper mechanisms (Patent...

    Office of Scientific and Technical Information (OSTI)

    Apparatus for loading shape memory gripper mechanisms Title: Apparatus for loading shape memory gripper mechanisms A method and apparatus for loading deposit material, such as an ...

  18. The Future of Memory. (Conference) | SciTech Connect

    Office of Scientific and Technical Information (OSTI)

    The Future of Memory. Citation Details In-Document Search Title: The Future of Memory. Authors: Marinella, Matthew Publication Date: 2013-03-01 OSTI Identifier: 1067546 Report ...

  19. Whirlpools on the Nanoscale Could Multiply Magnetic Memory

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Whirlpools on the Nanoscale Could Multiply Magnetic Memory Whirlpools on the Nanoscale Could Multiply Magnetic Memory Print Tuesday, 21 May 2013 00:00 Research at the Advanced...

  20. Shape memory polymer foams for endovascular therapies (Patent...

    Office of Scientific and Technical Information (OSTI)

    A system for occluding a physical anomaly. One embodiment comprises a shape memory material body wherein the shape memory material body fits within the physical anomaly occluding ...

  1. Ultralow-fatigue shape memory alloy films (Journal Article) ...

    Office of Scientific and Technical Information (OSTI)

    Ultralow-fatigue shape memory alloy films Citation Details In-Document Search Title: Ultralow-fatigue shape memory alloy films Authors: Chluba, Christoph ; Ge, Wenwei ; Lima de ...

  2. Energy scaling advantages of resistive memory crossbar based...

    Office of Scientific and Technical Information (OSTI)

    Energy scaling advantages of resistive memory crossbar based computation and its application to sparse coding Prev Next Title: Energy scaling advantages of resistive memory ...

  3. Low density biodegradable shape memory polyurethane foams for...

    Office of Scientific and Technical Information (OSTI)

    Low density biodegradable shape memory polyurethane foams for embolic biomedical applications Citation Details In-Document Search Title: Low density biodegradable shape memory...

  4. Rebuilding it Better: Greensburg, Kansas, Kiowa County Memorial...

    Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

    it Better: Greensburg, Kansas, Kiowa County Memorial Hospital (Brochure) (Revised) DOE and NREL Technical Assistance Building Green in Greensburg: Kiowa County Memorial Hospital

  5. Rebuilding it Better: Greensburg, Kansas, Kiowa County Memorial...

    Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

    Memorial Hospital in Greensburg, Kansas. PDF icon 47461.pdf More Documents & Publications Rebuilding it Better: Greensburg, Kansas, Kiowa County Memorial Hospital (Brochure) ...

  6. Controlling the Actuation Rate of Low Density Shape Memory Polymer...

    Office of Scientific and Technical Information (OSTI)

    Memory Polymer Foams in Water Citation Details In-Document Search Title: Controlling the Actuation Rate of Low Density Shape Memory Polymer Foams in Water Authors: Singhal, P ; ...

  7. Product-form solution techniques for the performance analysis of multiple-bus multiprocessor systems with nonuniform memory references

    SciTech Connect (OSTI)

    Chiola, G.; Marsan, M.A.; Balbo, G.

    1988-05-01

    Recursive relations are derived for the exact computation of the steady-state probability distribution of some queueing models with passive resources that can be used to analyze the performance of multiple-bus multiprocessor system architectures. The most general case that was shown to admit a product-form solution is described, and a recursive solution is obtained considering different processor access rates, different memory selection probabilities, and an FCFS bus scheduling policy. Several simpler cases allowing easier model solutions are also considered. Numerical evaluations of large computing systems with nonuniform memory references show the usefulness of the results.

  8. Performing an allreduce operation using shared memory

    DOE Patents [OSTI]

    Archer, Charles J.; Dozsa, Gabor; Ratterman, Joseph D.; Smith, Brian E.

    2012-04-17

    Methods, apparatus, and products are disclosed for performing an allreduce operation using shared memory that include: receiving, by at least one of a plurality of processing cores on a compute node, an instruction to perform an allreduce operation; establishing, by the core that received the instruction, a job status object for specifying a plurality of shared memory allreduce work units, the plurality of shared memory allreduce work units together performing the allreduce operation on the compute node; determining, by an available core on the compute node, a next shared memory allreduce work unit in the job status object; and performing, by that available core on the compute node, that next shared memory allreduce work unit.

  9. Performing an allreduce operation using shared memory

    SciTech Connect (OSTI)

    Archer, Charles J; Dozsa, Gabor; Ratterman, Joseph D; Smith, Brian E

    2014-06-10

    Methods, apparatus, and products are disclosed for performing an allreduce operation using shared memory that include: receiving, by at least one of a plurality of processing cores on a compute node, an instruction to perform an allreduce operation; establishing, by the core that received the instruction, a job status object for specifying a plurality of shared memory allreduce work units, the plurality of shared memory allreduce work units together performing the allreduce operation on the compute node; determining, by an available core on the compute node, a next shared memory allreduce work unit in the job status object; and performing, by that available core on the compute node, that next shared memory allreduce work unit.

  10. (U) Computation acceleration using dynamic memory

    SciTech Connect (OSTI)

    Hakel, Peter

    2014-10-24

    Many computational applications require the repeated use of quantities, whose calculations can be expensive. In order to speed up the overall execution of the program, it is often advantageous to replace computation with extra memory usage. In this approach, computed values are stored and then, when they are needed again, they are quickly retrieved from memory rather than being calculated again at great cost. Sometimes, however, the precise amount of memory needed to store such a collection is not known in advance, and only emerges in the course of running the calculation. One problem accompanying such a situation is wasted memory space in overdimensioned (and possibly sparse) arrays. Another issue is the overhead of copying existing values to a new, larger memory space, if the original allocation turns out to be insufficient. In order to handle these runtime problems, the programmer therefore has the extra task of addressing them in the code.

  11. Temperature and electrical memory of polymer fibers

    SciTech Connect (OSTI)

    Yuan, Jinkai; Zakri, Ccile; Grillard, Fabienne; Neri, Wilfrid; Poulin, Philippe

    2014-05-15

    We report in this work studies of the shape memory behavior of polymer fibers loaded with carbon nanotubes or graphene flakes. These materials exhibit enhanced shape memory properties with the generation of a giant stress upon shape recovery. In addition, they exhibit a surprising temperature memory with a peak of generated stress at a temperature nearly equal to the temperature of programming. This temperature memory is ascribed to the presence of dynamical heterogeneities and to the intrinsic broadness of the glass transition. We present recent experiments related to observables other than mechanical properties. In particular nanocomposite fibers exhibit variations of electrical conductivity with an accurate memory. Indeed, the rate of conductivity variations during temperature changes reaches a well defined maximum at a temperature equal to the temperature of programming. Such materials are promising for future actuators that couple dimensional changes with sensing electronic functionalities.

  12. NBP_RFI_Data_Access.PDF | Department of Energy

    Office of Environmental Management (EM)

    NBPRFIDataAccess.PDF NBPRFIDataAccess.PDF (104.55 KB) More Documents & Publications NBPRFICommunicationsRequirements.PDF NBP RFI: Data Access RE: NBP RFI: Data Access

  13. Boston solar retrofits: studies of solar access and economics

    SciTech Connect (OSTI)

    Shapiro, M.

    1980-11-01

    Studies of solar access and solar retrofit economics are described for residential applications in the City of Boston. The study of solar access was based upon a random sample of 94 buildings; the sample was stratified to ensure a broad geographic representation from the city's various sections. Using available data on the heights and orientations of the sampled structures and surrounding buildings, each building's hourly access to sunlight was computed separately for the roof and south facing walls. These data were then aggregated by broad structural classifications in order to provide general measures of solar access. The second study was a comparative analysis of the economics of several solar heating and hot water systems. An active hot water system, installed using pre-assembled, commercially purchased equipment, was selected as a reference technology. A variety of measures of economic performance were computed for this system, with and without existing tax credits and under various financing arrangements. Next, a number of alternative approaches for solar space and water heating were identified from interviews with individuals and groups involved in solar retrofit projects in the Boston area. The objective was to identify approaches that many of those interviewed believe to be low-cost means of applying solar energy in residential settings. The approaches selected include thermal window covers, wall collectors, bread box water heaters, and sun spaces. Preliminary estimates of the performance of several representative designs were developed and the economics of these designs evaluated.

  14. Network Randomization and Dynamic Defense for Critical Infrastructure Systems

    SciTech Connect (OSTI)

    Chavez, Adrian R.; Martin, Mitchell Tyler; Hamlet, Jason; Stout, William M.S.; Lee, Erik

    2015-04-01

    Critical Infrastructure control systems continue to foster predictable communication paths, static configurations, and unpatched systems that allow easy access to our nation's most critical assets. This makes them attractive targets for cyber intrusion. We seek to address these attack vectors by automatically randomizing network settings, randomizing applications on the end devices themselves, and dynamically defending these systems against active attacks. Applying these protective measures will convert control systems into moving targets that proactively defend themselves against attack. Sandia National Laboratories has led this effort by gathering operational and technical requirements from Tennessee Valley Authority (TVA) and performing research and development to create a proof-of-concept solution. Our proof-of-concept has been tested in a laboratory environment with over 300 nodes. The vision of this project is to enhance control system security by converting existing control systems into moving targets and building these security measures into future systems while meeting the unique constraints that control systems face.

  15. Expanding Solar Access to Nonprofits

    Broader source: Energy.gov [DOE]

    The Solar Foundation is leading a team that developed the CivicPACE program through an award from the SunShot Initiative. CivicPACE addresses the underwriting and access challenges of solar financing for tax-exempt organizations, such as churches, nonprofit affordable housing, community clinics, and education institutions.

  16. LANSCE personnel access control system

    SciTech Connect (OSTI)

    Sturrock, J.C.; Gallegos, F.R.; Hall, M.J.

    1997-01-01

    The Radiation Security System (RSS) at the Los Alamos Neutron Science Center (LANSCE) provides personnel protection from prompt radiation due to accelerated beam. The Personnel Access Control System (PACS) is a component of the RSS that is designed to prevent personnel access to areas where prompt radiation is a hazard. PACS was designed to replace several older personnel safety systems (PSS) with a single modem unified design. Lessons learned from the operation over the last 20 years were incorporated into a redundant sensor, single-point failure safe, fault tolerant, and tamper-resistant system that prevents access to the beam areas by controlling the access keys and beam stoppers. PACS uses a layered philosophy to the physical and electronic design. The most critical assemblies are battery backed up, relay logic circuits; less critical devices use Programmable Logic Controllers (PLCs) for timing functions and communications. Outside reviewers have reviewed the operational safety of the design. The design philosophy, lessons learned, hardware design, software design, operation, and limitations of the device are described.

  17. Chapter_12_Special_Access_Programs

    Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

    2 Special Access Programs This chapter describes the DOE Special Access Program (SAP) at DOE HQ and implements the requirements of: * Executive Order 13526, Classified National Security Information, Section 4.3, Special Access Programs, and Section 5.4, General Responsibilities, subparagraph (d). * DOE Order 471.5, Special Access Programs. A SAP is a program established for a specific class of classified information that imposes safeguarding and access requirements exceeding those normally

  18. Remote Access Options | Department of Energy

    Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

    Remote Access Options Remote Access Options A Virtual Private Network (VPN) is a private connection between two resources that uses the public telecommunication infrastructure. It maintains privacy through the use of a tunneling protocol and security procedures and provides the following abilities. * Messaging via Outlook Web Access (OWA) * Remote desktop and application access via VDI and Citrix(tm) Workplace * Secure access to DOE Headquarters mission-specific internal network resources

  19. Energy-aware Thread and Data Management in Heterogeneous Multi-core, Multi-memory Systems

    SciTech Connect (OSTI)

    Su, Chun-Yi

    2014-12-16

    By 2004, microprocessor design focused on multicore scaling—increasing the number of cores per die in each generation—as the primary strategy for improving performance. These multicore processors typically equip multiple memory subsystems to improve data throughput. In addition, these systems employ heterogeneous processors such as GPUs and heterogeneous memories like non-volatile memory to improve performance, capacity, and energy efficiency. With the increasing volume of hardware resources and system complexity caused by heterogeneity, future systems will require intelligent ways to manage hardware resources. Early research to improve performance and energy efficiency on heterogeneous, multi-core, multi-memory systems focused on tuning a single primitive or at best a few primitives in the systems. The key limitation of past efforts is their lack of a holistic approach to resource management that balances the tradeoff between performance and energy consumption. In addition, the shift from simple, homogeneous systems to these heterogeneous, multicore, multi-memory systems requires in-depth understanding of efficient resource management for scalable execution, including new models that capture the interchange between performance and energy, smarter resource management strategies, and novel low-level performance/energy tuning primitives and runtime systems. Tuning an application to control available resources efficiently has become a daunting challenge; managing resources in automation is still a dark art since the tradeoffs among programming, energy, and performance remain insufficiently understood. In this dissertation, I have developed theories, models, and resource management techniques to enable energy-efficient execution of parallel applications through thread and data management in these heterogeneous multi-core, multi-memory systems. I study the effect of dynamic concurrent throttling on the performance and energy of multi-core, non-uniform memory access

  20. Data Movement Dominates: Advanced Memory Technology to Address the Real Exascale Power Problem

    SciTech Connect (OSTI)

    Bergman, Keren

    2014-08-28

    Energy is the fundamental barrier to Exascale supercomputing and is dominated by the cost of moving data from one point to another, not computation. Similarly, performance is dominated by data movement, not computation. The solution to this problem requires three critical technologies: 3D integration, optical chip-to-chip communication, and a new communication model. The central goal of the Sandia led "Data Movement Dominates" project aimed to develop memory systems and new architectures based on these technologies that have the potential to lower the cost of local memory accesses by orders of magnitude and provide substantially more bandwidth. Only through these transformational advances can future systems reach the goals of Exascale computing with a manageable power budgets. The Sandia led team included co-PIs from Columbia University, Lawrence Berkeley Lab, and the University of Maryland. The Columbia effort of Data Movement Dominates focused on developing a physically accurate simulation environment and experimental verification for optically-connected memory (OCM) systems that can enable continued performance scaling through high-bandwidth capacity, energy-efficient bit-rate transparency, and time-of-flight latency. With OCM, memory device parallelism and total capacity can scale to match future high-performance computing requirements without sacrificing data-movement efficiency. When we consider systems with integrated photonics, links to memory can be seamlessly integrated with the interconnection network-in a sense, memory becomes a primary aspect of the interconnection network. At the core of the Columbia effort, toward expanding our understanding of OCM enabled computing we have created an integrated modeling and simulation environment that uniquely integrates the physical behavior of the optical layer. The PhoenxSim suite of design and software tools developed under this effort has enabled the co-design of and performance evaluation photonics-enabled OCM

  1. Securing non-volatile memory regions

    DOE Patents [OSTI]

    Faraboschi, Paolo; Ranganathan, Parthasarathy; Muralimanohar, Naveen

    2013-08-20

    Methods, apparatus and articles of manufacture to secure non-volatile memory regions are disclosed. An example method disclosed herein comprises associating a first key pair and a second key pair different than the first key pair with a process, using the first key pair to secure a first region of a non-volatile memory for the process, and using the second key pair to secure a second region of the non-volatile memory for the same process, the second region being different than the first region.

  2. Non-volatile memory for checkpoint storage

    SciTech Connect (OSTI)

    Blumrich, Matthias A.; Chen, Dong; Cipolla, Thomas M.; Coteus, Paul W.; Gara, Alan; Heidelberger, Philip; Jeanson, Mark J.; Kopcsay, Gerard V.; Ohmacht, Martin; Takken, Todd E.

    2014-07-22

    A system, method and computer program product for supporting system initiated checkpoints in high performance parallel computing systems and storing of checkpoint data to a non-volatile memory storage device. The system and method generates selective control signals to perform checkpointing of system related data in presence of messaging activity associated with a user application running at the node. The checkpointing is initiated by the system such that checkpoint data of a plurality of network nodes may be obtained even in the presence of user applications running on highly parallel computers that include ongoing user messaging activity. In one embodiment, the non-volatile memory is a pluggable flash memory card.

  3. Crystallographic attributes of a shape-memory alloy

    SciTech Connect (OSTI)

    Bhattacharya, K.

    1999-01-01

    Shape-memory alloys are attractive for many potential applications. In an attempt to provide ideas and guidelines for the development of new shape-memory alloys, this paper reports on a series of investigations that examine the reasons in the crystallography that made (i) shape-memory alloys special amongst martensites and (ii) Nickel-Titanium special among shape-memory alloys.

  4. Enforcement Letter, Battelle Memorial Institute- May 5, 2004

    Office of Energy Efficiency and Renewable Energy (EERE)

    Issued to Battelle Memorial Institute related to Radiological Work Practices at the Pacific Northwest National Laboratory

  5. Searching game trees under memory constraints

    SciTech Connect (OSTI)

    Bhattacharya, S.; Bagchi, A.

    1996-12-31

    The best-first game-tree search algorithm SSS* has greater pruning power than the depth-first algorithm Alpha-Beta. Yet it is seldom used in practice because it is slow in execution and requires substantial memory. Variants of SSS* have been proposed in recent years that overcome some, but not all, of its limitations. The recursive controlled-memory best-first search scheme MemSSS* described here is a new derivative of SSS* that compares favourably with Alpha-Beta in respect of all three major performance measures, namely, pruning power, running time and memory needs. MemSSS* improves upon an earlier controlled-memory algorithm IterSSS* which has most of the desired properties but is slow in execution.

  6. Search for: shape memory* | DOE PAGES

    Office of Scientific and Technical Information (OSTI)

    ... Stress transfer during different deformation stages in a nano-precipitate-strenthened Ni-Ti shape memory alloy Dong, Y. H. ; Cong, D. Y. ; Nie, Z. H. ; He, Z. B. ; Wang, Z. L. ; ...

  7. Bulk-memory processor for data acquisition

    SciTech Connect (OSTI)

    Nelson, R.O.; McMillan, D.E.; Sunier, J.W.; Meier, M.; Poore, R.V.

    1981-01-01

    To meet the diverse needs and data rate requirements at the Van de Graaff and Weapons Neutron Research (WNR) facilities, a bulk memory system has been implemented which includes a fast and flexible processor. This bulk memory processor (BMP) utilizes bit slice and microcode techniques and features a 24 bit wide internal architecture allowing direct addressing of up to 16 megawords of memory and histogramming up to 16 million counts per channel without overflow. The BMP is interfaced to the MOSTEK MK 8000 bulk memory system and to the standard MODCOMP computer I/O bus. Coding for the BMP both at the microcode level and with macro instructions is supported. The generalized data acquisition system has been extended to support the BMP in a manner transparent to the user.

  8. Distributed trace using central performance counter memory

    SciTech Connect (OSTI)

    Satterfield, David L.; Sexton, James C.

    2013-01-22

    A plurality of processing cores, are central storage unit having at least memory connected in a daisy chain manner, forming a daisy chain ring layout on an integrated chip. At least one of the plurality of processing cores places trace data on the daisy chain connection for transmitting the trace data to the central storage unit, and the central storage unit detects the trace data and stores the trace data in the memory co-located in with the central storage unit.

  9. Post polymerization cure shape memory polymers

    DOE Patents [OSTI]

    Wilson, Thomas S; Hearon, Michael Keith; Bearinger, Jane P

    2014-11-11

    This invention relates to chemical polymer compositions, methods of synthesis, and fabrication methods for devices regarding polymers capable of displaying shape memory behavior (SMPs) and which can first be polymerized to a linear or branched polymeric structure, having thermoplastic properties, subsequently processed into a device through processes typical of polymer melts, solutions, and dispersions and then crossed linked to a shape memory thermoset polymer retaining the processed shape.

  10. Associative memory in phasing neuron networks

    SciTech Connect (OSTI)

    Nair, Niketh S; Bochove, Erik J.; Braiman, Yehuda

    2014-01-01

    We studied pattern formation in a network of coupled Hindmarsh-Rose model neurons and introduced a new model for associative memory retrieval using networks of Kuramoto oscillators. Hindmarsh-Rose Neural Networks can exhibit a rich set of collective dynamics that can be controlled by their connectivity. Specifically, we showed an instance of Hebb's rule where spiking was correlated with network topology. Based on this, we presented a simple model of associative memory in coupled phase oscillators.