National Library of Energy BETA

Sample records for networks including hardware

  1. Flexible Hardware Abstraction for Wireless Sensor Networks

    E-Print Network [OSTI]

    California at Berkeley, University of

    Flexible Hardware Abstraction for Wireless Sensor Networks Vlado Handziski, Joseph Polastre, Jan; Computer Science Department Berkeley, CA 94720 US Abstract-- We present a flexible Hardware Abstraction gradually adapts the capabilities of the underlying hardware plat- forms to the selected platform

  2. Compiling Synchronous Kahn Networks to Efficient Reconfigurable Hardware

    E-Print Network [OSTI]

    Vuillemin, Jean

    Compiling Synchronous Kahn Networks to Efficient Reconfigurable Hardware Jean Vuillemin , Jean research on automatically compiling efficient reconfigurable hardware from high level software stream. Commercial systems exist to generate hardware (say VHDL) from high-level (say C) code [6]. Yet

  3. Fast Filament Tracking Using Graphics Hardware Brain Networks Lab

    E-Print Network [OSTI]

    Keyser, John

    Fast Filament Tracking Using Graphics Hardware Brain Networks Lab Texas A&M University TAMU, that are difficult to visualize. In this paper, we de- scribe a method for tracking filaments and show how data set, a large volume is processed allowing the filaments to be traced in a local frame positioned

  4. Chemistry-inspired Programmable Hardware in Communication and Networking Systems

    E-Print Network [OSTI]

    Vetter, Thomas

    Chemistry-inspired Programmable Hardware in Communication and Networking Systems Massimo Monti April, 2014 Abstract Chemistry-inspired algorithms represent a novel approach to control dynamics of using Chemistry-inspired algorithms range from the design (i.e., enabling runtime programmability

  5. Hardware demonstration of high-speed networks for satellite applications.

    SciTech Connect (OSTI)

    Donaldson, Jonathon W.; Lee, David S.

    2008-09-01

    This report documents the implementation results of a hardware demonstration utilizing the Serial RapidIO{trademark} and SpaceWire protocols that was funded by Sandia National Laboratories (SNL's) Laboratory Directed Research and Development (LDRD) office. This demonstration was one of the activities in the Modeling and Design of High-Speed Networks for Satellite Applications LDRD. This effort has demonstrated the transport of application layer packets across both RapidIO and SpaceWire networks to a common downlink destination using small topologies comprised of commercial-off-the-shelf and custom devices. The RapidFET and NEX-SRIO debug and verification tools were instrumental in the successful implementation of the RapidIO hardware demonstration. The SpaceWire hardware demonstration successfully demonstrated the transfer and routing of application data packets between multiple nodes and also was able reprogram remote nodes using configuration bitfiles transmitted over the network, a key feature proposed in node-based architectures (NBAs). Although a much larger network (at least 18 to 27 nodes) would be required to fully verify the design for use in a real-world application, this demonstration has shown that both RapidIO and SpaceWire are capable of routing application packets across a network to a common downlink node, illustrating their potential use in real-world NBAs.

  6. Locating hardware faults in a data communications network of a parallel computer

    DOE Patents [OSTI]

    Archer, Charles J. (Rochester, MN); Megerian, Mark G. (Rochester, MN); Ratterman, Joseph D. (Rochester, MN); Smith, Brian E. (Rochester, MN)

    2010-01-12

    Hardware faults location in a data communications network of a parallel computer. Such a parallel computer includes a plurality of compute nodes and a data communications network that couples the compute nodes for data communications and organizes the compute node as a tree. Locating hardware faults includes identifying a next compute node as a parent node and a root of a parent test tree, identifying for each child compute node of the parent node a child test tree having the child compute node as root, running a same test suite on the parent test tree and each child test tree, and identifying the parent compute node as having a defective link connected from the parent compute node to a child compute node if the test suite fails on the parent test tree and succeeds on all the child test trees.

  7. A Roadmap for Hardware and Software Support for Developing Energy-Efficient Sensor Networks

    E-Print Network [OSTI]

    Turau, Volker

    A Roadmap for Hardware and Software Support for Developing Energy-Efficient Sensor Networks. In this paper a roadmap of a combined hardware and software approach is presented. The main idea is to collect is important for debugging and evaluation purposes. In this paper a roadmap of our combined hardware

  8. Communication in automation, including networking and wireless

    E-Print Network [OSTI]

    Antsaklis, Panos

    Communication in automation, including networking and wireless Nicholas Kottenstette and Panos J and networking in automation is given. Digital communication fundamentals are reviewed and networked control are presented. 1 Introduction 1.1 Why communication is necessary in automated systems Automated systems use

  9. Hardware/Software Codesign for Embbeded Implementation of Neural Networks

    E-Print Network [OSTI]

    Girau, Bernard

    , Mexico ctorres@inaoep.mx 2 CORTEX team, LORIA-INRIA Lorraine Campus Scientifique, B. P. 239, Vandoeuvre circuits such as Field Programmable Gate Arrays (FPGA) increases at a very fast rate. Their fine-Specific Programmable Cir- cuits) approach that requires a strong hardware expertise. In this paper a high-level design

  10. Computer hardware fault administration

    DOE Patents [OSTI]

    Archer, Charles J. (Rochester, MN); Megerian, Mark G. (Rochester, MN); Ratterman, Joseph D. (Rochester, MN); Smith, Brian E. (Rochester, MN)

    2010-09-14

    Computer hardware fault administration carried out in a parallel computer, where the parallel computer includes a plurality of compute nodes. The compute nodes are coupled for data communications by at least two independent data communications networks, where each data communications network includes data communications links connected to the compute nodes. Typical embodiments carry out hardware fault administration by identifying a location of a defective link in the first data communications network of the parallel computer and routing communications data around the defective link through the second data communications network of the parallel computer.

  11. Introduction to Information Systems Hardware basics, computer networks and architectures, proto-

    E-Print Network [OSTI]

    Kallenrode, May-Britt

    Teaching Introduction to Information Systems Hardware basics, computer networks and architectures on a use case from the information systems practice by making use of already acquired methods and concepts and documentation. Contact Prof. Dr. Frank Teuteberg c/o Univserity of Osnabrueck Accounting and Information Systems

  12. A hardware-based approach to adaptive load-sharing on a local area network 

    E-Print Network [OSTI]

    Reddy, Harikrishna M

    1994-01-01

    . This chip also aids a heavily-loaded processor in speeding up the process of finding a lightly-loaded partner on the network. The collisions on the Ethernet can be easily detected at the hardware level and thus by shifting the process of finding a lightly...

  13. Hardware-and-software-based collective communication on the Quadrics network.

    SciTech Connect (OSTI)

    Petrini, F. (Fabrizio); Coll, S. (Salvador); Frachtemberg, E. (Eitan); Hoisie, A. (Adolfy)

    2001-01-01

    The efficient implementation of collective communication patterns in a parallel machine is a challenging design effort, that requires the solution of many problems. In this paper we present an in-depth description of how the Quadrics network supports both hardware- and software-based collectives. We describe the main features of the two building blocks of this network, a network interface that can perform zero-copy user-level communication and a wormhole switch. We also focus our attention on the routing and $ow control algorithms, deadlock avoidance and on how the processing nodes are integrated in a global, virtual shared memory. Experimental results conducted on 64-node AlphaServer cluster indicate that the time to complete the hardware-based barrier synchronization on the whole network is as low as 6 ps, with veiy good scalability. Good latency and scalability are also achieved with the software-based synchronization, which takes about 15 ps. With the broadcast, similar performance is achieved by the hardware- and software-based implementations, which can deliver messages of up to 256 b,ytes in 13 ps and can get a sustained bandwidth of 288 Mbyteshec on all the nodes, with wressages larger than 64KB. The hardware-based barrier is almost insensitive to the network congestion, with 93% of the synchronizations taking less than 20 ps. On the other hand, the software based implementation suflers from a signif cant performance degradation. In high load environments the hardware broadcast maintains a reasonably good performance, delivering messages up to 2KB in 200 ps, while the software broadcast suffers from slightly higher latencies inherited by the synchronization mechanism.

  14. The NIDS Cluster: Scalable, Stateful Network Intrusion Detection on Commodity Hardware

    SciTech Connect (OSTI)

    Tierney, Brian L; Vallentin, Matthias; Sommer, Robin; Lee, Jason; Leres, Craig; Paxson, Vern; Tierney, Brian

    2007-09-19

    In this work we present a NIDS cluster as a scalable solution for realizing high-performance, stateful network intrusion detection on commodity hardware. The design addresses three challenges: (i) distributing traffic evenly across an extensible set of analysis nodes in a fashion that minimizes the communication required for coordination, (ii) adapting the NIDS's operation to support coordinating its low-level analysis rather than just aggregating alerts; and (iii) validating that the cluster produces sound results. Prototypes of our NIDS cluster now operate at the Lawrence Berkeley National Laboratory and the University of California at Berkeley. In both environments the clusters greatly enhance the power of the network security monitoring.

  15. Specific Group Hardware

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Specific Group Hardware Specific Group Hardware ALICE palicevo1 The Virtual Organization (VO) server. Serves as gatekeeper for ALICE jobs. It's duties include getting assignments...

  16. Software-Hardware Co-Defined Network Switch (SHADES) for a Label Switching Protocol

    E-Print Network [OSTI]

    Karadeniz, Turhan

    2015-01-01

    4.2.1 The Switch Fabric . . . . . . . . . . .of a Network-on-Chip Based Load Balancing Switch Fabric 4.15.3 MRG Based Switch Fabric Architecture . . . . . . . .

  17. Wireless Sensor Networks : the hardware challenge and the cross-layering opportunity

    E-Print Network [OSTI]

    Ingrand, François

    #12;Target applications for wireless sensor networks Flight test instrumentation Pilot ­ crew;Target applications for wireless sensor networks Wireless flight test instrumentation Long term Low or medium data rate, low power nodes High number of nodes, different kind of sensors

  18. The NIDS Cluster: Scalable, Stateful Network Intrusion Detection on Commodity Hardware

    E-Print Network [OSTI]

    Tierney, Brian L

    2008-01-01

    a similar problem with Bro’s IRC analyzer, which tracks asigni?cant amount of state for each IRC user encountered.campus network, the share of IRC tra?c is relatively large,

  19. Minimizing power consumption is crucial in battery power limited secure wireless mobile networks. In this paper, we (a) introduce a hardware/software set-up to

    E-Print Network [OSTI]

    Subbalakshmi , K.P. "Suba"

    mobile networks. In this paper, we (a) introduce a hardware/software set-up to measure the battery power hurdle in providing information security in mobile wireless devices is the limited battery power. The pace of advancements in battery technologies has not kept up with that of wireless technologies

  20. Hardware-oriented Specification Hardware Circuits Hardware Description in C Hardware Design for Cryptographers

    E-Print Network [OSTI]

    Schaumont, Patrick

    Hardware-oriented Specification Hardware Circuits Hardware Description in C Hardware Design, VA Design and Security of Cryptographic Functions, Algorithms and Devices, 2013 #12;Hardware-oriented Specification Hardware Circuits Hardware Description in C Why should a cryptographer care about hardware? Many

  1. Locating hardware faults in a parallel computer

    DOE Patents [OSTI]

    Archer, Charles J.; Megerian, Mark G.; Ratterman, Joseph D.; Smith, Brian E.

    2010-04-13

    Locating hardware faults in a parallel computer, including defining within a tree network of the parallel computer two or more sets of non-overlapping test levels of compute nodes of the network that together include all the data communications links of the network, each non-overlapping test level comprising two or more adjacent tiers of the tree; defining test cells within each non-overlapping test level, each test cell comprising a subtree of the tree including a subtree root compute node and all descendant compute nodes of the subtree root compute node within a non-overlapping test level; performing, separately on each set of non-overlapping test levels, an uplink test on all test cells in a set of non-overlapping test levels; and performing, separately from the uplink tests and separately on each set of non-overlapping test levels, a downlink test on all test cells in a set of non-overlapping test levels.

  2. A low cost network of spectrometer radiation detectors based on the ArduSiPM a compact transportable Software/Hardware Data Acquisition system with Arduino DUE

    E-Print Network [OSTI]

    Bocci, Valerio; Iacoangeli, Francesco; Nuccetelli, Massimo; Recchia, Luigi

    2015-01-01

    The necessity to use Photo Multipliers (PM) as light detector limited in the past the use of crystals in radiation handled device preferring the Geiger approach. The Silicon Photomultipliers (SiPMs) are very small and cheap, solid photon detectors with good dynamic range and single photon detection capability, they are usable to supersede in some application cumbersome and difficult to use Photo Multipliers (PM). A SiPM can be coupled with a scintillator crystal to build efficient, small and solid radiation detector. A cost effective and easily replicable Hardware software module for SiPM detector readout is made using the ArduSiPM solution [1]. The ArduSiPM is an easily battery operable handled device using an Arduino DUE (an open Software/Hardware board) as processor board and a piggy-back custom designed board (ArduSiPM Shield), the Shield contains all the blocks features to monitor, set and acquire the SiPM using internet network.

  3. Demonstration of Datacenter Automation Software and Hardware (DASH) at the California Franchise Tax Board

    E-Print Network [OSTI]

    Bell, Geoffrey C.

    2010-01-01

    of Datacenter Automation Software and Hardware (DASH) at theof Datacenter Automation Software and Hardware (DASH) at theprotocol for building automation and control networks. It is

  4. Theorem Proving Support for Hardware Veri cation |Preliminary Draft|

    E-Print Network [OSTI]

    Kapur, Deepak

    Theorem Proving Support for Hardware Veri#12;cation |Preliminary Draft| Deepak Kapur ? Department reasoning is viewed as a critical technology in designing complex hardware chips, con- trollers, network. Hardware chips are becoming complex, because of which it is increasingly being felt that formal techniques

  5. A Comparison of Software and Hardware Synchronization Mechanisms for Distributed Shared Memory Multiprocessors

    E-Print Network [OSTI]

    A Comparison of Software and Hardware Synchronization Mechanisms for Distributed Shared Memory of traditional multiprocessors have included hardware support only for simple operations such as compare primitives in hardware. In particular, as part of maintaining data consistency, these architectures maintain

  6. GENI: Grid Hardware and Software

    SciTech Connect (OSTI)

    2012-01-09

    GENI Project: The 15 projects in ARPA-E’s GENI program, short for “Green Electricity Network Integration,” aim to modernize the way electricity is transmitted in the U.S. through advances in hardware and software for the electric grid. These advances will improve the efficiency and reliability of electricity transmission, increase the amount of renewable energy the grid can utilize, and provide energy suppliers and consumers with greater control over their power flows in order to better manage peak power demand and cost.

  7. Hardware Sizing for Software Application

    E-Print Network [OSTI]

    Swaminathan, Ganesh

    2009-05-15

    Hardware sizing is an approximation of the hardware resources required to support a software implementation. Just like any theoretical model, hardware sizing model is an approximation of the reality. Depending on the infrastructure needs, workload...

  8. Hardware Transactional Memory

    E-Print Network [OSTI]

    Lie, Sean

    This work shows how hardware transactional memory (HTM) can be implemented to support transactions of arbitrarily large size, while ensuring that small transactions run efficiently. Our implementation handles small ...

  9. Hardware multiplier processor

    DOE Patents [OSTI]

    Pierce, Paul E. (Albuquerque, NM)

    1986-01-01

    A hardware processor is disclosed which in the described embodiment is a memory mapped multiplier processor that can operate in parallel with a 16 bit microcomputer. The multiplier processor decodes the address bus to receive specific instructions so that in one access it can write and automatically perform single or double precision multiplication involving a number written to it with or without addition or subtraction with a previously stored number. It can also, on a single read command automatically round and scale a previously stored number. The multiplier processor includes two concatenated 16 bit multiplier registers, two 16 bit concatenated 16 bit multipliers, and four 16 bit product registers connected to an internal 16 bit data bus. A high level address decoder determines when the multiplier processor is being addressed and first and second low level address decoders generate control signals. In addition, certain low order address lines are used to carry uncoded control signals. First and second control circuits coupled to the decoders generate further control signals and generate a plurality of clocking pulse trains in response to the decoded and address control signals.

  10. Pipeline including network and topology for identifying, locating and quantifying physical phenomena

    DOE Patents [OSTI]

    Richardson, John G.; Moore, Karen A.; Carrington, Robert A.

    2006-02-14

    A method and system for detecting, locating and quantifying a physical phenomena such as strain or a deformation in a structure. A plurality of laterally adjacent conductors may each include a plurality of segments. Each segment is constructed to exhibit a unit value representative of a defined energy transmission characteristic. A plurality of identity groups are defined with each identity group comprising a plurality of segments including at least one segment from each of the plurality of conductors. The segments contained within an identity group are configured and arranged such that each of their associated unit values may be represented by a concatenated digit string which is a unique number relative to the other identity groups. Additionally, the unit values of the segments within an identity group maintain unique ratios with respect to the other unit values in the identity group.

  11. Hardware packet pacing using a DMA in a parallel computer

    DOE Patents [OSTI]

    Chen, Dong; Heidelberger, Phillip; Vranas, Pavlos

    2013-08-13

    Method and system for hardware packet pacing using a direct memory access controller in a parallel computer which, in one aspect, keeps track of a total number of bytes put on the network as a result of a remote get operation, using a hardware token counter.

  12. C3E also includes a network of leaders from the public, private, non-profit

    Broader source: Energy.gov (indexed) [DOE]

    AFDC Printable Version Share this resource Send a link to EERE: Alternative Fuels Data Center Home Page to someone by E-mail Share EERE: Alternative Fuels Data Center Home Page on Facebook Tweet about EERE: Alternative Fuels Data Center Home Page on Twitter Bookmark EERE: Alternative Fuels Data Center Homesum_a_epg0_fpd_mmcf_m.xls" ,"Available from WebQuantity of Natural GasAdjustmentsShirley Ann JacksonDepartment|Marketing, LLCEfficiency | DepartmentEnergyofC3E also includes a

  13. Hardware device binding and mutual authentication

    DOE Patents [OSTI]

    Hamlet, Jason R; Pierson, Lyndon G

    2014-03-04

    Detection and deterrence of device tampering and subversion by substitution may be achieved by including a cryptographic unit within a computing device for binding multiple hardware devices and mutually authenticating the devices. The cryptographic unit includes a physically unclonable function ("PUF") circuit disposed in or on the hardware device, which generates a binding PUF value. The cryptographic unit uses the binding PUF value during an enrollment phase and subsequent authentication phases. During a subsequent authentication phase, the cryptographic unit uses the binding PUF values of the multiple hardware devices to generate a challenge to send to the other device, and to verify a challenge received from the other device to mutually authenticate the hardware devices.

  14. Energy star compliant voice over internet protocol (VoIP) telecommunications network including energy star compliant VoIP devices

    DOE Patents [OSTI]

    Kouchri, Farrokh Mohammadzadeh

    2012-11-06

    A Voice over Internet Protocol (VoIP) communications system, a method of managing a communications network in such a system and a program product therefore. The system/network includes an ENERGY STAR (E-star) aware softswitch and E-star compliant communications devices at system endpoints. The E-star aware softswitch allows E-star compliant communications devices to enter and remain in power saving mode. The E-star aware softswitch spools messages and forwards only selected messages (e.g., calls) to the devices in power saving mode. When the E-star compliant communications devices exit power saving mode, the E-star aware softswitch forwards spooled messages.

  15. Junior Intermediate Senior Chiefland Hardware &

    E-Print Network [OSTI]

    Hill, Jeffrey E.

    Junior Intermediate Senior Chiefland Hardware & Farm Supply Williston Ace Hardware Bronson Ace Hardware #12;#12;MAP OF YOUR GARDEN ROWS RUN NORTH TO SOUTH BETWEEN ROW SPACING WITHIN ROW PLANT SPACING, and pesticides for growing a garden 20 feet by 26 feet and is donated by BRONSON, WILLISTON ACE HARDWARE

  16. HARDWARE AND INSTRUMENTATION -

    E-Print Network [OSTI]

    HARDWARE AND INSTRUMENTATION - Note Noise Amplification in Parallel Whole-Head Ultra-Low- Field. Ilmoniemi2 In ultra-low-field magnetic resonance imaging, arrays of up to hundreds of highly sensitive by the precessing magnetization. Here, we investigate the noise amplification in sensitivity-encoded ultra- low

  17. Program Obfuscation with Leaky Hardware

    E-Print Network [OSTI]

    Bitansky, Nir

    2011-01-01

    We consider general program obfuscation mechanisms using “somewhat trusted” hardware devices, with the goal of minimizing the usage of the hardware, its complexity, and the required trust. Specifically, our solution has ...

  18. 1196 IEEE TRANSACTIONS ON NEURAL NETWORKS, VOL. 19, NO. 7, JULY 2008 On Real-Time AER 2-D Convolutions Hardware for

    E-Print Network [OSTI]

    Barranco, Bernabe Linares

    1196 IEEE TRANSACTIONS ON NEURAL NETWORKS, VOL. 19, NO. 7, JULY 2008 On Real-Time AER 2-D­event-rep- resentation (AER) technique, which is a spike-based biologically inspired image and video representation interfaces have been developed for generating AER streams from conven- tional computers and feeding them

  19. Silencing Hardware Backdoors Adam Waksman

    E-Print Network [OSTI]

    Silencing Hardware Backdoors Adam Waksman Computer Architecture and Security Technology Lab York, USA simha@cs.columbia.edu Abstract--Hardware components can contain hidden back- doors, which can us to build trustworthy hardware systems from components designed by untrusted designers or procured

  20. 1 Computer Architecture hardware components

    E-Print Network [OSTI]

    Verschelde, Jan

    Outline 1 Computer Architecture hardware components programming environments 2 Getting Started January 2015 Intro to Computer Science (MCS 260) Computer Architecture L-2 14 January 2015 1 / 23 #12;Computer Architecture Hardware & Software A computer system consists of 1 Hardware: physical components

  1. RTL Hardware Design Chapter 2 1

    E-Print Network [OSTI]

    Chu, Pong P.

    RTL Hardware Design by P. Chu Chapter 2 1 Hardware Description Language #12;RTL Hardware Design by P. Chu Chapter 2 2 Outline 1. Overview on hardware description language 2. Basic VHDL Concept via an example 3. VHDL in development flow #12;RTL Hardware Design by P. Chu Chapter 2 3 1. Overview on hardware

  2. RTL Hardware Design Chapter 2 1

    E-Print Network [OSTI]

    Chu, Pong P.

    1 RTL Hardware Design by P. Chu Chapter 2 1 Hardware Description Language RTL Hardware Design by P. Chu Chapter 2 2 Outline 1. Overview on hardware description language 2. Basic VHDL Concept via an example 3. VHDL in development flow RTL Hardware Design by P. Chu Chapter 2 3 1. Overview on hardware

  3. Reviews of computing technology: An overview of neural networks

    SciTech Connect (OSTI)

    Rainsford, A.E.

    1992-02-15

    This report discusses the historical background, models, computer hardware, and uses of neural networks. (LSP)

  4. RTL Hardware Design Chapter 5 1

    E-Print Network [OSTI]

    Chu, Pong P.

    RTL Hardware Design by P. Chu Chapter 5 1 Sequential Statements #12;RTL Hardware Design by P. Chu statement 4. If statement 5. Case statement 6. Simple for loop statement #12;RTL Hardware Design by P. Chu of a black box · May or may not be able to be mapped to physical hardware #12;RTL Hardware Design by P. Chu

  5. RTL Hardware Design Chapter 10 1

    E-Print Network [OSTI]

    Chu, Pong P.

    1 RTL Hardware Design by P. Chu Chapter 10 1 Finite State Machine RTL Hardware Design by P. Chu. FSM design examples RTL Hardware Design by P. Chu Chapter 10 3 1. Overview on FSM · Contain "random RTL Hardware Design by P. Chu Chapter 10 4 2. Representation of FSM · State diagram RTL Hardware

  6. RTL Hardware Design Chapter 5 1

    E-Print Network [OSTI]

    Chu, Pong P.

    1 RTL Hardware Design by P. Chu Chapter 5 1 Sequential Statements RTL Hardware Design by P. Chu statement 4. If statement 5. Case statement 6. Simple for loop statement RTL Hardware Design by P. Chu of a black box · May or may not be able to be mapped to physical hardware RTL Hardware Design by P. Chu

  7. Chapter 10 - RIGGING HARDWARE

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    AFDC Printable Version Share this resource Send a link to EERE: Alternative Fuels Data Center Home Page to someone by E-mail Share EERE: Alternative Fuels Data Center Home Page on Facebook Tweet about EERE: Alternative Fuels Data Center Home Page on Twitter Bookmark EERE: Alternative Fuels Data Center Homesum_a_epg0_fpd_mmcf_m.xls" ,"Available from WebQuantity ofkandz-cm11 OutreachProductswsicloudwsiclouddenDVA N C E D BGene Network ShapingDate: M-16-04-04Journal Article: Chaos

  8. Inferred Models for Dynamic and Sparse Hardware-Software Spaces Weidan Wu Benjamin C. Lee

    E-Print Network [OSTI]

    Lee, Benjamin C.

    Inferred Models for Dynamic and Sparse Hardware-Software Spaces Weidan Wu Benjamin C. Lee Duke University {weidan.wu, benjamin.c.lee}@duke.edu Abstract Diverse software and heterogeneous hardware pose new hardware-software analysis. These strategies include (i) identifying shared software behavior; (ii

  9. Goal-oriented hardware design

    E-Print Network [OSTI]

    Chau, Man Ping Grace

    2008-01-01

    This thesis presents Fide, a hardware design system that uses Goal-oriented programming. Goal-oriented programming is a programming framework to specify open-ended decision logic. This approach relies on two fundamental ...

  10. Enterprise Applications User Services Hardware and Networking

    E-Print Network [OSTI]

    Pittendrigh, Barry

    @purdue.edu Web site: http://www.krannert.purdue.edu/departments/kcc Adam Lawson IT Director Jeff Ello Associate Website Communications Specialist Web Marketing Eric Hitze Help Desk Manager Michele Markley IT Coordinator Kris Knotts Web Marketing and Development Manager Tim Newton Director External Relations

  11. Hardware device to physical structure binding and authentication

    SciTech Connect (OSTI)

    Hamlet, Jason R.; Stein, David J.; Bauer, Todd M.

    2013-08-20

    Detection and deterrence of device tampering and subversion may be achieved by including a cryptographic fingerprint unit within a hardware device for authenticating a binding of the hardware device and a physical structure. The cryptographic fingerprint unit includes an internal physically unclonable function ("PUF") circuit disposed in or on the hardware device, which generate an internal PUF value. Binding logic is coupled to receive the internal PUF value, as well as an external PUF value associated with the physical structure, and generates a binding PUF value, which represents the binding of the hardware device and the physical structure. The cryptographic fingerprint unit also includes a cryptographic unit that uses the binding PUF value to allow a challenger to authenticate the binding.

  12. Hardware support for collecting performance counters directly to memory

    DOE Patents [OSTI]

    Gara, Alan; Salapura, Valentina; Wisniewski, Robert W.

    2012-09-25

    Hardware support for collecting performance counters directly to memory, in one aspect, may include a plurality of performance counters operable to collect one or more counts of one or more selected activities. A first storage element may be operable to store an address of a memory location. A second storage element may be operable to store a value indicating whether the hardware should begin copying. A state machine may be operable to detect the value in the second storage element and trigger hardware copying of data in selected one or more of the plurality of performance counters to the memory location whose address is stored in the first storage element.

  13. RTL Hardware Design Chapter 3 1

    E-Print Network [OSTI]

    Chu, Pong P.

    . Chu Chapter 3 15 2. Lexical elements and program format RTL Hardware Design by P. Chu Chapter 3 16 elements: ­ Comments ­ Identifiers ­ Reserved words ­ Numbers ­ Characters ­ Strings RTL Hardware Design1 RTL Hardware Design by P. Chu Chapter 3 1 Basic Language Constructs of VHDL RTL Hardware Design

  14. RTL Hardware Design Chapter 10 1

    E-Print Network [OSTI]

    Chu, Pong P.

    RTL Hardware Design by P. Chu Chapter 10 1 Finite State Machine #12;RTL Hardware Design by P. Chu. FSM design examples #12;RTL Hardware Design by P. Chu Chapter 10 3 1. Overview on FSM · Contain output #12;RTL Hardware Design by P. Chu Chapter 10 4 2. Representation of FSM · State diagram #12;RTL

  15. RTL Hardware Design Chapter 13 1

    E-Print Network [OSTI]

    Chu, Pong P.

    RTL Hardware Design by P. Chu Chapter 13 1 HIERARCHICAL DESIGN #12;RTL Hardware Design by P. Chu constructs #12;RTL Hardware Design by P. Chu Chapter 13 3 1. Introduction · How to deal with 1M gates or more? · Hierarchical design ­ Divided-and-conquer strategy ­ Divide a system into smaller parts #12;RTL Hardware Design

  16. RTL Hardware Design Chapter 11 1

    E-Print Network [OSTI]

    Chu, Pong P.

    1 RTL Hardware Design by P. Chu Chapter 11 1 Register Transfer Methodology I RTL Hardware Design of FSMD 6. Sequential add-and-shift multiplier RTL Hardware Design by P. Chu Chapter 11 3 1. Introduction · How to realize an algorithm in hardware? · Two characteristics of an algorithm: ­ Use of variables

  17. RTL Hardware Design Chapter 11 1

    E-Print Network [OSTI]

    Chu, Pong P.

    RTL Hardware Design by P. Chu Chapter 11 1 Register Transfer Methodology I #12;RTL Hardware Design of FSMD 6. Sequential add-and-shift multiplier #12;RTL Hardware Design by P. Chu Chapter 11 3 1. Introduction · How to realize an algorithm in hardware? · Two characteristics of an algorithm: ­ Use

  18. RTL Hardware Design Chapter 12 1

    E-Print Network [OSTI]

    Chu, Pong P.

    RTL Hardware Design by P. Chu Chapter 12 1 Register Transfer Methodology II #12;RTL Hardware Design #12;RTL Hardware Design by P. Chu Chapter 12 3 1. One­shot pulse generator · Sequential circuit in different types · FSMD is most flexible · One­shot pulse generator as an example #12;RTL Hardware Design

  19. RTL Hardware Design Chapter 13 1

    E-Print Network [OSTI]

    Chu, Pong P.

    1 RTL Hardware Design by P. Chu Chapter 13 1 HIERARCHICAL DESIGN RTL Hardware Design by P. Chu constructs RTL Hardware Design by P. Chu Chapter 13 3 1. Introduction · How to deal with 1M gates or more? · Hierarchical design ­ Divided-and-conquer strategy ­ Divide a system into smaller parts RTL Hardware Design

  20. RTL Hardware Design Chapter 16 1

    E-Print Network [OSTI]

    Chu, Pong P.

    RTL Hardware Design by P. Chu Chapter 16 1 Clock and Synchronization #12;RTL Hardware Design by P-clock system 4. Meta-stability and synchronization failure 5. Synchronizer #12;RTL Hardware Design by P. Chu Chapter 16 3 1. Why synchronous #12;RTL Hardware Design by P. Chu Chapter 16 4 Timing of a combinational

  1. RTL Hardware Design Chapter 8 1

    E-Print Network [OSTI]

    Chu, Pong P.

    RTL Hardware Design by P. Chu Chapter 8 1 Sequential Circuit Design: Principle #12;RTL Hardware analysis 7. Alternative one-segment coding style 8. Use of variable for sequential circuit #12;RTL Hardware latch ­ D FF (Flip-Flop) ­ RAM · Synchronous vs asynchronous circuit #12;RTL Hardware Design by P. Chu

  2. RTL Hardware Design Chapter 16 1

    E-Print Network [OSTI]

    Chu, Pong P.

    1 RTL Hardware Design by P. Chu Chapter 16 1 Clock and Synchronization RTL Hardware Design by P-clock system 4. Meta-stability and synchronization failure 5. Synchronizer RTL Hardware Design by P. Chu Chapter 16 3 1. Why synchronous RTL Hardware Design by P. Chu Chapter 16 4 Timing of a combinational

  3. RTL Hardware Design Chapter 9 1

    E-Print Network [OSTI]

    Chu, Pong P.

    RTL Hardware Design by P. Chu Chapter 9 1 Sequential Circuit Design: Practice #12;RTL Hardware as fast temporary storage 4. Pipelined circuit #12;RTL Hardware Design by P. Chu Chapter 9 3 1. Poor #12;RTL Hardware Design by P. Chu Chapter 9 4 Misuse of asynchronous reset · Poor design: use reset

  4. Resource Management for Dynamic Reconfigurable Hardware Structures

    E-Print Network [OSTI]

    Huss, Sorin A.

    Resource Management for Dynamic Reconfigurable Hardware Structures Andreas K¨uhn, Felix Madlener|madlener|huss}@iss.tu-darmstadt.de Abstract-- Garbage-Collection for reconfigurable hardware systems is another step to make dynamic reconfigurable hardware usable. By now, dynamic reconfiguration of FPGAs is still based on common hardware design

  5. RTL Hardware Design Chapter 9 1

    E-Print Network [OSTI]

    Chu, Pong P.

    1 RTL Hardware Design by P. Chu Chapter 9 1 Sequential Circuit Design: Practice RTL Hardware Design temporary storage 4. Pipelined circuit RTL Hardware Design by P. Chu Chapter 9 3 1. Poor design practice) ­ Misuse of asynchronous reset ­ Misuse of gated clock ­ Misuse of derived clock RTL Hardware Design by P

  6. RTL Hardware Design Chapter 8 1

    E-Print Network [OSTI]

    Chu, Pong P.

    1 RTL Hardware Design by P. Chu Chapter 8 1 Sequential Circuit Design: Principle RTL Hardware analysis 7. Alternative one-segment coding style 8. Use of variable for sequential circuit RTL Hardware latch ­ D FF (Flip-Flop) ­ RAM · Synchronous vs asynchronous circuit RTL Hardware Design by P. Chu

  7. RTL Hardware Design Chapter 12 1

    E-Print Network [OSTI]

    Chu, Pong P.

    1 RTL Hardware Design by P. Chu Chapter 12 1 Register Transfer Methodology II RTL Hardware Design RTL Hardware Design by P. Chu Chapter 12 3 1. One­shot pulse generator · Sequential circuit divided is most flexible · One­shot pulse generator as an example RTL Hardware Design by P. Chu Chapter 12 4

  8. RTL Hardware Design Chapter 3 1

    E-Print Network [OSTI]

    Chu, Pong P.

    RTL Hardware Design by P. Chu Chapter 3 1 Basic Language Constructs of VHDL #12;RTL Hardware Design. Data type and operators #12;RTL Hardware Design by P. Chu Chapter 3 3 1. Basic VHDL program #12;RTL Hardware Design by P. Chu Chapter 3 4 Design unit · Building blocks in a VHDL program · Each design unit

  9. W-026 acceptance test plan plant control system hardware (submittal {number_sign} 216)

    SciTech Connect (OSTI)

    Watson, T.L., Fluor Daniel Hanford

    1997-02-14

    Acceptance Testing of the WRAP 1 Plant Control System Hardware will be conducted throughout the construction of WRAP I with the final testing on the Process Area hardware being completed in November 1996. The hardware tests will be broken out by the following functional areas; Local Control Units, Operator Control Stations in the WRAP Control Room, DMS Server, PCS Server, Operator Interface Units, printers, DNS terminals, WRAP Local Area Network/Communications, and bar code equipment. This document will contain completed copies of each of the hardware tests along with the applicable test logs and completed test exception reports.

  10. Mixed random walks with a trap in scale-free networks including nearest-neighbor and next-nearest-neighbor jumps

    E-Print Network [OSTI]

    Zhang, Zhongzhi; Sheng, Yibin

    2015-01-01

    Random walks including non-nearest-neighbor jumps appear in many real situations such as the diffusion of adatoms and have found numerous applications including PageRank search algorithm, however, related theoretical results are much less for this dynamical process. In this paper, we present a study of mixed random walks in a family of fractal scale-free networks, where both nearest-neighbor and next-nearest-neighbor jumps are included. We focus on trapping problem in the network family, which is a particular case of random walks with a perfect trap fixed at the central high-degree node. We derive analytical expressions for the average trapping time (ATT), a quantitative indicator measuring the efficiency of the trapping process, by using two different methods, the results of which are consistent with each other. Furthermore, we analytically determine all the eigenvalues and their multiplicities for the fundamental matrix characterizing the dynamical process. Our results show that although next-nearest-neighb...

  11. Hardware Architecture for Semantic Comparison 

    E-Print Network [OSTI]

    Mohan, Suneil

    2012-07-16

    Semantic Routed Networks provide a superior infrastructure for complex search engines. In a Semantic Routed Network (SRN), the routers are the critical component and they perform semantic comparison as their key computation. ...

  12. Awarded Products Maintenance, Repair & Operations TOOLS & HARDWARE

    E-Print Network [OSTI]

    California at San Diego, University of

    Awarded Products Maintenance, Repair & Operations (MRO): TOOLS & HARDWARE Such as hand and power tools, cutting tools, fasteners, etc. Maintenance, Repair & Operations (MRO): TOOLS & HARDWARE Such as hand and power tools, cutting tools, fasteners, etc. Maintenance, Repair & Operations (MRO): TOOLS

  13. A methodology for hardware-software codesign

    E-Print Network [OSTI]

    King, Myron Decker

    2013-01-01

    Special purpose hardware is vital to embedded systems as it can simultaneously improve performance while reducing power consumption. The integration of special purpose hardware into applications running in software is ...

  14. Hardware support for unbounded transactional memory

    E-Print Network [OSTI]

    Lie, Sean, 1980-

    2004-01-01

    In this thesis, I propose a design for hardware transactional memory where the transaction size is not bounded by a specialized hardware buffer such as a cache. I describe an unbounded transactional memory system called ...

  15. Dependable Computing Techniques for Reconfigurable Hardware

    E-Print Network [OSTI]

    Stanford University

    Hardware Wei-Je Robert Huang TR 01-7 June 2001 Center for Reliable Computing Gates Building 2A, Room 236 "Dependable Computing Techniques for Reconfigurable Hardware." Funding: This research was supported TECHNIQUES FOR RECONFIGURABLE HARDWARE A DISSERTATION SUBMITTED TO THE DEPARTMENT OF ELECTRICAL ENGINEERING

  16. Evaluation of SeaSonde Hardware Diagnostic Parameters as Performance Metrics Brian M. Emery and Libe Washburn

    E-Print Network [OSTI]

    California at Santa Barbara, University of

    Evaluation of SeaSonde Hardware Diagnostic Parameters as Performance Metrics Brian M. EmerySonde software reports hardware diagnostic statistics, including a number of parameters associated the suitability of the parameters as operational metrics. The hardware parameters considered in this analysis

  17. ECE 587 Hardware/Software Co-Design Lecture 25 Hardware Optimization III

    E-Print Network [OSTI]

    Wang, Jia

    System Design Trends ECE 587 ­ Hardware/Software Co-Design Spring 2015 3/22 #12;Resource Optimization Co-Design Spring 2015 5/22 #12;Outline Overview Pipelining System Design Trends ECE 587 ­ Hardware/SoftwareECE 587 ­ Hardware/Software Co-Design Lecture 25 Hardware Optimization III Professor Jia Wang

  18. Exascale Hardware Architectures Working Group

    SciTech Connect (OSTI)

    Hemmert, S; Ang, J; Chiang, P; Carnes, B; Doerfler, D; Leininger, M; Dosanjh, S; Fields, P; Koch, K; Laros, J; Noe, J; Quinn, T; Torrellas, J; Vetter, J; Wampler, C; White, A

    2011-03-15

    The ASC Exascale Hardware Architecture working group is challenged to provide input on the following areas impacting the future use and usability of potential exascale computer systems: processor, memory, and interconnect architectures, as well as the power and resilience of these systems. Going forward, there are many challenging issues that will need to be addressed. First, power constraints in processor technologies will lead to steady increases in parallelism within a socket. Additionally, all cores may not be fully independent nor fully general purpose. Second, there is a clear trend toward less balanced machines, in terms of compute capability compared to memory and interconnect performance. In order to mitigate the memory issues, memory technologies will introduce 3D stacking, eventually moving on-socket and likely on-die, providing greatly increased bandwidth but unfortunately also likely providing smaller memory capacity per core. Off-socket memory, possibly in the form of non-volatile memory, will create a complex memory hierarchy. Third, communication energy will dominate the energy required to compute, such that interconnect power and bandwidth will have a significant impact. All of the above changes are driven by the need for greatly increased energy efficiency, as current technology will prove unsuitable for exascale, due to unsustainable power requirements of such a system. These changes will have the most significant impact on programming models and algorithms, but they will be felt across all layers of the machine. There is clear need to engage all ASC working groups in planning for how to deal with technological changes of this magnitude. The primary function of the Hardware Architecture Working Group is to facilitate codesign with hardware vendors to ensure future exascale platforms are capable of efficiently supporting the ASC applications, which in turn need to meet the mission needs of the NNSA Stockpile Stewardship Program. This issue is relatively immediate, as there is only a small window of opportunity to influence hardware design for 2018 machines. Given the short timeline a firm co-design methodology with vendors is of prime importance.

  19. Hardware Support for Controlled Interaction of Guaranteed and BestEffort Communication \\Lambda

    E-Print Network [OSTI]

    Rexford, Jennifer

    with the communication media and protocols of distributed systems results in a hybrid en­ vironment well­suited to real and switch­ ing. Unlike protocol software, network hardware can exercise efficient, fine­grain control over for real­time multi­hop networks [7, 8]. Designed as the front­end interface for HARTS [17], SPIDER

  20. Problem Description:Problem Description: Installing traditional, wired, structural health monitoring netwInstalling traditional, wired, structural health monitoring networks has severeorks has severe physical, hardware, cost, and time limitations.physical

    E-Print Network [OSTI]

    Heaton, Thomas H.

    , DC-2000 Hz, MEMS accelerometer; 24-bit A/D conversion board. · Crossbow imote2 wireless sensor node piezoelectric accelerometers mounted to same base plate as MEMS sensor. · Sine wave input at fixed frequencies for Embedded Networked SensingCenter for Embedded Networked Sensing · Portable, wireless vibration sensor

  1. Comparison of the hardware performance of the AES candidates using reconfigurable hardware Kris Gaj and Pawel Chodowiec

    E-Print Network [OSTI]

    Gaj, Krzysztof

    1 Comparison of the hardware performance of the AES candidates using reconfigurable hardware Kris. Performance of four alternative hardware architectures is discussed and compared. The AES candidates are divided into three classes depending on their hardware performance characteristics. Recommendation

  2. New Constructions for UC Secure Computation using Tamper-proof Hardware

    E-Print Network [OSTI]

    International Association for Cryptologic Research (IACR)

    New Constructions for UC Secure Computation using Tamper-proof Hardware Nishanth Chandran Vipul such trusted setup assumptions. In his model, the physical setup phase includes the parties exchanging tamper proof hard- ware tokens implementing some functionality. The tamper proof hardware is modeled so

  3. Comparing Evolvable Hardware to Conventional Classifiers for

    E-Print Network [OSTI]

    Glette, Kyrre

    Comparing Evolvable Hardware to Conventional Classifiers for Electromyographic Prosthetic Hand electromyographic (EMG) signals. Such signals consist of a transient phase and a steady state phase. While some

  4. Manipulation hardware for microgravity research

    SciTech Connect (OSTI)

    Herndon, J.N.; Glassell, R.L.; Butler, P.L.; Williams, D.M. (Oak Ridge National Lab., TN (USA)); Rohn, D.A. (National Aeronautics and Space Administration, Cleveland, OH (USA). Lewis Research Center); Miller, J.H. (Sverdrup Technology, Inc., Brook Park, OH (USA))

    1990-01-01

    The establishment of permanent low earth orbit occupation on the Space Station Freedom will present new opportunities for the introduction of productive flexible automation systems into the microgravity environment of space. The need for robust and reliable robotic systems to support experimental activities normally intended by astronauts will assume great importance. Many experimental modules on the space station are expected to require robotic systems for ongoing experimental operations. When implementing these systems, care must be taken not to introduce deleterious effects on the experiments or on the space station itself. It is important to minimize the acceleration effects on the experimental items being handled while also minimizing manipulator base reaction effects on adjacent experiments and on the space station structure. NASA Lewis Research Center has been performing research on these manipulator applications, focusing on improving the basic manipulator hardware, as well as developing improved manipulator control algorithms. By utilizing the modular manipulator concepts developed during the Laboratory Telerobotic Manipulator program, Oak Ridge National Laboratory has developed an experimental testbed system called the Microgravity Manipulator, incorporating two pitch-yaw modular positioners to provide a 4 dof experimental manipulator arm. A key feature in the design for microgravity manipulation research was the use of traction drives for torque transmission in the modular pitch-yaw differentials.

  5. Tomographic image reconstruction and rendering with texture-mapping hardware

    SciTech Connect (OSTI)

    Azevedo, S.G.; Cabral, B.K.; Foran, J.

    1994-07-01

    The image reconstruction problem, also known as the inverse Radon transform, for x-ray computed tomography (CT) is found in numerous applications in medicine and industry. The most common algorithm used in these cases is filtered backprojection (FBP), which, while a simple procedure, is time-consuming for large images on any type of computational engine. Specially-designed, dedicated parallel processors are commonly used in medical CT scanners, whose results are then passed to graphics workstation for rendering and analysis. However, a fast direct FBP algorithm can be implemented on modern texture-mapping hardware in current high-end workstation platforms. This is done by casting the FBP algorithm as an image warping operation with summing. Texture-mapping hardware, such as that on the Silicon Graphics Reality Engine (TM), shows around 600 times speedup of backprojection over a CPU-based implementation (a 100 Mhz R4400 in this case). This technique has the further advantages of flexibility and rapid programming. In addition, the same hardware can be used for both image reconstruction and for volumetric rendering. The techniques can also be used to accelerate iterative reconstruction algorithms. The hardware architecture also allows more complex operations than straight-ray backprojection if they are required, including fan-beam, cone-beam, and curved ray paths, with little or no speed penalties.

  6. New Hardware to be Integrated by Jan 7, 2013

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    New Hardware to be Integrated by Jan 7, 2013 New Hardware to be Integrated by Jan 7, 2013 December 27, 2012 by Kirsten Fagnan (0 Comments) The new hardware that has been tested...

  7. Experimentsteuerung Hardware und Software fr PC und Peripherie

    E-Print Network [OSTI]

    Osnabrück, Universität

    Experimentsteuerung Hardware und Software für PC und Peripherie Klaus Betzler Universität Osnabrück Sommersemester 1990 Inhaltsverzeichnis 1 PC-Hardware 1 1.1 Die CPU Intel 8086.2.2 Ein/Ausgabe-Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 Software

  8. Guest Editors' Introduction: Confronting the Hardware

    E-Print Network [OSTI]

    , or foundry. Detection of such alterations (i.e., hardware Trojans) is extremely difficult since a very large of interest for this special issue were Trojan detection and isolation, authenticating the foundry of origin

  9. Hardware Acceleration of Electronic Design Automation Algorithms 

    E-Print Network [OSTI]

    Gulati, Kanupriya

    2010-07-14

    With the advances in very large scale integration (VLSI) technology, hardware is going parallel. Software, which was traditionally designed to execute on single core microprocessors, now faces the tough challenge of taking ...

  10. Embedding Hardware Description Languages in Proof Systems 

    E-Print Network [OSTI]

    Goossens, Kees G W

    The aim of this thesis is to investigate the integration of hardware description lamguaages (HDLs) and automated proof systems. Simulation of circuit designs written in an HDL is an important method of testing their ...

  11. Proof Planning for Automating Hardware Verification 

    E-Print Network [OSTI]

    Cantu-Ortiz, Francisco Javier

    In this thesis we investigate the applicability of proof planning to automate the verification of hardware systems. Proof planning is a meta-level reasoning technique which captures patterns of proof common to a family of theorems. It contributes...

  12. Hardware model of a shipboard generator

    E-Print Network [OSTI]

    Elkins, Gregory L. (Gregory Lewis)

    2009-01-01

    A hardware model of the Gas Turbine Generator (GTG) in use on the US Navy's DDG-51 Class Destroyer is constructed for use as a lab apparatus at the Massachusetts Institute of Technology's Laboratory for Electromagnetic and ...

  13. IP routing lookup: hardware and software approach 

    E-Print Network [OSTI]

    Chakaravarthy, Ravikumar V.

    2005-08-29

    The work presented in this thesis is motivated by the dual goal of developing a scalable and efficient approach for IP lookup using both hardware and software approach. The work involved designing algorithms and techniques to increase the capacity...

  14. A circuit based Evolvable Hardware Architecture

    E-Print Network [OSTI]

    Sanchez, Delano Christopher

    2006-01-01

    This thesis presents an Evolvable Hardware Architecture that was developed in the Quantum Nanostructures and Nanofabrication Laboratory. We believe intrinsic evolution is a promising tool that can be used to exploit the ...

  15. Automatic generation of hardware/software interfaces

    E-Print Network [OSTI]

    King, Myron D.

    Enabling new applications for mobile devices often requires the use of specialized hardware to reduce power consumption. Because of time-to-market pressure, current design methodologies for embedded applications require ...

  16. Correct Hardware Design and Verification Methods

    E-Print Network [OSTI]

    Margaria, T.; Melham, T.F.

    Margaria,T. Melham,T.F. Correct Hardware Design and Verification Methods: 11th IFIP WG10.5 Advanced Research Working Conference, CHARME 2001: UK Springer Verlag

  17. Extreme Balance of System Hardware Cost Reduction

    Broader source: Energy.gov [DOE]

    On September 1, 2011, DOE announced $42.4 million in funding over three years for the Extreme Balance of System Hardware Cost Reduction (BOS-X) funding opportunity. Part of the SunShot Systems...

  18. Effect of Jatropha based Biodiesel, on Engine Hardware Reliability...

    Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

    Jatropha based Biodiesel, on Engine Hardware Reliability, Emission and Performance Effect of Jatropha based Biodiesel, on Engine Hardware Reliability, Emission and Performance...

  19. "Hardware Verification for Arithmetic Circuits" Michael Shliselberg, Jordan Kaplan

    E-Print Network [OSTI]

    Mountziaris, T. J.

    "Hardware Verification for Arithmetic Circuits" Michael Shliselberg, Jordan Kaplan Professor Maciej Ciesielski Our research pertains to finding either new or more efficient methods of hardware verification

  20. Supervised Learning in Neural Networks without Feedback Networks

    E-Print Network [OSTI]

    Lin, Feng

    Supervised Learning in Neural Networks without Feedback Networks Robert D. Brandt and Feng Lin Abstract In this paper, we study the supervised learning in neural networks. Unlike the com- mon practice (hardware) implementation of arti cial neural networks. This research is supported in part by the National

  1. RTL Hardware Design Chapter 6 1 Synthesis Of VHDL Code

    E-Print Network [OSTI]

    Chu, Pong P.

    1 RTL Hardware Design Chapter 6 1 Synthesis Of VHDL Code RTL Hardware Design Chapter 6 2 Outline 1. VHDL synthesis flow 5. Timing consideration RTL Hardware Design Chapter 6 3 1. Fundamental limitation of EDA software · Can "C-to-hardware" be done? · EDA tools: ­ Core: optimization algorithms ­ Shell

  2. BlackjackBench: Portable Hardware Characterization with Automated Results Analysis

    E-Print Network [OSTI]

    Dongarra, Jack

    ForReview Only BlackjackBench: Portable Hardware Characterization with Automated Results Analysis-Benchmarks, Hardware Characterization, Statistical Analysis #12;ForReview Only BlackjackBench: Portable Hardware characterizes the targetted hardware and optimizes the application codes accordingly. We present the Blackjack

  3. RTL Hardware Design Chapter 4 1 Concurrent Signal Assignment

    E-Print Network [OSTI]

    Chu, Pong P.

    1 RTL Hardware Design Chapter 4 1 Concurrent Signal Assignment Statements RTL Hardware Design signal assignment RTL Hardware Design Chapter 4 3 1. Combinational vs. sequential circuit · Combinational · Sequential circuit to be discussed later RTL Hardware Design Chapter 4 4 2. Simple signal assignment

  4. The SPARCHS Project Hardware Support for Software Security

    E-Print Network [OSTI]

    August, David

    The SPARCHS Project Hardware Support for Software Security Simha Sethumadhavan, Salvatore J. Stolfo the security mechanisms down to hardware, which is typically immutable. Growing on-chip transistor budgets, there are two further advantages to implementing security mechanisms in hardware. First, hardware supported

  5. The SPARCHS Project Hardware Support for Software Security

    E-Print Network [OSTI]

    Keromytis, Angelos D.

    The SPARCHS Project Hardware Support for Software Security Simha Sethumadhavan, Salvatore J. Stolfo mechanisms down to hardware, which is typically immutable. Growing on-chip transistor budgets provide advantages to implementing security mechanisms in hardware. First, hardware supported security mechanisms can

  6. A Primer on Hardware Security: Models, Methods, and Metrics

    E-Print Network [OSTI]

    INVITED P A P E R A Primer on Hardware Security: Models, Methods, and Metrics The paper is a primer on hardware security threat models, metrics, and remedies. By Masoud Rostami, Farinaz Koushanfar, and Ramesh) production supply chain has intro- duced hardware-based vulnerabilities. Existing literature in hardware

  7. Heterogeneous Hardware Accelerator Architecture for Streaming Image Processing

    E-Print Network [OSTI]

    Bertels, Koen

    Heterogeneous Hardware Accelerator Architecture for Streaming Image Processing Cuong PhamCuong,Z.Al-Ars,K.L.M.Bertels}@tudelft.nl Abstract--This paper proposes a heterogeneous hardware-processed on a host processor and sent to hardware kernels. The host processor and the hardware kernels process

  8. Transportation Perspectives on Automotive Cyber Physical System: Integrating Hardware-in-the-Loop, Software-in-the-Loop and Human-in-the-Loop Simulations

    E-Print Network [OSTI]

    Rajkumar, Ragunathan "Raj"

    1 Transportation Perspectives on Automotive Cyber Physical System: Integrating Hardware and development environment to evaluate automotive cyber physical system (CPS) as well as its components foundation of the automotive CPS for developing and testing vehicular networking and sensing technologies

  9. Class network routing

    DOE Patents [OSTI]

    Bhanot, Gyan (Princeton, NJ); Blumrich, Matthias A. (Ridgefield, CT); Chen, Dong (Croton On Hudson, NY); Coteus, Paul W. (Yorktown Heights, NY); Gara, Alan G. (Mount Kisco, NY); Giampapa, Mark E. (Irvington, NY); Heidelberger, Philip (Cortlandt Manor, NY); Steinmacher-Burow, Burkhard D. (Mount Kisco, NY); Takken, Todd E. (Mount Kisco, NY); Vranas, Pavlos M. (Bedford Hills, NY)

    2009-09-08

    Class network routing is implemented in a network such as a computer network comprising a plurality of parallel compute processors at nodes thereof. Class network routing allows a compute processor to broadcast a message to a range (one or more) of other compute processors in the computer network, such as processors in a column or a row. Normally this type of operation requires a separate message to be sent to each processor. With class network routing pursuant to the invention, a single message is sufficient, which generally reduces the total number of messages in the network as well as the latency to do a broadcast. Class network routing is also applied to dense matrix inversion algorithms on distributed memory parallel supercomputers with hardware class function (multicast) capability. This is achieved by exploiting the fact that the communication patterns of dense matrix inversion can be served by hardware class functions, which results in faster execution times.

  10. HARDWARE TROJANS: Data Leakage Using General

    E-Print Network [OSTI]

    Huss, Sorin A.

    devices have at least one LED. These LEDs of various colors are used with the power switch of yourHARDWARE TROJANS: Data Leakage Using General Purpose LEDs Technical Report - TUD-CS-2010.2. LED Drive Settings 12 3.3. Detection & Assessment 13 4............ Analog Detector Design 14 4

  11. 4 NYU EDUCATIONAL ROBOT 2. Hardware

    E-Print Network [OSTI]

    Mishra, Bud

    YES Emergency Stop YES (Hardware and Software) Table 1: ED I Features The main­link motors (Yokogawa to be incorporated with computer generated animation graphics, controlling a reactive gripper, etc. Last in­house con­ struction are simple aluminum (3 \\Theta 5 00 ) box tubings and are rather easy

  12. Hardware Supported Flexible Monitoring: Early Results

    E-Print Network [OSTI]

    Zhai, Antonia

    Hardware Supported Flexible Monitoring: Early Results Antonia Zhai, Guojin He, and Mats P. Monitoring of software's execution is crucial in numerous software development tasks. Current monitoring software must be studied in its pro- duction environment. To address this fundamental software engineering

  13. Symbolic Verification of Timed Asynchronous Hardware Protocols

    E-Print Network [OSTI]

    Stevens, Ken

    of system level verification by applying symbolic model checking techniques to help mitigate the state constraints into verification models to prove timed behavioral correctness of systems employing timed protocol to model timing in asynchronous hardware protocols ­ a novel mapping of tim- ing into the verification flow

  14. Hardware Metering: A Survey Farinaz Koushanfar

    E-Print Network [OSTI]

    -fabrication. Metering is particularly needed in the hori- zontal semiconductor business model where the design houses is a precursor for metering: In passive metering, each ICs is specifi- cally identified, either in terms of its passive and active hardware metering methods available. Electrical and Computer Engineering Department

  15. Cathode side hardware for carbonate fuel cells

    DOE Patents [OSTI]

    Xu, Gengfu (Danbury, CT); Yuh, Chao-Yi (New Milford, CT)

    2011-03-29

    Carbonate fuel cathode side hardware having a thin coating of a conductive ceramic formed from one of LSC (La.sub.0.8Sr.sub.0.2CoO.sub.3) and lithiated NiO (Li.sub.xNiO, where x is 0.1 to 1).

  16. Hardware support for software controlled fast reconfiguration of performance counters

    DOE Patents [OSTI]

    Salapura, Valentina; Wisniewski, Robert W

    2013-09-24

    Hardware support for software controlled reconfiguration of performance counters may include a plurality of performance counters collecting one or more counts of one or more selected activities. A storage element stores data value representing a time interval, and a timer element reads the data value and detects expiration of the time interval based on the data value and generates a signal. A plurality of configuration registers stores a set of performance counter configurations. A state machine receives the signal and selects a configuration register from the plurality of configuration registers for reconfiguring the one or more performance counters.

  17. Hardware support for software controlled fast reconfiguration of performance counters

    DOE Patents [OSTI]

    Salapura, Valentina; Wisniewski, Robert W.

    2013-06-18

    Hardware support for software controlled reconfiguration of performance counters may include a plurality of performance counters collecting one or more counts of one or more selected activities. A storage element stores data value representing a time interval, and a timer element reads the data value and detects expiration of the time interval based on the data value and generates a signal. A plurality of configuration registers stores a set of performance counter configurations. A state machine receives the signal and selects a configuration register from the plurality of configuration registers for reconfiguring the one or more performance counters.

  18. Design and implementation of an integrated network management system for TCP/IP-based distributed networks 

    E-Print Network [OSTI]

    Patel, Samir K.

    1993-01-01

    in designing of tools for network management. Various workstation vendors have developed such tools for their window systems, but many of the tools are not compatible for other systems. The X Window System, however, provides hardware independent and network...

  19. Combining multi-layered bitmap files using network specific hardware

    DOE Patents [OSTI]

    DuBois, David H. (Los Alamos, NM); DuBois, Andrew J. (Santa Fe, NM); Davenport, Carolyn Connor (Los Alamos, NM)

    2012-02-28

    Images and video can be produced by compositing or alpha blending a group of image layers or video layers. Increasing resolution or the number of layers results in increased computational demands. As such, the available computational resources limit the images and videos that can be produced. A computational architecture in which the image layers are packetized and streamed through processors can be easily scaled so to handle many image layers and high resolutions. The image layers are packetized to produce packet streams. The packets in the streams are received, placed in queues, and processed. For alpha blending, ingress queues receive the packetized image layers which are then z sorted and sent to egress queues. The egress queue packets are alpha blended to produce an output image or video.

  20. Embedded SFE: Offloading Server and Network using Hardware Tokens

    E-Print Network [OSTI]

    International Association for Cryptologic Research (IACR)

    , the following sce- nario appears in a variety of practical applications: a service provider (server S) and user Megabytes or Gigabytes even for relatively small and simple functions (e.g., the GC for AES has size 0

  1. HARDWARE AND SOFTWARE STATUS OF QCDOC.

    SciTech Connect (OSTI)

    BOYLE,P.A.; CHEN,D.; CHRIST,N.H.; PETROV.K.; ET AL.

    2003-07-15

    QCDOC is a massively parallel supercomputer whose processing nodes are based on an application-specific integrated circuit (ASIC). This ASIC was custom-designed so that crucial lattice QCD kernels achieve an overall sustained performance of 50% on machines with several 10,000 nodes. This strong scalability, together with low power consumption and a price/performance ratio of $1 per sustained MFlops, enable QCDOC to attack the most demanding lattice QCD problems. The first ASICs became available in June of 2003, and the testing performed so far has shown all systems functioning according to specification. We review the hardware and software status of QCDOC and present performance figures obtained in real hardware as well as in simulation.

  2. Battery Hardware in the Loop | Department of Energy

    Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

    Hardware in the Loop Battery Hardware in the Loop Presentation from the U.S. DOE Office of Vehicle Technologies "Mega" Merit Review 2008 on February 25, 2008 in Bethesda, Maryland....

  3. Non-Hardware ("Soft") Cost-Reduction Roadmap for

    E-Print Network [OSTI]

    Non-Hardware ("Soft") Cost- Reduction Roadmap for Residential and Small Commercial Solar Golden, CO 80401 303-275-3000 · www.nrel.gov Non-Hardware ("Soft") Cost- Reduction Roadmap

  4. Security challenges and opportunities in adaptive and reconfigurable hardware

    E-Print Network [OSTI]

    Costan, Victor Marius

    We present a novel approach to building hardware support for providing strong security guarantees for computations running in the cloud (shared hardware in massive data centers), while maintaining the high performance and ...

  5. A united model for hardware/software codesign

    E-Print Network [OSTI]

    Dave, Nirav Hemant, 1982-

    2011-01-01

    Embedded systems are almost always built with parts implemented in both hardware and software. Market forces encourage such systems to be developed with dierent hardware-software decompositions to meet dierent points on ...

  6. Reduced hardware transactions: a new approach to hybrid transactional memory

    E-Print Network [OSTI]

    Matveev, Alexander

    For many years, the accepted wisdom has been that the key to adoption of best-effort hardware transactions is to guarantee progress by combining them with an all software slow-path, to be taken if the hardware transactions ...

  7. Energy Department Announces $7 Million to Reduce Non-Hardware...

    Office of Environmental Management (EM)

    Million to Reduce Non-Hardware Costs of Solar Energy Systems Energy Department Announces 7 Million to Reduce Non-Hardware Costs of Solar Energy Systems November 15, 2011 - 4:52pm...

  8. Basing Obfuscation on Simple Tamper-Proof Hardware Assumptions

    E-Print Network [OSTI]

    International Association for Cryptologic Research (IACR)

    Basing Obfuscation on Simple Tamper-Proof Hardware Assumptions Nico D¨ottling, Thilo Mie, J¨orn M for obfuscation, and using tamper-proof hardware tokens to achieve general code obfuscation. Following this last on the security of this CRS. Keywords: Obfuscation, Stateless Tamper-Proof hardware, Universal Composability

  9. Founding Cryptography on Tamper-Proof Hardware Tokens Vipul Goyal

    E-Print Network [OSTI]

    International Association for Cryptologic Research (IACR)

    Founding Cryptography on Tamper-Proof Hardware Tokens Vipul Goyal MSR India vipul of works have investigated using tamper-proof hardware tokens as tools to achieve a variety of cryp if the parties are allowed to generate and exchange tamper-proof hardware tokens. · Unconditional non

  10. An Embedded Language Approach to Teaching Hardware Compilation

    E-Print Network [OSTI]

    Pace, Gordon J.

    An Embedded Language Approach to Teaching Hardware Compilation Koen Claessen 1 and Gordon J. Pace 2, Grenoble, France (Gordon.Pace@imag.fr) Abstract. This paper describes a course in hardware description and synthesis (hardware compilation), taught as an introductory graduate course at Chalmers University

  11. An Embedded Language Approach to Teaching Hardware Compilation

    E-Print Network [OSTI]

    Pace, Gordon J.

    An Embedded Language Approach to Teaching Hardware Compilation Koen Claessen1 and Gordon J. Pace2 1, France (Gordon.Pace@imag.fr) Abstract. This paper describes a course in hardware description and synthesis (hardware compilation), taught as an introductory graduate course at Chalmers University

  12. A Framework for Object Oriented Hardware Specification, Verification, and Synthesis*

    E-Print Network [OSTI]

    Ould Ahmedou, Mohameden

    A Framework for Object Oriented Hardware Specification, Verification, and Synthesis* T. Kuhn, T of hardware. For this purpose the object oriented language `e' is introduced along with a powerful run Object oriented hardware modeling, verification, high-level synthesis. 1. INTRODUCTION The ever

  13. Constraint-Based Hardware Synthesis Andrea Triossi1

    E-Print Network [OSTI]

    Orlando, Salvatore

    Constraint-Based Hardware Synthesis Andrea Triossi1 , Salvatore Orlando1 , Alessandra Raffaet`a1-level hardware description environment which aims at re- ducing the gap between application design and the well-established hardware description frameworks. Our motivations rise from an explicit demand for design representation lan

  14. Object Oriented Hardware Synthesis and Verification T. Kuhn, T. Oppold,

    E-Print Network [OSTI]

    Ould Ahmedou, Mohameden

    Object Oriented Hardware Synthesis and Verification T. Kuhn, T. Oppold, C. Schulz-Key, M of hardware from object oriented specifications is presented. Our approach utilizes the e language that has been proven to be highly efficient for the verification of hardware. The e language is similar to Java

  15. A Hardware Backend for SUIF C. Scott Ananian

    E-Print Network [OSTI]

    Ananian, C. Scott

    Silicon C: A Hardware Backend for SUIF C. Scott Ananian High-level languages have much to offer on the high-level tasks the machine is incapable of? In addition, a successful hardware compiler for a high-level language allows for more flexible hardware-software co-design and simulation. Ide- ally, a single high

  16. Software-Based Cache Coherence with Hardware-Assisted Selective

    E-Print Network [OSTI]

    Cintra, Marcelo

    Software-Based Cache Coherence with Hardware-Assisted Selective Self-Invalidations Using Bloom memory consistency models on top of hardware caches gives rise to the well-known cache coherence problem. The standard solution involves implementing coherence protocols in hardware, an approach with some design

  17. Hardware Synthesis from C/C++ Models Giovanni De Micheli

    E-Print Network [OSTI]

    De Micheli, Giovanni

    Hardware Synthesis from C/C++ Models Giovanni De Micheli CSL - Stanford University Stanford, CA hardware for quite a while. Different design methodologies have exploited the advantages of flexibility software languages) in expressing power (for hardware systems) has caused several difficulties

  18. General calculations using graphics hardware, with application to interactive caustics

    E-Print Network [OSTI]

    Stewart, James

    General calculations using graphics hardware, with application to interactive caustics Chris Trendall and A. James Stewart iMAGIS--GRAVIR/IMAG and University of Toronto Abstract. Graphics hardware has been developed with image production in mind, but current hardware can be exploited for much more

  19. INTEGRATING HARDWARE EXPERIENCES INTO A COMPUTER ARCHITECTURE CORE COURSE

    E-Print Network [OSTI]

    INTEGRATING HARDWARE EXPERIENCES INTO A COMPUTER ARCHITECTURE CORE COURSE Fred G. Martin University@cs.uml.edu ABSTRACT A core curriculum computer architecture course is designed with a significant hardware component on their own PC. The lab kit supports introductory, hardware-based activities in digital logic

  20. WCCCE Conference -Vancouver, 1998 Hardware/Software Codesign

    E-Print Network [OSTI]

    Gardner, William

    1 of 8 WCCCE Conference - Vancouver, 1998 Hardware/Software Codesign - introducing entitled "VLSI Design, CAD and Hardware/Software Codesign" under the rubric of "Special Topics", where.0 What is Hardware/Software Codesign? In this presentation, it is important that we first start

  1. Area 5: Computer Hardware Prof. Natalie Enright Jerger

    E-Print Network [OSTI]

    Area 5: Computer Hardware Prof. Natalie Enright Jerger #12;Courses · Kernel Course ­ ECE342: Computer Hardware · Technical Electives ­ ECE532: Digital Systems Design ­ ECE552: Computer Architecture ­ ECE451: VLSI Systems and Design #12;What is computer hardware? · Complex components working together

  2. BlackjackBench: Portable Hardware Characterization with Automated

    E-Print Network [OSTI]

    Luszczek, Piotr

    BlackjackBench: Portable Hardware Characterization with Automated Results' Analysis ANTHONY DANALIS. Such a compiler automatically characterizes the targetted hardware and optimizes the application codes accordingly discover the effective sizes and speeds of the hardware environment rather than the often unattainable peak

  3. A Hardware Backend for SUIF C. Scott Ananian

    E-Print Network [OSTI]

    Ananian, C. Scott

    Silicon C: A Hardware Backend for SUIF C. Scott Ananian May, 1998 High­level languages have much to work on the high­level tasks the machine is incapable of? In addition, a successful hardware compiler for a high­level language allows for more flexible hardware­software co­design and simulation. Ide­ ally

  4. Deterrence of device counterfeiting, cloning, and subversion by substitution using hardware fingerprinting

    DOE Patents [OSTI]

    Hamlet, Jason R; Bauer, Todd M; Pierson, Lyndon G

    2014-09-30

    Deterrence of device subversion by substitution may be achieved by including a cryptographic fingerprint unit within a computing device for authenticating a hardware platform of the computing device. The cryptographic fingerprint unit includes a physically unclonable function ("PUF") circuit disposed in or on the hardware platform. The PUF circuit is used to generate a PUF value. A key generator is coupled to generate a private key and a public key based on the PUF value while a decryptor is coupled to receive an authentication challenge posed to the computing device and encrypted with the public key and coupled to output a response to the authentication challenge decrypted with the private key.

  5. Groundwater Monitoring Network

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Groundwater Monitoring Network Groundwater Monitoring Network The network includes 92 natural sources, 102 regional aquifer wells, 41 intermediate-depth wells and springs, and 67...

  6. OFC Review 2013 Software Defined Network (SDN)

    E-Print Network [OSTI]

    California at Davis, University of

    and transmission rate w/o hardware change Dedicated PCE to scale OpenFlow architectutre #12;Network ArchitectureOFC Review 2013 Software Defined Network (SDN) M. Farhan Habib May 10, 2013 Friday Group Meeting Networks Lab @ UCD #12;NTu3F: SDN in Today's Network #12;SDN: What and Why · Traditional distributed

  7. Cathode side hardware for carbonate fuel cells

    DOE Patents [OSTI]

    Xu, Gengfu (Danbury, CT); Yuh, Chao-Yi (New Milford, CT)

    2011-04-05

    Carbonate fuel cathode side hardware having a thin coating of a conductive ceramic formed from one of Perovskite AMeO.sub.3, wherein A is at least one of lanthanum and a combination of lanthanum and strontium and Me is one or more of transition metals, lithiated NiO (Li.sub.xNiO, where x is 0.1 to 1) and X-doped LiMeO.sub.2, wherein X is one of Mg, Ca, and Co.

  8. Tuning Hardware and Software for Multiprocessors

    E-Print Network [OSTI]

    Mohiyuddin, Marghoob

    2012-01-01

    In Journal of High Performance Computing Applications, [83]editors, High-Performance Computing and Networking, volumeLittle’s Law and High-Performance Computing, 1997. [6] D.

  9. A Real-Time Procedural Shading System for Programmable Graphics Hardware

    E-Print Network [OSTI]

    Stanford University

    A Real-Time Procedural Shading System for Programmable Graphics Hardware Kekoa Proudfoot£ Stanford University Abstract Real-time graphics hardware is becoming programmable, but this programmable hardware one computation frequency. Internally, our system virtualizes limited hardware resources to allow

  10. Network

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    AFDC Printable Version Share this resource Send a link to EERE: Alternative Fuels Data Center Home Page to someone by E-mail Share EERE: Alternative Fuels Data Center Home Page on Facebook Tweet about EERE: Alternative Fuels Data Center Home Page on Twitter Bookmark EERE: Alternative Fuels Data Center Homesum_a_epg0_fpd_mmcf_m.xls" ,"Available from WebQuantity of NaturalDukeWakefieldSulfateSciTechtail.Theory ofDid you notHeatMaRIEdioxide capture CSNationalNational UserNaval TheNetwork

  11. Hardware-in-the-loop testing of wireless systems in realistic environments.

    SciTech Connect (OSTI)

    Burkholder, R. J. (Ohio State University ElectroScience Laboratory); Mariano, Robert J.; Gupta, I. J. (Ohio State University ElectroScience Laboratory); Schniter, P. (Ohio State University ElectroScience Laboratory)

    2006-06-01

    This document describes an approach for testing of wireless systems in realistic environments that include intentional as well as unintentional radio frequency interference. In the approach, signal generators along with radio channel simulators are used to carry out hardware-in-the-loop testing. The channel parameters are obtained independently via channel sounding measurements and/or EM simulations.

  12. Chico: An On-Chip Hardware Checker for Pipeline Control Logic

    E-Print Network [OSTI]

    Bertacco, Valeria

    Chico: An On-Chip Hardware Checker for Pipeline Control Logic Andrew DeOrio, Adam Bauserman es- caped design errors in these high risk functional blocks. Our solution includes an on of a pipeline's control logic is such a complex problem that it is often un- achievable. As a result

  13. ECE 587 Hardware/Software Co-Design Lecture 07 SystemC

    E-Print Network [OSTI]

    Wang, Jia

    ECE 587 ­ Hardware/Software Co-Design Spring 2015 4/25 VHDL | library ieee; | use ieee.std_logic_1164C // dff.h #include "systemc.h" class dff : public sc_module { public: sc_in din; sc_in clock/25 #12;Modules class dff : public sc_module { public: ... }; Or simply SC_MODULE(dff) { ... }; Module

  14. Power Electronics and Balance of System Hardware Technologies

    Office of Energy Efficiency and Renewable Energy (EERE)

    DOE is targeting solar technology improvements related to power electronics and balance of system (BOS) hardware technologies to reduce the installed cost of solar photovoltaic (PV) electricity and...

  15. Rethinking components: From hardware and software to systems

    E-Print Network [OSTI]

    Messerschmitt, David G.

    2007-01-01

    and C. Syperski, Software Ecosystem: Understanding anComponents: From Hardware and Software to Systems [7] D.BThe flexible factory,[ Software Development Mag. , Nov. 12,

  16. Energy and task management in energy harvesting wireless sensor networks for structural health monitoring

    E-Print Network [OSTI]

    Steck, Jamie Bradley

    2009-01-01

    A wireless sensor network (WSN) is composed of a collectionmanagement used on systems, a WSN must have a method foras hardware advances and WSN demands expand. Energy

  17. ARCHITECTURE AND MAIN HARDWARE COMPONENTS OF THE FEL CONTROL SYSTEM

    E-Print Network [OSTI]

    Kozak, Victor R.

    ARCHITECTURE AND MAIN HARDWARE COMPONENTS OF THE FEL CONTROL SYSTEM E.N. Dementiev, V.R. Kozak, E general structure and listing the main features and hardware of individual components. Comparative as the reasons for choosing certain standards. Main issues of the future development of the control system

  18. A HARDWARE ALGORITHM FOR HIGH SPEED MORPHEME EXTRACTION

    E-Print Network [OSTI]

    A HARDWARE ALGORITHM FOR HIGH SPEED MORPHEME EXTRACTION AND ITS IMPLEMENTATION Toshikazu Fukushima- gorithms (Matsumoto, 1986) (Haas, 1987) (Ryt- ter, 1987) -(Fukushima, 1990b) have been pro- posed. However speed-up (Fukushima, 1989b) -(Fukushima, 1990a). This paper describes a new hardware algorithm for high

  19. A verified development of hardware using CSP B

    E-Print Network [OSTI]

    Schneider, Steve

    A verified development of hardware using CSP B Alistair McEwan Department of Computing University show how a combination of the process algebra CSP and the state-based formalism B, combined into a single notation called CSP B can be used in the formal development of hardware. The use of CSP B

  20. The Yin and Yang of Hardware Heterogeneity: Can Software Survive?

    E-Print Network [OSTI]

    McKinley, Kathryn S.

    . As processor speeds increased, the costs of abstraction reduced in each hardware generation. Unfortu- nately, physical limits in hardware are forcing a disruptive break in this virtuous cycle of innovation, in part. Shrinking transistors lowers their gate delay and until recently translated into faster clock fre- quencies

  1. Fair and Comprehensive Methodology for Comparing Hardware Performance of Fourteen

    E-Print Network [OSTI]

    Gaj, Krzysztof

    Fair and Comprehensive Methodology for Comparing Hardware Performance of Fourteen Round Two SHA-3 to make it fair, transparent, practical, and ac- ceptable for the majority of the cryptographic community it to the comparison of hardware performance of 14 Round 2 SHA-3 candidates. The most important aspects of our

  2. SPH Simulations with Reconfigurable Hardware Accelerator

    E-Print Network [OSTI]

    N. Nakasato; T. Hamada; T. Fukushige

    2006-04-13

    We present a novel approach to accelerate astrophysical hydrodynamical simulations. In astrophysical many-body simulations, GRAPE (GRAvity piPE) system has been widely used by many researchers. However, in the GRAPE systems, its function is completely fixed because specially developed LSI is used as a computing engine. Instead of using such LSI, we are developing a special purpose computing system using Field Programmable Gate Array (FPGA) chips as the computing engine. Together with our developed programming system, we have implemented computing pipelines for the Smoothed Particle Hydrodynamics (SPH) method on our PROGRAPE-3 system. The SPH pipelines running on PROGRAPE-3 system have the peak speed of 85 GFLOPS and in a realistic setup, the SPH calculation using one PROGRAPE-3 board is 5-10 times faster than the calculation on the host computer. Our results clearly shows for the first time that we can accelerate the speed of the SPH simulations of a simple astrophysical phenomena using considerable computing power offered by the hardware.

  3. System Setup Track-A-Worm requires the following major hardware components

    E-Print Network [OSTI]

    1 System Setup Track-A-Worm requires the following major hardware components: A stereomicroscope). The hardware used in our system is shown in Figure 1. For alternative hardware, please consider choosing a fast-A-Worm software to accommodate different hardware. Figure 1. Track-A-Worm hardware setup. The major components

  4. Comparison of leading parallel NAS file systems on commodity hardware

    SciTech Connect (OSTI)

    Hedges, R; Fitzgerald, K; Gary, M; Stearman, D M

    2010-11-08

    High performance computing has experienced tremendous gains in system performance over the past 20 years. Unfortunately other system capabilities, such as file I/O, have not grown commensurately. In this activity, we present the results of our tests of two leading file systems (GPFS and Lustre) on the same physical hardware. This hardware is the standard commodity storage solution in use at LLNL and, while much smaller in size, is intended to enable us to learn about differences between the two systems in terms of performance, ease of use and resilience. This work represents the first hardware consistent study of the two leading file systems that the authors are aware of.

  5. The NUCLARR databank: Human reliability and hardware failure data for the nuclear power industry

    SciTech Connect (OSTI)

    Reece, W.J.

    1993-05-01

    Under the sponsorship of the US Nuclear Regulatory Commission (NRC), the Nuclear Computerized Library for Assessing Reactor Reliability (NUCLARR) was developed to provide human reliability and hardware failure data to analysts in the nuclear power industry. This IBM-compatible databank is contained on a set of floppy diskettes which include data files and a menu-driven system for locating, reviewing, sorting, and retrieving the data. NUCLARR contains over 2500 individual data records, drawn from more, than 60 sources. The system is upgraded annually, to include additional human error and hardware component failure data and programming enhancements (i.e., increased user-friendliness). NUCLARR is available from the NRC through project staff at the INEL.

  6. An Integrated Hardware-Software CosimulationEnvironment for Heterogeneous SystemsPrototyping

    E-Print Network [OSTI]

    Ha, Soonhoi

    An Integrated Hardware-Software CosimulationEnvironment for Heterogeneous Systems - In this paper, we present a hardware-software cosimulation environment for heterogeneoussystems of heterogeneous systems whose hardware and software components are interacting. Traditionally, the task has been

  7. Recovery Act: Energy Efficiency of Data Networks through Rate Adaptation (EEDNRA) - Final Technical Report

    SciTech Connect (OSTI)

    Matthew Andrews; Spyridon Antonakopoulos; Steve Fortune; Andrea Francini; Lisa Zhang

    2011-07-12

    This Concept Definition Study focused on developing a scientific understanding of methods to reduce energy consumption in data networks using rate adaptation. Rate adaptation is a collection of techniques that reduce energy consumption when traffic is light, and only require full energy when traffic is at full provisioned capacity. Rate adaptation is a very promising technique for saving energy: modern data networks are typically operated at average rates well below capacity, but network equipment has not yet been designed to incorporate rate adaptation. The Study concerns packet-switching equipment, routers and switches; such equipment forms the backbone of the modern Internet. The focus of the study is on algorithms and protocols that can be implemented in software or firmware to exploit hardware power-control mechanisms. Hardware power-control mechanisms are widely used in the computer industry, and are beginning to be available for networking equipment as well. Network equipment has different performance requirements than computer equipment because of the very fast rate of packet arrival; hence novel power-control algorithms are required for networking. This study resulted in five published papers, one internal report, and two patent applications, documented below. The specific technical accomplishments are the following: • A model for the power consumption of switching equipment used in service-provider telecommunication networks as a function of operating state, and measured power-consumption values for typical current equipment. • An algorithm for use in a router that adapts packet processing rate and hence power consumption to traffic load while maintaining performance guarantees on delay and throughput. • An algorithm that performs network-wide traffic routing with the objective of minimizing energy consumption, assuming that routers have less-than-ideal rate adaptivity. • An estimate of the potential energy savings in service-provider networks using feasibly-implementable rate adaptivity. • A buffer-management algorithm that is designed to reduce the size of router buffers, and hence energy consumed. • A packet-scheduling algorithm designed to minimize packet-processing energy requirements. Additional research is recommended in at least two areas: further exploration of rate-adaptation in network switching equipment, including incorporation of rate-adaptation in actual hardware, allowing experimentation in operational networks; and development of control protocols that allow parts of networks to be shut down while minimizing disruption to traffic flow in the network. The research is an integral part of a large effort within Bell Laboratories, Alcatel-Lucent, aimed at dramatic improvements in the energy efficiency of telecommunication networks. This Study did not explicitly consider any commercialization opportunities.

  8. A power aware partitioning framework for hardware-software codesign 

    E-Print Network [OSTI]

    Kappagantula, Vijay Rama Pramod

    2003-01-01

    Existing approaches in hardware-software partitioning do not consider the maximum available system power while making the partitioning decision. Such a decision is sensitive to design efficiency when the target system is reconfigurable and supports...

  9. Gate-Level Characterization: Foundations and Hardware Security Applications

    E-Print Network [OSTI]

    Potkonjak, Miodrag

    Security Keywords Gate-level characterization, thermal conditioning, hardware Trojan horse, manufacturing leakage energy, ever increasing sub- strate noise, profound and intrinsic manufacturing variabil- ity (MV rights management. However, GLC is challenging due to the existence of manufacturing variability (MV

  10. Database architecture (R)evolution: New hardware vs. new software

    E-Print Network [OSTI]

    Madden, Samuel R.

    The last few years have been exciting for data management system designers. The explosion in user and enterprise data coupled with the availability of newer, cheaper, and more capable hardware have lead system designers ...

  11. Future value chains in the computer hardware industry

    E-Print Network [OSTI]

    Roy, Shaunak, S.M. Massachusetts Institute of Technology

    2006-01-01

    Companies in the computer hardware industry can benefit by incorporating future business scenarios in their present decision-making processes. Any decision regarding strategic supply chain design is one such area where ...

  12. Towards An Automated Approach to Hardware/Software Decomposition

    E-Print Network [OSTI]

    Qin, Shengchao

    We propose in this paper an algebraic approach to hard-ware/software partitioning in Verilog Hardware Description Language (HDL). We explore a collection of algebraic laws for Verilog programs, from which we design a set ...

  13. Hardware/Software Co-Design via Specification Refinement

    E-Print Network [OSTI]

    Peck, Wesley Graham

    2011-12-31

    implementation architecture. This work provides two contributions that ease the implementation process. The Rosetta synthesis capability generates hardware/software co-designed implementations from specifications that contain low level implementation details...

  14. Experiments in Automating Hardware Verification using Inductive Proof Planning 

    E-Print Network [OSTI]

    Cantu, Francisco; Bundy, Alan; Smaill, Alan; Basin, David

    1996-01-01

    We present a new approach to automating the verification of hardware designs based on planning techniques. A database of methods is developed that combines tactics, which construct proofs, using specifications of their ...

  15. Pump apparatus including deconsolidator

    DOE Patents [OSTI]

    Sonwane, Chandrashekhar; Saunders, Timothy; Fitzsimmons, Mark Andrew

    2014-10-07

    A pump apparatus includes a particulate pump that defines a passage that extends from an inlet to an outlet. A duct is in flow communication with the outlet. The duct includes a deconsolidator configured to fragment particle agglomerates received from the passage.

  16. ECE 587 Hardware/Software Co-Design Lecture 10 Software Processor Modeling II

    E-Print Network [OSTI]

    Wang, Jia

    ECE 587 ­ Hardware/Software Co-Design Lecture 10 Software Processor Modeling II Professor Jia Wang ­ Hardware/Software Co-Design Spring 2015 1/20 #12;Reading Assignment This lecture: 3.4 Next lecture: 3.5 ECE 587 ­ Hardware/Software Co-Design Spring 2015 2/20 #12;Outline Overview Hardware Abstraction Layer

  17. Compiling Application-Specific Hardware Mihai Budiu and Seth Copen Goldstein

    E-Print Network [OSTI]

    Goldstein, Seth Copen

    Compiling Application-Specific Hardware Mihai Budiu and Seth Copen Goldstein Carnegie Mellon for imple- menting Application-Specific Hardware. ASH is based on automatic hardware synthesis from high CASH, a scalable compiler framework for ASH, which generates hardware from programs written in C. Our

  18. From UML to HDL: a Model Driven Architectural Approach to Hardware-Software Co-Design

    E-Print Network [OSTI]

    Thornton, Mitchell

    From UML to HDL: a Model Driven Architectural Approach to Hardware-Software Co-Design Frank P the problem of hardware/software co-design via an open source laboratory for studying hardware- based system descriptions that can be implemented in either hardware or software. Utilizing component

  19. 2. Computer hardware David Keil Computer Science I 8/14 D. Keil, 8/13

    E-Print Network [OSTI]

    Keil, David M.

    2. Computer hardware David Keil Computer Science I 8/14 D. Keil, 8/13 David Keil Computer Science I Using Java 2. Hardware 6/14 1 David M. Keil, Framingham State University CSCI 152 Computer Science I-language programs 2. Computer hardware David Keil Computer Science I Using Java 2. Hardware 6/14 2 Inquiry · How

  20. Modular Full-System Verification of Hardware Muralidaran Vijayaraghavan and Joonwon Choi

    E-Print Network [OSTI]

    Modular Full-System Verification of Hardware Muralidaran Vijayaraghavan and Joonwon Choi 1 of full-system verification for hardware designs. What does a full-system verification for a hardware of how to give a hardware specification and its implementation, and what the respective semantics are

  1. DAQ hardware and software development for the ATLAS Pixel Detector

    E-Print Network [OSTI]

    Stramaglia, Maria Elena; The ATLAS collaboration

    2015-01-01

    In 2014, the Pixel Detector of the ATLAS experiment has been extended by about 12 million pixels thanks to the installation of the Insertable B-Layer (IBL). Data-taking and tuning procedures have been implemented along with newly designed read-out hardware to support high bandwidth for data readout and calibration. The hardware is supported by an embedded software stack running on the read-out boards. The same boards will be used to upgrade the read-out bandwidth for the two outermost layers of the ATLAS Pixel Barrel (54 million pixels). We present the IBL read-out hardware and the supporting software architecture used to calibrate and operate the 4-layer ATLAS Pixel detector. We discuss the technical implementations and status for data taking, validation of the DAQ system in recent cosmic ray data taking, in-situ calibrations, and results from additional tests in preparation for Run 2 at the LHC.

  2. Datacenter-Scale Network Research on FPGAs Zhangxi Tan

    E-Print Network [OSTI]

    Asanovi?, Krste

    Datacenter-Scale Network Research on FPGAs Zhangxi Tan Computer Science Division UC Berkeley, CA an FPGA-based datacenter network simulator to allow researchers to rapidly experiment with O(10, 000) node datacenter network architectures. We configure the FPGA hardware to implement abstract models of key dat

  3. An FPGA-based Simulator for Datacenter Networks Zhangxi Tan

    E-Print Network [OSTI]

    Asanovic, Krste

    An FPGA-based Simulator for Datacenter Networks Zhangxi Tan Computer Science Division UC Berkeley an FPGA-based datacenter network simulator for researchers to rapidly experiment with O(10,000) node datacenter network architectures. Our simulation approach configures the FPGA hardware to implement abstract

  4. Spent fuel disassembly hardware and other non-fuel bearing components: characterization, disposal cost estimates, and proposed repository acceptance requirements

    SciTech Connect (OSTI)

    Luksic, A.T.; McKee, R.W.; Daling, P.M.; Konzek, G.J.; Ludwick, J.D.; Purcell, W.L.

    1986-10-01

    There are two categories of waste considered in this report. The first is the spent fuel disassembly (SFD) hardware. This consists of the hardware remaining after the fuel pins have been removed from the fuel assembly. This includes end fittings, spacer grids, water rods (BWR) or guide tubes (PWR) as appropriate, and assorted springs, fasteners, etc. The second category is other non-fuel-bearing (NFB) components the DOE has agreed to accept for disposal, such as control rods, fuel channels, etc., under Appendix E of the standard utiltiy contract (10 CFR 961). It is estimated that there will be approximately 150 kg of SFD and NFB waste per average metric ton of uranium (MTU) of spent uranium. PWR fuel accounts for approximately two-thirds of the average spent-fuel mass but only 50 kg of the SFD and NFB waste, with most of that being spent fuel disassembly hardware. BWR fuel accounts for one-third of the average spent-fuel mass and the remaining 100 kg of the waste. The relatively large contribution of waste hardware in BWR fuel, will be non-fuel-bearing components, primarily consisting of the fuel channels. Chapters are devoted to a description of spent fuel disassembly hardware and non-fuel assembly components, characterization of activated components, disposal considerations (regulatory requirements, economic analysis, and projected annual waste quantities), and proposed acceptance requirements for spent fuel disassembly hardware and other non-fuel assembly components at a geologic repository. The economic analysis indicates that there is a large incentive for volume reduction.

  5. Comprehensive Hardware and Software Support for Operating Systems

    E-Print Network [OSTI]

    Torrellas, Josep

    Comprehensive Hardware and Software Support for Operating Systems to Exploit MP Memory Hierarchies are becoming increasingly popular. Since many of the workloads running on these machines are operating-system intensive, we are interested in exploring the types of support for the operating system that the memory

  6. HARDWARE IMPLEMENTATION OF THE MEDIANRATIONAL HYBRID FILTERS FOR COLOUR IMAGES

    E-Print Network [OSTI]

    Gabbouj, Moncef

    ­mail: bernac@ipl.univ.trieste.it ABSTRACT A new class of nonlinear Filters called Vector Median Rational Hybrid], and of the Directional­Distance Filter (DDF), reported in [4]. In this paper we also present a hardware implementation in FPGA's. Since implementations of the median filter are widely #12; reported in literature, in this work

  7. Hardware Implementation of the LMS Adaptive Filter for a

    E-Print Network [OSTI]

    Slatton, Clint

    Hardware Implementation of the LMS Adaptive Filter for a Brain-Machine Interface March 13, 2002@cnel.ufl.edu Advisors: Dr. José C. Principe Dr. Karl Gugel #12;Outline · Introduction · BMI Project Overview · LMS Adaptive Filter · TI C33 DSP · C33 PCI Development Board · Mathematics in DSP · LMS in DSP · Results

  8. Hardware Security for Device Authentication in the Smart Grid

    E-Print Network [OSTI]

    Murawski, Andrzej

    Hardware Security for Device Authentication in the Smart Grid Andrew J. Paverd and Andrew P. Martin. Secure communication between devices is a key aspect of smart grid security. In the future smart home environment, various smart devices, appliances and energy management systems will communicate with each other

  9. Runtime Assignment of Reconfigurable Hardware Components for Image Processing Pipelines

    E-Print Network [OSTI]

    Meleis, Waleed

    Runtime Assignment of Reconfigurable Hardware Components for Image Processing Pipelines Heather balance the benefits and costs of using FPGAs. Image processing applications of- ten consist of a pipeline implementations of image processing algorithms for a given problem. The pipeline assignment problem chooses from

  10. A Geographic Information System (GIS) integrates hardware, software, and data

    E-Print Network [OSTI]

    Gilbes, Fernando

    1 A Geographic Information System (GIS) integrates hardware, software, and data for capturing 1 2 34 5 #12;3 Geographic Information Systems (GIS) are specialized computer programs designed, managing, analyzing, and displaying all forms of geographically referenced information. GIS allows us

  11. Scalable Asynchronous Hardware Protocol Verification for Compositions with Relative Timing

    E-Print Network [OSTI]

    Stevens, Ken

    verification ensures correctness of a system given a required set of properties. Scalability due to state exploScalable Asynchronous Hardware Protocol Verification for Compositions with Relative Timing Krishnaji Desai Kenneth S. Stevens University of Utah Electrical and Computer Engineering Department

  12. Hardware-Accelerated Texture Advection For Unsteady Flow Visualization

    E-Print Network [OSTI]

    Erlebacher, Gordon

    animations of over 65,000 particles at 2 frames/sec on an SGI Octane with EMXI graphics. High image quality is achieved by careful attention to edge effects, noise frequency, and image enhancement. We provide not possible before [9], an enhancement not previously possible. In this paper, we propose a hardware

  13. Guidelines on Hardware-Rooted Security in Mobile

    E-Print Network [OSTI]

    Guidelines on Hardware- Rooted Security in Mobile Devices (Draft) Recommendationsof the National Franklin Andrew Regenscheid Computer Security Division Information Technology Laboratory National Institute for the cost-effective security and privacy of other than national security-related information in Federal

  14. Finding mold removal directions using graphics hardware Rahul Khardekar

    E-Print Network [OSTI]

    McMains, Sara

    Finding mold removal directions using graphics hardware Rahul Khardekar University of California, Berkeley Sara McMains University of California, Berkeley 1 Introduction In molding and casting manufacturing processes, molten raw ma- terial is shaped in molds from which the resulting part must be re

  15. SHard: a Scheme to Hardware Compiler Xavier Saint-Mleux

    E-Print Network [OSTI]

    Feeley, Marc

    , system cost, time-to-market, production volume, processing speed, power consumption, reliability better perfor- mance and power consumption than a software implementation, typically at a higher that is incrementally transformed into hardware until the required performance is achieved. This is often a manual

  16. CONTROL SYSTEM OF VEPP-2000 COLLIDER (SOFTWARE, HARDWARE)

    E-Print Network [OSTI]

    Kozak, Victor R.

    CONTROL SYSTEM OF VEPP-2000 COLLIDER (SOFTWARE, HARDWARE) D.E.Berkaev, P.B.Cheblakov, V, implementation and functionality of the software of the collider control system. The software according. Control system software is based on several TCP/IP connected PC platforms working under operating system

  17. Corrosion investigation of coatings for surface protection of military hardware

    SciTech Connect (OSTI)

    Lindsey, N.; Vasanth, K.L.

    1996-10-01

    A product improvement program (PIP) for the surface finish of some steel military hardware has been recently initiated by the Navy. Presently the metal cleaning methods, interior and exterior surface finishes and corrosion protection requirements for such hardware are specified in MIL-P-18948. The coated hardware are stored in a warehouse structure for long durations. Because these storage places are not environmentally controlled (that is, no temperature or humidity control) the corrosion protection has not been adequate. The exterior surfaces of the hardware are coated with a corrosion inhibiting alkyd primer coating (TT-P-664) or a rust inhibiting lacquer primer coating (MIL-P-11414) to a thickness of 0.4 to 0.6 mils. The exterior color paint, (MIL-E-52891 or MIL-P11195), is applied to a thickness of 1.5 mils. The investigation of various coatings to replace the present system is an ongoing effort. The coatings have been examined from a corrosion protection vantage point and results have been correlated. The coatings were evaluated by exposing them to natural marine atmosphere and seawater wetdown tests. The coatings were also exposed to a 5.0% sodium chloride solution in a laboratory environmental salt fog chamber for 500 hours. Selected coatings were examined using Electrochemical Impedance Spectroscopy (EIS). The results obtained from field tests, salt fog, and EIS measurements are discussed.

  18. Componentizing Hardware/Software Interface Kecheng Hao and Fei Xie

    E-Print Network [OSTI]

    Xie, Fei

    optimized embedded systems de- mands hardware/software (HW/SW) co-design. A key challenge in co-design is the design of HW/SW interfaces, which is often a design bottleneck. We propose a novel approach to HW/SW interface design based on the concept of bridge component. Bridge components fill the HW/SW semantic gap

  19. High Level antitative Hardware Prediction Modeling using Statistical methods

    E-Print Network [OSTI]

    Bertels, Koen

    essential to have efficient prediction models to drive early HW-SW partitioning and co-design. In this paper development and HW-SW co-design. Given an application composed of different kernels, in order to map one-level language description as input, enabling hardware prediction in the early design stages. We calibrate

  20. Benchmarking in Wireless Networks Shafqat Ur Rehman, Thierry Turletti, Walid Dabbous

    E-Print Network [OSTI]

    Boyer, Edmond

    1 Benchmarking in Wireless Networks Shafqat Ur Rehman, Thierry Turletti, Walid Dabbous Abstract--Experimentation is evolving as a viable and realistic performance analysis approach in wireless networking research. Realism is provisioned by deploying real software (network stack, drivers, OS), and hardware (wireless cards, network

  1. EmergeNet: Robust, Rapidly Deployable Cellular Networks Daniel Iland and Elizabeth M. Belding

    E-Print Network [OSTI]

    Belding-Royer, Elizabeth M.

    . Keywords-Cellular networks, community cellular networks, emergency networks, GSM, solar energy, wireless deployable, small scale cellular network. In this article, we describe EmergeNet, which addresses high load, limited bandwidth, and software or hardware failures. EmergeNet is uniquely well suited

  2. Summary of multi-core hardware and programming model investigations

    SciTech Connect (OSTI)

    Kelly, Suzanne Marie; Pedretti, Kevin Thomas Tauke; Levenhagen, Michael J.

    2008-05-01

    This report summarizes our investigations into multi-core processors and programming models for parallel scientific applications. The motivation for this study was to better understand the landscape of multi-core hardware, future trends, and the implications on system software for capability supercomputers. The results of this study are being used as input into the design of a new open-source light-weight kernel operating system being targeted at future capability supercomputers made up of multi-core processors. A goal of this effort is to create an agile system that is able to adapt to and efficiently support whatever multi-core hardware and programming models gain acceptance by the community.

  3. Web tools to monitor and debug DAQ hardware

    SciTech Connect (OSTI)

    Eugene Desavouret; Jerzy M. Nogiec

    2003-06-04

    A web-based toolkit to monitor and diagnose data acquisition hardware has been developed. It allows for remote testing, monitoring, and control of VxWorks data acquisition computers and associated instrumentation using the HTTP protocol and a web browser. This solution provides concurrent and platform independent access, supplementary to the standard single-user rlogin mechanism. The toolkit is based on a specialized web server, and allows remote access and execution of select system commands and tasks, execution of test procedures, and provides remote monitoring of computer system resources and connected hardware. Various DAQ components such as multiplexers, digital I/O boards, analog to digital converters, or current sources can be accessed and diagnosed remotely in a uniform and well-organized manner. Additionally, the toolkit application supports user authentication and is able to enforce specified access restrictions.

  4. Suppression of quantum chaos in a quantum computer hardware

    SciTech Connect (OSTI)

    Lages, J.; Shepelyansky, D. L. [Laboratoire de Physique Theorique, UMR 5152 du CNRS, Universite Paul Sabatier, 31062 Toulouse Cedex 4 (France)

    2006-08-15

    We present numerical and analytical studies of a quantum computer proposed by the Yamamoto group in Phys. Rev. Lett. 89, 017901 (2002). The stable and quantum chaos regimes in the quantum computer hardware are identified as a function of magnetic field gradient and dipole-dipole couplings between qubits on a square lattice. It is shown that a strong magnetic field gradient leads to suppression of quantum chaos.

  5. Suppression of quantum chaos in a quantum computer hardware

    E-Print Network [OSTI]

    J. Lages; D. L. Shepelyansky

    2005-10-14

    We present numerical and analytical studies of a quantum computer proposed by the Yamamoto group in Phys. Rev. Lett. 89, 017901 (2002). The stable and quantum chaos regimes in the quantum computer hardware are identified as a function of magnetic field gradient and dipole-dipole couplings between qubits on a square lattice. It is shown that a strong magnetic field gradient leads to suppression of quantum chaos.

  6. Markovian Energy-Based Computer Vision Algorithms on Graphics Hardware

    E-Print Network [OSTI]

    Mignotte, Max

    Markovian Energy-Based Computer Vision Algorithms on Graphics Hardware Pierre-Marc Jodoin, Max Mignotte, and Jean-Fran¸cois St-Amour Universit´e de Montr´eal, DIRO, P.O. Box 6128, Studio Centre-Ville, Montr´eal, Qu´ebec, H3C 3J7 {jodoinp, mignotte, stamourj}@iro.umontreal.ca Abstract. This paper shows

  7. Accounting for Classical Hardware in the Control of Quantum Devices

    E-Print Network [OSTI]

    Ian N. Hincks; Christopher Granade; Troy W. Borneman; D. G. Cory

    2014-09-29

    High fidelity coherent control of quantum systems is critical to building quantum devices and quantum computers. We provide a general optimal control framework for designing control sequences that account for hardware control distortions while maintaining robustness to environmental noise. We demonstrate the utility of our algorithm by presenting examples of robust quantum gates optimized in the presence of nonlinear distortions. We show that nonlinear classical controllers do not necessarily incur additional computational cost to pulse optimization, enabling more powerful quantum devices.

  8. Numerical studies of galaxy formation using special purpose hardware

    E-Print Network [OSTI]

    Matthias Steinmetz

    2002-01-25

    I review recent progress in numerically simulating the formation and evolution of galaxies in hierarchically clustering universes. Special emphasis is given to results based on high-resolution gas dynamical simulations using the N-body hardware integrator GRAPE. Applications address the origin of the spin of disk galaxies, the structure and kinematics of damped Lyman-alpha systems, and the origin of galaxy morphology and of galaxy scaling laws.

  9. 0 + 0 = 1 : the appliance model of selling software bundled with hardware

    E-Print Network [OSTI]

    Hein, Bettina

    2007-01-01

    The business model of selling software bundled with hardware is called the appliance model. As hardware becomes less and less expensive and open source software is being offered for free, the traditional business model of ...

  10. Hardware-aware motion estimation search algorithm development for high-efficiency video coding (HEVC) standard

    E-Print Network [OSTI]

    Sinangil, Mahmut E.

    This work presents a hardware-aware search algorithm for HEVC motion estimation. Implications of several decisions in search algorithm are considered with respect to their hardware implementation costs (in terms of area ...

  11. Visualization of 3D Geologic maps: an example using volumetric clipping with hardware

    E-Print Network [OSTI]

    Caumon, Guillaume

    Visualization of 3D Geologic maps: an example using volumetric clipping with hardware Guillaume is never explicitly computed in three-dimensions, but filled by graphics hardware in screen space using

  12. Toward Lean Hardware/Software System Development: An Evaluation of Selected Complex Electronic System Development Methodologies

    E-Print Network [OSTI]

    Hou, Alex

    The development of electronic hardware and software has become a major component of major DoD systems. This report surveys a wide set of new electronic hardware/software development methods and develops a system to evaluate ...

  13. Programming and Hardware Aspects Pub. No. 01-999014-00, Rev. A0398

    E-Print Network [OSTI]

    Zhou, Pei

    VNMR Pulse Sequences Programming and Hardware Aspects Pub. No. 01-999014-00, Rev. A0398 #12;VNMR Pulse Sequences Programming and Hardware Aspects Pub. No. 01-999014-00, Rev. A0398 By Rolf Kyburz rolf

  14. Systems Using Hardware-in-the-Loop (Poster) Lundstrom, B.; Shirazi...

    Office of Scientific and Technical Information (OSTI)

    HARDWARE; LOOP; POSTER; Buildings; Electricity, Resources, and Buildings Systems; Solar Energy - Thermal ELECTRICITY; GRID; ICS; INTERCONNECTION; SYSTEM; EVALUATOR;...

  15. Component-based hardware/software co-verification for building trustworthy embedded systems q

    E-Print Network [OSTI]

    Xie, Fei

    -based approach to hardware/software co-verification of embedded systems using model checking. Embedded systemsComponent-based hardware/software co-verification for building trustworthy embedded systems q Fei systems require extensive verification. The close interactions between hardware and software of embedded

  16. Scaling of hybrid-electric vehicle powertrain components for Hardware-in-the-loop simulation

    E-Print Network [OSTI]

    Brennan, Sean

    Scaling of hybrid-electric vehicle powertrain components for Hardware-in-the-loop simulation: Hardware-in-the-loop Hybrid electric vehicle Buckingham Pi Theorem Battery model a b s t r a c t Hardware to correctly scale electric vehicle components, particularly the following subsystems: electric motor

  17. On Efficient Non-Interactive Oblivious Transfer with Tamper-Proof Hardware

    E-Print Network [OSTI]

    International Association for Cryptologic Research (IACR)

    On Efficient Non-Interactive Oblivious Transfer with Tamper-Proof Hardware Maria Dubovitskaya by using tamper-proof hardware tokens. His construction only needs few evaluations of a block cipher-interactive string OT using tamper-proof hardware tokens. While from one side our tokens need to be stateful, our

  18. ECE 587 Hardware/Software Co-Design Lecture 18 Software Synthesis II

    E-Print Network [OSTI]

    Wang, Jia

    a deadline is tolerable if overall service quality remains acceptable. ECE 587 ­ Hardware/Software Co a deadline is tolerable if overall service quality remains acceptable. ECE 587 ­ Hardware/Software Co a deadline is tolerable if overall service quality remains acceptable. ECE 587 ­ Hardware/Software Co

  19. ECE 587 Hardware/Software Co-Design Lecture 28 Final Exam Review

    E-Print Network [OSTI]

    Wang, Jia

    of Electrical and Computer Engineering Illinois Institute of Technology April 29, 2015 ECE 587 ­ Hardware/Software Verification ECE 587 ­ Hardware/Software Co-Design Spring 2015 3/46 #12;System Design Trends Traditional: boardECE 587 ­ Hardware/Software Co-Design Lecture 28 Final Exam Review Professor Jia Wang Department

  20. ECE 587 Hardware/Software Co-Design Lecture 09 Software Processor Modeling I

    E-Print Network [OSTI]

    Wang, Jia

    ECE 587 ­ Hardware/Software Co-Design Lecture 09 Software Processor Modeling I Professor Jia Wang ­ Hardware/Software Co-Design Spring 2015 1/22 #12;Reading Assignment This lecture: 3.4 Next lecture: 3.4 ECE 587 ­ Hardware/Software Co-Design Spring 2015 2/22 #12;Outline Software Processor Modeling Application

  1. ECE 587 Hardware/Software Co-Design Lecture 17 Software Synthesis I

    E-Print Network [OSTI]

    Wang, Jia

    ECE 587 ­ Hardware/Software Co-Design Lecture 17 Software Synthesis I Professor Jia Wang Department of Electrical and Computer Engineering Illinois Institute of Technology March 23, 2015 ECE 587 ­ Hardware/Software 587 ­ Hardware/Software Co-Design Spring 2015 2/19 #12;Outline Software Synthesis Code Generation ECE

  2. Watchdog: Hardware for Safe and Secure Manual Memory Management and Full Memory Safety

    E-Print Network [OSTI]

    Plotkin, Joshua B.

    Watchdog: Hardware for Safe and Secure Manual Memory Management and Full Memory Safety Santosh) to become the root cause of exploitable security vulnerabilities. This paper proposes Watchdog, a hardware full hardware-enforced memory safety at low overheads. 1. Introduction Languages such as C and C

  3. Transcending Static Deployment of Circuits: Dynamic Run-Time Systems and Mobile Hardware

    E-Print Network [OSTI]

    Kent, University of

    Transcending Static Deployment of Circuits: Dynamic Run-Time Systems and Mobile Hardware Processes of reconfigurable hardware has been shown in research and commercial applications. Unquestionably, this has. The advancements in this technology have particularly led to a convergence between software and hardware domains

  4. High-voltage pulse switching hardware for electro-optic studies of conducting aqueous solutions

    E-Print Network [OSTI]

    Augustine, Mathew P.

    High-voltage pulse switching hardware for electro-optic studies of conducting aqueous solutions 22 April 2002 The hardware necessary for the electro-optic study of conducting polyelectrolyte is to present the design of hardware that is applicable, available, and practical for biological electro

  5. An Infrastructure for Hardware-Software Co-design of Embedded Real-Time Java Applications

    E-Print Network [OSTI]

    Wagner, Flávio Rech

    An Infrastructure for Hardware-Software Co-design of Embedded Real-Time Java Applications Elias of Kansas, USA dandrews@ittc.ku.edu Abstract The partitioning of applications into hardware and software in hardware in the context of the Real Time Specification for Java (RTSJ) standard. There is a Java class

  6. Efficient Automata-Based Assertion-Checker Synthesis of SEREs for Hardware Emulation

    E-Print Network [OSTI]

    Zilic, Zeljko

    Efficient Automata-Based Assertion-Checker Synthesis of SEREs for Hardware Emulation Marc Boul allows the adoption of ABV in hardware emulation. Towards that goal, we introduce the algorithms. INTRODUCTION Hardware verification aims to ensure that a design fulfills its given specification by either

  7. WICT PROCEEDINGS, DECEMBER 2008 1 Meta-Functional Languages for Hardware Design and Verification

    E-Print Network [OSTI]

    Pace, Gordon J.

    WICT PROCEEDINGS, DECEMBER 2008 1 Meta-Functional Languages for Hardware Design and Verification of embedding hardware description lan- guages in general-purpose languages has been widely explored in the literature and has been shown to aid hardware design and verification. In this paper we ex- plore the use

  8. The Challenges of Hardware Synthesis from C-like Languages Stephen A. Edwards

    E-Print Network [OSTI]

    The Challenges of Hardware Synthesis from C-like Languages Stephen A. Edwards Department of integrated circuits we can fabricate imposes a continuing need for ways to de- scribe complex hardware as specification languages for digital hardware. Yet, tools based on this idea have seen little commercial interest

  9. We propose UNITD, a unified hardware coherence framework that integrates translation coherence into the

    E-Print Network [OSTI]

    Lebeck, Alvin R.

    1 Abstract We propose UNITD, a unified hardware coherence framework that integrates translation. For caches that hold instructions or data, coherence is almost invariably maintained with an all-hardware cache coherence protocol. Hardware controllers at the caches coordinate amongst them- selves

  10. Blind Optimization for Exploiting Hardware Dan Knights, Todd Mytkowicz, Peter F. Sweeney,

    E-Print Network [OSTI]

    Mozer, Michael C.

    Blind Optimization for Exploiting Hardware Features Dan Knights, Todd Mytkowicz, Peter F. Sweeney microprocessors. While there has been much work on hardware-aware optimizations, two factors limit their benefit use a simplified model of the hardware (e.g., they may be cache-aware but they may ignore other

  11. A Hardware Assisted High Performance PHK Memory Manager Wentong Li Saraju P. Mohanty Krishna Kavi

    E-Print Network [OSTI]

    Kavi, Krishna

    A Hardware Assisted High Performance PHK Memory Manager Wentong Li Saraju P. Mohanty Krishna Kavi that uses hardware assistance to improve the performance of a existing software allocator (PHK allocator, and the search is in the criti- cal path of allocator performance. Hardware allocators can perform parallel

  12. Graphics Hardware (2004) T. Akenine-Mller, M. McCool (Editors)

    E-Print Network [OSTI]

    Stanford University

    2004-01-01

    Graphics Hardware (2004) T. Akenine-Möller, M. McCool (Editors) Efficient Partitioning of Fragment Shaders for Multiple-Output Hardware Tim Foley, Mike Houston and Pat Hanrahan Stanford University for virtualizing shading resource limits in graphics hardware. The Recursive Dominator Split (RDS) algorithm

  13. Designing Modular Hardware Accelerators in C With ROCCC 2.0

    E-Print Network [OSTI]

    Najjar, Walid A.

    Designing Modular Hardware Accelerators in C With ROCCC 2.0 Jason Villarreal, Adrian Park Jacquard, Riverside {najjar, rhalstea}@cs.ucr.edu Abstract--While FPGA-based hardware accelerators have re- peatedly acceptance by application code developers. These platforms are typically programmed in a low level hardware

  14. Recommended Hardware and Software (documented by Echo360 as of Sept. 2013)

    E-Print Network [OSTI]

    Pittendrigh, Barry

    Recommended Hardware and Software (documented by Echo360 as of Sept. 2013) The following table and verified in house. While we make every attempt to support a wide variety of hardware and devices, we cannot Capture for Windows is not supported on netbook computers. OS Minimum Hardware for audio and display

  15. Case Study on Real-Time Visualization of Virtual Tubingen on Commodity PC Hardware

    E-Print Network [OSTI]

    Case Study on Real-Time Visualization of Virtual T¨ubingen on Commodity PC Hardware M. Meißner£ J amount of textures -- is one of the key problems. Until very recently, graphics hardware for commodity accomplish real-time frame up- dates on commodity PC Hardware. 1.1 Related Work Culling invisible objects

  16. Addressing the Challenges of Synchronization/Communication and Debugging Support in Hardware/Software Cosimulation

    E-Print Network [OSTI]

    Sherwood, Tim

    Addressing the Challenges of Synchronization/Communication and Debugging Support in Hardware component of ESL tools to simulate the hardware designs and software models concurrently. It helps of RTL memory from a software perspective. While cosimulation is fast compared to a complete hardware

  17. Network Management Network Management

    E-Print Network [OSTI]

    Giaccone, Paolo

    Network Management Pag. 1 Network Management Network management and QoS provisioning - 1Andrea of this license visit: http://creativecommons.org/licenses/by-nc- /3 0/ Network management and QoS provisioning ­ Chapter 9, Network Management, of the book Jim Kurose, Keith Ross, Computer Networking, A Top Down

  18. A Scalable Correlator Architecture Based on Modular FPGA Hardware, Reuseable Gateware, and Data Packetization

    E-Print Network [OSTI]

    Aaron Parsons; Donald Backer; Henry Chen; Pierre Droz; Terry Filiba; Jason Manley; David MacMahon; Peter McMahon; Arash Parsa; Andrew Siemion; Dan Werthimer; Melvyn Wright

    2009-03-17

    A new generation of radio telescopes is achieving unprecedented levels of sensitivity and resolution, as well as increased agility and field-of-view, by employing high-performance digital signal processing hardware to phase and correlate large numbers of antennas. The computational demands of these imaging systems scale in proportion to BMN^2, where B is the signal bandwidth, M is the number of independent beams, and N is the number of antennas. The specifications of many new arrays lead to demands in excess of tens of PetaOps per second. To meet this challenge, we have developed a general purpose correlator architecture using standard 10-Gbit Ethernet switches to pass data between flexible hardware modules containing Field Programmable Gate Array (FPGA) chips. These chips are programmed using open-source signal processing libraries we have developed to be flexible, scalable, and chip-independent. This work reduces the time and cost of implementing a wide range of signal processing systems, with correlators foremost among them,and facilitates upgrading to new generations of processing technology. We present several correlator deployments, including a 16-antenna, 200-MHz bandwidth, 4-bit, full Stokes parameter application deployed on the Precision Array for Probing the Epoch of Reionization.

  19. An Effective EMS Hardware and Software Interface- The Trained Operator 

    E-Print Network [OSTI]

    Cherry, C. L.

    1986-01-01

    at the plant maintenance reporting device. The operator is now interfacing with the EMS and using it to solve real problems in a particular build ing. On-the-job training (OJT) is an example of application training that can work well or not at all. 'l... HARDWARE AND SOFTWARE THE TRAINED OPER~TQR Christene ~. Cherry Johnson Controls Institute INTERFACE Milwaukee, ABSTRAC'l' A computerized Energy Management Sys tem (EMS) is a tool that allows the user to moni tor and control building heating...

  20. Resolution-independent surface rendering using programmable graphics hardware

    DOE Patents [OSTI]

    Loop, Charles T. (Bellevue, WA); Blinn, James Frederick (Bellevue, WA)

    2008-12-16

    Surfaces defined by a Bezier tetrahedron, and in particular quadric surfaces, are rendered on programmable graphics hardware. Pixels are rendered through triangular sides of the tetrahedra and locations on the shapes, as well as surface normals for lighting evaluations, are computed using pixel shader computations. Additionally, vertex shaders are used to aid interpolation over a small number of values as input to the pixel shaders. Through this, rendering of the surfaces is performed independently of viewing resolution, allowing for advanced level-of-detail management. By individually rendering tetrahedrally-defined surfaces which together form complex shapes, the complex shapes can be rendered in their entirety.

  1. Entwurf und Verifikation von Hardware/Software -SystemenEntwurf und Verifikation von Hardware/Software -Systemen Lehrstuhl fr Technische Informatik

    E-Print Network [OSTI]

    Ould Ahmedou, Mohameden

    Entwurf und Verifikation von Hardware/Software - SystemenEntwurf und Verifikation von Hardware/Software-Level- Konfigurat. Software: C/C++ global Header Skript-basierte Konfiguration Analyse- datenbank SystemC Simulation Bewertung hardwarenaher SoftwareEntwurf und Bewertung hardwarenaher Software C C R T OS R T OS PV / PVT PV

  2. Analytical Analysis of Data and Decision Fusion in Sensor Networks

    E-Print Network [OSTI]

    Gupta, Ajay

    accuracy and reliability of sensed readings of a network of wireless devices, while increasing the lifetime the significance of CSP might prompt hardware and software designers to optimize wireless sensor networks operations by simple averaging techniques. In practice, d is much larger than f. Therefore, total

  3. BAAP: Blackhole Attack Avoidance Protocol for Wireless Network

    E-Print Network [OSTI]

    Dharmaraja, S.

    BAAP: Blackhole Attack Avoidance Protocol for Wireless Network Saurabh Gupta Indian Institute without the contraint of special hardware and dependency on physical medium of wireless network. BAAP and router at the same time. Most of the previous research has focused on problems of routing

  4. GRAPESPH: Cosmological SPH simulations with the special purpose hardware GRAPE

    E-Print Network [OSTI]

    Matthias Steinmetz

    1995-04-15

    A combined N--body/SPH code is presented which benefits from the high speed of the special purpose hardware GRAPE (GRAvity PipE). Besides gravitational forces, GRAPE also returns the list of neighbours and can, therefore, be used to speed up the hydrodynamical part, too. After the interaction list has been passed, density, pressure forces, propagation and interpolation of particles etc. are calculated on the front end, a 50 MHz SUN SPARC 10. In order to combine SPH and GRAPE, possible limitations due to the hardware design of GRAPE are carefully analyzed and modifications compared to current SPH codes are discussed. The resulting code, GRAPESPH, is similarly flexible as TREESPH. It seems especially well suited to investigate the formation of individual objects in a large scale structure environment, like eg. galaxies or clusters. The total performance is at least half as good as treesph on a CRAY and for most applications it seems to be even better. The CPU time per time step is only slightly dependent on the clustering state. GRAPESPH, therefore, provides a very attractive alternative to the use of supercomputers in cosmology.

  5. SenSearch: GPS and Witness Assisted Tracking for Delay Tolerant Sensor Networks

    E-Print Network [OSTI]

    Cerpa, Alberto E.

    as a function of memory usage, power consumption, localization error and data delivery rate. I. INTRODUCTION platform. These days, most hardware in sensor networks is half the size of your typical cellphone

  6. Optimizing Wireless Network Protocols Using Real-Time Predictive Propagation Modeling

    E-Print Network [OSTI]

    Stancil, Daniel D.

    on the battlefield [1] and emergency disaster relief personnel coordinating efforts after a hurricane or earthquake in the network before they cause packets to be lost or delayed. Hardware Control (power, antenna, thresholds, etc

  7. Wireless sensor network planning with application to UWB localization in GPS-denied environments

    E-Print Network [OSTI]

    Jourdan, Damien, 1978-

    2006-01-01

    Wireless Sensor Networks (WSN) have received much attention in the past 5 years, and much progress has been made in designing hardware, communications protocols, routing, and sensor fusion algorithms. The planning and ...

  8. Simultaneous localization and tracking in wireless ad-hoc sensor networks

    E-Print Network [OSTI]

    Taylor, Christopher J. (Christopher Jorgen)

    2005-01-01

    In this thesis we present LaSLAT, a sensor network algorithm that uses range measurements between sensors and a moving target to simultaneously localize the sensors, calibrate sensing hardware, and recover the target's ...

  9. Implementing technical transitions through schedule-based policy : insights from the Military's Airborne Tactical Network

    E-Print Network [OSTI]

    Rohrbach, Amanda K. (Amanda Kaye)

    2013-01-01

    Due to a need for congestion relief, as well as a projected increase in capacity constraints, the US Military's Airborne Tactical Network (ATN) is at the onset of a technical transition of their communication hardware and ...

  10. Arduino Remote Infrared Network Adapter Ren Neff, Thomas Trimborn & Matthias Wbbeling

    E-Print Network [OSTI]

    Clausen, Michael

    #12;ARINA: Arduino Remote Infrared Network Adapter René Neff, Thomas Trimborn & Matthias Wübbeling photodiode IR diode resistor cables Arduino Mega 2560 Arduino Ethernet Shield breadboard 9 #12;Hardware II 10

  11. A quantum access network

    E-Print Network [OSTI]

    Bernd Fröhlich; James F. Dynes; Marco Lucamarini; Andrew W. Sharpe; Zhiliang Yuan; Andrew J. Shields

    2014-09-02

    The theoretically proven security of quantum key distribution (QKD) could revolutionise how information exchange is protected in the future. Several field tests of QKD have proven it to be a reliable technology for cryptographic key exchange and have demonstrated nodal networks of point-to-point links. However, so far no convincing answer has been given to the question of how to extend the scope of QKD beyond niche applications in dedicated high security networks. Here we show that adopting simple and cost-effective telecommunication technologies to form a quantum access network can greatly expand the number of users in quantum networks and therefore vastly broaden their appeal. We are able to demonstrate that a high-speed single-photon detector positioned at a network node can be shared between up to 64 users for exchanging secret keys with the node, thereby significantly reducing the hardware requirements for each user added to the network. This point-to-multipoint architecture removes one of the main obstacles restricting the widespread application of QKD. It presents a viable method for realising multi-user QKD networks with resource efficiency and brings QKD closer to becoming the first widespread technology based on quantum physics.

  12. DISTRIBUTED POSE AVERAGING IN CAMERA NETWORKS VIA CONSENSUS ON SE(3) Roberto Tron, Rene Vidal

    E-Print Network [OSTI]

    DISTRIBUTED POSE AVERAGING IN CAMERA NETWORKS VIA CONSENSUS ON SE(3) Roberto Tron, Ren´e Vidal distributed algorithms for esti- mating the average pose of an object viewed by a localized network of camera networks; pose estimation; consensus; optimization on manifolds. 1. INTRODUCTION Recent hardware

  13. The Network Pump is a Govern-ment off-the-shelf (GOTS) High As-

    E-Print Network [OSTI]

    of acknowledgement. The Network Pump® implements a NRL- patented algorithm that statistically modulates the delayThe Network Pump® is a Govern- ment off-the-shelf (GOTS) High As- surance "One-Way" Guard that ena Pump® works with any operating system on any hardware platform that supports a TCP/IP network. NRL

  14. Abstract--A new architecture is proposed for digital multiphase modulators that leads to a natural hardware

    E-Print Network [OSTI]

    hardware efficient realization without compromise in hardware or performance. The combined modulator time. Hardware efficiency is achieved by using only a single high resolution block that is time shared requiring significant additional hardware per phase. The duty cycle command is updated at the fast rate of N

  15. Optical Hardware Accelerators using Nonlinear Dispersion Modes for Energy Efficient Computing

    E-Print Network [OSTI]

    Jalali, Bahram

    2015-01-01

    This paper proposes a new class of hardware accelerators to alleviate bottlenecks in the acquisition, analytics, storage and computation of information carried by wideband streaming signals.

  16. A Dynamically Reconfigurable Hardware Co-Processor for a Multi-Standard Wireless MAC Processor

    E-Print Network [OSTI]

    Nabi, S.W.; Vanderbauwhede, W.

    Nabi,S.W. Vanderbauwhede,W. Wells,C.C. NASA/ESA Conference on Adaptive Hardware and Systems pp 368-375 IEEE Computer Society Press

  17. Network Management Network Management

    E-Print Network [OSTI]

    Giaccone, Paolo

    Network Management Pag. 1 Network Management Andrea Bianco Telecommunication Network Group Network management and QoS provisioning - 1Andrea Bianco ­ TNG group - Politecnico di Torino Telecommunication management and QoS provisioning - 2Andrea Bianco ­ TNG group - Politecnico di Torino Stanford, California

  18. Hardware Architectures for Data-Intensive Computing Problems: A Case Study for String Matching

    SciTech Connect (OSTI)

    Tumeo, Antonino; Villa, Oreste; Chavarría-Miranda, Daniel

    2012-12-28

    DNA analysis is an emerging application of high performance bioinformatic. Modern sequencing machinery are able to provide, in few hours, large input streams of data, which needs to be matched against exponentially growing databases of known fragments. The ability to recognize these patterns effectively and fastly may allow extending the scale and the reach of the investigations performed by biology scientists. Aho-Corasick is an exact, multiple pattern matching algorithm often at the base of this application. High performance systems are a promising platform to accelerate this algorithm, which is computationally intensive but also inherently parallel. Nowadays, high performance systems also include heterogeneous processing elements, such as Graphic Processing Units (GPUs), to further accelerate parallel algorithms. Unfortunately, the Aho-Corasick algorithm exhibits large performance variability, depending on the size of the input streams, on the number of patterns to search and on the number of matches, and poses significant challenges on current high performance software and hardware implementations. An adequate mapping of the algorithm on the target architecture, coping with the limit of the underlining hardware, is required to reach the desired high throughputs. In this paper, we discuss the implementation of the Aho-Corasick algorithm for GPU-accelerated high performance systems. We present an optimized implementation of Aho-Corasick for GPUs and discuss its tradeoffs on the Tesla T10 and he new Tesla T20 (codename Fermi) GPUs. We then integrate the optimized GPU code, respectively, in a MPI-based and in a pthreads-based load balancer to enable execution of the algorithm on clusters and large sharedmemory multiprocessors (SMPs) accelerated with multiple GPUs.

  19. The NIDS Cluster: Scalable, Stateful Network Intrusion Detection on Commodity Hardware

    E-Print Network [OSTI]

    Tierney, Brian L

    2008-01-01

    Mai, M. , Paxson, V. , Sommer, R. : Dynamic Application-24) (1999) 2435–2463 3. Sommer, R. , Paxson, V. : ExploitingA. , Paxson, V. , Sommer, R. : Operational Experiences with

  20. Authenticity, Authority, and Assemblage Masculinity: Geek Identity and Hardware Production in Networked Spaces

    E-Print Network [OSTI]

    Ross, Ian W.

    2014-01-01

    announcement of Occulus Rift’s buyout by Facebook, we arecontention in the wake of the buyout announcement was one ofthe system following the buyout. The fear expressed by Lucky

  1. Software-Hardware Co-Defined Network Switch (SHADES) for a Label Switching Protocol

    E-Print Network [OSTI]

    Karadeniz, Turhan

    2015-01-01

    Kazemian, Mart Haitjema, Neda Beheshti, Stephen Stuart, andQueued Switch. 2000. [70] Neda Beheshti, Yashar Ganjali,

  2. Specifying and Verifying Hardware for Tamper-Resistant Software David Lie John Mitchell Chandramohan A. Thekkath

    E-Print Network [OSTI]

    Lee, Ruby B.

    Specifying and Verifying Hardware for Tamper-Resistant Software David Lie John Mitchell Abstract We specify a hardware architecture that supports tamper-resistant software by identifying) to compare executions of the idealized and actual models. In this approach, software tampering occurs

  3. Static Fault Attack on Hardware DES Registers Philippe Loubet-Moundi, Francis Olivier, and David Vigilant

    E-Print Network [OSTI]

    International Association for Cryptologic Research (IACR)

    Static Fault Attack on Hardware DES Registers Philippe Loubet-Moundi, Francis Olivier, and David deals with static faults which lie in between. A static fault modifies a value loaded in a volatile], quickly became a privileged target for DFA. #12;2 Static Fault Attacks on Hardware DES Registers Indeed

  4. How to Predict the Output of a Hardware Random Number Generator

    E-Print Network [OSTI]

    International Association for Cryptologic Research (IACR)

    How to Predict the Output of a Hardware Random Number Generator Markus Dichtl Siemens AG, Corporate Technology Email: Markus.Dichtl@siemens.com Abstract. A hardware random number generator was described at CHES 2002 in [Tka03]. In this paper, we analyze its method of generating randomness and

  5. D. Keil, 8/13 4. Hardware David Keil Introduction to Information Technology Spring 2015

    E-Print Network [OSTI]

    Keil, David M.

    D. Keil, 8/13 4. Hardware David Keil Introduction to Information Technology Spring 2015 David Keil Introduction to Information Technology Spring 2015 1 David M. Keil, Framingham State University CSCI 120 Introduction to Information Technology 4. Computer hardware 1. Digital processing and representation

  6. Phoenix: Detecting and Recovering from Permanent Processor Design Bugs with Programmable Hardware

    E-Print Network [OSTI]

    Torrellas, Josep

    Phoenix: Detecting and Recovering from Permanent Processor Design Bugs with Programmable Hardware, and Motorola processors, this paper proposes and evalu- ates Phoenix -- novel field-programmable on-chip hardware that de- tects and recovers from design defects. Phoenix taps key logic signals and, based

  7. What Scientific Applications can Benefit from Hardware Transactional Memory?

    SciTech Connect (OSTI)

    Schindewolf, M; Bihari, B; Gyllenhaal, J; Schulz, M; Wang, A; Karl, W

    2012-06-04

    Achieving efficient and correct synchronization of multiple threads is a difficult and error-prone task at small scale and, as we march towards extreme scale computing, will be even more challenging when the resulting application is supposed to utilize millions of cores efficiently. Transactional Memory (TM) is a promising technique to ease the burden on the programmer, but only recently has become available on commercial hardware in the new Blue Gene/Q system and hence the real benefit for realistic applications has not been studied, yet. This paper presents the first performance results of TM embedded into OpenMP on a prototype system of BG/Q and characterizes code properties that will likely lead to benefits when augmented with TM primitives. We first, study the influence of thread count, environment variables and memory layout on TM performance and identify code properties that will yield performance gains with TM. Second, we evaluate the combination of OpenMP with multiple synchronization primitives on top of MPI to determine suitable task to thread ratios per node. Finally, we condense our findings into a set of best practices. These are applied to a Monte Carlo Benchmark and a Smoothed Particle Hydrodynamics method. In both cases an optimized TM version, executed with 64 threads on one node, outperforms a simple TM implementation. MCB with optimized TM yields a speedup of 27.45 over baseline.

  8. A Fast hardware tracker for the ATLAS Trigger

    E-Print Network [OSTI]

    Pandini, Carlo Enrico; The ATLAS collaboration

    2015-01-01

    The trigger system at the ATLAS experiment is designed to lower the event rate occurring from the nominal bunch crossing at 40 MHz to about 1 kHz for a designed LHC luminosity of 10$^{34}$ cm$^{-2}$ s$^{-1}$. To achieve high background rejection while maintaining good efficiency for interesting physics signals, sophisticated algorithms are needed which require extensive use of tracking information. The Fast TracKer (FTK) trigger system, part of the ATLAS trigger upgrade program, is a highly parallel hardware device designed to perform track-finding at 100 kHz and based on a mixture of advanced technologies. Modern, powerful Field Programmable Gate Arrays (FPGA) form an important part of the system architecture, and the combinatorial problem of pattern recognition is solved by ~8000 standard-cell ASICs named Associative Memories. The availability of the tracking and subsequent vertex information within a short latency ensures robust selections and allows improved trigger performance for the most difficult sign...

  9. A Fast hardware Tracker for the ATLAS Trigger system

    E-Print Network [OSTI]

    Pandini, Carlo Enrico; The ATLAS collaboration

    2015-01-01

    The trigger system at the ATLAS experiment is designed to lower the event rate occurring from the nominal bunch crossing at 40 MHz to about 1 kHz for a designed LHC luminosity of 10$^{34}$ cm$^{-2}$ s$^{-1}$. After a very successful data taking run the LHC is expected to run starting in 2015 with much higher instantaneous luminosities and this will increase the load on the High Level Trigger system. More sophisticated algorithms will be needed to achieve higher background rejection while maintaining good efficiency for interesting physics signals, which requires a more extensive use of tracking information. The Fast Tracker (FTK) trigger system, part of the ATLAS trigger upgrade program, is a highly parallel hardware device designed to perform full-scan track-finding at the event rate of 100 kHz. FTK is a dedicated processor based on a mixture of advanced technologies. Modern, powerful, Field Programmable Gate Arrays form an important part of the system architecture, and the combinatorial problem of pattern r...

  10. A Fast Hardware Tracker for the ATLAS Trigger System

    E-Print Network [OSTI]

    Mark S. Neubauer; for the ATLAS Collaboration

    2011-10-10

    In hadron collider experiments, triggering the detector to store interesting events for offline analysis is a challenge due to the high rates and multiplicities of particles produced. Maintaining high trigger efficiency for the physics we are most interested in while at the same time suppressing high rate physics from inclusive QCD processes is a difficult but important problem. It is essential that the trigger system be flexible and robust, with sufficient redundancy and operating margin. Providing high quality track reconstruction over the full ATLAS detector by the start of processing at LVL2 is an important element to achieve these needs. As the instantaneous luminosity increases, the computational load on the LVL2 system will significantly increase due to the need for more sophisticated algorithms to suppress backgrounds. The Fast Tracker (FTK) is a proposed upgrade to the ATLAS trigger system. It is designed to enable early rejection of background events and thus leave more LVL2 execution time by moving track reconstruction into a hardware system that takes massively parallel processing to the extreme. The FTK system completes global track reconstruction with near offline resolution shortly after the start of LVL2 processing by rapidly finding and fitting tracks in the inner detector for events passing LVL1 using pattern recognition from a large, pre-computed bank of possible hit patterns. We describe the FTK system design and expected performance in the areas of b-tagging, {\\tau}-tagging, and lepton isolation which play and important role in the ATLAS physics program.

  11. Steady-state and transient thermal performance of subsea hardware

    SciTech Connect (OSTI)

    Zabaras, G.J.; Zhang, J.

    1998-06-01

    The thermal performance of subsea hardware is of ultimate importance to the economic development and reliable operation of deepwater subsea oil and gas systems because of the potential for hydrate formation. Results of numerical calculations are presented on the thermal performance of subsea equipment such as wellheads, tubing and flowline jumpers, and flowline field joints. In contrast to previous published studies on the thermal performance of insulated subsea wellbores and flowlines, this paper addresses the thermal performance of the subsea equipment that can provide weak thermal links for the subsea system. A two-dimensional (2D), general-purpose, finite-element, partial-differential equation solver was used to analyze the steady-state and transient thermal behavior at different cross sections of the subsea tree. This paper presents a new method for predicting pressure profiles in oil and gas wells. The method combines mechanistic flow-pattern transition criteria with physical models for pressure-loss and liquid-holdup calculations for each of the flow patterns considered. Past published methods relied heavily on empirical fit of limited field data. As a result, they are inaccurate when used outside the range of data upon which they are based. In contrast, the new method is universally applicable to all types of wells under all operating scenarios because it is based on fundamental physics rather than the curve-fit of field data. Its prediction performance has been demonstrated by extensive comparison to field data from a variety of wells.

  12. Proposing Individualization of the design of cryptographic hardware accelerators as

    E-Print Network [OSTI]

    International Association for Cryptologic Research (IACR)

    against side-channel attacks I. INTRODUCTION With the advent of wireless sensor networks (WSN. This is due to the fact that devices disappearing in a WSN are somewhat normal. I.e. some devices devices from a WSN and running an attack is feasible and can even go undetected by the owner of the WSN

  13. Countries Gasoline Prices Including Taxes

    Gasoline and Diesel Fuel Update (EIA)

    Crude oil, gasoline, heating oil, diesel, propane, and other liquids including biofuels and natural gas liquids. Natural Gas Exploration and reserves, storage, imports and...

  14. Multiply-agile encryption in high speed communication networks

    SciTech Connect (OSTI)

    Pierson, L.G. [Sandia National Labs., Albuquerque, NM (United States); Witzke, E.L. [RE/SPEC Inc., Albuquerque, NM (United States)

    1997-05-01

    Different applications have different security requirements for data privacy, data integrity, and authentication. Encryption is one technique that addresses these requirements. Encryption hardware, designed for use in high-speed communications networks, can satisfy a wide variety of security requirements if that hardware is key-agile, robustness-agile and algorithm-agile. Hence, multiply-agile encryption provides enhanced solutions to the secrecy, interoperability and quality of service issues in high-speed networks. This paper defines these three types of agile encryption. Next, implementation issues are discussed. While single-algorithm, key-agile encryptors exist, robustness-agile and algorithm-agile encryptors are still research topics.

  15. Precision Irrigators Network 

    E-Print Network [OSTI]

    Bynum, J.; Cothren, T.; Marek, T.; Piccinni, G.

    2007-01-01

    conservation including an "Agricultural Irrigation Water Use Management" BMPs section. The full TWDB Report 362 can be found at: http://www.twdb.state.tx.us/assistance/conservation/consindex.asp. DSS include the Texas High Plains Evapotranspiration Network...

  16. Neutralino relic density including coannihilations

    E-Print Network [OSTI]

    Paolo Gondolo; Joakim Edsjo

    1997-11-25

    We give an overview of our precise calculation of the relic density of the lightest neutralino, in which we included relativistic Boltzmann averaging, subthreshold and resonant annihilations, and coannihilation processes with charginos and neutralinos.

  17. Installation instructions, File Structure, and Hardware and Software Requirements for Groundwater Toolbox, version 1.1 (April 2015)

    E-Print Network [OSTI]

    1 Installation instructions, File Structure, and Hardware and Software Requirements for Groundwater of the distribution, and (C) the hardware and software requirements for the GW Toolbox. The installation instructions

  18. Hardware In The Loop Simulator in UAV Rapid Development Life Cycle

    E-Print Network [OSTI]

    Adiprawita, Widyawardana; Semibiring, Jaka

    2008-01-01

    Field trial is very critical and high risk in autonomous UAV development life cycle. Hardware in the loop (HIL) simulation is a computer simulation that has the ability to simulate UAV flight characteristic, sensor modeling and actuator modeling while communicating in real time with the UAV autopilot hardware. HIL simulation can be used to test the UAV autopilot hardware reliability, test the closed loop performance of the overall system and tuning the control parameter. By rigorous testing in the HIL simulator, the risk in the field trial can be minimized.

  19. Hardware design document for the Infrasound Prototype for a CTBT IMS station

    SciTech Connect (OSTI)

    Breding, D.R.; Kromer, R.P.; Whitaker, R.W.; Sandoval, T.

    1997-11-01

    The Hardware Design Document (HDD) describes the various hardware components used in the Comprehensive Test Ban Treaty (CTBT) Infrasound Prototype and their interrelationships. It divides the infrasound prototype into hardware configurations items (HWCIs). The HDD uses techniques such as block diagrams and parts lists to present this information. The level of detail provided in the following sections should be sufficient to allow potential users to procure and install the infrasound system. Infrasonic monitoring is a low cost, robust, and effective technology for detecting atmospheric explosions. Low frequencies from explosion signals propagate to long ranges (few thousand kilometers) where they can be detected with an array of sensors.

  20. Power Hardware-in-the-Loop (PHIL) Testing Facility for Distributed Energy Storage (Poster)

    SciTech Connect (OSTI)

    Neubauer.J.; Lundstrom, B.; Simpson, M.; Pratt, A.

    2014-06-01

    The growing deployment of distributed, variable generation and evolving end-user load profiles presents a unique set of challenges to grid operators responsible for providing reliable and high quality electrical service. Mass deployment of distributed energy storage systems (DESS) has the potential to solve many of the associated integration issues while offering reliability and energy security benefits other solutions cannot. However, tools to develop, optimize, and validate DESS control strategies and hardware are in short supply. To fill this gap, NREL has constructed a power hardware-in-the-loop (PHIL) test facility that connects DESS, grid simulator, and load bank hardware to a distribution feeder simulation.

  1. Design and implementation of a hardware-in-the-loop simulation system for small-scale UAV helicopters q

    E-Print Network [OSTI]

    Benmei, Chen

    Design and implementation of a hardware-in-the-loop simulation system for small-scale UAV: Hardware-in-the-loop simulation UAV Helicopter Flight control a b s t r a c t We present in the paper constructed unmanned-aerial-vehicle (UAV) helicopter systems. Real-time hardware-in-the-loop simulation is one

  2. Reiner Hartenstein, TU Kaiserslautern http://hartenstein.de CASHE stands for Computer-Aided Software / Hardware Engineering

    E-Print Network [OSTI]

    Hartenstein, Reiner

    -Aided Software / Hardware Engineering July 1993 Reiner Hartenstein: CASHE using a new Machine Paradigm; Codes/CASHE'93 - 2nd IFIP International Workshop on Hardware/Software Codesign, May 24 ­ 27, 1993 1 #12;Reiner Hartenstein, TU Kaiserslautern http://hartenstein.de CASHE stands for Computer-Aided Software / Hardware

  3. Bren School Computing Hardware Policy Faculty members are normally provided a new, desktop computer with standard Bren

    E-Print Network [OSTI]

    California at Santa Barbara, University of

    Bren School Computing Hardware Policy Faculty Faculty members are normally provided a new, desktop adequate computing hardware. MESM Students MESM students are not provided computers. They are provided on the hardware and software configuration for lab machine purchases. Users that purchase non-standard systems

  4. Designing Hardware that Supports Cycle-Accurate Deterministic Replay Brian Greskamp, Smruti R. Sarangi, and Josep Torrellas

    E-Print Network [OSTI]

    Torrellas, Josep

    Designing Hardware that Supports Cycle-Accurate Deterministic Replay Brian Greskamp, Smruti R://iacoma.cs.uiuc.edu Abstract Most computer hardware today is nondeterministic, meaning that two executions of a program verification and makes hardware faults detected during bringup more difficult to re- produce and analyze

  5. hierarchischer Beschreibungen, hierbei erfolgt eine Umsetzung des Hierarchie-Konzepts in Hardware mittels eines Handshake-Mechanismus.

    E-Print Network [OSTI]

    Ould Ahmedou, Mohameden

    6 hierarchischer Beschreibungen, hierbei erfolgt eine Umsetzung des Hierarchie-Konzepts in Hardware Entwurfsumgebung für die Umsetzung von C-Verhaltensspezi- fikationen in Hardware-Strukturen vorgestellt, sowie augenblicklichen Forschungsarbeiten liegen im Bereich Hardware/Software- Codesign in der Bereitstellung von

  6. Addressing the Energy-Delay Tradeoff in Wireless Networks with Load-Proportional Energy Usage

    E-Print Network [OSTI]

    Sikdar, Biplab

    Addressing the Energy-Delay Tradeoff in Wireless Networks with Load-Proportional Energy Usage Jie and achieve load-proportional energy usage. These techniques slow down the operation of the hardware and thus the energy-delay tradeoff while achieving load-proportional energy usage in wireless networks. The proposed

  7. EC--ME--SE 544 Networking the Physical World Prof. T.D.C. Little

    E-Print Network [OSTI]

    and potential applications 2. Embedded MCU hardware, system, radio; sunspot platform 3. Sampling, sensing; leader election; swarms 12. Databases concepts related to sensor networks 13. Autonomous vehicles; car Sensor Network 3. Collecting, Saving, and Visualizing Data from the Physical World 4. Steering the Car 5

  8. Solar Projects to Reduce Non-Hardware Balance of System Costs

    Office of Energy Efficiency and Renewable Energy (EERE)

    Seven projects are focused on creating tools and developing methods to reduce the cost of non-hardware components for installed solar energy systems and reducing market barriers. These projects...

  9. Generalized external interaction with tamper-resistant hardware with bounded information leakage

    E-Print Network [OSTI]

    Yu, Xiangyao

    This paper investigates secure ways to interact with tamper-resistant hardware leaking a strictly bounded amount of information. Architectural support for the interaction mechanisms is studied and performance implications ...

  10. Synthesis and Hardware Implementation of an Unmanned Aerial Vehicle Automatic Landing System Utilizing Quantitative Feedback Theory 

    E-Print Network [OSTI]

    Woodbury, Timothy Daniel

    2014-07-08

    that the control synthesis process using Quantitative Feedback Theory provides robust controllers with generally adequate performance, based on simulation and hardware results. The Quantitative Feedback Theory framework provides a good method for synthesizing...

  11. A Hardware Implementation of a Coherent SOQPSK-TG Demodulator for FEC Applications

    E-Print Network [OSTI]

    Rea Zanabria, Gino

    2011-03-31

    This thesis presents a hardware design of a coherent demodulator for shaped offset quadrature phase shift keying, telemetry group version (SOQPSK-TG) for use in forward error correction (FEC) applications. Implementation details for data sequence...

  12. Investigating Evolvable Hardware Classification for the BioSleeve Electromyographic Interface

    E-Print Network [OSTI]

    Glette, Kyrre

    Investigating Evolvable Hardware Classification for the BioSleeve Electromyographic Interface Kyrre signals. The BioSleeve is equipped with a high number of electromyographic (EMG) channels, with more

  13. Extreme Balance of System Hardware Cost Reduction (BOS-X) Funding Opportunity

    Broader source: Energy.gov [DOE]

    Under the Extreme Balance of System Hardware Cost Reduction (BOS-X) program, DOE is funding new components and system designs to overcome scientific, technological, and engineering barriers to...

  14. A Comparison of Hardware Implementations for Low-Level Vision Algorithms

    E-Print Network [OSTI]

    Gamble, Ed

    1989-11-01

    Early and intermediate vision algorithms, such as smoothing and discontinuity detection, are often implemented on general-purpose serial, and more recently, parallel computers. Special-purpose hardware implementations ...

  15. A comparative evaluation of high-level hardware synthesis using Reed-Solomon decoder

    E-Print Network [OSTI]

    Agarwal, Abhinav

    Using the example of a Reed-Solomon decoder, we provide insights into what type of hardware structures are needed to be generated to achieve specific performance targets. Due to the presence of run-time dependencies, ...

  16. Keeping Secrets in Hardware: the Microsoft Xbox(TM) Case Study

    E-Print Network [OSTI]

    Huang, Andrew "bunnie"

    2002-05-26

    This paper discusses the hardware foundations of the cryptosystem employed by the Xbox(TM) video game console from Microsoft. A secret boot block overlay is buried within a system ASIC. This secret boot block decrypts and ...

  17. Medical Hardware for the Space Environment: An Engineering Experience at the National Aeronautics and Space Administration 

    E-Print Network [OSTI]

    Reyna, Baraquiel

    2011-10-21

    The complexity and amount of medical hardware needed by National Aeronautics and Space Administration (NASA) constantly shifts with mission requirements. Early missions such as Mercury, Gemini, and Apollo required minimal, relatively non-complex...

  18. Energy harvesting to power sensing hardware onboard wind turbine blade

    SciTech Connect (OSTI)

    Carlson, Clinton P; Schichting, Alexander D; Quellette, Scott; Farinholt, Kevin M; Park, Gyuhae

    2009-10-05

    Wind turbines are becoming a larger source of renewable energy in the United States. However, most of the designs are geared toward the weather conditions seen in Europe. Also, in the United States, manufacturers have been increasing the length of the turbine blades, often made of composite materials, to maximize power output. As a result of the more severe loading conditions in the United States and the material level flaws in composite structures, blade failure has been a more common occurrence in the U.S. than in Europe. Therefore, it is imperative that a structural health monitoring system be incorporated into the design of the wind turbines in order to monitor flaws before they lead to a catastrophic failure. Due to the rotation of the turbine and issues related to lightning strikes, the best way to implement a structural health monitoring system would be to use a network of wireless sensor nodes. In order to provide power to these sensor nodes, piezoelectric, thermoelectric and photovoltaic energy harvesting techniques are examined on a cross section of a CX-100 wind turbine blade in order to determine the feasibility of powering individual nodes that would compose the sensor network.

  19. Hardware Verification using ANSI-C Programs as a Reference Edmund Clarke Daniel Kroening

    E-Print Network [OSTI]

    Clarke, Edmund M.

    -412-621-5473 Fax: +1-412-268-5576 e-mail: emc@cs.cmu.edu e-mail kroening@cs.cmu.edu ABSTRACT We describe an algorithm to verify a hardware design given in Verilog using an ANSI-C program as a specification. We use implementation of the data encryption standard (DES) algorithm. I. INTRODUCTION A common hardware design approach

  20. UC-Secure Multi-Session OT Using Tamper-Proof Hardware Tokens

    E-Print Network [OSTI]

    International Association for Cryptologic Research (IACR)

    UC-Secure Multi-Session OT Using Tamper-Proof Hardware Tokens Kaoru Kurosawa1 Ryo Nojima2 Le Trieu-no,phong}@nict.go.jp Abstract In this paper, we show the first UC-secure multi-session OT proto- col using tamper-proof hardware under the Many DH assumption or under the DDHE assumption (in the standard model). Keywords: tamper

  1. FISSILE MATERIAL HOLDUP MEASUREMENT SYSTEMS: AN HISTORICAL REVIEW OF HARDWARE AND SOFTWARE

    SciTech Connect (OSTI)

    Chapman, Jeffrey Allen [ORNL; Smith, Steven E [ORNL; Rowe, Nathan C [ORNL

    2015-01-01

    The measurement of fissile material holdup is accomplished by passively measuring the energy-dependent photon flux and/or passive neutron flux emitted from the fissile material deposited within an engineered process system. Both measurement modalities photon and neutron require the implementation of portable, battery-operated systems that are transported, by hand, from one measurement location to another. Because of this portability requirement, gamma-ray spectrometers are typically limited to inorganic scintillators, coupled to photomultiplier tubes, a small multi-channel analyzer, and a handheld computer for data logging. For neutron detection, polyethylene-moderated, cadmium-back-shielded He-3 thermal neutron detectors are used, coupled to nuclear electronics for supplying high voltage to the detector, and amplifying the signal chain to the scaler for counting. Holdup measurement methods, including the concept of Generalized Geometry Holdup (GGH), are well presented by T. Douglas Reilly in LA-UR-07-5149 and P. Russo in LA-14206, yet both publications leave much of the evolutionary hardware and software to the imagination of the reader. This paper presents an historical review of systems that have been developed and implemented since the mid-1980s for the nondestructive assay of fissile material, in situ. Specifications for the next-generation holdup measurements systems are conjectured.

  2. Demonstration of Datacenter Automation Software and Hardware (DASH) at the California Franchise Tax Board

    SciTech Connect (OSTI)

    Bell, Geoffrey C.; Federspiel, Clifford

    2009-12-18

    Control software and wireless sensors designed for closed-loop, monitoring and control of IT equipment's inlet air temperatures in datacenters were evaluated and tested while other datacenter cooling best practices were implemented. The controls software and hardware along with each best practice were installed sequentially and evaluated using a measurement and verification procedure between each measure. The results show that the overall project eliminates 475,239 kWh per year, which is 21.3percent of the baseline energy consumption of the data center. The total project, including the best practices will save $42,772 per year and cost $134,057 yielding a simple payback of 3.1 years. However, the control system alone eliminates 59.6percent of the baseline energy used to move air in the datacenter and 13.6percent of the baseline cooling energy, which is 15.2percent of the baseline energy consumption (see Project Approach, Task 1, below, for additional information) while keeping temperatures substantially within the limits recommended by ASHRAE. Savings attributed to the control system are $30,564 per year with a cost $56,824 for a simple payback of 1.9 years.

  3. Portals 4 network API definition and performance measurement

    SciTech Connect (OSTI)

    Brightwell, R. B.

    2012-03-01

    Portals is a low-level network programming interface for distributed memory massively parallel computing systems designed by Sandia, UNM, and Intel. Portals has been designed to provide high message rates and to provide the flexibility to support a variety of higher-level communication paradigms. This project developed and analyzed an implementation of Portals using shared memory in order to measure and understand the impact of using general-purpose compute cores to handle network protocol processing functions. The goal of this study was to evaluate an approach to high-performance networking software design and hardware support that would enable important DOE modeling and simulation applications to perform well and to provide valuable input to Intel so they can make informed decisions about future network software and hardware products that impact DOE applications.

  4. Seven Deadliest Network Attacks

    SciTech Connect (OSTI)

    Prowell, Stacy J [ORNL; Borkin, Michael [None; Kraus, Robert [Solutionary, Inc.

    2010-05-01

    Do you need to keep up with the latest hacks, attacks, and exploits effecting networks? Then you need "Seven Deadliest Network Attacks". This book pinpoints the most dangerous hacks and exploits specific to networks, laying out the anatomy of these attacks including how to make your system more secure. You will discover the best ways to defend against these vicious hacks with step-by-step instruction and learn techniques to make your computer and network impenetrable. Attacks detailed in this book include: Denial of Service; War Dialing; Penetration 'Testing'; Protocol Tunneling; Spanning Tree Attacks; Man-in-the-Middle; and, Password Replay. Knowledge is power, find out about the most dominant attacks currently waging war on computers and networks globally. Discover the best ways to defend against these vicious attacks; step-by-step instruction shows you how. Institute countermeasures, don't be caught defenseless again, learn techniques to make your computer and network impenetrable.

  5. Sensor Networks Challenges for Intelligent Buildings Alberto Eduardo Cerpa

    E-Print Network [OSTI]

    Cerpa, Alberto E.

    research challenges to realize sensor network technology for intelligent buildings. Hardware Cost: the current cost of each individual sensor unit is still very high. Commercially available platforms cost prototypes of low-power consumption cameras costing in the order of $200 per unit [4]. It is critical

  6. Life Improvement of Pot Hardware in Continuous Hot Dipping Processes

    Broader source: Energy.gov [DOE]

    Flat-rolled surface-coated steel, including galvanized and aluminized sheet, is one of the fastest growing, most profitable sectors of the U.S. steel industry. Coating steel sheets by continuous...

  7. Insecurity of Wireless Networks

    SciTech Connect (OSTI)

    Sheldon, Frederick T; Weber, John Mark; Yoo, Seong-Moo; Pan, W. David

    2012-01-01

    Wireless is a powerful core technology enabling our global digital infrastructure. Wi-Fi networks are susceptible to attacks on Wired Equivalency Privacy, Wi-Fi Protected Access (WPA), and WPA2. These attack signatures can be profiled into a system that defends against such attacks on the basis of their inherent characteristics. Wi-Fi is the standard protocol for wireless networks used extensively in US critical infrastructures. Since the Wired Equivalency Privacy (WEP) security protocol was broken, the Wi-Fi Protected Access (WPA) protocol has been considered the secure alternative compatible with hardware developed for WEP. However, in November 2008, researchers developed an attack on WPA, allowing forgery of Address Resolution Protocol (ARP) packets. Subsequent enhancements have enabled ARP poisoning, cryptosystem denial of service, and man-in-the-middle attacks. Open source systems and methods (OSSM) have long been used to secure networks against such attacks. This article reviews OSSMs and the results of experimental attacks on WPA. These experiments re-created current attacks in a laboratory setting, recording both wired and wireless traffic. The article discusses methods of intrusion detection and prevention in the context of cyber physical protection of critical Internet infrastructure. The basis for this research is a specialized (and undoubtedly incomplete) taxonomy of Wi-Fi attacks and their adaptations to existing countermeasures and protocol revisions. Ultimately, this article aims to provide a clearer picture of how and why wireless protection protocols and encryption must achieve a more scientific basis for detecting and preventing such attacks.

  8. Maximizing Static Network Lifetime of Wireless Broadcast Adhoc Networks

    E-Print Network [OSTI]

    Poovendran, Radha

    of the important applications of wireless static adhoc net- works includes wireless sensor networks. The technology- cast routing over wireless static adhoc network where host mobility is not involved. We define the lifetime of a network as the dura- tion of time until the first node failure due to battery depletion. We

  9. Tidal networks 2. Watershed delineation and comparative network morphology

    E-Print Network [OSTI]

    Fagherazzi, Sergio

    of three, we quantify various tidal network properties including common power law relationships which have common power law relationships quantified for terrestrial systems to tidal systems and use these analysesTidal networks 2. Watershed delineation and comparative network morphology Andrea Rinaldo,1 Sergio

  10. Hardware IP Protection during Evaluation Using Embedded Sequential Trojan

    E-Print Network [OSTI]

    Bhunia, Swarup

    encryption and vendor-specific toolsets, which may be unacceptable due to lack of flexibility to use in-house IPs from piracy and reverse- engineering include passive defenses like watermarking [1] as well. It creates the possibility of a design house illegally using an IP in an IC design or selling it to external

  11. f you listen carefully you'll hear the rumblings of a true revolution in the making. Startling advances in computer graphics hardware are making it

    E-Print Network [OSTI]

    Hill, Gary

    advances in computer graphics hardware are making it possible for owners of ordinary desktop computers

  12. The application of neural networks with artificial intelligence technique in the modeling of industrial processes

    SciTech Connect (OSTI)

    Saini, K. K.; Saini, Sanju [CDLM engg. College Panniwala Mota, Sirsa and Murthal, Sonipat, Haryana (India)

    2008-10-07

    Neural networks are a relatively new artificial intelligence technique that emulates the behavior of biological neural systems in digital software or hardware. These networks can 'learn', automatically, complex relationships among data. This feature makes the technique very useful in modeling processes for which mathematical modeling is difficult or impossible. The work described here outlines some examples of the application of neural networks with artificial intelligence technique in the modeling of industrial processes.

  13. Remote facility sharing with ATM networks [PC based ATM Link Delay Simulator (LDS)]. Final report

    SciTech Connect (OSTI)

    Kung, H. T.

    2001-06-01

    The ATM Link Delay Simulator (LDS) adds propagation delay to the ATM link on which it is installed, to allow control of link propagation delay in network protocol experiments simulating an adjustable piece of optical fiber. Our LDS simulates a delay of between 1.5 and 500 milliseconds and is built with commodity PC hardware, only the ATM network interface card is not generally available. Our implementation is special in that it preserves the exact spacing of ATM data cells a feature that requires sustained high performance. Our implementation shows that applications demanding sustained high performance are possible on commodity PC hardware. This illustrates the promise that PC hardware has for adaptability to demanding specialized testing of high speed network.

  14. Optimization in Networks

    E-Print Network [OSTI]

    Adilson E. Motter; Zoltan Toroczkai

    2007-07-07

    The recent surge in the network modeling of complex systems has set the stage for a new era in the study of fundamental and applied aspects of optimization in collective behavior. This Focus Issue presents an extended view of the state of the art in this field and includes articles from a large variety of domains where optimization manifests itself, including physical, biological, social, and technological networked systems.

  15. Hardware/Software Solution Unifying DALI, IBECS, and BACnet

    SciTech Connect (OSTI)

    Koch, Ed; Rubinstein, Francis; Sila, Kiliccote

    2004-12-01

    The goal of this project was to investigate broader building-level systems/strategies that enable further energy savings and control. This project investigated the potential savings offered by broader centralized control features and the potential advantages they may add to this system through such features as addressability and load shedding. This report documents the results of LBNL's work in this area. This report focuses on building-level systems and strategies and a multi-protocol gateway solution that is indifferent to the specific choice of lighting control/communications technique used to control the office lighting. The elegance of the IEEE 1451 intelligent gateway proposed in this report is that the overall building communications system should work regardless of whether the office lighting is controlled by DALI, UPB, IBECS, ZigBee or any other accepted communications protocol. Many lighting control companies have robust local lighting control systems with functional strategies for the office level controls. What the industry lacks is the efficient integration of local controls with building controls and energy management systems in order to utilize sensory data. LBNL proposes a framework for a gateway with a level of embedded intelligence, linking various device area networks (DANs) to building control systems. The proposed gateway acts as a translator for DANs enabling them to talk to each other and with a building control system. Just like a PC recognizing a mouse as soon as it is plugged in, the gateway will recognize devices with embedded or virtual Transducer Electronic Data Sheet (TEDS). This presents a truly ''plug and play'' capability for the building control systems. As a result, sensory data can be automatically calibrated, collected and utilized with minimal labor for effective and efficient building controls. The mature market cost of the proposed gateway is not yet known. But current product suggest that $1000/bridge is achievable today with off-the-shelf components and wireless routers that are common today for computer applications do not have significantly lower capabilities than the $1000 product and are now available at $100-$200. If it is configured so that it caters to commissioning, maintenance and energy monitoring, its benefit from a mere energy saving equipment can be extended to reduction in installation and maintenance costs.

  16. Parallel processing data network of master and slave transputers controlled by a serial control network

    DOE Patents [OSTI]

    Crosetto, D.B.

    1996-12-31

    The present device provides for a dynamically configurable communication network having a multi-processor parallel processing system having a serial communication network and a high speed parallel communication network. The serial communication network is used to disseminate commands from a master processor to a plurality of slave processors to effect communication protocol, to control transmission of high density data among nodes and to monitor each slave processor`s status. The high speed parallel processing network is used to effect the transmission of high density data among nodes in the parallel processing system. Each node comprises a transputer, a digital signal processor, a parallel transfer controller, and two three-port memory devices. A communication switch within each node connects it to a fast parallel hardware channel through which all high density data arrives or leaves the node. 6 figs.

  17. Parallel processing data network of master and slave transputers controlled by a serial control network

    DOE Patents [OSTI]

    Crosetto, Dario B. (DeSoto, TX)

    1996-01-01

    The present device provides for a dynamically configurable communication network having a multi-processor parallel processing system having a serial communication network and a high speed parallel communication network. The serial communication network is used to disseminate commands from a master processor (100) to a plurality of slave processors (200) to effect communication protocol, to control transmission of high density data among nodes and to monitor each slave processor's status. The high speed parallel processing network is used to effect the transmission of high density data among nodes in the parallel processing system. Each node comprises a transputer (104), a digital signal processor (114), a parallel transfer controller (106), and two three-port memory devices. A communication switch (108) within each node (100) connects it to a fast parallel hardware channel (70) through which all high density data arrives or leaves the node.

  18. #include #include

    E-Print Network [OSTI]

    Kessler, Christoph

    ] (where a[n] = +infty). C's * bsearch() can't be used, it requires a[j]==key. */ int findloc( void *key Combine­CRCW BSP­Quicksort * variant by Gerbessiotis/Valiant JPDC 22(1994) * implemented in NestStep­C. */ int N=10; // default value /** findloc(): find largest index j in [0..n­1] with * a[j

  19. Numerical Field Calculation in Support of the Hardware Commissioning of the LHC

    E-Print Network [OSTI]

    Schwerg, N; Russenschuck, S; 10.1109/TASC.2011.2157344

    2011-01-01

    The hardware commissioning of the Large Hadron Collider (LHC) required the testing and qualification of the cryogenic and vacuum system, as well as the electrical systems for the powering of more than 10000 superconducting magnets. Non-conformities had to be resolved within a tight schedule. In this paper we focus on the role that electromagnetic field computation has played during hardware commissioning in terms of analysis of magnet quench, electromagnetic force calculations in busbars and splices, as well as field-quality prediction for the optimization of powering cycles.

  20. Detecting and Blocking Network Attacks at Ultra High Speeds

    SciTech Connect (OSTI)

    Paxson, Vern

    2010-11-29

    Stateful, in-depth, in-line traffic analysis for intrusion detection and prevention has grown increasingly more difficult as the data rates of modern networks rise. One point in the design space for high-performance network analysis - pursued by a number of commercial products - is the use of sophisticated custom hardware. For very high-speed processing, such systems often cast the entire analysis process in ASICs. This project pursued a different architectural approach, which we term Shunting. Shunting marries a conceptually quite simple hardware device with an Intrusion Prevention System (IPS) running on commodity PC hardware. The overall design goal is was to keep the hardware both cheap and readily scalable to future higher speeds, yet also retain the unparalleled flexibility that running the main IPS analysis in a full general-computing environment provides. The Shunting architecture we developed uses a simple in-line hardware element that maintains several large state tables indexed by packet header fields, including IP/TCP flags, source and destination IP addresses, and connection tuples. The tables yield decision values the element makes on a packet-by-packet basis: forward the packet, drop it, or divert ('shunt') it through the IPS (the default). By manipulating table entries, the IPS can, on a fine-grained basis: (i) specify the traffic it wishes to examine, (ii) directly block malicious traffic, and (iii) 'cut through' traffic streams once it has had an opportunity to 'vet' them, or (iv) skip over large items within a stream before proceeding to further analyze it. For the Shunting architecture to yield benefits, it needs to operate in an environment for which the monitored network traffic has the property that - after proper vetting - much of it can be safely skipped. This property does not universally hold. For example, if a bank needs to examine all Web traffic involving its servers for regulatory compliance, then a monitor in front of one of the bank's server farms cannot safely omit a subset of the traffic from analysis. In this environment, Shunting cannot realize its main performance benefits, and the monitoring task likely calls for using custom hardware instead. However, in many other environments we find Shunting holds promise for delivering major performance gains. This arises due to the the widely documented 'heavy tail' nature of most forms of network traffic, which we might express as 'a few of the connections carry just about all the bytes.' The key additional insight is '... and very often for these few large connections, the very beginning of the connection contains nearly all the information of interest from a security analysis perspective.' We argue that this second claim holds because it is at the beginning of connections that authentication exchanges occur, data or file names and types are specified, request and reply status codes conveyed, and encryption is negotiated. Once these occur, we have seen most of the interesting facets of the dialog. Certainly the remainder of the connection might also yield some grist for analysis, but this is generally less likely, and thus if we want to lower analysis load at as small a loss as possible of information relevant to security analysis, we might best do so by skipping the bulk of large connections. In a different context, the 'Time Machine' work by Kornexl and colleagues likewise shows that in some environments we can realize major reductions in the volume of network traffic processed, by limiting the processing to the first 10-20 KB of each connection. As a concrete example, consider an IPS that monitors SSH traffic. When a new SSH connection arrives and the Shunt fails to find an entry for it in any of its tables (per-address, per-port, per-connection), it executes the default action of diverting the connection through the IPS. The IPS analyzes the beginning of the connection in this fashion. As long as it is satisified with the dialog, it reinjects the packets forwarded to it so that the connection can continue. If the connection successfully

  1. Design and Analysis of Communication Protocols for Quantum Repeater Networks

    E-Print Network [OSTI]

    Cody Jones; Danny Kim; Matthew T. Rakher; Paul G. Kwiat; Thaddeus D. Ladd

    2015-05-06

    We analyze how the performance of a quantum-repeater network depends on the protocol employed to distribute entanglement, and we find that the choice of repeater-to-repeater link protocol has a profound impact on communication rate as a function of hardware parameters. We develop numerical simulations of quantum networks using different protocols, where the repeater hardware is modeled in terms of key performance parameters, such as photon generation rate and collection efficiency. These parameters are motivated by recent experimental demonstrations in quantum dots, trapped ions, and nitrogen-vacancy centers in diamond. We find that a quantum-dot repeater with the newest protocol ("MidpointSource") delivers the highest communication rate when there is low probability of establishing entanglement per transmission, and in some cases the rate is orders of magnitude higher than other schemes. Our simulation tools can be used to evaluate communication protocols as part of designing a large-scale quantum network.

  2. Merging photovoltaic hardware development with hybrid applications in the USA

    SciTech Connect (OSTI)

    Bower, W.

    1993-11-01

    The use of multi-source power systems, ``hybrids,`` is one of the fastest growing, potentially significant markets for photovoltaic (PV) system technology today. Cost-effective applications today include remote facility power, remote area power supplies, remote home and village power, and power for dedicated electrical loads such as communications systems. This market sector is anticipated to be one of the most important growth opportunities for PV over the next five years. The US Department of Energy (USDOE) and Sandia National Laboratories (SNL) are currently engaged in an effort to accelerate the adoption of market-driven PV hybrid power systems and to effectively integrate PV with other energy sources. This paper provides details of this development and the ongoing hybrid activities in the United States. Hybrid systems are the primary focus of this paper.

  3. Developing and Deploying Advanced Algorithms to Novel Supercomputing Hardware

    E-Print Network [OSTI]

    Robert J. Brunner; Volodymyr V. Kindratenko; Adam D. Myers

    2007-11-21

    The objective of our research is to demonstrate the practical usage and orders of magnitude speedup of real-world applications by using alternative technologies to support high performance computing. Currently, the main barrier to the widespread adoption of this technology is the lack of development tools and case studies that typically impede non-specialists that might otherwise develop applications that could leverage these technologies. By partnering with the Innovative Systems Laboratory at the National Center for Supercomputing, we have obtained access to several novel technologies, including several Field-Programmable Gate Array (FPGA) systems, NVidia Graphics Processing Units (GPUs), and the STI Cell BE platform. Our goal is to not only demonstrate the capabilities of these systems, but to also serve as guides for others to follow in our path. To date, we have explored the efficacy of the SRC-6 MAP-C and MAP-E and SGI RASC Athena and RC100 reconfigurable computing platforms in supporting a two-point correlation function which is used in a number of different scientific domains. In a brute force test, the FPGA based single-processor system has achieved an almost two orders of magnitude speedup over a single-processor CPU system. We are now developing implementations of this algorithm on other platforms, including one using a GPU. Given the considerable efforts of the cosmology community in optimizing these classes of algorithms, we are currently working to implement an optimized version of the basic family of correlation functions by using tree-based data structures. Finally, we are also exploring other algorithms, such as instance-based classifiers, power spectrum estimators, and higher-order correlation functions that are also commonly used in a wide range of scientific disciplines.

  4. Power Management in Wireless Networks Kevin Klues

    E-Print Network [OSTI]

    Jain, Raj

    Power Management in Wireless Networks Kevin Klues Abstract This paper presents a survey on the various power saving techniques used in wireless networking today. The work presented covers topics at each layer of a wireless networking protocol stack. The types of wireless networks considered include

  5. Designing Neural Networks Using Gene Expression Programming

    E-Print Network [OSTI]

    Fernandez, Thomas

    1 Designing Neural Networks Using Gene Expression Programming CândidaFerreira Gepsoft, 73 Elmtree aspects of neural networks, such as the weights, the thresholds, and the network architec- ture. Indeed neural network, including the architecture, the weights and thresholds, could be totally encoded

  6. Hardware Architecture for Measurements for 50-V Battery Modules

    SciTech Connect (OSTI)

    Patrick Bald; Evan Juras; Jon P. Christophersen; William Morrison

    2012-06-01

    Energy storage devices, especially batteries, have become critical for several industries including automotive, electric utilities, military and consumer electronics. With the increasing demand for electric and hybrid electric vehicles and the explosion in popularity of mobile and portable electronic devices such as laptops, cell phones, e-readers, tablet computers and the like, reliance on portable energy storage devices such as batteries has likewise increased. Because many of the systems these batteries integrated into are critical, there is an increased need for an accurate in-situ method of monitoring battery state-of-health. Over the past decade the Idaho National Laboratory (INL), Montana Tech of the University of Montana (Tech), and Qualtech Systems, Inc. (QSI) have been developing the Smart Battery Status Monitor (SBSM), an integrated battery management system designed to monitor battery health, performance and degradation and use this knowledge for effective battery management and increased battery life. Key to the success of the SBSM is an in-situ impedance measurement system called the Impedance Measurement Box (IMB). One of the challenges encountered has been development of a compact IMB system that will perform rapid accurate measurements of a battery impedance spectrum working with higher voltage batteries of up to 300 volts. This paper discusses the successful realization of a system that will work up to 50 volts.

  7. A UNIFIED HARDWARE/SOFTWARE PRIORITY SCHEDULING MODEL FOR GENERAL PURPOSE SYSTEMS

    E-Print Network [OSTI]

    Preston, Keith Alan

    2012-05-31

    be applied past the scheduling decision itself to also reduce the non-predictable delays associated with interrupts and timers. By expanding the window of hardware/software co-design to these invocation mechanisms, we seek to understand if the jitter...

  8. Hardware Security: Threat Models and Metrics M. Rostami and F. Koushanfar

    E-Print Network [OSTI]

    , combining them, and generating the layout through sev- eral synthesis and verification steps. The foundry, resulting in IP piracy. An untrusted foundry may overbuild ICs and sell them illegally [3]. An attacker can concludes the paper. 2. HARDWARE TROJANS 3PIP Vendor SoC Integrator Foundry User 1 2 ? ?? ? Figure 2: Two

  9. Engineering Test Facilities Having the facilities to develop and test spaceflight hardware

    E-Print Network [OSTI]

    Mojzsis, Stephen J.

    Engineering Test Facilities Having the facilities to develop and test spaceflight hardware onsite is a key ingredient to LASP's success. Our extensive test and calibration facilities enable our in-house engineers to work closely with scientists and mission operations staff in "test-like-you-fly" scenarios. Our

  10. EE 361 Fall 2003 University of Hawaii 1 Hardware Design Tips

    E-Print Network [OSTI]

    Sasaki, Galen H.

    1 EE 361 Fall 2003 University of Hawaii 1 Hardware Design Tips EE 361 University of Hawaii EE 361 Fall 2003 University of Hawaii 2 Outline · Verilog: some subleties · Simulators · Test Benching · Implementing the MIPS ­ Actually a simplified 16 bit version #12;2 EE 361 Fall 2003 University of Hawaii 3

  11. Design of Reconfigurable Composite Microsystems Based on Hardware/Software Codesign Principles 1

    E-Print Network [OSTI]

    Chakrabarty, Krishnendu

    Design of Reconfigurable Composite Microsystems Based on Hardware/Software Co­design Principles 1 Tianhao Zhang, Krishnendu Chakrabarty and Richard B. Fair Department of Electrical and Computer microelec­ tromechanic and microelectrofluidic devices are emerg­ ing as the next generation of system

  12. Efficient Hardware Code Generation ZHI GUO, WALID NAJJAR; and BETUL BUYUKKURT

    E-Print Network [OSTI]

    Najjar, Walid A.

    6 Efficient Hardware Code Generation for FPGAs ZHI GUO, WALID NAJJAR; and BETUL BUYUKKURT-intensive Authors' address: Zhi Guo, Walid Najjar, and Betul Buyukkurt, University of California, Riverside computing, high-level synthesis, data reuse, FPGA, VHDL ACM Reference Format: Guo, Z., Najjar, W

  13. Suppression of quantum chaos in a quantum computer hardware J. Lages* and D. L. Shepelyansky

    E-Print Network [OSTI]

    Shepelyansky, Dima

    Suppression of quantum chaos in a quantum computer hardware J. Lages* and D. L. Shepelyansky computer proposed by the Yamamoto group in Phys. Rev. Lett. 89, 017901 2002 . The stable and quantum chaos gradient leads to suppression of quantum chaos. DOI: 10.1103/PhysRevE.74.026208 PACS number s : 05.45.Mt

  14. Time-Domain Passivity Control of Haptic Interfaces with Tunable Damping Hardware

    E-Print Network [OSTI]

    Hayward, Vincent

    . Gosline and Vincent Hayward Haptics Laboratory, Center For Intelligent Machines McGill University, Montr´eal extracting energy from a haptic in- terface. A passivity observer monitors the energy flow of the virtual environment, and damping hardware is used to remove any energy contributions from the virtual environ- ment

  15. Clearing, Sanitization, and Destruction of Information System Storage Media, Memory Devices, and Related Hardware Manual

    Broader source: Directives, Delegations, and Requirements [Office of Management (MA)]

    2005-06-21

    The manual establishes the DOE requirements and responsibilities for clearing, sanitizing, and destroying DOE information system storage media, memory devices, and related hardware to ensure that no unauthorized information can be retrieved. Canceled by DOE N 205.17. Cancels DOE N 205.12

  16. Graphics Hardware (2003) M. Doggett, W. Heidrich, W. Mark, A. Schilling (Editors)

    E-Print Network [OSTI]

    Moreno Maza, Marc

    2003-01-01

    of Computer Science, University of New Mexico, Albuquerque, NM, USA Abstract The Fourier transform is a well of the graphics pipeline. As of late, computer graphics hardware has become amazingly cheap, powerful as part of the rendering pipeline. Categories and Subject Descriptors (according to ACM CCS): I.3

  17. Hardware Accelerator for the Tate Pairing in Characteristic Three Based on

    E-Print Network [OSTI]

    Detrey, Jérémie

    , 07300 M´exico City, M´exico Abstract. This paper is devoted to the design of fast parallel accel propose here a novel hardware imple- mentation of Miller's loop based on a pipelined Karatsuba-Ofman multi to the Tate pairing, we manage to keep the pipeline busy. We also describe the strategies we considered

  18. Hardware JIT compilation for off-the-shelf dynamically reconfigurable FPGAs

    E-Print Network [OSTI]

    Feeley, Marc

    Hardware JIT compilation for off-the-shelf dynamically reconfigurable FPGAs Etienne Bergeron, Marc Montr´eal GRM, ´Ecole Polytechnique de Montr´eal Abstract. JIT compilation is a model of execution which translates at run time critical parts of the program to a low level representation. Typically a JIT compiler

  19. Hierarchical Approach for Hardware/ Software Systems Tudor NICULIU Sorin COTOFANA* Anton MANOLESCU

    E-Print Network [OSTI]

    Cotofana, Sorin

    ) and verification (functional simulation of the system's structure), as well on higher as on lower abstractionHierarchical Approach for Hardware/ Software Systems Tudor NICULIU Sorin COTOFANA* Anton MANOLESCU Bucuresti, Romania, E-mail: tudor@messnet.pub.ro (*)Delft University of Technology, Faculty of Electrical

  20. New Concepts in Hardware and Processes to Conserve Oil and Gas in Industrial Processes 

    E-Print Network [OSTI]

    Humphrey, J. L.

    1982-01-01

    A broad program to identify and evaluate new types of hardware and processes to conserve oil and gas in chemical plants and petroleum refineries has been completed. During the course of this program, which was sponsored by the Office of Industrial...

  1. Hardware Support for QoS-based Function Allocation in Reconfigurable Systems

    E-Print Network [OSTI]

    Paris-Sud XI, Université de

    Hardware Support for QoS-based Function Allocation in Reconfigurable Systems Michael Ullmann}@itiv.uni-karlsruhe.de Abstract This contribution presents a new approach for allocating suitable function-implementation variants depending on given quality-of-service function- requirements for run-time reconfigurable multi

  2. Hardware Support for QoS-based Function Allocation in Reconfigurable Systems

    E-Print Network [OSTI]

    Ullmann, Michael; Becker, Jurgen

    2011-01-01

    This contribution presents a new approach for allocating suitable function-implementation variants depending on given quality-of-service function-requirements for run-time reconfigurable multi-device systems. Our approach adapts methodologies from the domain of knowledge-based systems which can be used for doing run-time hardware/software resource usage optimizations.

  3. Generalized External Interaction with Tamper-Resistant Hardware with Bounded Information Leakage

    E-Print Network [OSTI]

    Reif, Rafael

    Generalized External Interaction with Tamper-Resistant Hardware with Bounded Information Leakage of Technology devadas@mit.edu ABSTRACT This paper investigates secure ways to interact with tamper- resistant on top of a recently- proposed secure processor Ascend [11]. Ascend is chosen because unlike other tamper

  4. On the Energy-Efficiency of Speculative Hardware Nana B. Sam

    E-Print Network [OSTI]

    Burtscher, Martin

    On the Energy-Efficiency of Speculative Hardware Nana B. Sam Computer Systems Laboratory Cornell, several researchers have pro- posed and evaluated energy-efficient variants of speculation mechanisms to accurately com- pare the energy-efficiency of speculative architectures. Our met- ric is based on runtime

  5. AN RNS-BASED ARCHITECTURE TARGETING HARDWARE ACCELERATORS FOR MODULAR ARITHMETIC

    E-Print Network [OSTI]

    Sousa, Leonel

    AN RNS-BASED ARCHITECTURE TARGETING HARDWARE ACCELERATORS FOR MODULAR ARITHMETIC Samuel Antão- rithms relying on modular arithmetic fully supported by the Residue Number System (RNS). The systematic to date. Index Terms-- Residue Number System (RNS), Modu- lar Arithmetic, Cryptography, Embedded Systems

  6. Structural Design Composition for C++ Hardware Models Frederic Doucet, Vivek Sinha, Rajesh Gupta

    E-Print Network [OSTI]

    Gupta, Rajesh

    Structural Design Composition for C++ Hardware Models Frederic Doucet, Vivek Sinha, Rajesh Gupta design to specify these structural concerns. 1. Introduction High level modeling using C/C++ models [11,vsinha,rguptag@ics.uci.edu Abstract This paper addresses the modeling of layout structure in high level C++ models. Researchers agree

  7. 7/26/02 /home/lml/frame/hardware/EWGMaintenance.fm EWG Maintenance/Operation

    E-Print Network [OSTI]

    Barrash, Warren

    7/26/02 /home/lml/frame/hardware/EWGMaintenance.fm EWG Maintenance/Operation Transporting the EWG. The State of Idaho does not require a license for this trailer. Engine/Hydraulic Maintenance/Operation 1 when operating EWG. EWG Maintenance/Operation 1. Prior to each day's operation, grease hydraulic arm

  8. Comparison of two wireless ad hoc routing protocols on a hardware test-bed

    E-Print Network [OSTI]

    Brown, Timothy X.

    Comparison of two wireless ad hoc routing protocols on a hardware test-bed Shweta Bhandare of the rout- ing protocols is carried out using the Click modular router infrastructure on laptops with wireless ethernet cards running Linux. We demonstrate the working of both ad hoc routing protocols through

  9. Cleanup Verification Package for the 118-F-7, 100-F Miscellaneous Hardware Storage Vault

    SciTech Connect (OSTI)

    M. J. Appel

    2006-11-02

    This cleanup verification package documents completion of remedial action for the 118-F-7, 100-F Miscellaneous Hardware Storage Vault. The site consisted of an inactive solid waste storage vault used for temporary storage of slightly contaminated reactor parts that could be recovered and reused for the 100-F Area reactor operations.

  10. Hardware/Software Co-design for Energy-Efficient Seismic Modeling

    E-Print Network [OSTI]

    Oliker, Leonid

    Wave implementation can offer up to 8× and 3.5× energy efficiency improvement per node respectivelyHardware/Software Co-design for Energy-Efficient Seismic Modeling Jens Krueger , David Donofrio of conventional cluster technology has prompted investigation of architectural alternatives that offer higher

  11. ESIF Plugs Utility-Scale Hardware into Simulated Grids to Assess Integration Effects (Fact Sheet)

    SciTech Connect (OSTI)

    Not Available

    2014-04-01

    At NREL's Energy Systems Integration Facility (ESIF), integrated, megawatt-scale power hardware-in-the-loop (PHIL) capability allows researchers and manufacturers to test new energy technologies at full power in real-time simulations - safely evaluating component and system performance and reliability before going to market.

  12. Unreliable Data Transmissions and Limited Hardware Communication Buffers in Automotive E/E Virtual Prototypes

    E-Print Network [OSTI]

    Teich, Jürgen

    Unreliable Data Transmissions and Limited Hardware Communication Buffers in Automotive E/E Virtual automotive E/E architectures requires a thorough sys- tem evaluation already in early design phases. This can validation. A case-study from the automotive infotainment domain highlights the benefit that results from

  13. Hardware Profile-guided Automatic Page Placement for ccNUMA Systems

    E-Print Network [OSTI]

    Mueller, Frank

    Department of Computer Science, North Carolina State University, Raleigh, NC 27695-7534 e-mail: muellerHardware Profile-guided Automatic Page Placement for ccNUMA Systems Jaydeep Marathe Frank Mueller on automated profiling. The placement scheme allocates pages near processors that most frequently access

  14. Exploration of Short Reads Genome Mapping in Hardware Edward Fernandez, Walid Najjar

    E-Print Network [OSTI]

    Najjar, Walid A.

    Exploration of Short Reads Genome Mapping in Hardware Edward Fernandez, Walid Najjar Department, such as Illumina/Solexa Genome Analyzer and ABI SOLiD, can generate hundreds of millions of short DNA "reads" from a single run. These reads must be matched against a reference genome to identify their original location

  15. Hardware assembly and prototype testing for the development of a dedicated liquefied propane gas ultra low emission vehicle

    SciTech Connect (OSTI)

    1995-07-01

    On February 3, 1994, IMPCO Technologies, Inc. started the development of a dedicated LPG Ultra Low Emissions Vehicle (ULEV) under contract to the Midwest Research Institute National Renewable Energy Laboratory Division (NREL). The objective was to develop a dedicated propane vehicle that would meet or exceed the California ULEV emissions standards. The project is broken into four phases to be performed over a two year period. The four phases of the project include: (Phase 1) system design, (Phase 2) prototype hardware assembly and testing, (Phase 3) full-scale systems testing and integration, (Phase 4) vehicle demonstration. This report describes the approach taken for the development of the vehicle and the work performed through the completion of Phase II dynamometer test results. Work was started on Phase 2 (Hardware Assembly and Prototype Testing) in May 1994 prior to completion of Phase 1 to ensure that long lead items would be available in a timely fashion for the Phase 2 work. In addition, the construction and testing of the interim electronic control module (ECM), which was used to test components, was begun prior to the formal start of Phase 2. This was done so that the shortened revised schedule for the project (24 months) could be met. In this report, a brief summary of the activities of each combined Phase 1 and 2 tasks will be presented, as well as project management activities. A technical review of the system is also given, along with test results and analysis. During the course of Phase 2 activities, IMPCO staff also had the opportunity to conduct cold start performance tests of the injectors. The additional test data was most positive and will be briefly summarized in this report.

  16. Making the Most of Thin Data: A Hardware-Software Approach

    E-Print Network [OSTI]

    Martin, Paul Daniel

    2013-01-01

    ing for structural health monitoring sensor networks. ” Inthe application of Structural Health Monitoring (SHM). By

  17. Network Economics Anna Nagurney

    E-Print Network [OSTI]

    Nagurney, Anna

    Performance/Efficiency Measure with Applications to a Variety of Network Systems · Transportation Network Network Satellite and Undersea Cable Networks Duke Energy Gas Pipeline Network Transportation with transportation as the unifying application. #12;Subway Network Railroad Network Iridium Satellite Constellation

  18. CPS Principal Inves0gator's Mee0ng -Washington D.C. -August 1-2, 2011 Wireless Sensor Actuator Networks

    E-Print Network [OSTI]

    Lemmon, Michael

    #12;CPS Principal Inves0gator's Mee0ng - Washington D.C. - August 1-2, 2011 and collection networks · Traffic networks #12;CPS Principal Inves0gator's Mee0ng - Washington D in hardware ­ Technology transfer #12;CPS Principal Inves0gator's Mee0ng - Washington D

  19. Hardware Configuration

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    AFDC Printable Version Share this resource Send a link to EERE: Alternative Fuels Data Center Home Page to someone by E-mail Share EERE: Alternative Fuels Data Center Home Page on Facebook Tweet about EERE: Alternative Fuels Data Center Home Page on Twitter Bookmark EERE: Alternative Fuels Data Center Homesum_a_epg0_fpd_mmcf_m.xls" ,"Available from WebQuantity ofkandz-cm11 Outreach Home Room NewsInformation Current HABFESOpportunitiesNERSCGrid-based29Hai

  20. Optical Network Testbeds Workshop

    SciTech Connect (OSTI)

    Joe Mambretti

    2007-06-01

    This is the summary report of the third annual Optical Networking Testbed Workshop (ONT3), which brought together leading members of the international advanced research community to address major challenges in creating next generation communication services and technologies. Networking research and development (R&D) communities throughout the world continue to discover new methods and technologies that are enabling breakthroughs in advanced communications. These discoveries are keystones for building the foundation of the future economy, which requires the sophisticated management of extremely large qualities of digital information through high performance communications. This innovation is made possible by basic research and experiments within laboratories and on specialized testbeds. Initial network research and development initiatives are driven by diverse motives, including attempts to solve existing complex problems, the desire to create powerful new technologies that do not exist using traditional methods, and the need to create tools to address specific challenges, including those mandated by large scale science or government agency mission agendas. Many new discoveries related to communications technologies transition to wide-spread deployment through standards organizations and commercialization. These transition paths allow for new communications capabilities that drive many sectors of the digital economy. In the last few years, networking R&D has increasingly focused on advancing multiple new capabilities enabled by next generation optical networking. Both US Federal networking R&D and other national R&D initiatives, such as those organized by the National Institute of Information and Communications Technology (NICT) of Japan are creating optical networking technologies that allow for new, powerful communication services. Among the most promising services are those based on new types of multi-service or hybrid networks, which use new optical networking technologies. Several years ago, when many of these optical networking research topics were first being investigated, they were the subject of controversial debate. The new techniques challenged many long-held concepts related to architecture and technology. However, today all major networking organizations are transitioning toward infrastructure that incorporates these new concepts. This progress has been assisted through the series of Optical Networking Testbed Workshops (ONT). The first (ONT1) outlined a general framework of key issues and topics and developed a series of recommendations (www.nren.nasa.gov/workshop7). The second (ONT2) developed a common vision of optical network technologies, services, infrastructure, and organizations (www.nren.nasa.gov/workshop8). Processes that allow for a common vision encourage widespread deployment of these types of resources among advanced networking communities. Also, such a shared vision enables key concepts and technologies to migrate from basic research testbeds to wider networking communities. The ONT-3 workshop built on these earlier activities by expanding discussion to include additional considerations of the international interoperability and of greater impact of optical networking technology on networking in general. In accordance with this recognition, the workshop confirmed that future-oriented research and development is indispensable to fundamentally change the current Internet architecture to create a global network incorporating completely new concepts. The workshop also recognized that the first priority to allow for this progress is basic research and development, including international collaborative activities, which are important for the global realization of interoperability of a new generation architecture.

  1. Coupling sensing hardware with data interrogation software for structural health monitoring.

    SciTech Connect (OSTI)

    Farrar, C. R. (Charles R.); Allen, D. W. (David W.); Ball, S. (Steven); Masquelier, Michael P.; Park, G. H. (Gyu Hae)

    2004-01-01

    The process of implementing a damage detection strategy for aerospace, civil and mechanical engineering infrastructure is referred to as structural health monitoring (SHM). The authors approach is to address the SIAM problem in the context of a statistical pattern recognition paradigm. In this paradigm, the process can be broken down into four parts: (1) Operational Evaluation, (2) Data Acquisition and Cleansing, (3) Feature Extraction and Data Compression, and (4) Statistical Model Development for Feature Discrimination. These processes must be implemented through hardware or software and, in general, some combination of these two approaches will be used. This paper will discuss each portion of the SHM process with particular emphasis on the coupling of a general purpose data interrogation software package for structural health monitoring (DIAMOND 11) with a modular wireless sensing and processing platform that is being jointly developed with Motorola Labs. More specifically, this paper will address the need to take an integrated hardware/software approach to developing SHM solutions.

  2. PCI data acquisition and signal processing hardware modules for long pulse operation

    SciTech Connect (OSTI)

    Sousa, J.; Batista, A.J.N.; Combo, A.; Pereira, R.; Correia, Miguel; Cruz, N.; Carvalho, P.; Correia, Carlos; Varandas, C.A.F. [Associacao EURATOM/IST, Centro de Fusao Nuclear, Instituto Superior Tecnico, Avenue Rovisco Pais, 1049-001 Lisbon (Portugal)

    2004-10-01

    A set of PCI instrumentation modules was developed at the EURATOM/IST Association. The modules were engineered around a reconfigurable hardware core which permits one to reduce the development time of instrument for new applications, provide support for long time or even continuous operation, and is able to perform real-time digital signal processing. The core was engineered at low cost and the modules incorporate a high number of channels, which contribute to reduce the total cost per channel. Field results are as expected in terms of performance both in data throughput and input characteristics. Currently, a 2 MSPS, 14-bit, eight channel galvanic isolated transient recorder; a 200 MSPS, 8-bit, four channel pulse digitizer; an eight channel time-to-digital-converter with a resolution of 0.4 ns, and a reconfigurable hardware expandable board, are implemented.

  3. Clearing, Sanitizing, and Destroying Information System Storage Media, Memory Devices, and Other Related Hardware

    Broader source: Directives, Delegations, and Requirements [Office of Management (MA)]

    2004-02-19

    This Notice establishes Department of Energy policy requirements and responsibilities for clearing, sanitizing, and destroying DOE information system storage media, memory devices, and other related hardware to ensure no unauthorized information can be retrieved and provides instructions for the same. DOE N 205.15, dated 3-18-05, extends this directive until 3-18-06. No cancellations. Canceled by DOE M 205.1-2.

  4. A Principled Kernel Testbed for Hardware/Software Co-Design Research

    E-Print Network [OSTI]

    Kaiser, Alex

    2010-01-01

    Int’l. Journal of High Performance Computing Applications 5,In Proc. SC2009: High performance computing, networking, andIn Proc. SC2009: High performance computing, networking, and

  5. Prices include compostable serviceware and linen tablecloths

    E-Print Network [OSTI]

    California at Davis, University of

    APPETIZERS Prices include compostable serviceware and linen tablecloths for the food tables.ucdavis.edu. BUTTERNUT SQUASH & BLACK BEAN ENCHILADAS #12;BUFFETS Prices include compostable serviceware and linen

  6. Profiling the atmospheric water vapor content using a GPS-Meteorology network

    E-Print Network [OSTI]

    Mountziaris, T. J.

    Profiling the atmospheric water vapor content using a GPS-Meteorology network Jayson Maldonado-Meteorological stations. Research Objectives · Develop the hardware necessary for the collection atmospheric water content gives the real Water Vapor Content (WVC) in 3D instead of the Zenith Delay. Future Work · Testing

  7. Scaling-Up Bayesian Network Learning to Thousands of Variables Using Local Learning Techniques

    E-Print Network [OSTI]

    Brown, Laura E.

    ,000 variables using ordinary PC hardware. The novel algorithm pushes the envelope of Bayesian Network learning) is a formalization that has proved itself a useful and important tool in medicine for building decision support causal modeling and causal discovery [5]. Despite the great advances in BN learning tech- niques

  8. PAN: A High-Performance Active Network Node Supporting Multiple Mobile Code Systems

    E-Print Network [OSTI]

    , not specialized hardware Page 4 #12;Obtaining High Performance Approach: Look at the active processing critical copies (bring capsule data into cache) Code interpretation, loading, or translation in critical path UserPAN: A High-Performance Active Network Node Supporting Multiple Mobile Code Systems Erik Nygren

  9. Languages for Software-Defined Networks Nate Foster, Michael J. Freedman, Arjun Guha, Rob Harrison,

    E-Print Network [OSTI]

    Rexford, Jennifer

    ) are poised to change this by offering a clean and open interface between networking devices and the software-level APIs that mimic the underlying switch hardware. To reach SDN's full potential, we need to identify complicated distributed protocol [3]. To conserve energy, the controller can selectively shut down links

  10. Mobile Networks and Applications 9, 455457, 2004 2004 Kluwer Academic Publishers. Manufactured in The Netherlands.

    E-Print Network [OSTI]

    Madiraju, Praveen

    ZASLAVSKY School of Computer Science and Software Engineering, Monash University, Melbourne, Australia PANOS a heterogeneous network. Mobile computing therefore involves mobility of users, hardware, software and data agents. The workshop closed with an open discussion session on the trends and future of mobile computing

  11. DEEJAM: Defeating Energy-Efficient Jamming in IEEE 802.15.4-based Wireless Networks

    E-Print Network [OSTI]

    Zhou, Gang

    that renders most higher-layer security mechanisms moot--yet it is often ignored in WSN design. We show of jamming on common WSN hardware with solutions that are shown empirically to en- able continued with the limited resources available to most ad hoc and wireless sensor network (WSN) nodes [1]. Nodes may

  12. Simulating BDI-based Wireless Sensor Networks Alexis Morris, Paolo Giorgini, Sameh Abdel-Naby

    E-Print Network [OSTI]

    in constructing complex distributed systems. Wireless Sensor Networks (WSN) represent such systems, and may techniques have been recently applied to WSN's; however, due to hardware limitations nodes (agents simulator for testing interactions in autonomous WSN's. The belief, desire, intention (BDI) agent model

  13. Fault-tolerant Implementations of the Atomic-state Communication Model in Weaker Networks ?

    E-Print Network [OSTI]

    Johnen, Colette

    of increasing power, are called safe, regular, and atomic. Program design is easier assuming atomic registersFault-tolerant Implementations of the Atomic-state Communication Model in Weaker Networks ? Colette rather than weaker registers but the hardware implementation of an atomic register is costlier than

  14. BER Science Network Requirements Workshop -- July 26-27,2007

    SciTech Connect (OSTI)

    Tierney, Brian L.; Dart, Eli

    2008-02-01

    The Energy Sciences Network (ESnet) is the primary provider of network connectivity for the US Department of Energy Office of Science, the single largest supporter of basic research in the physical sciences in the United States of America. In support of the Office of Science programs, ESnet regularly updates and refreshes its understanding of the networking requirements of the instruments, facilities, scientists, and science programs that it serves. This focus has helped ESnet to be a highly successful enabler of scientific discovery for over 20 years. In July 2007, ESnet and the Biological and Environmental Research (BER) Program Office of the DOE Office of Science organized a workshop to characterize the networking requirements of the science programs funded by the BER Program Office. These included several large programs and facilities, including Atmospheric Radiation Measurement (ARM) Program and the ARM Climate Research Facility (ACRF), Bioinformatics and Life Sciences Programs, Climate Sciences Programs, the Environmental Molecular Sciences Laboratory at PNNL, the Joint Genome Institute (JGI). National Center for Atmospheric Research (NCAR) also participated in the workshop and contributed a section to this report due to the fact that a large distributed data repository for climate data will be established at NERSC, ORNL and NCAR, and this will have an effect on ESnet. Workshop participants were asked to codify their requirements in a 'case study' format, which summarizes the instruments and facilities necessary for the science and the process by which the science is done, with emphasis on the network services needed and the way in which the network is used. Participants were asked to consider three time scales in their case studies--the near term (immediately and up to 12 months in the future), the medium term (3-5 years in the future), and the long term (greater than 5 years in the future). In addition to achieving its goal of collecting and characterizing the network requirements of the science endeavors funded by the BER Program Office, the workshop emphasized some additional points. These included the need for a future ESnet presence in the Denver area, a desire for ESnet to continue support of collaboration services, and the need for ESnet to support dedicated bandwidth or 'virtual circuit' services. In addition, it is clear that the BER facilities are going to experience significant growth in data production over the next 5 years. The reasons for this vary (model resolution and supercomputer allocations for climate, detector upgrades for EMSL and ARM, sequencing hardware upgrades for JGI), but all indicators point to significant growth in data volumes over the near to medium term. This growth in data volume, combined with the ever-expanding scope of scientific collaboration, will continue to demand ever-increasing bandwidth, reliability and service richness from the networks that support DOE science.

  15. A Network Contention Model for the Extreme-scale Simulator

    SciTech Connect (OSTI)

    Engelmann, Christian [ORNL; Naughton, III, Thomas J [ORNL

    2015-01-01

    The Extreme-scale Simulator (xSim) is a performance investigation toolkit for high-performance computing (HPC) hardware/software co-design. It permits running a HPC application with millions of concurrent execution threads, while observing its performance in a simulated extreme-scale system. This paper details a newly developed network modeling feature for xSim, eliminating the shortcomings of the existing network modeling capabilities. The approach takes a different path for implementing network contention and bandwidth capacity modeling using a less synchronous and accurate enough model design. With the new network modeling feature, xSim is able to simulate on-chip and on-node networks with reasonable accuracy and overheads.

  16. Sensor networks for social networks

    E-Print Network [OSTI]

    Farry, Michael P. (Michael Patrick)

    2006-01-01

    This thesis outlines the development of software that makes use of Bayesian belief networks and signal processing techniques to make meaningful inferences about real-world phenomena using data obtained from sensor networks. ...

  17. QoS-oriented Integrated Network Planning for Industrial Wireless Sensor Networks

    E-Print Network [OSTI]

    Breu, Ruth

    , Industry Automation Division, Germany {feng.chen,german,dressler}@informatik.uni-erlangen.de Abstract including industrial automation. This also includes Wireless Sensor Network (WSN) technology [1] basedQoS-oriented Integrated Network Planning for Industrial Wireless Sensor Networks Feng Chen

  18. Specification and Verification of Synchronous Hardware using LOTOS. In Jianping Wu, Samuel T. Chanson, Quiang Gao, editors, Proc. Formal Methods

    E-Print Network [OSTI]

    Turner, Ken

    . Chanson, Quiang Gao, editors, Proc. Formal Methods for Protocol Engineering and Distributed Systems (FORTE, University of Stirling, Stirling FK9 4LA, Scotland Keywords: Digital Logic, Hardware Description, LOTOS

  19. Qualification of the IBM CSC factory in Singapore : resource estimation and allocation in software and hardware services

    E-Print Network [OSTI]

    Li, Chengguang, M. Eng. Massachusetts Institute of Technology

    2007-01-01

    The CSC department of IBM Singapore has been established two years ago. It provides a variety of hardware and software services for its customers. Due to the complex mix of products and the different ways of completing the ...

  20. Hardware model of a shipboard zonal electrical distribution system (ZEDS) : alternating current/direct current (AC/DC)

    E-Print Network [OSTI]

    Tidd, Chad N. (Chad Norman)

    2010-01-01

    A hardware model of a shipboard electrical distribution system based on aspects of the DDG 51 Flight IIA, Arleigh Burke class, 60Hz Alternating Current (AC) and the future direct current (DC), zonal electrical distribution ...

  1. The effect of hardware configuration on the performance of residential air conditioning systems at high outdoor ambient temperatures 

    E-Print Network [OSTI]

    Bain, Joel Alan

    1995-01-01

    A study was performed which investigated the effect of hardware configuration on air conditioning cooling system performance at high outdoor temperatures. The initial phase of the investigation involved the testing of ten residential air...

  2. Reducing cold start hydrocarbon emissions from port fuel injected spark ignition engines with improved management of hardware & controls

    E-Print Network [OSTI]

    Lang, Kevin R., 1980-

    2006-01-01

    An experimental study was performed to investigate strategies for reducing cold start hydrocarbon (HC) emissions from port fuel injected (PFI) spark ignition (SI) engines with better use of existing hardware and control ...

  3. The design and construction of electronic motor control and network interface hardware for advance concept urban mobility vehicles

    E-Print Network [OSTI]

    Morrissey, Bryan L. (Bryan Lawrence)

    2008-01-01

    Over the past several years, the Smart Cities Group at MIT's Media Lab has engaged in research to develop several advanced concepts for vehicles to improve urban mobility. This research has focused on developing a modular ...

  4. Oct 22, 2004 www.dcs.bbk.ac.uk/~gmagoulas/teaching.html 1 Web Servers Hardware and

    E-Print Network [OSTI]

    Magoulas, George D.

    1 Oct 22, 2004 www.dcs.bbk.ac.uk/~gmagoulas/teaching.html 1 E-commerce Web Servers Hardware business needs. Oct 22, 2004 www.dcs.bbk.ac.uk/~gmagoulas/teaching.html 2 Outline l E-commerce Web sites l server hardware l Web hosting #12;2 Oct 22, 2004 www.dcs.bbk.ac.uk/~gmagoulas/teaching.html 3 Learning

  5. Network interdiction with budget constraints

    SciTech Connect (OSTI)

    Santhi, Nankakishore; Pan, Feng

    2009-01-01

    Several scenarios exist in the modern interconnected world which call for efficient network interdiction algorithms. Applications are varied, including computer network security, prevention of spreading of Internet worms, policing international smuggling networks, controlling spread of diseases and optimizing the operation of large public energy grids. In this paper we consider some natural network optimization questions related to the budget constrained interdiction problem over general graphs. Many of these questions turn out to be computationally hard to tackle. We present a particularly interesting practical form of the interdiction question which we show to be computationally tractable. A polynomial time algorithm is then presented for this problem.

  6. Declarative Failure Recovery for Sensor Networks

    E-Print Network [OSTI]

    Gummadi, Ramakrishna; Kothari, Nupur; Millstein, Todd; Govindan, Ramesh

    2007-01-01

    developing wireless embedded systems software. CENS-TR-9,Approach to Networked Embedded Systems. In PLDI 2003. [14]culties of traditional embedded systems, including scale,

  7. Streaming Exascale Data over 100Gbps Networks

    E-Print Network [OSTI]

    Balman, Mehmet

    2014-01-01

    Network   Initiative   (ANI 1 )   supported   by   the  As   a   part   of   the   ANI   project,   ESnet 2  and  In  addition,  the  ANI  project  also  includes  a  

  8. Modular sensor network node

    DOE Patents [OSTI]

    Davis, Jesse Harper Zehring (Berkeley, CA); Stark, Jr., Douglas Paul (Tracy, CA); Kershaw, Christopher Patrick (Hayward, CA); Kyker, Ronald Dean (Livermore, CA)

    2008-06-10

    A distributed wireless sensor network node is disclosed. The wireless sensor network node includes a plurality of sensor modules coupled to a system bus and configured to sense a parameter. The parameter may be an object, an event or any other parameter. The node collects data representative of the parameter. The node also includes a communication module coupled to the system bus and configured to allow the node to communicate with other nodes. The node also includes a processing module coupled to the system bus and adapted to receive the data from the sensor module and operable to analyze the data. The node also includes a power module connected to the system bus and operable to generate a regulated voltage.

  9. Cognitive Radio Networks as Sensor Networks

    E-Print Network [OSTI]

    Bandari, Dorna; Yang, Seung R.; Zhao, Yue; Pottie, Gregory

    2007-01-01

    assuming the cognitive radios know their own coordinates.Networked Sensing Cognitive Radio Networks As SensorIntroduction: Cognitive Radio (CR) Networks The Need For

  10. Global interrupt and barrier networks

    DOE Patents [OSTI]

    Blumrich, Matthias A. (Ridgefield, CT); Chen, Dong (Croton-On-Hudson, NY); Coteus, Paul W. (Yorktown Heights, NY); Gara, Alan G. (Mount Kisco, NY); Giampapa, Mark E (Irvington, NY); Heidelberger, Philip (Cortlandt Manor, NY); Kopcsay, Gerard V. (Yorktown Heights, NY); Steinmacher-Burow, Burkhard D. (Mount Kisco, NY); Takken, Todd E. (Mount Kisco, NY)

    2008-10-28

    A system and method for generating global asynchronous signals in a computing structure. Particularly, a global interrupt and barrier network is implemented that implements logic for generating global interrupt and barrier signals for controlling global asynchronous operations performed by processing elements at selected processing nodes of a computing structure in accordance with a processing algorithm; and includes the physical interconnecting of the processing nodes for communicating the global interrupt and barrier signals to the elements via low-latency paths. The global asynchronous signals respectively initiate interrupt and barrier operations at the processing nodes at times selected for optimizing performance of the processing algorithms. In one embodiment, the global interrupt and barrier network is implemented in a scalable, massively parallel supercomputing device structure comprising a plurality of processing nodes interconnected by multiple independent networks, with each node including one or more processing elements for performing computation or communication activity as required when performing parallel algorithm operations. One multiple independent network includes a global tree network for enabling high-speed global tree communications among global tree network nodes or sub-trees thereof. The global interrupt and barrier network may operate in parallel with the global tree network for providing global asynchronous sideband signals.

  11. Optimal Gradient Clock Synchronization in Dynamic Networks

    E-Print Network [OSTI]

    with hardware clocks, but the rate of the hard- ware clocks can vary arbitrarily within specific bounds hardware clock, which can be used for this pur- pose; however, hardware clocks of different nodes run

  12. INSTRUMENTATION, INCLUDING NUCLEAR AND PARTICLE DETECTORS; RADIATION

    Office of Scientific and Technical Information (OSTI)

    interval technical basis document Chiaro, P.J. Jr. 44 INSTRUMENTATION, INCLUDING NUCLEAR AND PARTICLE DETECTORS; RADIATION DETECTORS; RADIATION MONITORS; DOSEMETERS;...

  13. Google matrix analysis of directed networks

    E-Print Network [OSTI]

    Leonardo Ermann; Klaus M. Frahm; Dima L. Shepelyansky

    2015-06-19

    In past ten years, modern societies developed enormous communication and social networks. Their classification and information retrieval processing become a formidable task for the society. Due to the rapid growth of World Wide Web, social and communication networks, new mathematical methods have been invented to characterize the properties of these networks on a more detailed and precise level. Various search engines are essentially using such methods. It is highly important to develop new tools to classify and rank enormous amount of network information in a way adapted to internal network structures and characteristics. This review describes the Google matrix analysis of directed complex networks demonstrating its efficiency on various examples including World Wide Web, Wikipedia, software architecture, world trade, social and citation networks, brain neural networks, DNA sequences and Ulam networks. The analytical and numerical matrix methods used in this analysis originate from the fields of Markov chains, quantum chaos and Random Matrix theory.

  14. Area of cooperation includes: Joint research and development on

    E-Print Network [OSTI]

    Buyya, Rajkumar

    with its expertise in the application area and market penetration will help us to transform our Grid computer hardware. IDC (International Data Corporation) projects the total grid technology market technologies to meet market requirements and make them attractive for enterprise applications" said Dr

  15. Preliminary Experimental Results of Integrated Gasification Fuel Cell Operation Using Hardware Simulation

    SciTech Connect (OSTI)

    Traverso, Alberto; Tucker, David; Haynes, Comas L.

    2012-07-01

    A newly developed integrated gasification fuel cell (IGFC) hybrid system concept has been tested using the Hybrid Performance (Hyper) project hardware-based simulation facility at the U.S. Department of Energy, National Energy Technology Laboratory. The cathode-loop hardware facility, previously connected to the real-time fuel cell model, was integrated with a real-time model of a gasifier of solid (biomass and fossil) fuel. The fuel cells are operated at the compressor delivery pressure, and they are fueled by an updraft atmospheric gasifier, through the syngas conditioning train for tar removal and syngas compression. The system was brought to steady state; then several perturbations in open loop (variable speed) and closed loop (constant speed) were performed in order to characterize the IGFC behavior. Coupled experiments and computations have shown the feasibility of relatively fast control of the plant as well as a possible mitigation strategy to reduce the thermal stress on the fuel cells as a consequence of load variation and change in gasifier operating conditions. Results also provided an insight into the different features of variable versus constant speed operation of the gas turbine section.

  16. Power-efficient hydraulic systems. Volume 2. Hardware demonstration phase. Final report, October 1985-July 1988

    SciTech Connect (OSTI)

    Hupp, R.V.; Haning, R.K.

    1988-07-01

    Energy-saving concepts for aircraft hydraulic systems were studied in a two-phase program. Task I was an investigation of methods and techniques to reduce overall hydraulic-system power requirements by lowering system demands and increasing component efficiencies. Task II involved hardware demonstration tests on selected concepts. Task I: Study phase. A baseline hydraulic system for an advanced aircraft design was established. Twenty energy-saving techniques were studied as candidates for application to the baseline vehicle. A global systems analysis approach was employed. The candidates were compared on the basis of total fuel consumption and six qualitative factors. Task II: Hardware demonstration phase. Two techniques demonstrated for energy savings were control valves with overlap and dual pressure-level systems. Tests were conducted on control valves, a servo actuator, dual pressure pumps, and a lightweight hydraulic system simulator. Valves with 0.002-in. overlap reduced system energy consumption 18% compared to using valves with zero lap. Operation at 4000 psi reduced system energy consumption 53% compared to operation at 8000 psi. Pressure-level switching was accomplished with excellent results.

  17. High-speed quantum networking by ship

    E-Print Network [OSTI]

    Simon J. Devitt; Andrew D. Greentree; Ashley M. Stephens; Rodney Van Meter

    2015-12-07

    Quantum communication will improve the security of cryptographic systems and decision-making algorithms, support secure client-server computation, and improve the sensitivity of scientific instruments. As these applications consume quantum entanglement, a method for replenishing networked entanglement is essential. Direct transmission of quantum signals over long distances is prevented by fibre attenuation and the no-cloning theorem. This has motivated the development of quantum repeaters, which are designed to purify entanglement and extend its range. Quantum repeaters have been demonstrated over short distances, but an error-corrected repeater network with sufficient bandwidth over global distances will require new technology. In particular, no proposed hardware appears suitable for deployment along undersea cables, leaving the prospect of isolated metropolitan networks. Here we show that error-corrected quantum memories installed in cargo containers and carried by ship could provide a flexible and scalable connection between local networks, enabling low-latency, high-fidelity quantum communication across global distances. With recent demonstrations of quantum technology with sufficient fidelity to enable topological error correction, implementation of the necessary quantum memories is within reach, and effective bandwidth will increase with improvements in fabrication. Thus, our architecture provides a new approach to quantum networking that avoids many of the technological requirements of undersea quantum repeaters, providing an alternate path to a worldwide Quantum Internet.

  18. Course may include: Research in Education

    E-Print Network [OSTI]

    Course may include: Research in Education Statistics in Education Theories of Educational Admin Policy Analysis Sociological Aspects of Education Approaches to Literacy Development Information and Communication Technologies Issues in Education Final Project Seminar Master of Education Educational

  19. An accelerator-based wireless sensor network processor in 130nm CMOS Mark Hempstead, Gu-Yeon Wei, David Brooks

    E-Print Network [OSTI]

    Hempstead, Mark

    , we propose an accelerator-based system architec- ture. Our design fully embraces the accelerator) System Block Diagram specifically to address event driven computation and long idle times that characterize wireless sensor network workloads. The system employs application specific hardware accelerators

  20. A Multi-Radio 802.11 Mesh Network Architecture Krishna Ramachandran Irfan Sheriff Elizabeth M. Belding Kevin Almeroth

    E-Print Network [OSTI]

    Belding-Royer, Elizabeth M.

    to challenges in three key areas. The first is the construction of a Split Wireless Router that enables modular wireless mesh routers to be constructed from commodity hardware. The second is the design of a centralized networks. We set two goals in its design. First, we must be able to build modular wireless mesh routers

  1. Gas storage materials, including hydrogen storage materials

    DOE Patents [OSTI]

    Mohtadi, Rana F; Wicks, George G; Heung, Leung K; Nakamura, Kenji

    2014-11-25

    A material for the storage and release of gases comprises a plurality of hollow elements, each hollow element comprising a porous wall enclosing an interior cavity, the interior cavity including structures of a solid-state storage material. In particular examples, the storage material is a hydrogen storage material, such as a solid state hydride. An improved method for forming such materials includes the solution diffusion of a storage material solution through a porous wall of a hollow element into an interior cavity.

  2. Gas storage materials, including hydrogen storage materials

    DOE Patents [OSTI]

    Mohtadi, Rana F; Wicks, George G; Heung, Leung K; Nakamura, Kenji

    2013-02-19

    A material for the storage and release of gases comprises a plurality of hollow elements, each hollow element comprising a porous wall enclosing an interior cavity, the interior cavity including structures of a solid-state storage material. In particular examples, the storage material is a hydrogen storage material such as a solid state hydride. An improved method for forming such materials includes the solution diffusion of a storage material solution through a porous wall of a hollow element into an interior cavity.

  3. Benchmarking Non-Hardware Balance-of-System (Soft) Costs for U.S. Photovoltaic Systems, Using a Bottom-Up Approach and Installer Survey - Second Edition

    SciTech Connect (OSTI)

    Friedman, B.; Ardani, K.; Feldman, D.; Citron, R.; Margolis, R.; Zuboy, J.

    2013-10-01

    This report presents results from the second U.S. Department of Energy (DOE) sponsored, bottom-up data-collection and analysis of non-hardware balance-of-system costs -- often referred to as 'business process' or 'soft' costs -- for U.S. residential and commercial photovoltaic (PV) systems. In service to DOE's SunShot Initiative, annual expenditure and labor-hour-productivity data are analyzed to benchmark 2012 soft costs related to (1) customer acquisition and system design (2) permitting, inspection, and interconnection (PII). We also include an in-depth analysis of costs related to financing, overhead, and profit. Soft costs are both a major challenge and a major opportunity for reducing PV system prices and stimulating SunShot-level PV deployment in the United States. The data and analysis in this series of benchmarking reports are a step toward the more detailed understanding of PV soft costs required to track and accelerate these price reductions.

  4. Development and operativity of a real-time radiological monitoring network centered on the nuclear power plant of Almaraz (Spain)

    SciTech Connect (OSTI)

    Baeza, A.; Miro, C.; Puerto, J.A. del; Rio, M. del; Ortiz, F.; Paniagua, J.M.

    1993-12-01

    This work presents the hardware and software characteristics of the environmental surveillance radiological network that has been installed around the nuclear power station of Almaraz (Spain). A description is given of the program RADLINE which allows radiological data to be logged in real time, and a study is made of the operativity of the network and the methodology followed in establishing the radiological pre-alert and alert levels.

  5. In Neural Networks, vol. 1, S1, p.552, 1988. ON THE EXPEDIENT USE OF NEURAL NETWORKS. Tony

    E-Print Network [OSTI]

    Martinez, Tony R.

    In Neural Networks, vol. 1, S1, p.552, 1988. ON THE EXPEDIENT USE OF NEURAL NETWORKS. Tony Martinez computer, calculators, special purpose logic devices, neural networks, etc. Each differs in its mechanism applications. Neural network features include parallel execution, adaptive learning, generalization, etc

  6. Robust Planarization of Unlocalized Wireless Sensor Networks

    E-Print Network [OSTI]

    Jiang, Anxiao "Andrew"

    then, it has also been used in numerous other applications, including data-centric storage, network other applications, including data-centric storage [17], network localization [15] and topology discovery [18] [8] [9]. Here the data-centric storage schemes use the planar graph to help determine

  7. Scramjet including integrated inlet and combustor

    SciTech Connect (OSTI)

    Kutschenreuter, P.H. Jr.; Blanton, J.C.

    1992-02-04

    This patent describes a scramjet engine. It comprises: a first surface including an aft facing step; a cowl including: a leading edge and a trailing edge; an upper surface and a lower surface extending between the leading edge and the trailing edge; the cowl upper surface being spaced from and generally parallel to the first surface to define an integrated inlet-combustor therebetween having an inlet for receiving and channeling into the inlet-combustor supersonic inlet airflow; means for injecting fuel into the inlet-combustor at the step for mixing with the supersonic inlet airflow for generating supersonic combustion gases; and further including a spaced pari of sidewalls extending between the first surface to the cowl upper surface and wherein the integrated inlet-combustor is generally rectangular and defined by the sidewall pair, the first surface and the cowl upper surface.

  8. The Texas Solution to the Nation's Disposal Needs for Irradiated Hardware - 13337

    SciTech Connect (OSTI)

    Britten, Jay M. [Waste Control Specialists LLC, Andrews, TX 79714 (United States)] [Waste Control Specialists LLC, Andrews, TX 79714 (United States)

    2013-07-01

    The closure of the disposal facility in Barnwell, South Carolina, to out-of-compact states in 2008 left commercial nuclear power plants without a disposal option for Class B and C irradiated hardware. In 2012, Waste Control Specialists LLC (WCS) opened a highly engineered facility specifically designed and built for the disposal of Class B and C waste. The WCS facility is the first Interstate Compact low-level radioactive waste disposal facility to be licensed and operated under the Low-level Waste Policy Act of 1980, as amended in 1985. Due to design requirements of a modern Low Level Radioactive Waste (LLRW) facility, traditional methods for disposal were not achievable at the WCS site. Earlier methods primarily utilized the As Low as Reasonably Achievable (ALARA) concept of distance to accomplish worker safety. The WCS method required the use of all three ALARA concepts of time, distance, and shielding to ensure the safe disposal of this highly hazardous waste stream. (authors)

  9. Design of a Hardware Track Finder (Fast Tracker) for the ATLAS Trigger

    E-Print Network [OSTI]

    Cavaliere, Viviana; The ATLAS collaboration

    2015-01-01

    The use of tracking information at the trigger level in the LHC Run II period is crucial for the trigger an data acquisition (TDAQ) system and will be even more so as contemporary collisions that occur at every bunch crossing will increase in Run III. The Fast TracKer (FTK) is part of the ATLAS trigger upgrade project; it is a hardware processor that will provide every Level-1 accepted event (100 kHz) and within 100$\\mu$s, full tracking information for tracks with momentum as low as 1 GeV. Providing fast, extensive access to tracking information, with resolution comparable to the offline reconstruction, FTK will help in precise detection of the primary and secondary vertices to ensure robust selections and improve the trigger performance.

  10. Next generation hyper-scale software and hardware systems for big data analytics

    E-Print Network [OSTI]

    CERN. Geneva

    2013-01-01

    Building on foundational technologies such as many-core systems, non-volatile memories and photonic interconnects, we describe some current technologies and future research to create real-time, big data analytics, IT infrastructure. We will also briefly describe some of our biologically-inspired software and hardware architecture for creating radically new hyper-scale cognitive computing systems. About the speaker Rich Friedrich is the director of Strategic Innovation and Research Services (SIRS) at HP Labs. In this strategic role, he is responsible for research investments in nano-technology, exascale computing, cyber security, information management, cloud computing, immersive interaction, sustainability, social computing and commercial digital printing. Rich's philosophy is to fuse strategy and inspiration to create compelling capabilities for next generation information devices, systems and services. Using essential insights gained from the metaphysics of innnovation, he effectively leads ...

  11. Software Reliability Cases: The Bridge Between Hardware, Software and System Safety and Reliability

    SciTech Connect (OSTI)

    Herrmann, D.S.; Peercy, D.E.

    1999-01-08

    High integrity/high consequence systems must be safe and reliable; hence it is only logical that both software safety and software reliability cases should be developed. Risk assessments in safety cases evaluate the severity of the consequences of a hazard and the likelihood of it occurring. The likelihood is directly related to system and software reliability predictions. Software reliability cases, as promoted by SAE JA 1002 and 1003, provide a practical approach to bridge the gap between hardware reliability, software reliability, and system safety and reliability by using a common methodology and information structure. They also facilitate early insight into whether or not a project is on track for meeting stated safety and reliability goals, while facilitating an informed assessment by regulatory and/or contractual authorities.

  12. Electric Power Monthly, August 1990. [Glossary included

    SciTech Connect (OSTI)

    Not Available

    1990-11-29

    The Electric Power Monthly (EPM) presents monthly summaries of electric utility statistics at the national, Census division, and State level. The purpose of this publication is to provide energy decisionmakers with accurate and timely information that may be used in forming various perspectives on electric issues that lie ahead. Data includes generation by energy source (coal, oil, gas, hydroelectric, and nuclear); generation by region; consumption of fossil fuels for power generation; sales of electric power, cost data; and unusual occurrences. A glossary is included.

  13. The Community Environmental Monitoring Program in the 21st Century: The Evolution of a Monitoring Network

    SciTech Connect (OSTI)

    Hartwell, W.T.; Tappen, J.; Karr, L.

    2007-01-19

    This paper focuses on the evolution of the various operational aspects of the Community Environmental Monitoring Program (CEMP) network following the transfer of program administration from the U.S. Environmental Protection Agency (EPA) to the Desert Research Institute (DRI) of the Nevada System of Higher Education in 1999-2000. The CEMP consists of a network of 29 fixed radiation and weather monitoring stations located in Nevada, Utah, and California. Its mission is to involve stakeholders directly in monitoring for airborne radiological releases to the off site environment as a result of past or ongoing activities on the Nevada Test Site (NTS) and to make data as transparent and accessible to the general public as feasible. At its inception in 1981, the CEMP was a cooperative project of the U.S. Department of Energy (DOE), DRI, and EPA. In 1999-2000, technical administration of the CEMP transitioned from EPA to DRI. Concurrent with and subsequent to this transition, station and program operations underwent significant enhancements that furthered the mission of the program. These enhancements included the addition of a full suite of meteorological instrumentation, state-of-the-art electronic data collectors, on-site displays, and communications hardware. A public website was developed. Finally, the DRI developed a mobile monitoring station that can be operated entirely on solar power in conjunction with a deep-cell battery, and includes all meteorological sensors and a pressurized ion chamber for detecting background gamma radiation. Final station configurations have resulted in the creation of a platform that is well suited for use as an in-field multi-environment test-bed for prototype environmental sensors and in interfacing with other scientific and educational programs. Recent and near-future collaborators have included federal, state, and local agencies in both the government and private sectors. The CEMP also serves as a model for other programs wishing to involve stakeholders with a meaningful role in the process of monitoring and data collection.

  14. MOTIVATION INCLUDED OR EXCLUDED FROM Mihaela Cocea

    E-Print Network [OSTI]

    Cocea, Mihaela

    MOTIVATION ­ INCLUDED OR EXCLUDED FROM E-LEARNING Mihaela Cocea National College of Ireland Mayor, Dublin 1, Ireland sweibelzahl@ncirl.ie ABSTRACT The learners' motivation has an impact on the quality-Learning, motivation has been mainly considered in terms of instructional design. Research in this direction suggests

  15. Energy Consumption of Personal Computing Including Portable

    E-Print Network [OSTI]

    Namboodiri, Vinod

    processing unit (CPU) processing power and capacity of mass storage devices doubles every 18 months. Such growth in both processing and storage capabilities fuels the production of ever more powerful portableEnergy Consumption of Personal Computing Including Portable Communication Devices Pavel Somavat1

  16. Course may include: Research in Education

    E-Print Network [OSTI]

    Development Information and Communication Technologies Issues in Education Final Project Seminar Master, the Final Project Seminar. This graduate program will allow you to develop your skills and knowledgeCourse may include: Research in Education Qualitative Methods in Educational Research Fundamentals

  17. Collective network for computer structures

    DOE Patents [OSTI]

    Blumrich, Matthias A; Coteus, Paul W; Chen, Dong; Gara, Alan; Giampapa, Mark E; Heidelberger, Philip; Hoenicke, Dirk; Takken, Todd E; Steinmacher-Burow, Burkhard D; Vranas, Pavlos M

    2014-01-07

    A system and method for enabling high-speed, low-latency global collective communications among interconnected processing nodes. The global collective network optimally enables collective reduction operations to be performed during parallel algorithm operations executing in a computer structure having a plurality of the interconnected processing nodes. Router devices are included that interconnect the nodes of the network via links to facilitate performance of low-latency global processing operations at nodes of the virtual network. The global collective network may be configured to provide global barrier and interrupt functionality in asynchronous or synchronized manner. When implemented in a massively-parallel supercomputing structure, the global collective network is physically and logically partitionable according to the needs of a processing algorithm.

  18. Collective network for computer structures

    DOE Patents [OSTI]

    Blumrich, Matthias A. (Ridgefield, CT); Coteus, Paul W. (Yorktown Heights, NY); Chen, Dong (Croton On Hudson, NY); Gara, Alan (Mount Kisco, NY); Giampapa, Mark E. (Irvington, NY); Heidelberger, Philip (Cortlandt Manor, NY); Hoenicke, Dirk (Ossining, NY); Takken, Todd E. (Brewster, NY); Steinmacher-Burow, Burkhard D. (Wernau, DE); Vranas, Pavlos M. (Bedford Hills, NY)

    2011-08-16

    A system and method for enabling high-speed, low-latency global collective communications among interconnected processing nodes. The global collective network optimally enables collective reduction operations to be performed during parallel algorithm operations executing in a computer structure having a plurality of the interconnected processing nodes. Router devices ate included that interconnect the nodes of the network via links to facilitate performance of low-latency global processing operations at nodes of the virtual network and class structures. The global collective network may be configured to provide global barrier and interrupt functionality in asynchronous or synchronized manner. When implemented in a massively-parallel supercomputing structure, the global collective network is physically and logically partitionable according to needs of a processing algorithm.

  19. Broadening Industry Governance to Include Nonproliferation

    SciTech Connect (OSTI)

    Hund, Gretchen; Seward, Amy M.

    2008-11-11

    As industry is the first line of defense in detecting and thwarting illicit trade networks, the engagement of the private sector is critical to any government effort to strengthen existing mechanisms to protect goods and services throughout the supply chain. This study builds on previous PNNL work to continue to evaluate means for greater industry engagement to complement and strengthen existing governmental efforts to detect and stem the trade of illicit goods and to protect and secure goods that could be used in making a weapon of mass destruction. Specifically, the study evaluates the concept of Industry Self Regulation, defined as a systematic voluntary program undertaken by an industry or by individual companies to anticipate, implement, supplement, or substitute for regulatory requirements in a given field, generally through the adoption of best practices. Through a series of interviews with companies with a past history of non-compliance, trade associations and NGOs, the authors identify gaps in the existing regulatory infrastructure, drivers for a self regulation approach and the form such an approach might take, as well as obstacles to be overcome. The authors conclude that it is at the intersection of industry, government, and security that—through collaborative means—the effectiveness of the international nonproliferation system—can be most effectively strengthened to the mutual benefit of both government and the private sector. Industry has a critical stake in the success of this regime, and has the potential to act as an integrating force that brings together the existing mechanisms of the global nonproliferation regime: export controls, physical protection, and safeguards. The authors conclude that industry compliance is not enough; rather, nonproliferation must become a central tenant of a company’s corporate culture and be viewed as an integral component of corporate social responsibility (CSR).

  20. Subterranean barriers including at least one weld

    DOE Patents [OSTI]

    Nickelson, Reva A.; Sloan, Paul A.; Richardson, John G.; Walsh, Stephanie; Kostelnik, Kevin M.

    2007-01-09

    A subterranean barrier and method for forming same are disclosed, the barrier including a plurality of casing strings wherein at least one casing string of the plurality of casing strings may be affixed to at least another adjacent casing string of the plurality of casing strings through at least one weld, at least one adhesive joint, or both. A method and system for nondestructively inspecting a subterranean barrier is disclosed. For instance, a radiographic signal may be emitted from within a casing string toward an adjacent casing string and the radiographic signal may be detected from within the adjacent casing string. A method of repairing a barrier including removing at least a portion of a casing string and welding a repair element within the casing string is disclosed. A method of selectively heating at least one casing string forming at least a portion of a subterranean barrier is disclosed.

  1. Photoactive devices including porphyrinoids with coordinating additives

    DOE Patents [OSTI]

    Forrest, Stephen R; Zimmerman, Jeramy; Yu, Eric K; Thompson, Mark E; Trinh, Cong; Whited, Matthew; Diev, Vlacheslav

    2015-05-12

    Coordinating additives are included in porphyrinoid-based materials to promote intermolecular organization and improve one or more photoelectric characteristics of the materials. The coordinating additives are selected from fullerene compounds and organic compounds having free electron pairs. Combinations of different coordinating additives can be used to tailor the characteristic properties of such porphyrinoid-based materials, including porphyrin oligomers. Bidentate ligands are one type of coordinating additive that can form coordination bonds with a central metal ion of two different porphyrinoid compounds to promote porphyrinoid alignment and/or pi-stacking. The coordinating additives can shift the absorption spectrum of a photoactive material toward higher wavelengths, increase the external quantum efficiency of the material, or both.

  2. Power generation method including membrane separation

    DOE Patents [OSTI]

    Lokhandwala, Kaaeid A. (Union City, CA)

    2000-01-01

    A method for generating electric power, such as at, or close to, natural gas fields. The method includes conditioning natural gas containing C.sub.3+ hydrocarbons and/or acid gas by means of a membrane separation step. This step creates a leaner, sweeter, drier gas, which is then used as combustion fuel to run a turbine, which is in turn used for power generation.

  3. Rotor assembly including superconducting magnetic coil

    DOE Patents [OSTI]

    Snitchler, Gregory L. (Shrewsbury, MA); Gamble, Bruce B. (Wellesley, MA); Voccio, John P. (Somerville, MA)

    2003-01-01

    Superconducting coils and methods of manufacture include a superconductor tape wound concentrically about and disposed along an axis of the coil to define an opening having a dimension which gradually decreases, in the direction along the axis, from a first end to a second end of the coil. Each turn of the superconductor tape has a broad surface maintained substantially parallel to the axis of the coil.

  4. Nuclear reactor shield including magnesium oxide

    DOE Patents [OSTI]

    Rouse, Carl A. (Del Mar, CA); Simnad, Massoud T. (La Jolla, CA)

    1981-01-01

    An improvement in nuclear reactor shielding of a type used in reactor applications involving significant amounts of fast neutron flux, the reactor shielding including means providing structural support, neutron moderator material, neutron absorber material and other components as described below, wherein at least a portion of the neutron moderator material is magnesium in the form of magnesium oxide either alone or in combination with other moderator materials such as graphite and iron.

  5. Electric power monthly, September 1990. [Glossary included

    SciTech Connect (OSTI)

    Not Available

    1990-12-17

    The purpose of this report is to provide energy decision makers with accurate and timely information that may be used in forming various perspectives on electric issues. The power plants considered include coal, petroleum, natural gas, hydroelectric, and nuclear power plants. Data are presented for power generation, fuel consumption, fuel receipts and cost, sales of electricity, and unusual occurrences at power plants. Data are compared at the national, Census division, and state levels. 4 figs., 52 tabs. (CK)

  6. Energy Efficient Digital Networks

    E-Print Network [OSTI]

    Lanzisera, Steven

    2014-01-01

    equipment, market transformation for digital networks iimarket transformation of energy efficient digital networks.transformation activities. Table 7: Transforming the Network for Digital

  7. Social networks and research output

    E-Print Network [OSTI]

    Ductor, Lorenzo; Fafchamps, Marcel; Goyal, Sanjeev; van der Leij, Marco J.

    2013-11-12

    and Scheinkman (2002). In recent years, interest has shifted to the ways by which the architecture of social networks influences behavior and outcomes.2 Recent empirical papers on network effects include Bramoulle´, Djebbari and Fortin (2009), Calvo... the length of papers and the duration of the review process in economics, it is reasonable to suppose that collabora- tion entails communication over an extended period of time. These considerations – personal interaction and sustained communication – in turn...

  8. Arithmetic functions in torus and tree networks

    DOE Patents [OSTI]

    Bhanot, Gyan (Princeton, NJ); Blumrich, Matthias A. (Ridgefield, CT); Chen, Dong (Croton On Hudson, NY); Gara, Alan G. (Mount Kisco, NY); Giampapa, Mark E. (Irvington, NY); Heidelberger, Philip (Cortlandt Manor, NY); Steinmacher-Burow, Burkhard D. (Mount Kisco, NY); Vranas, Pavlos M. (Bedford Hills, NY)

    2007-12-25

    Methods and systems for performing arithmetic functions. In accordance with a first aspect of the invention, methods and apparatus are provided, working in conjunction of software algorithms and hardware implementation of class network routing, to achieve a very significant reduction in the time required for global arithmetic operation on the torus. Therefore, it leads to greater scalability of applications running on large parallel machines. The invention involves three steps in improving the efficiency and accuracy of global operations: (1) Ensuring, when necessary, that all the nodes do the global operation on the data in the same order and so obtain a unique answer, independent of roundoff error; (2) Using the topology of the torus to minimize the number of hops and the bidirectional capabilities of the network to reduce the number of time steps in the data transfer operation to an absolute minimum; and (3) Using class function routing to reduce latency in the data transfer. With the method of this invention, every single element is injected into the network only once and it will be stored and forwarded without any further software overhead. In accordance with a second aspect of the invention, methods and systems are provided to efficiently implement global arithmetic operations on a network that supports the global combining operations. The latency of doing such global operations are greatly reduced by using these methods.

  9. Simple AEAD Hardware Interface (SHI) in a SoC: Implementing an On-Chip Keyak/WhirlBob Coprocessor

    E-Print Network [OSTI]

    International Association for Cryptologic Research (IACR)

    Markku-Juhani O. Saarinen Norwegian University of Science and Technology Department of Telematics, O-equipped mid-range CPUs. Extended battery life and bandwidth resulting from ded- icated cryptographic hardware is vital for currently domi- nant computing and communication devices: mobile phones, tablets, and Internet

  10. Accepted for publication in Proceedings of the 1999 International Hardware Description Languages Conference and Exhibit (HDLCON '99).

    E-Print Network [OSTI]

    Esser, Robert

    makes models more amenable to formal verification based on state-space exploration. The language is also As the complexity ofintegrated hardware and software sys- tems increases, system-level design languages are becom. Designers focus first on the abstract properties of a system in various domains and devise a systems

  11. Electromagnetic Compatibility (EMC) of CAN+* Tobias Ziermann and Jrgen Teich, Hardware/Software Co-Design, Department of Computer Science,

    E-Print Network [OSTI]

    Teich, Jürgen

    Electromagnetic Compatibility (EMC) of CAN+* Tobias Ziermann and Jürgen Teich, Hardware/Software Co-Design to standard CAN in terms of EMC. 1 Introduction The CAN has established itself to be the de facto standard-cost. This is pos- sible because its popularity enables mass production. The only disadvantage of CAN

  12. Abstract--Better software and hardware for automatic classification of power quality (PQ) disturbances are desired for

    E-Print Network [OSTI]

    Mamishev, Alexander

    1 Abstract--Better software and hardware for automatic classification of power quality (PQ. The flexibility of this method allows classification of a very broad range of power quality events of this two-paper series [1]. Index Terms--Power Quality, Classification-Optimal TFR, Time-Frequency Ambiguity

  13. The Chinook Hardware/Software Co-Synthesis System Pai H. Chou Ross B. Ortega Gaetano Borriello

    E-Print Network [OSTI]

    Shinozuka, Masanobu

    The Chinook Hardware/Software Co-Synthesis System Pai H. Chou Ross B. Ortega Gaetano Borriello Department of Computer Science & Engineering University of Washington Seattle, WA 98195-2350 Abstract tools for embedded systems have not kept pace with these trends. The Chinook co-synthesis system

  14. Development of Multithread Real-Time Applications using a Hardware Scheduler Elias Teodoro Silva Jr1,2

    E-Print Network [OSTI]

    Wagner, Flávio Rech

    is the scheduler implementation (SW or HW) chosen by the designer. The scheduler is validated by a case study}@eletro.ufrgs.br Abstract This paper presents the design and evaluation of a scheduling system implemented in hardware- time application and emphasizing the flexibility given to the designer, who can easily choose among

  15. Fastpass: A Centralized “Zero-Queue” Datacenter Network

    E-Print Network [OSTI]

    Perry, Jonathan

    An ideal datacenter network should provide several properties, including low median and tail latency, high utilization (throughput), fair allocation of network resources between users or applications, deadline-aware ...

  16. Mobileflow: Applying SDN to Mobility in Wireless Networks 

    E-Print Network [OSTI]

    Al-Shaikhli, Raghdah

    2014-08-10

    Wireless technology has become an increasingly popular way for network access. Wireless networks provide efficient, reliable service; supporting a broad range of emerging applications including multimedia streaming and video conferencing. Currently...

  17. Network and adaptive system of systems modeling and analysis.

    SciTech Connect (OSTI)

    Lawton, Craig R.; Campbell, James E. Dr.; Anderson, Dennis James; Eddy, John P.

    2007-05-01

    This report documents the results of an LDRD program entitled ''Network and Adaptive System of Systems Modeling and Analysis'' that was conducted during FY 2005 and FY 2006. The purpose of this study was to determine and implement ways to incorporate network communications modeling into existing System of Systems (SoS) modeling capabilities. Current SoS modeling, particularly for the Future Combat Systems (FCS) program, is conducted under the assumption that communication between the various systems is always possible and occurs instantaneously. A more realistic representation of these communications allows for better, more accurate simulation results. The current approach to meeting this objective has been to use existing capabilities to model network hardware reliability and adding capabilities to use that information to model the impact on the sustainment supply chain and operational availability.

  18. 226 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, VOL. 19, NO. 2, FEBRUARY 2009 A Hardware Architecture for Real-Time

    E-Print Network [OSTI]

    Lunds Universitet

    226 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, VOL. 19, NO. 2, FEBRUARY 2009 A Hardware Architecture for Real-Time Video Segmentation Utilizing Memory Reduction Techniques Hongtu Jiang results and hardware efficiency. In addition, to achieve real-time performance with high resolution video

  19. High-Speed Real-Time Digital Emulation for Hardware-in-the-Loop Testing of Power Electronics: A New Paradigm in the Field of

    E-Print Network [OSTI]

    Sanders, Seth

    High-Speed Real-Time Digital Emulation for Hardware-in-the-Loop Testing of Power Electronics: A New Paradigm in the Field of Electronic Design Automation (EDA) for Power Electronics Systems Michel A. Kinsy-time emulation for Hardware-in-the-Loop (HiL) testing and design of high-power power electronics systems. Our

  20. Primal-Dual Interior Point Method Applied to the Short Term Hydroelectric Scheduling Including a

    E-Print Network [OSTI]

    Oliveira, Aurélio R. L.

    Primal-Dual Interior Point Method Applied to the Short Term Hydroelectric Scheduling Including that minimizes losses in the transmission and costs in the generation of a hydroelectric power system, formulated such perturbing parameter. Keywords-- Hydroelectric power system, Network flow, Predispatch, Primal-dual interior

  1. Optical panel system including stackable waveguides

    DOE Patents [OSTI]

    DeSanto, Leonard (Dunkirk, MD); Veligdan, James T. (Manorville, NY)

    2007-11-20

    An optical panel system including stackable waveguides is provided. The optical panel system displays a projected light image and comprises a plurality of planar optical waveguides in a stacked state. The optical panel system further comprises a support system that aligns and supports the waveguides in the stacked state. In one embodiment, the support system comprises at least one rod, wherein each waveguide contains at least one hole, and wherein each rod is positioned through a corresponding hole in each waveguide. In another embodiment, the support system comprises at least two opposing edge structures having the waveguides positioned therebetween, wherein each opposing edge structure contains a mating surface, wherein opposite edges of each waveguide contain mating surfaces which are complementary to the mating surfaces of the opposing edge structures, and wherein each mating surface of the opposing edge structures engages a corresponding complementary mating surface of the opposite edges of each waveguide.

  2. Thermovoltaic semiconductor device including a plasma filter

    DOE Patents [OSTI]

    Baldasaro, Paul F. (Clifton Park, NY)

    1999-01-01

    A thermovoltaic energy conversion device and related method for converting thermal energy into an electrical potential. An interference filter is provided on a semiconductor thermovoltaic cell to pre-filter black body radiation. The semiconductor thermovoltaic cell includes a P/N junction supported on a substrate which converts incident thermal energy below the semiconductor junction band gap into electrical potential. The semiconductor substrate is doped to provide a plasma filter which reflects back energy having a wavelength which is above the band gap and which is ineffectively filtered by the interference filter, through the P/N junction to the source of radiation thereby avoiding parasitic absorption of the unusable portion of the thermal radiation energy.

  3. Simple Model of Membrane Proteins Including Solvent

    E-Print Network [OSTI]

    D. L. Pagan; A. Shiryayev; T. P. Connor; J. D. Gunton

    2006-03-04

    We report a numerical simulation for the phase diagram of a simple two dimensional model, similar to one proposed by Noro and Frenkel [J. Chem. Phys. \\textbf{114}, 2477 (2001)] for membrane proteins, but one that includes the role of the solvent. We first use Gibbs ensemble Monte Caro simulations to determine the phase behavior of particles interacting via a square-well potential in two dimensions for various values of the interaction range. A phenomenological model for the solute-solvent interactions is then studied to understand how the fluid-fluid coexistence curve is modified by solute-solvent interactions. It is shown that such a model can yield systems with liquid-liquid phase separation curves that have both upper and lower critical points, as well as closed loop phase diagrams, as is the case with the corresponding three dimensional model.

  4. Unconditionally secure computers, algorithms and hardware, such as memories, processors, keyboards, flash and hard drives

    E-Print Network [OSTI]

    Laszlo B. Kish; Olivier Saidi

    2008-04-24

    In the case of the need of extraordinary security, Kirchhoff-loop-Johnson-(like)-noise ciphers can easily be integrated on existing types of digital chips in order to provide secure data communication between hardware processors, memory chips, hard disks and other units within a computer or other data processor system. The secure key exchange can take place at the very first run and the system can renew the key later at random times with an authenticated fashion to prohibit man-in-the-middle attack. The key can be stored in flash memories within the communicating chip units at hidden random addresses among other random bits that are continuously generated by the secure line but are never actually used. Thus, even if the system is disassembled, and the eavesdropper can have direct access to the communication lines between the units, or even if she is trying to use a man-in-the-middle attack, no information can be extracted. The only way to break the code is to learn the chip structure, to understand the machine code program and to read out the information during running by accessing the proper internal ports of the working chips. However such an attack needs extraordinary resources and even that can be prohibited by a password lockout. The unconditional security of commercial algorithms against piracy can be provided in a similar way.

  5. DEVELOPMENT OF SIGNAL PROCESSING TOOLS AND HARDWARE FOR PIEZOELECTRIC SENSOR DIAGNOSTIC PROCESSES

    SciTech Connect (OSTI)

    OVERLY, TIMOTHY G. [Los Alamos National Laboratory; PARK, GYUHAE [Los Alamos National Laboratory; FARRAR, CHARLES R. [Los Alamos National Laboratory

    2007-02-09

    This paper presents a piezoelectric sensor diagnostic and validation procedure that performs in -situ monitoring of the operational status of piezoelectric (PZT) sensor/actuator arrays used in structural health monitoring (SHM) applications. The validation of the proper function of a sensor/actuator array during operation, is a critical component to a complete and robust SHM system, especially with the large number of active sensors typically involved. The method of this technique used to obtain the health of the PZT transducers is to track their capacitive value, this value manifests in the imaginary part of measured electrical admittance. Degradation of the mechanical/electric properties of a PZT sensor/actuator as well as bonding defects between a PZT patch and a host structure can be identified with the proposed procedure. However, it was found that temperature variations and changes in sensor boundary conditions manifest themselves in similar ways in the measured electrical admittances. Therefore, they examined the effects of temperature variation and sensor boundary conditions on the sensor diagnostic process. The objective of this study is to quantify and classify several key characteristics of temperature change and to develop efficient signal processing techniques to account for those variations in the sensor diagnostis process. In addition, they developed hardware capable of making the necessary measurements to perform the sensor diagnostics and to make impedance-based SHM measurements. The paper concludes with experimental results to demonstrate the effectiveness of the proposed technique.

  6. Aging model for solid lubricants used in weapon stronglinks: tribological performance and hardware review

    SciTech Connect (OSTI)

    Dugger, M.T.; Peebles, D.E.; Sorroche, E.H.; Varga, K.S.; Bryan, R.M.

    1997-09-01

    The solid lubricant used most extensively in strong links throughout the enduring stockpile contains MoS{sub 2}, which is known to react with oxygen and water vapor resulting in a change in the material`s friction and wear behavior. The authors have examined the frictional behavior of this lubricant as a function of oxidation, in support of efforts to quantify the impact of changes in the material on the dynamic behavior of the MC2969 strong link. Their results show that the friction response of oxidized lubricant is strongly influenced by the amount of burnishing performed on the lubricant after deposition. Low levels of burnish leave a thick film, of which only the near surface degrades during oxidation. Rapid wear of the oxidized material leaves a surface whose properties are the same as non-oxidized material. Higher levels of burnish leave a thinner film of lubricant such that the entire film may be oxidized. The friction coefficient on this surface reaches a steady state value greater than that of non oxidized material. In addition to these fundamental differences in steady state behavior, they have shown that the initial friction coefficient on oxidized surfaces is related to the amount of sulfide converted to sulfate, regardless of the oxidation conditions used. Measurements on parts returned from the stockpile show that the friction behavior of aged hardware is consistent with the behavior observed on controlled substrates containing thin lubricant films.

  7. Fabrication of gas turbine water-cooled composite nozzle and bucket hardware employing plasma spray process

    DOE Patents [OSTI]

    Schilke, Peter W. (4 Hempshire Ct., Scotia, NY 12302); Muth, Myron C. (R.D. #3, Western Ave., Amsterdam, NY 12010); Schilling, William F. (301 Garnsey Rd., Rexford, NY 12148); Rairden, III, John R. (6 Coronet Ct., Schenectady, NY 12309)

    1983-01-01

    In the method for fabrication of water-cooled composite nozzle and bucket hardware for high temperature gas turbines, a high thermal conductivity copper alloy is applied, employing a high velocity/low pressure (HV/LP) plasma arc spraying process, to an assembly comprising a structural framework of copper alloy or a nickel-based super alloy, or combination of the two, and overlying cooling tubes. The copper alloy is plamsa sprayed to a coating thickness sufficient to completely cover the cooling tubes, and to allow for machining back of the copper alloy to create a smooth surface having a thickness of from 0.010 inch (0.254 mm) to 0.150 inch (3.18 mm) or more. The layer of copper applied by the plasma spraying has no continuous porosity, and advantageously may readily be employed to sustain a pressure differential during hot isostatic pressing (HIP) bonding of the overall structure to enhance bonding by solid state diffusion between the component parts of the structure.

  8. ATCA digital controller hardware for vertical stabilization of plasmas in tokamaks

    SciTech Connect (OSTI)

    Batista, A. J. N.; Sousa, J.; Varandas, C. A. F. [Associaca(tilde sign)o EURATOM/IST, Centro de Fusa(tilde sign)o Nuclear, Avenida Rovisco Pais 1, 1049-001 Lisbon (Portugal)

    2006-10-15

    The efficient vertical stabilization (VS) of plasmas in tokamaks requires a fast reaction of the VS controller, for example, after detection of edge localized modes (ELM). For controlling the effects of very large ELMs a new digital control hardware, based on the Advanced Telecommunications Computing Architecture trade mark sign (ATCA), is being developed aiming to reduce the VS digital control loop cycle (down to an optimal value of 10 {mu}s) and improve the algorithm performance. The system has 1 ATCA trade mark sign processor module and up to 12 ATCA trade mark sign control modules, each one with 32 analog input channels (12 bit resolution), 4 analog output channels (12 bit resolution), and 8 digital input/output channels. The Aurora trade mark sign and PCI Express trade mark sign communication protocols will be used for data transport, between modules, with expected latencies below 2 {mu}s. Control algorithms are implemented on a ix86 based processor with 6 Gflops and on field programmable gate arrays with 80 GMACS, interconnected by serial gigabit links in a full mesh topology.

  9. What are essential concepts about networks?

    E-Print Network [OSTI]

    Sayama, Hiroki; Porter, Mason A; Sheetz, Lori; Uzzo, Stephen

    2015-01-01

    Networks have become increasingly relevant to everyday life as our society has become increasingly connected. Attaining a basic understanding of networks has thus become a necessary form of literacy for all people living in today's society (and for youths in particular). At the NetSci 2014 conference, we initiated a year-long process to develop an educational resource that concisely summarizes essential concepts about networks that can be used by anyone of school age and older. The process involved several brainstorming sessions on one key question: "What should every person living in the 21st century know about networks by the time he/she finishes secondary education?" Different sessions reached diverse participants, which included professional researchers in network science, educators, and high-school students. The generated ideas were connected by the students to construct a concept network. We examined community structure in the concept network to group ideas into a set of important concepts, which we ref...

  10. The Design of a Bloom Filter Hardware Accelerator for Ultra Low Power Systems

    E-Print Network [OSTI]

    Brooks, David

    ,dbrooks}@eecs.harvard.edu ABSTRACT Battery-powered embedded systems require low energy usage to extend system lifetime. These systems and David Brooks School of Engineering and Applied Sciences, Harvard University, Cambridge, MA {mjlyons. Recent techniques for reducing energy consumption in wireless sensor networks, such as aggregation

  11. Expansion of the internet protocol address space with "minor" disruption of current hardware or software 

    E-Print Network [OSTI]

    Wheatley, Philip Stephen

    1996-01-01

    Currently, the Internet suite of protocols uses a 32 bit network layer address and requires that each machine have a unique address. The problem: 32 bits only distinguishes 2 32 or 4,294,967,296 machines. Even with four billion addresses, experts...

  12. Phoebus: Network Middleware for Next-Generation Network Computing

    SciTech Connect (OSTI)

    Martin Swany

    2012-06-16

    The Phoebus project investigated algorithms, protocols, and middleware infrastructure to improve end-to-end performance in high speed, dynamic networks. The Phoebus system essentially serves as an adaptation point for networks with disparate capabilities or provisioning. This adaptation can take a variety of forms including acting as a provisioning agent across multiple signaling domains, providing transport protocol adaptation points, and mapping between distributed resource reservation paradigms and the optical network control plane. We have successfully developed the system and demonstrated benefits. The Phoebus system was deployed in Internet2 and in ESnet, as well as in GEANT2, RNP in Brazil and over international links to Korea and Japan. Phoebus is a system that implements a new protocol and associated forwarding infrastructure for improving throughput in high-speed dynamic networks. It was developed to serve the needs of large DOE applications on high-performance networks. The idea underlying the Phoebus model is to embed Phoebus Gateways (PGs) in the network as on-ramps to dynamic circuit networks. The gateways act as protocol translators that allow legacy applications to use dedicated paths with high performance.

  13. Engine lubrication circuit including two pumps

    DOE Patents [OSTI]

    Lane, William H.

    2006-10-03

    A lubrication pump coupled to the engine is sized such that the it can supply the engine with a predetermined flow volume as soon as the engine reaches a peak torque engine speed. In engines that operate predominately at speeds above the peak torque engine speed, the lubrication pump is often producing lubrication fluid in excess of the predetermined flow volume that is bypassed back to a lubrication fluid source. This arguably results in wasted power. In order to more efficiently lubricate an engine, a lubrication circuit includes a lubrication pump and a variable delivery pump. The lubrication pump is operably coupled to the engine, and the variable delivery pump is in communication with a pump output controller that is operable to vary a lubrication fluid output from the variable delivery pump as a function of at least one of engine speed and lubrication flow volume or system pressure. Thus, the lubrication pump can be sized to produce the predetermined flow volume at a speed range at which the engine predominately operates while the variable delivery pump can supplement lubrication fluid delivery from the lubrication pump at engine speeds below the predominant engine speed range.

  14. Sensor networks offer a powerful combination of distributed sensing, computing and com-munication. They lend themselves to countless applications and, at the same time, offer

    E-Print Network [OSTI]

    Haenggi, Martin

    environmental data (air temperature, light, wind, relative humidity and rainfall) are gathered by a network to their peculiarities, primarily the stringent energy constraints to which sensing nodes are typically subjected. The distinguishing traits of sensor net- works have a direct impact on the hardware design of the nodes at at least

  15. Wireless Sensor Networks (WSN) consist of small, low-cost, resource-constrained embedded computers equipped with low-power radios and various sensors. When deployed, they form

    E-Print Network [OSTI]

    Maróti, Miklós

    Wireless Sensor Networks (WSN) consist of small, low-cost, resource-constrained embedded computers, healthcare, structural monitoring and the military among others. Many WSN applications rely on the location as they require no specialized hardware; they use the radio chip readily available on WSN nodes. RSS-based ranging

  16. Fuzzy Logic Based Anomaly Detection for Embedded Network Security Cyber Sensor

    SciTech Connect (OSTI)

    Ondrej Linda; Todd Vollmer; Jason Wright; Milos Manic

    2011-04-01

    Resiliency and security in critical infrastructure control systems in the modern world of cyber terrorism constitute a relevant concern. Developing a network security system specifically tailored to the requirements of such critical assets is of a primary importance. This paper proposes a novel learning algorithm for anomaly based network security cyber sensor together with its hardware implementation. The presented learning algorithm constructs a fuzzy logic rule based model of normal network behavior. Individual fuzzy rules are extracted directly from the stream of incoming packets using an online clustering algorithm. This learning algorithm was specifically developed to comply with the constrained computational requirements of low-cost embedded network security cyber sensors. The performance of the system was evaluated on a set of network data recorded from an experimental test-bed mimicking the environment of a critical infrastructure control system.

  17. This paper is included in the Proceedings of the 11th USENIX Symposium on Networked Systems

    E-Print Network [OSTI]

    Zhao, Feng

    Exploiting the increasingly wide use of Light-emitting Diode (LED) lighting, in this paper, we study the prob system exploiting visible Light-emitting Diode (LED) lighting infrastructure. Such work is in- spired

  18. STOMP: A Software Architecture for the Design and Simulation UAV-Based Sensor Networks

    SciTech Connect (OSTI)

    Jones, E D; Roberts, R S; Hsia, T C S

    2002-10-28

    This paper presents the Simulation, Tactical Operations and Mission Planning (STOMP) software architecture and framework for simulating, controlling and communicating with unmanned air vehicles (UAVs) servicing large distributed sensor networks. STOMP provides hardware-in-the-loop capability enabling real UAVs and sensors to feedback state information, route data and receive command and control requests while interacting with other real or virtual objects thereby enhancing support for simulation of dynamic and complex events.

  19. IEEE 342 Node Low Voltage Networked Test System

    SciTech Connect (OSTI)

    Schneider, Kevin P.; Phanivong, Phillippe K.; Lacroix, Jean-Sebastian

    2014-07-31

    The IEEE Distribution Test Feeders provide a benchmark for new algorithms to the distribution analyses community. The low voltage network test feeder represents a moderate size urban system that is unbalanced and highly networked. This is the first distribution test feeder developed by the IEEE that contains unbalanced networked components. The 342 node Low Voltage Networked Test System includes many elements that may be found in a networked system: multiple 13.2kV primary feeders, network protectors, a 120/208V grid network, and multiple 277/480V spot networks. This paper presents a brief review of the history of low voltage networks and how they evolved into the modern systems. This paper will then present a description of the 342 Node IEEE Low Voltage Network Test System and power flow results.

  20. ASCR Science Network Requirements

    SciTech Connect (OSTI)

    Dart, Eli; Tierney, Brian

    2009-08-24

    The Energy Sciences Network (ESnet) is the primary provider of network connectivity for the US Department of Energy Office of Science, the single largest supporter of basic research in the physical sciences in the United States. In support of the Office of Science programs, ESnet regularly updates and refreshes its understanding of the networking requirements of the instruments, facilities, scientists, and science programs that it serves. This focus has helped ESnet to be a highly successful enabler of scientific discovery for over 20 years. In April 2009 ESnet and the Office of Advanced Scientific Computing Research (ASCR), of the DOE Office of Science, organized a workshop to characterize the networking requirements of the programs funded by ASCR. The ASCR facilities anticipate significant increases in wide area bandwidth utilization, driven largely by the increased capabilities of computational resources and the wide scope of collaboration that is a hallmark of modern science. Many scientists move data sets between facilities for analysis, and in some cases (for example the Earth System Grid and the Open Science Grid), data distribution is an essential component of the use of ASCR facilities by scientists. Due to the projected growth in wide area data transfer needs, the ASCR supercomputer centers all expect to deploy and use 100 Gigabit per second networking technology for wide area connectivity as soon as that deployment is financially feasible. In addition to the network connectivity that ESnet provides, the ESnet Collaboration Services (ECS) are critical to several science communities. ESnet identity and trust services, such as the DOEGrids certificate authority, are widely used both by the supercomputer centers and by collaborations such as Open Science Grid (OSG) and the Earth System Grid (ESG). Ease of use is a key determinant of the scientific utility of network-based services. Therefore, a key enabling aspect for scientists beneficial use of high performance networks is a consistent, widely deployed, well-maintained toolset that is optimized for wide area, high-speed data transfer (e.g. GridFTP) that allows scientists to easily utilize the services and capabilities that the network provides. Network test and measurement is an important part of ensuring that these tools and network services are functioning correctly. One example of a tool in this area is the recently developed perfSONAR, which has already shown its usefulness in fault diagnosis during the recent deployment of high-performance data movers at NERSC and ORNL. On the other hand, it is clear that there is significant work to be done in the area of authentication and access control - there are currently compatibility problems and differing requirements between the authentication systems in use at different facilities, and the policies and mechanisms in use at different facilities are sometimes in conflict. Finally, long-term software maintenance was of concern for many attendees. Scientists rely heavily on a large deployed base of software that does not have secure programmatic funding. Software packages for which this is true include data transfer tools such as GridFTP as well as identity management and other software infrastructure that forms a critical part of the Open Science Grid and the Earth System Grid.

  1. Rheology of fractal networks

    E-Print Network [OSTI]

    Pedro Patricio; Catarina R. Leal; Jorge Duarte; Cristina Januario

    2015-08-03

    We model the cytoskeleton as a fractal network by identifying each segment with a simple Kelvin-Voigt element, with a well defined equilibrium length. The final structure retains the elastic characteristics of a solid or a gel, which may support stress, without relaxing. By considering a very simple regular self-similar structure of segments in series and in parallel, in 1, 2 or 3 dimensions, we are able to express the viscoelasticity of the network as an effective generalised Kelvin-Voigt model with a power law spectrum of retardation times, $\\cal L\\sim\\tau^{\\alpha}$. We relate the parameter $\\alpha$ with the fractal dimension of the gel. In some regimes ($0power law behaviours of the elastic and viscous moduli with the angular frequencies, $G'\\sim G''\\sim w^\\alpha$, that occur in a variety of soft materials, including living cells. In other regimes, we find different power laws for $G'$ and $G''$.

  2. Neural Networks Early Neural Network Modeling

    E-Print Network [OSTI]

    Yuste, Rafael

    Appendix E Neural Networks Early Neural Network Modeling Neurons Are Computational Devices A Neuron? This is the central question moti- vating the study of neural networks. In this appendix we provide a brief historical review of the field, intro- duce some key concepts, and discuss two influential models of neural networks

  3. Ionic liquids, electrolyte solutions including the ionic liquids, and energy storage devices including the ionic liquids

    DOE Patents [OSTI]

    Gering, Kevin L.; Harrup, Mason K.; Rollins, Harry W.

    2015-12-08

    An ionic liquid including a phosphazene compound that has a plurality of phosphorus-nitrogen units and at least one pendant group bonded to each phosphorus atom of the plurality of phosphorus-nitrogen units. One pendant group of the at least one pendant group comprises a positively charged pendant group. Additional embodiments of ionic liquids are disclosed, as are electrolyte solutions and energy storage devices including the embodiments of the ionic liquid.

  4. The ArduSiPM a compact trasportable Software/Hardware Data Acquisition system for SiPM detector

    E-Print Network [OSTI]

    Bocci, Valerio; Iacoangeli, Francesco; Nuccetelli, Massimo; Recchia, Luigi

    2014-01-01

    The acquisition of a single Silicon Photomultiplier require multiple and expensive electronics modules as : preamplifier, discriminator, bias voltage power supply, temperature monitor, Scalers, Analog to Digital Converter and Time to Digital Converter . The developed ArduSiPM is a compact cost effective and easily replicable Hardware software module for SiPM detector readout. The ArduSiPM uses an Arduino DUE (an open Software/Hardware board based on an ARM Cortex-M3 microcontroller) as processor board and a piggyback custom designed board (Shield), these are controlled by custom developed software and interface. The Shield contains different electronics features both to monitor, to set and to acquire the SiPM signals using the microcontroller board. The shield embed a controlled bias voltage power supply, a fast voltage preamplifier, a programmable fast discriminator to generate over threshold digital pulse , a peak hold to measure the pulse height, a temperature monitor system, a scaler to monitor over thres...

  5. Fractional Immunization in Networks B. Aditya Prakash

    E-Print Network [OSTI]

    Faloutsos, Christos

    § Christos Faloutsos¶ Abstract Preventing contagion in networks is an important prob- lem in public health, the assumption that selected nodes can be rendered completely immune does not hold for infections for which network datasets including US-MEDICARE and state-level interhospital patient transfer data. We find

  6. Post-Processing Free Spatio-Temporal Optical Random Number Generator Resilient to Hardware Failure and Signal Injection Attacks

    E-Print Network [OSTI]

    Mario Stip?evi?; John Bowers

    2014-10-09

    We present a random number generator based on quantum effects in photonic emission and detection. It is unique in simultaneous use of both spatial and temporal quantum information contained in the system which makes it resilient to hardware failure and signal injection attacks. We show that its deviation from randomness cam be estimated based on simple measurements. Generated numbers pass NIST Statistical test suite without post-processing.

  7. Survey of historical incidences with Controls-Structures Interaction and recommended technology improvements needed to put hardware in space

    SciTech Connect (OSTI)

    Ketner, G.L.

    1989-03-01

    Pacific Northwest Laboratory (PNL) conducted a survey for the Controls-Structures Interaction (CSI) Office of the National Aeronautics and Space Administration's (NASA) Langley Research Center. The purpose of the survey was to collect information documenting past incidences of problems with CSI during design, analysis, ground development, test and/or flight operation of space systems in industry. The survey was conducted to also compile recommended improvements in technology to support future needs for putting hardware into space. 3 refs., 1 tab.

  8. Reverse Supply Chain Management and Electronic Waste Recycling: A Multitiered Network Equilibrium Framework for E-Cycling

    E-Print Network [OSTI]

    Nagurney, Anna

    Reverse Supply Chain Management and Electronic Waste Recycling: A Multitiered Network Equilibrium for the modeling of reverse supply chain management of electronic waste, which includes recycling. We describe networks; Environment; Waste management; Reverse logistics; Variational inequali- ties; Network equilibrium

  9. Wireless Sensor Network for Advanced Energy Management Solutions

    SciTech Connect (OSTI)

    Peter J. Theisen; Bin Lu, Charles J. Luebke

    2009-09-23

    Eaton has developed an advanced energy management solution that has been deployed to several Industries of the Future (IoF) sites. This demonstrated energy savings and reduced unscheduled downtime through an improved means for performing predictive diagnostics and energy efficiency estimation. Eaton has developed a suite of online, continuous, and inferential algorithms that utilize motor current signature analysis (MCSA) and motor power signature analysis (MPSA) techniques to detect and predict the health condition and energy usage condition of motors and their connect loads. Eaton has also developed a hardware and software platform that provided a means to develop and test these advanced algorithms in the field. Results from lab validation and field trials have demonstrated that the developed advanced algorithms are able to detect motor and load inefficiency and performance degradation. Eaton investigated the performance of Wireless Sensor Networks (WSN) within various industrial facilities to understand concerns about topology and environmental conditions that have precluded broad adoption by the industry to date. A Wireless Link Assessment System (WLAS), was used to validate wireless performance under a variety of conditions. Results demonstrated that wireless networks can provide adequate performance in most facilities when properly specified and deployed. Customers from various IoF expressed interest in applying wireless more broadly for selected applications, but continue to prefer utilizing existing, wired field bus networks for most sensor based applications that will tie into their existing Computerized Motor Maintenance Systems (CMMS). As a result, wireless technology was de-emphasized within the project, and a greater focus placed on energy efficiency/predictive diagnostics. Commercially available wireless networks were only utilized in field test sites to facilitate collection of motor wellness information, and no wireless sensor network products were developed under this project. As an outgrowth of this program, Eaton developed a patented energy-optimizing drive control technology that is complementary to a traditional variable frequency drives (VFD) to enable significant energy savings for motors with variable torque applications, such as fans, pumps, and compressors. This technology provides an estimated energy saving of 2%-10% depending on the loading condition, in addition to the savings obtained from a traditional VFD. The combination of a VFD with the enhanced energy-optimizing controls will provide significant energy savings (10% to 70% depending on the load and duty cycle) for motors that are presently connected with across the line starters. It will also provide a more favorable return on investment (ROI), thus encouraging industries to adopt VFDs for more motors within their facilities. The patented technology is based on nonintrusive algorithms that estimate the instantaneous operating efficiency and motor speed and provide active energy-optimizing control of a motor, using only existing voltage and current sensors. This technology is currently being commercialized by Eaton’s Industrial Controls Division in their next generation motor control products. Due to the common nonintrusive and inferential nature of various algorithms, this same product can also include motor and equipment condition monitoring features, providing the facility owner additional information to improve process uptime and the associated energy savings. Calculations estimated potential energy savings of 261,397GWh/Yr ($15.7B/yr), through retrofitting energy-optimizing VFDs into existing facilities, and incorporating the solution into building equipment sold by original equipment manufacturers (OEMs) and installed by mechanical and electrical contractors. Utilizing MCSA and MPSA for predictive maintenance (PM) of motors and connected equipment reduces process downtime cost and the cost of wasted energy associated with shutting down and restarting the processes. Estimated savings vary depending on the industry segment and equi

  10. From the book Networks, Crowds, and Markets: Reasoning about a Highly Connected World. By David Easley and Jon Kleinberg. Cambridge University Press, 2010.

    E-Print Network [OSTI]

    Kleinberg, Jon

    transmission based on coughs and sneezes, the contact network will include a huge number of links, including

  11. Visualizing criminal networks reconstructed from mobile phone records

    E-Print Network [OSTI]

    Ferrara, Emilio

    Visualizing criminal networks reconstructed from mobile phone records Emilio Ferrara School and the organization of criminal networks is of fundamental importance for both the investi- gations informative sources includ- ing the records of phone traffic, the social networks, surveil- lance data

  12. Performance, Algorithmic, and Robustness Attributes of Perfect Difference Networks

    E-Print Network [OSTI]

    Liebling, Michael

    tolerance relative to their complexity or implementation cost. Index Terms--Bipartite graph, chordal ring to interconnection networks with similar cost/performance, including certain generalized hypercubes of these networks, concluding that PDNs and their derivatives allow the construction of very low diameter networks

  13. Research and Implementation of Computer Simulation System for Neural Networks

    E-Print Network [OSTI]

    Byrne, John H.

    Research and Implementation of Computer Simulation System for Neural Networks Chen, Houjin Yuan: The ability of a neural network to process information and to generate a specific pattern of electrical computer simulation system for neural networks was designed and implemented including system architecture

  14. Local Algorithms for Finding Interesting Individuals in Large Networks

    E-Print Network [OSTI]

    Ives, Zachary G.

    or interests in so- cial networks such as Facebook, and other mechanisms that may return vertices would we actually find them -- especially considering that for many such networks (including the Web, or for non- employee researchers of online social networks such as Facebook), there may not exist an acces

  15. An SoC (system on a chip) integrates a processor, memory modules, I/O periph-erals, and custom hardware accelerators into a single integrated circuit. As the

    E-Print Network [OSTI]

    Chu, Pong P.

    , and custom hardware accelerators into a single integrated circuit. As the capacity of FPGA (field and is sometimes known as SoPC (system on a programmable chip). In a traditional embedded system, the hardware of the programmability of FPGA devices, customized hardware can be incorporated into the embedded sys- tem as well. We

  16. Reiner W. Hartenstein, Jrgen Becker, et al.: CoDe-X: A Novel Two-Level Hardware/Software Co-Design Framework; Proc. of VLSI Design 96 Conf., Bangalore, India, January 1996

    E-Print Network [OSTI]

    Hartenstein, Reiner

    Reiner W. Hartenstein, Jürgen Becker, et al.: CoDe-X: A Novel Two-Level Hardware/Software Co holder. Xputer Lab Abstract A novel hardware/software co-design framework (CoDe-X) is presented in this paper, where an Xputer is used as universal accelerator based on a reconfigurable datapath hardware. Co

  17. Bayesian network learning and applications in Bioinformatics

    E-Print Network [OSTI]

    Lin, Xiaotong

    2012-08-31

    Abstract A Bayesian network (BN) is a compact graphic representation of the probabilistic re- lationships among a set of random variables. The advantages of the BN formalism include its rigorous mathematical basis, the ...

  18. Quantization in acquisition and computation networks

    E-Print Network [OSTI]

    Sun, John Zheng

    2013-01-01

    In modern systems, it is often desirable to extract relevant information from large amounts of data collected at different spatial locations. Applications include sensor networks, wearable health-monitoring devices and a ...

  19. Imbibition well stimulation via neural network design

    DOE Patents [OSTI]

    Weiss, William (Socorro, NM)

    2007-08-14

    A method for stimulation of hydrocarbon production via imbibition by utilization of surfactants. The method includes use of fuzzy logic and neural network architecture constructs to determine surfactant use.

  20. CSP 545: Wireless Networking Technologies and Applications Yi-Bing Lin, Imrich Chlamtac, Wireless and Mobile Network Architectures.

    E-Print Network [OSTI]

    Heller, Barbara

    CSP 545: Wireless Networking Technologies and Applications Texts Yi-Bing Lin, Imrich Chlamtac, Wireless and Mobile Network Architectures. Reference: Theodore S. Rappaport, Theodore Rappaport, Wireless local area network technologies including 802.11b (wireless Ethernet) and Bluetooth, and third

  1. Structure-Preserving Sparsification of Social Networks

    E-Print Network [OSTI]

    Lindner, Gerd; Hamann, Michael; Meyerhenke, Henning; Wagner, Dorothea

    2015-01-01

    Sparsification reduces the size of networks while preserving structural and statistical properties of interest. Various sparsifying algorithms have been proposed in different contexts. We contribute the first systematic conceptual and experimental comparison of \\textit{edge sparsification} methods on a diverse set of network properties. It is shown that they can be understood as methods for rating edges by importance and then filtering globally by these scores. In addition, we propose a new sparsification method (\\textit{Local Degree}) which preserves edges leading to local hub nodes. All methods are evaluated on a set of 100 Facebook social networks with respect to network properties including diameter, connected components, community structure, and multiple node centrality measures. Experiments with our implementations of the sparsification methods (using the open-source network analysis tool suite NetworKit) show that many network properties can be preserved down to about 20\\% of the original set of edges....

  2. What if CLIQUE were fast? Maximum Cliques in Information Networks and Strong Components in Temporal Networks

    E-Print Network [OSTI]

    Rossi, Ryan A; Gebremedhin, Assefaw H; Patwary, Md Mostofa Ali

    2012-01-01

    Exact maximum clique finders have progressed to the point where we can investigate cliques in million-node social and information networks, as well as find strongly connected components in temporal networks. We use one such finder to study a large collection of modern networks emanating from biological, social, and technological domains. We show inter-relationships between maximum cliques and several other common network properties, including network density, maximum core, and number of triangles. In temporal networks, we find that the largest temporal strong components have around 20-30% of the vertices of the entire network. These components represent groups of highly communicative individuals. In addition, we discuss and improve the performance and utility of the maximum clique finder itself.

  3. Rheology of fractal networks

    E-Print Network [OSTI]

    Patricio, Pedro; Duarte, Jorge; Januario, Cristina

    2015-01-01

    We investigate the rheology of a fractal network, in the framework of the linear theory of viscoelasticity. We identify each segment of the network with a simple Kelvin-Voigt element, with a well defined equilibrium length. The final structure retains the elastic characteristics of a solid or a gel. By considering a very simple regular self-similar structure of segments in series and in parallel, in 1, 2 or 3 dimensions, we are able to express the viscoelasticity of the network as an effective generalised Kelvin-Voigt model with a power law spectrum of retardation times, $\\phi\\sim\\tau^{\\alpha-1}$. We relate the parameter $\\alpha$ with the fractal dimension of the gel. In some regimes ($0power law behaviours of the elastic and viscous moduli with the angular frequencies, $G'\\sim G''\\sim w^\\alpha$, that occur in a variety of soft materials, including living cells. In other regimes, we find different and interesting power laws for $G'$ and $G''$.

  4. Network Monitoring in Multicast Networks Using Network Coding

    E-Print Network [OSTI]

    Ho, Tracey

    , and give some experimental results for one and two link failures in randomly generated networks. We also inference of possible locations of link failures or losses in a network. For distributed randomized network coding, we bound the probability of being able to distinguish among a given set of failure events

  5. Rethinking Information Theory for Mobile Ad Hoc Networks

    E-Print Network [OSTI]

    Andrews, Jeff; Haenggi, Martin; Berry, Randy; Jafar, Syed; Guo, Dongning; Shakkottai, Sanjay; Heath, Robert; Neely, Michael; Weber, Steven; Yener, Aylin

    2007-01-01

    The subject of this paper is the long-standing open problem of developing a general capacity theory for wireless networks, particularly a theory capable of describing the fundamental performance limits of mobile ad hoc networks (MANETs). A MANET is a peer-to-peer network with no pre-existing infrastructure. MANETs are the most general wireless networks, with single-hop, relay, interference, mesh, and star networks comprising special cases. The lack of a MANET capacity theory has stunted the development and commercialization of many types of wireless networks, including emergency, military, sensor, and community mesh networks. Information theory, which has been vital for links and centralized networks, has not been successfully applied to decentralized wireless networks. Even if this was accomplished, for such a theory to truly characterize the limits of deployed MANETs it must overcome three key roadblocks. First, most current capacity results rely on the allowance of unbounded delay and reliability. Second, ...

  6. The Network

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    AFDC Printable Version Share this resource Send a link to EERE: Alternative Fuels Data Center Home Page to someone by E-mail Share EERE: Alternative Fuels Data Center Home Page on Facebook Tweet about EERE: Alternative Fuels Data Center Home Page on Twitter Bookmark EERE: Alternative Fuels Data Center Homesum_a_epg0_fpd_mmcf_m.xls" ,"Available from WebQuantity of NaturalDukeWakefieldSulfateSciTechtail.Theory ofDidDevelopment TopMetathesisSediments and RelatedProject HomeNetwork

  7. A study on the generation of silicon-based hardware Plc by means of the direct conversion of the ladder diagram to circuit design language

    E-Print Network [OSTI]

    Du, Daoshan; Xu, Xiaodong; Yamazaki, Kazuo

    2010-01-01

    to implement FPGA-based PLC with high efficient performance,of silicon-based hardware Plc by means of the directProgrammable logic controller (PLC) is one of the most

  8. HOW MIGHT INDUSTRY GOVERNANCE BE BROADENED TO INCLUDE NONPROLIFERATION

    SciTech Connect (OSTI)

    Hund, Gretchen; Seward, Amy M.

    2009-10-06

    Broadening industry governance to support nonproliferation could provide significant new leverage in preventing the spread/diversion of nuclear, radiological, or dual-use material or technology that could be used in making a nuclear or radiological weapon. Industry is defined broadly to include 1) the nuclear industry, 2) dual-use industries, and 3) radioactive source manufacturers and selected radioactive source-user industries worldwide. This paper describes how industry can be an important first line of defense in detecting and thwarting proliferation, such as an illicit trade network or an insider theft case, by complementing and strengthening existing governmental efforts. For example, the dual-use industry can play a critical role by providing export, import, or security control information that would allow a government or the International Atomic Energy Agency (IAEA) to integrate this information with safeguards, export, import, and physical protection information it has to create a more complete picture of the potential for proliferation. Because industry is closest to users of the goods and technology that could be illicitly diverted throughout the supply chain, industry information can potentially be more timely and accurate than other sources of information. Industry is in an ideal position to help ensure that such illicit activities are detected. This role could be performed more effectively if companies worked together within a particular industry to promote nonproliferation by implementing an industry-wide self-regulation program. Performance measures could be used to ensure their materials and technologies are secure throughout the supply chain and that customers are legitimately using and/or maintaining oversight of these items. Nonproliferation is the overarching driver that industry needs to consider in adopting and implementing a self-regulation approach. A few foreign companies have begun such an approach to date; it is believed that, ultimately, broad engagement of global industry leaders in self regulation is needed to result in the greatest nonproliferation benefit.

  9. Introduction to Network Analysis 1 Introduction to Network Analysis

    E-Print Network [OSTI]

    Safro, Ilya

    Networks from networksandservers.blogspot.com #12;Introduction to Network Analysis 7 Natural gas major

  10. Nov 5, 2004 www.dcs.bbk.ac.uk/~gmagoulas/teaching.html 1 A variety of software and hardware is used to

    E-Print Network [OSTI]

    Magoulas, George D.

    Programs l Web server hardware l Web hosting Nov 5, 2004 www.dcs.bbk.ac.uk/~gmagoulas/teaching.html 3 E/Server Architectures Nov 5, 2004 www.dcs.bbk.ac.uk/~gmagoulas/teaching.html 6 Software for Web servers- Popular server programs #12;2 Nov 5, 2004 www.dcs.bbk.ac.uk/~gmagoulas/teaching.html 7 Web Server Hardware l Web server

  11. PCDAS Version 2. 2: Remote network control and data acquisition

    SciTech Connect (OSTI)

    Fishbaugher, M.J.

    1987-09-01

    This manual is intended for both technical and non-technical people who want to use the PCDAS remote network control and data acquisition software. If you are unfamiliar with remote data collection hardware systems designed at Pacific Northwest Laboratory (PNL), this introduction should answer your basic questions. Even if you have some experience with the PNL-designed Field Data Acquisition Systems (FDAS), it would be wise to review this material before attempting to set up a network. This manual was written based on the assumption that you have a rudimentary understanding of personal computer (PC) operations using Disk Operating System (DOS) version 2.0 or greater (IBM 1984). You should know how to create subdirectories and get around the subdirectory tree.

  12. Network coding for robust wireless networks

    E-Print Network [OSTI]

    Kim, MinJi, Ph. D. Massachusetts Institute of Technology

    2012-01-01

    Wireless networks and communications promise to allow improved access to services and information, ubiquitous connectivity, and mobility. However, current wireless networks are not well-equipped to meet the high bandwidth ...

  13. Energy aware network coding in wireless networks

    E-Print Network [OSTI]

    Shi, Xiaomeng, Ph. D. Massachusetts Institute of Technology

    2012-01-01

    Energy is one of the most important considerations in designing reliable low-power wireless communication networks. We focus on the problem of energy aware network coding. In particular, we investigate practical energy ...

  14. Efficient network camouflaging in wireless networks 

    E-Print Network [OSTI]

    Jiang, Shu

    2006-04-12

    (e.g. broadcast, node mobility) that traditional wired networks do not possess. This necessitates developing new techniques that take account of properties of wireless networks and are able to achieve a good balance between performance and security...

  15. Flexible network wireless transceiver and flexible network telemetry transceiver

    DOE Patents [OSTI]

    Brown, Kenneth D. (Grain Valley, MO)

    2008-08-05

    A transceiver for facilitating two-way wireless communication between a baseband application and other nodes in a wireless network, wherein the transceiver provides baseband communication networking and necessary configuration and control functions along with transmitter, receiver, and antenna functions to enable the wireless communication. More specifically, the transceiver provides a long-range wireless duplex communication node or channel between the baseband application, which is associated with a mobile or fixed space, air, water, or ground vehicle or other platform, and other nodes in the wireless network or grid. The transceiver broadly comprises a communication processor; a flexible telemetry transceiver including a receiver and a transmitter; a power conversion and regulation mechanism; a diplexer; and a phased array antenna system, wherein these various components and certain subcomponents thereof may be separately enclosed and distributable relative to the other components and subcomponents.

  16. Examining System-Wide Impacts of Solar PV Control Systems with a Power Hardware-in-the-Loop Platform

    SciTech Connect (OSTI)

    Williams, Tess L.; Fuller, Jason C.; Schneider, Kevin P.; Palmintier, Bryan; Lundstrom, Blake; Chakraborty, Sudipta

    2014-10-11

    High penetration levels of distributed solar PV power generation can lead to adverse power quality impacts such as excessive voltage rise, voltage flicker, and reactive power values that result in unacceptable voltage levels. Advanced inverter control schemes have been proposed that have the potential to mitigate many power quality concerns. However, closed-loop control may lead to unintended behavior in deployed systems as complex interactions can occur between numerous operating devices. In order to enable the study of the performance of advanced control schemes in a detailed distribution system environment, a Hardware-in-the-Loop (HIL) platform has been developed. In the HIL system, GridLAB-D, a distribution system simulation tool, runs in real-time mode at the Pacific Northwest National Laboratory (PNNL) and supplies power system parameters at a point of common coupling to hardware located at the National Renewable Energy Laboratory (NREL). Hardware inverters interact with grid and PV simulators emulating an operational distribution system and power output from the inverters is measured and sent to PNNL to update the real-time distribution system simulation. The platform is described and initial test cases are presented. The platform is used to study the system-wide impacts and the interactions of controls applied to inverters that are integrated into a simulation of the IEEE 8500-node test feeder, with inverters in either constant power factor control or active volt/VAR control. We demonstrate that this HIL platform is well-suited to the study of advanced inverter controls and their impacts on the power quality of a distribution feeder. Additionally, the results from HIL are used to validate GridLAB-D simulations of advanced inverter controls. ?

  17. Performance Metric Sensitivity Computation for Optimization and Trade-off Analysis in Wireless Networks

    E-Print Network [OSTI]

    Baras, John S.

    for multi- hop wireless networks, including MANETs. We introduce an approximate (throughput) loss model is the different nature of wired and wireless networks rendering the use of wired network techniques inappropriate for the case of wireless networks. Key quantities, such as the link capacity, that remain constant in a wired

  18. Impact of Social Relation and Group Size in Multicast Ad Hoc Networks

    E-Print Network [OSTI]

    Wang, Xinbing

    1 Impact of Social Relation and Group Size in Multicast Ad Hoc Networks Yi Qin, Riheng Jia, Jinbei wireless social networks. We adopt the two-layer network model, which includes the social layer and the networking layer. In the social layer, the social group size of each source node is modeled as power

  19. A Big World Inside Small-World Networks Zhihua Zhang, Jianzhi Zhang*

    E-Print Network [OSTI]

    Zhang, Jianzhi

    A Big World Inside Small-World Networks Zhihua Zhang, Jianzhi Zhang* Department of Ecology networks, including biological networks, are known to have the small-world property, characterized: Zhang Z, Zhang J (2009) A Big World Inside Small-World Networks. PLoS ONE 4(5): e5686. doi:10

  20. Cooperative Wireless Network Behnaam Aazhang

    E-Print Network [OSTI]

    Aazhang, Behnaam

    Cooperative Wireless Network Behnaam Aazhang #12;Cooperative Wireless Network Behnaam Aazhang Sabharwal #12;Wireless Network · Infrastructure · Ad hoc · Mesh network #12;Engineering Wireless Network · Wireless links ­ Per link design #12;Single Wireless Link · Additive Gaussian Channels ­ Achievable rate