Sample records for fault circuit interrupters

  1. Apparatus for and method of testing an electrical ground fault circuit interrupt device

    DOE Patents [OSTI]

    Andrews, Lowell B. (2181-13th Ave. SW., Largo, FL 34640)

    1998-01-01T23:59:59.000Z

    An apparatus for testing a ground fault circuit interrupt device includes a processor, an input device connected to the processor for receiving input from an operator, a storage media connected to the processor for storing test data, an output device connected to the processor for outputting information corresponding to the test data to the operator, and a calibrated variable load circuit connected between the processor and the ground fault circuit interrupt device. The ground fault circuit interrupt device is configured to trip a corresponding circuit breaker. The processor is configured to receive signals from the calibrated variable load circuit and to process the signals to determine a trip threshold current and/or a trip time. A method of testing the ground fault circuit interrupt device includes a first step of providing an identification for the ground fault circuit interrupt device. Test data is then recorded in accordance with the identification. By comparing test data from an initial test with test data from a subsequent test, a trend of performance for the ground fault circuit interrupt device is determined.

  2. Apparatus for and method of testing an electrical ground fault circuit interrupt device

    DOE Patents [OSTI]

    Andrews, L.B.

    1998-08-18T23:59:59.000Z

    An apparatus for testing a ground fault circuit interrupt device includes a processor, an input device connected to the processor for receiving input from an operator, a storage media connected to the processor for storing test data, an output device connected to the processor for outputting information corresponding to the test data to the operator, and a calibrated variable load circuit connected between the processor and the ground fault circuit interrupt device. The ground fault circuit interrupt device is configured to trip a corresponding circuit breaker. The processor is configured to receive signals from the calibrated variable load circuit and to process the signals to determine a trip threshold current and/or a trip time. A method of testing the ground fault circuit interrupt device includes a first step of providing an identification for the ground fault circuit interrupt device. Test data is then recorded in accordance with the identification. By comparing test data from an initial test with test data from a subsequent test, a trend of performance for the ground fault circuit interrupt device is determined. 17 figs.

  3. 1. Detect ground faults in PV arrays mounted on the roofs of 2. Interrupt the fault current

    E-Print Network [OSTI]

    Johnson, Eric E.

    1. Detect ground faults in PV arrays mounted on the roofs of dwellings 2. Interrupt the fault current 3. Indicate that a ground fault had occurred 4. Disconnect the faulted part of the PV array 5. "Crowbar" (short-circuit) the PV array The original GFPD prototype was developed in two versions that were

  4. Hybrid high direct current circuit interrupter

    DOE Patents [OSTI]

    Rockot, J.H.; Mikesell, H.E.; Jha, K.N.

    1998-08-11T23:59:59.000Z

    A device and a method are disclosed for interrupting very high direct currents (greater than 100,000 amperes) and simultaneously blocking high voltages (greater than 600 volts). The device utilizes a mechanical switch to carry very high currents continuously with low loss and a silicon controlled rectifier (SCR) to bypass the current around the mechanical switch while its contacts are separating. A commutation circuit, connected in parallel with the SCR, turns off the SCR by utilizing a resonant circuit to divert the SCR current after the switch opens. 7 figs.

  5. Hybrid high direct current circuit interrupter

    SciTech Connect (OSTI)

    Rockot, J.H.; Mikesell, H.E.; Jha, K.N.

    1996-12-31T23:59:59.000Z

    A device and a method for interrupting very high direct currents (greater than 100,000 amperes) and simultaneously blocking high voltages (greater than 600 volts). The device utilizes a mechanical switch to carry very high currents continuously with low loss and a silicon controlled rectifier (SCR) to bypass the current around the mechanical switch while its contacts are separating. A commutation circuit, connected in parallel with the SCR, turns off the SCR by utilizing a resonant circuit to divert the SCR current after the switch opens.

  6. Development and interrupting tests on 250KV 8KA HVDC circuit breaker

    SciTech Connect (OSTI)

    Tokuyama, S.; Arimatsu, K.; Hirata, K.; Kato, Y.; Yoshioka, Y.

    1985-09-01T23:59:59.000Z

    This paper describes the circuit and component selections, development and equivalent circuit test results on an HVDC circuit breaker for an HVDC transmission line. A puffer type SF/sub 6/ gas interrupter for AC circuit breakers is utilized for interrupting DC current with injection of high-frequency inverse current from a commutating capacitor precharged to HVDC line voltage. Also, the effectiveness of application of the HVDC breaker to an HVDC system with two parallel transmission lines is demonstrated through the EMTP simulation.

  7. A 4000-A HVDC (high-voltage direct-current) circuit breaker with fast fault-clearing capability: Final report

    SciTech Connect (OSTI)

    Not Available

    1988-04-01T23:59:59.000Z

    This project is a follow-up of the first development of a 500 kV HVDC airblast circuit breaker (EPRI project 1507-3). The objective was to increase the current interrupting capability from 2200 A to 4000 A and shorten its fault clearing time. A high current 500 kV HVDC circuit breaker has been built using the passive commutation circuit. The breaker is modular in construction and can be designed for a wide variety of system conditions. More than 400 current interruptions were carried out successfully. Tests have shown that this circuit breaker is capable of interrupting more than 4000 A dc. Practical breakers with current interrupting capability of even 5500 A dc could be built. The circuit breaker operation and the fault-clearing process can be materially speeded up if the trip signal is given as soon as the fault is detected and without waiting for the current levels to come down in response to converter control action. The new dc breakers are shown to be capable of withstanding these transient arc currents of 8000 A without affecting its ability to interrupt the direct current that follows the transient. This transient current withstand capability is greater than is likely to occur during dc faults. The fault clearing time of this HVDC circuit breaker is comparable to the fault clearing time of conventional ac breakers for ac faults. The developed HVDC circuit breaker is now commercially available and can be supplied for use in HVDC systems. Its use in such systems is expected to provide flexibility in system design and contribute to system stability. 38 refs., 52 figs., 9 tabs.

  8. Switch contact device for interrupting high current, high voltage, AC and DC circuits

    DOE Patents [OSTI]

    Via, Lester C.; Witherspoon, F. Douglas; Ryan, John M.

    2005-01-04T23:59:59.000Z

    A high voltage switch contact structure capable of interrupting high voltage, high current AC and DC circuits. The contact structure confines the arc created when contacts open to the thin area between two insulating surfaces in intimate contact. This forces the arc into the shape of a thin sheet which loses heat energy far more rapidly than an arc column having a circular cross-section. These high heat losses require a dramatic increase in the voltage required to maintain the arc, thus extinguishing it when the required voltage exceeds the available voltage. The arc extinguishing process with this invention is not dependent on the occurrence of a current zero crossing and, consequently, is capable of rapidly interrupting both AC and DC circuits. The contact structure achieves its high performance without the use of sulfur hexafluoride.

  9. Probabilistic model of fault detection in quantum circuits

    E-Print Network [OSTI]

    Anindita Banerjee; Anirban Pathak

    2009-05-12T23:59:59.000Z

    It is shown that the fault testing for quantum circuits does not follow conventional classical techniques. If probabilistic gate like Hadamard gate is included in a circuit then the classical notion of test vector is shown to fail. We have reported several new and distinguishing features of quantum fault and also presented a general methodology for detection of functional faults in a quantum circuit. The technique can generate test vectors for detection of different kinds of fault. Specific examples are given and time complexity of the proposed quantum fault detection algorithm is reported.

  10. Arcing fault in sub-distribution branch circuits

    SciTech Connect (OSTI)

    Parise, G.; Grasseli, U.; Luozzo, V. Di (Univ. di Roma, Rome (Italy). Dept. di Ingegneria Elettrica)

    1993-04-01T23:59:59.000Z

    It's well known the importance of short-circuit current evaluation for the design of any power system. Every system is subject to faults, moreover short-circuits and ground faults can be expected in any point. Even if the maximum and minimum values are generally defined with reference at a bolted-fault, bolted short-circuits are rare and the fault usually involves arcing and burning; particularly the limit value of minimum short-circuit depends really on arcing-fault. In earlier experimental investigations into the functional simulation of insulation loss, in branch circuit conductors, the authors chose to normalize the arcing-fault simulation to be used in laboratory tests. This conventional simulation allows characterization of this intrinsically random phenomenon by means of a probabilistic approach, in order to define in statistical terms the expected short circuit value. The authors examine more closely the arcing-fault in the design of sub distribution branch-circuits as weak points of the installation. In fact, what they propose are straightforward criteria, whether in the structure of the system or in the coordination of protection, which afford a more rational control on arcing-fault.

  11. Fault simulation of combinational circuits based on critical path tracing

    E-Print Network [OSTI]

    Burnett, Charles James

    1992-01-01T23:59:59.000Z

    advantage of the computer's internal architecture and does not intelligently analyze the CUT. The deductive simulator traverses the good circuit to determine the value of each line. At the same time, every fault that causes a line to have a different... of the faults on a line within the circuit is detected for a given test vector, the line is marked as critical [10]. These faults that are detected are marked as covered. This very quickly gathers faults without direct simulation to the outputs, however...

  12. Test generation and fault detection for VLSI PPL circuits

    SciTech Connect (OSTI)

    Amin, A.A.M.

    1987-01-01T23:59:59.000Z

    The problem of design for testability of PPL logic circuits is addressed. A test-generation package was developed which utilizes the special features of PPL logic to generate high fault coverage test vectors at a reduced computational cost. The test strategy assumes that one of the scan design techniques is used. A new methodology for test-vectors compaction without compromising the fault coverage is also proposed. A fault-oriented test-generation algorithm combined with a heuristic test-generation algorithm are the essential ingredients of this package. The fault-oriented algorithm uses a modified D-algorithm which includes look-ahead features and a new seven-valued logic to improve the average speed of the test-generation process. Fault coverages in the 90% range were obtained using the test sequences generated by this package.

  13. Fault current limiter and alternating current circuit breaker

    DOE Patents [OSTI]

    Boenig, H.J.

    1998-03-10T23:59:59.000Z

    A solid-state circuit breaker and current limiter are disclosed for a load served by an alternating current source having a source impedance, the solid-state circuit breaker and current limiter comprising a thyristor bridge interposed between the alternating current source and the load, the thyristor bridge having four thyristor legs and four nodes, with a first node connected to the alternating current source, and a second node connected to the load. A coil is connected from a third node to a fourth node, the coil having an impedance of a value calculated to limit the current flowing therethrough to a predetermined value. Control means are connected to the thyristor legs for limiting the alternating current flow to the load under fault conditions to a predetermined level, and for gating the thyristor bridge under fault conditions to quickly reduce alternating current flowing therethrough to zero and thereafter to maintain the thyristor bridge in an electrically open condition preventing the alternating current from flowing therethrough for a predetermined period of time. 9 figs.

  14. A Smart Algorithm for the Diagnosis of Short-Circuit Faults in a Photovoltaic Generator

    E-Print Network [OSTI]

    Paris-Sud XI, Université de

    A Smart Algorithm for the Diagnosis of Short-Circuit Faults in a Photovoltaic Generator Wail Rezgui observations distributed over classes is used for simulation purposes. Keywords--Photovoltaic generator, SVM, k-NN, short-circuit fault, smart classification, linear programming. NOMENCLATURE PV = Photovoltaic; SVM

  15. Abstract-This paper investigates four different short circuit fault conditions which can occur for an inverter-fed perma-

    E-Print Network [OSTI]

    Jantsch, Axel

    for an inverter-fed perma- nent magnet synchronous motor (PMSM) with buried mag- nets. The fault conditions Condition #... Inverter PM machine (at steady state) N Short circuit fault conditions of a buried PMSM

  16. Abstract--The FREEDM grid utilizes solid state transformers (SST) and solid state fault interruption devices (FID) which may

    E-Print Network [OSTI]

    Kimball, Jonathan W.

    bidirectional power flow between the system and the renewable energy sources. The system also includes solid of a Distribution Grid with Solid State Power Devices Karl Stefanski, Hengsi Qin, Badrul H. Chowdhury, Senior Member1 Abstract-- The FREEDM grid utilizes solid state transformers (SST) and solid state fault

  17. Low Insertion HVDC Circuit Breaker: Magnetically Pulsed Hybrid Breaker for HVDC Power Distribution Protection

    SciTech Connect (OSTI)

    None

    2012-01-09T23:59:59.000Z

    GENI Project: General Atomics is developing a direct current (DC) circuit breaker that could protect the grid from faults 100 times faster than its alternating current (AC) counterparts. Circuit breakers are critical elements in any electrical system. At the grid level, their main function is to isolate parts of the grid where a fault has occurred—such as a downed power line or a transformer explosion—from the rest of the system. DC circuit breakers must interrupt the system during a fault much faster than AC circuit breakers to prevent possible damage to cables, converters and other grid-level components. General Atomics’ high-voltage DC circuit breaker would react in less than 1/1,000th of a second to interrupt current during a fault, preventing potential hazards to people and equipment.

  18. Creating dynamic equivalent PV circuit models with impedance spectroscopy for arc-fault modeling.

    SciTech Connect (OSTI)

    Johnson, Jay Dean; Kuszmaul, Scott S.; Strauch, Jason E.; Schoenwald, David Alan

    2011-06-01T23:59:59.000Z

    Article 690.11 in the 2011 National Electrical Code{reg_sign} (NEC{reg_sign}) requires new photovoltaic (PV) systems on or penetrating a building to include a listed arc fault protection device. Currently there is little experimental or empirical research into the behavior of the arcing frequencies through PV components despite the potential for modules and other PV components to filter or attenuate arcing signatures that could render the arc detector ineffective. To model AC arcing signal propagation along PV strings, the well-studied DC diode models were found to inadequately capture the behavior of high frequency arcing signals. Instead dynamic equivalent circuit models of PV modules were required to describe the impedance for alternating currents in modules. The nonlinearities present in PV cells resulting from irradiance, temperature, frequency, and bias voltage variations make modeling these systems challenging. Linearized dynamic equivalent circuits were created for multiple PV module manufacturers and module technologies. The equivalent resistances and capacitances for the modules were determined using impedance spectroscopy with no bias voltage and no irradiance. The equivalent circuit model was employed to evaluate modules having irradiance conditions that could not be measured directly with the instrumentation. Although there was a wide range of circuit component values, the complex impedance model does not predict filtering of arc fault frequencies in PV strings for any irradiance level. Experimental results with no irradiance agree with the model and show nearly no attenuation for 1 Hz to 100 kHz input frequencies.

  19. Malcolm, N. and Aggarwal, R.k. (2014) An Analysis of Reducing Back Flashover Faults with Surge Arresters on 69/138 kV Double

    E-Print Network [OSTI]

    McCusker, Guy

    Arresters on 69/138 kV Double Circuit Transmission Lines Due to Direct Lightning Strikes on the Shield Wires-EMTP, Back flashover faults, Lightning strokes, Surge arrester, Transmission lines. Abstract Back flashover causes of power interruptions on the double-circuit 69/138 kV overhead transmission lines in Jamaica

  20. Energy Efficient Digital Networks

    E-Print Network [OSTI]

    Lanzisera, Steven

    2014-01-01T23:59:59.000Z

    Class 2 Transformers and Ground Fault Circuit Interrupters,fault circuit interrupter (GFCI) outlets Doorbell transformersfault circuit interrupters) and class II transformers. In

  1. Superior model for fault tolerance computation in designing nano-sized circuit systems

    SciTech Connect (OSTI)

    Singh, N. S. S., E-mail: narinderjit@petronas.com.my; Muthuvalu, M. S., E-mail: msmuthuvalu@gmail.com [Fundamental and Applied Sciences Department, Universiti Teknologi PETRONAS, Bandar Seri Iskandar, Perak (Malaysia); Asirvadam, V. S., E-mail: vijanth-sagayan@petronas.com.my [Electrical and Electronics Engineering Department, Universiti Teknologi PETRONAS, Bandar Seri Iskandar, Perak (Malaysia)

    2014-10-24T23:59:59.000Z

    As CMOS technology scales nano-metrically, reliability turns out to be a decisive subject in the design methodology of nano-sized circuit systems. As a result, several computational approaches have been developed to compute and evaluate reliability of desired nano-electronic circuits. The process of computing reliability becomes very troublesome and time consuming as the computational complexity build ups with the desired circuit size. Therefore, being able to measure reliability instantly and superiorly is fast becoming necessary in designing modern logic integrated circuits. For this purpose, the paper firstly looks into the development of an automated reliability evaluation tool based on the generalization of Probabilistic Gate Model (PGM) and Boolean Difference-based Error Calculator (BDEC) models. The Matlab-based tool allows users to significantly speed-up the task of reliability analysis for very large number of nano-electronic circuits. Secondly, by using the developed automated tool, the paper explores into a comparative study involving reliability computation and evaluation by PGM and, BDEC models for different implementations of same functionality circuits. Based on the reliability analysis, BDEC gives exact and transparent reliability measures, but as the complexity of the same functionality circuits with respect to gate error increases, reliability measure by BDEC tends to be lower than the reliability measure by PGM. The lesser reliability measure by BDEC is well explained in this paper using distribution of different signal input patterns overtime for same functionality circuits. Simulation results conclude that the reliability measure by BDEC depends not only on faulty gates but it also depends on circuit topology, probability of input signals being one or zero and also probability of error on signal lines.

  2. Effect of neglecting resistance in calculations of short circuit faults on power systems

    E-Print Network [OSTI]

    Mayo, Samuel Jonathan

    1948-01-01T23:59:59.000Z

    of Conductor B. Ef feet of Locat ion of i"ault C. Effect of Generator Impedances Effect of ". utual Impedance in Overhead ircuits E. 'ffect of Ground '&!res F. Effect of Type of Fault 1. Line to Line Fault 2, D&uble Line to Ground Fault Single Line...) Configuration of conductorS Fig. P . 59Ste, m 1. Two overheaci circu (rs with mutual coupling 12 IO t GEOAf ETR IC PER IV DIsT~NGE OF GRovND o' I RE F Ro III Co N D v c 7'ORS ~ 20 )(Io f 25 )(lo + fog FEET {a) One ground wire to 10 GEOM KTR I C...

  3. ABBGroup-1-Thermal interruption

    E-Print Network [OSTI]

    Basse, Nils Plesner

    and breaking currents under specified abnormal circuit conditions such as those of a short circuit. A circuit above diagram: · Top: System voltage · Center: Rated current · Bottom: Maximal short-circuit current #12 and breaking currents under normal circuit conditions and also making, carrying for a specified time

  4. Fault Locating, Prediction and Protection (FLPPS)

    SciTech Connect (OSTI)

    Yinger, Robert, J.; Venkata, S., S.; Centeno, Virgilio

    2010-09-30T23:59:59.000Z

    One of the main objectives of this DOE-sponsored project was to reduce customer outage time. Fault location, prediction, and protection are the most important aspects of fault management for the reduction of outage time. In the past most of the research and development on power system faults in these areas has focused on transmission systems, and it is not until recently with deregulation and competition that research on power system faults has begun to focus on the unique aspects of distribution systems. This project was planned with three Phases, approximately one year per phase. The first phase of the project involved an assessment of the state-of-the-art in fault location, prediction, and detection as well as the design, lab testing, and field installation of the advanced protection system on the SCE Circuit of the Future located north of San Bernardino, CA. The new feeder automation scheme, with vacuum fault interrupters, will limit the number of customers affected by the fault. Depending on the fault location, the substation breaker might not even trip. Through the use of fast communications (fiber) the fault locations can be determined and the proper fault interrupting switches opened automatically. With knowledge of circuit loadings at the time of the fault, ties to other circuits can be closed automatically to restore all customers except the faulted section. This new automation scheme limits outage time and increases reliability for customers. The second phase of the project involved the selection, modeling, testing and installation of a fault current limiter on the Circuit of the Future. While this project did not pay for the installation and testing of the fault current limiter, it did perform the evaluation of the fault current limiter and its impacts on the protection system of the Circuit of the Future. After investigation of several fault current limiters, the Zenergy superconducting, saturable core fault current limiter was selected for installation. Because of some testing problems with the Zenergy fault current limiter, installation was delayed until early 2009 with it being put into operation on March 6, 2009. A malfunction of the FCL controller caused the DC power supply to the superconducting magnet to be turned off. This inserted the FCL impedance into the circuit while it was in normal operation causing a voltage resonance condition. While these voltages never reached a point where damage would occur on customer equipment, steps were taken to insure this would not happen again. The FCL was reenergized with load on December 18, 2009. A fault was experienced on the circuit with the FCL in operation on January 14, 2010. The FCL operated properly and reduced the fault current by about 8%, what was expected from tests and modeling. As of the end of the project, the FCL was still in operation on the circuit. The third phase of the project involved the exploration of several advanced protection ideas that might be at a state where they could be applied to the Circuit of the Future and elsewhere in the SCE electrical system. Based on the work done as part of the literature review and survey, as well as a number of internal meetings with engineering staff at SCE, a number of ideas were compiled. These ideas were then evaluated for applicability and ability to be applied on the Circuit of the Future in the time remaining for the project. Some of these basic ideas were implemented on the circuit including measurement of power quality before and after the FCL. It was also decided that we would take what was learned as part of the Circuit of the Future work and extend it to the next generation circuit protection for SCE. Also at this time, SCE put in a proposal to the DOE for the Irvine Smart Grid Demonstration using ARRA funding. SCE was successful in obtaining funding for this proposal, so it was felt that exploration of new protection schemes for this Irvine Smart Grid Demonstration would be a good use of the project resources. With this in mind, a protection system that uses fault interrupting switches, hi

  5. Accurate resistive bridge fault modeling, simulation, and test generation

    E-Print Network [OSTI]

    Sar-Dessai, Vijay Ramesh

    1999-01-01T23:59:59.000Z

    Resistive bridging faults in CMOS combinational circuits are studied in this work. Bridging faults are modeled using HSPICE circuit simulation of the various types of bridging faults that can occur in CMOS combinational circuits. The results...

  6. Commutation circuit for an HVDC circuit breaker

    DOE Patents [OSTI]

    Premerlani, William J. (Scotia, NY)

    1981-01-01T23:59:59.000Z

    A commutation circuit for a high voltage DC circuit breaker incorporates a resistor capacitor combination and a charging circuit connected to the main breaker, such that a commutating capacitor is discharged in opposition to the load current to force the current in an arc after breaker opening to zero to facilitate arc interruption. In a particular embodiment, a normally open commutating circuit is connected across the contacts of a main DC circuit breaker to absorb the inductive system energy trapped by breaker opening and to limit recovery voltages to a level tolerable by the commutating circuit components.

  7. Commutation circuit for an HVDC circuit breaker

    DOE Patents [OSTI]

    Premerlani, W.J.

    1981-11-10T23:59:59.000Z

    A commutation circuit for a high voltage DC circuit breaker incorporates a resistor capacitor combination and a charging circuit connected to the main breaker, such that a commutating capacitor is discharged in opposition to the load current to force the current in an arc after breaker opening to zero to facilitate arc interruption. In a particular embodiment, a normally open commutating circuit is connected across the contacts of a main DC circuit breaker to absorb the inductive system energy trapped by breaker opening and to limit recovery voltages to a level tolerable by the commutating circuit components. 13 figs.

  8. Accurate resistive bridge fault modeling, simulation, and test generation 

    E-Print Network [OSTI]

    Sar-Dessai, Vijay Ramesh

    1999-01-01T23:59:59.000Z

    Resistive bridging faults in CMOS combinational circuits are studied in this work. Bridging faults are modeled using HSPICE circuit simulation of the various types of bridging faults that can occur in CMOS combinational ...

  9. Interrupted polysilanes useful as photoresists

    DOE Patents [OSTI]

    Zeigler, John M. (2208 Lester Dr, NE., Albuquerque, NM 87112)

    1988-01-01T23:59:59.000Z

    Polysilane polymers in which the Si backbone is interrupted by atoms such as O, Ge, Sn, P, etc., are useful photoresists especially in the solvent development mode.

  10. Interrupted polysilanes useful as photoresists

    DOE Patents [OSTI]

    Zeigler, J.M.

    1988-08-02T23:59:59.000Z

    Polysilane polymers in which the Si backbone is interrupted by atoms such as O, Ge, Sn, P, etc., are useful photoresists especially in the solvent development mode.

  11. Transition-fault test generation

    E-Print Network [OSTI]

    Cobb, Bradley Douglas

    2013-02-22T23:59:59.000Z

    . One way to detect these timing defects is to apply test patterns to the integrated circuit that are generated using the transition-fault model. Unfortunately, industry's current transition-fault test generation schemes produce test sets that are too...

  12. Design of a Universal Logic Block for Fault-Tolerant Realization of any Logic Operation in Trapped-Ion Quantum Circuits

    E-Print Network [OSTI]

    Hadi Goudarzi; Mohammad Javad Dousti; Alireza Shafaei; Massoud Pedram

    2015-01-12T23:59:59.000Z

    This paper presents a physical mapping tool for quantum circuits, which generates the optimal Universal Logic Block (ULB) that can perform any logical fault-tolerant (FT) quantum operations with the minimum latency. The operation scheduling, placement, and qubit routing problems tackled by the quantum physical mapper are highly dependent on one another. More precisely, the scheduling solution affects the quality of the achievable placement solution due to resource pressures that may be created as a result of operation scheduling whereas the operation placement and qubit routing solutions influence the scheduling solution due to resulting distances between predecessor and current operations, which in turn determines routing latencies. The proposed flow for the quantum physical mapper captures these dependencies by applying (i) a loose scheduling step, which transforms an initial quantum data flow graph into one that explicitly captures the no-cloning theorem of the quantum computing and then performs instruction scheduling based on a modified force-directed scheduling approach to minimize the resource contention and quantum circuit latency, (ii) a placement step, which uses timing-driven instruction placement to minimize the approximate routing latencies while making iterative calls to the aforesaid force-directed scheduler to correct scheduling levels of quantum operations as needed, and (iii) a routing step that finds dynamic values of routing latencies for the qubits. In addition to the quantum physical mapper, an approach is presented to determine the single best ULB size for a target quantum circuit by examining the latency of different FT quantum operations mapped onto different ULB sizes and using information about the occurrence frequency of operations on critical paths of the target quantum algorithm to weigh these latencies.

  13. Avoiding and Managing Interruptions of Electric Service Under an Interruptible Contract or Tariff

    E-Print Network [OSTI]

    Evans, G. W.

    Many large industrial consumers of electricity purchase power through special interruptible contracts or curtailable tariffs. Historically, the number of actual interruptions has been very small -many interruptible consumers have never been required...

  14. FAULT & COORDINATION STUDY FOR T PLANT COMPLEX

    SciTech Connect (OSTI)

    MCDONALD, G.P.; BOYD-BODIAU, E.A.

    2004-09-01T23:59:59.000Z

    A short circuit study is performed to determine the maximum fault current that the system protective devices, transformers, and interconnections would he subject to in event of a three phase, phase-to-phase, or phase-to-ground fault. Generally, the short circuit study provides the worst case fault current levels at each bus or connection point of the system.

  15. High temperature superconducting fault current limiter

    DOE Patents [OSTI]

    Hull, J.R.

    1997-02-04T23:59:59.000Z

    A fault current limiter for an electrical circuit is disclosed. The fault current limiter includes a high temperature superconductor in the electrical circuit. The high temperature superconductor is cooled below its critical temperature to maintain the superconducting electrical properties during operation as the fault current limiter. 15 figs.

  16. High temperature superconducting fault current limiter

    DOE Patents [OSTI]

    Hull, John R. (Hinsdale, IL)

    1997-01-01T23:59:59.000Z

    A fault current limiter (10) for an electrical circuit (14). The fault current limiter (10) includes a high temperature superconductor (12) in the electrical circuit (14). The high temperature superconductor (12) is cooled below its critical temperature to maintain the superconducting electrical properties during operation as the fault current limiter (10).

  17. Optimal fault location

    E-Print Network [OSTI]

    Knezev, Maja

    2009-05-15T23:59:59.000Z

    are triggered. Protection system consisting of protection relays and circuit breakers (CBs) will operate in order to de-energize faulted line. Different Intelligent Electronic Devices (IEDs) located in substations for the purpose of monitoring... in the control center by an operator who will mark fault event in a spreadsheet and inform other staff responsible for dealing with fault analysis and repair such as protection group or maintenance respectively. Protective relaying staff will be ready...

  18. Optimal fault location

    E-Print Network [OSTI]

    Knezev, Maja

    2008-10-10T23:59:59.000Z

    are triggered. Protection system consisting of protection relays and circuit breakers (CBs) will operate in order to de-energize faulted line. Different Intelligent Electronic Devices (IEDs) located in substations for the purpose of monitoring... in the control center by an operator who will mark fault event in a spreadsheet and inform other staff responsible for dealing with fault analysis and repair such as protection group or maintenance respectively. Protective relaying staff will be ready...

  19. Realistic fault modeling and quality test generation of combined delay faults 

    E-Print Network [OSTI]

    Thadhlani, Ajaykumar A

    2001-01-01T23:59:59.000Z

    With increasing operating speed and shrinking technology, timing defects in integrated circuits are becoming increasingly important. The well established stuck-at-fault model is not sufficient because it is a static fault ...

  20. Industrial Interruptible Power: An Economical Alternative 

    E-Print Network [OSTI]

    Reynolds, S. D.; Gardner, J. R.

    1984-01-01T23:59:59.000Z

    and Chemicals, Inc. Diamond Shamrock Corp. Kemanord, Inc. Kerr-McGee Chemical Corp. Monsanto Company Occidental Chemical Corp. Pennwalt Corporation Stauffer Chemical Co. Total Interruptible Under Contract: 640 MW EXHIBIT II Sample Monthly Power...

  1. An efficient logic fault diagnosis framework based on effect-cause approach

    E-Print Network [OSTI]

    Wu, Lei

    2009-05-15T23:59:59.000Z

    Fault diagnosis plays an important role in improving the circuit design process and the manufacturing yield. With the increasing number of gates in modern circuits, determining the source of failure in a defective circuit is becoming more and more...

  2. Short Circuit Analysis of Induction Machines Wind Power Application

    SciTech Connect (OSTI)

    Starke, Michael R [ORNL; Smith, Travis M [ORNL; Howard, Dustin [Georgia Institute of Technology; Harley, Ronald [Georgia Institute of Technology

    2012-01-01T23:59:59.000Z

    he short circuit behavior of Type I (fixed speed) wind turbine-generators is analyzed in this paper to aid in the protection coordination of wind plants of this type. A simple network consisting of one wind turbine-generator is analyzed for two network faults: a three phase short circuit and a phase A to ground fault. Electromagnetic transient simulations and sequence network calculations are compared for the two fault scenarios. It is found that traditional sequence network calculations give accurate results for the short circuit currents in the balanced fault case, but are inaccurate for the un-faulted phases in the unbalanced fault case. The time-current behavior of the fundamental frequency component of the short circuit currents for both fault cases are described, and found to differ significantly in the unbalanced and balanced fault cases

  3. Interruptions : using activity transitions to trigger proactive messages

    E-Print Network [OSTI]

    Ho, Joyce (Joyce Carmen)

    2004-01-01T23:59:59.000Z

    The proliferation of mobile devices and their tendency to present information proactively has led to an increase in device generated interruptions experienced by users. These interruptions are not confined to a particular ...

  4. IMPROVING CATASTROPHE MODELING FOR BUSINESS INTERRUPTION INSURANCE NEEDS

    E-Print Network [OSTI]

    Wang, Hai

    IMPROVING CATASTROPHE MODELING FOR BUSINESS INTERRUPTION INSURANCE NEEDS by Adam Rose Price School, Surrey, UK KT21 2BT May 10, 2012 #12;1 IMPROVING CATASTROPHE MODELING FOR BUSINESS INTERRUPTION INSURANCE modeling of business interruption (BI) is still in a relative state of infancy. One reason

  5. Short-Circuit Modeling of a Wind Power Plant: Preprint

    SciTech Connect (OSTI)

    Muljadi, E.; Gevorgian, V.

    2011-03-01T23:59:59.000Z

    This paper investigates the short-circuit behavior of a WPP for different types of wind turbines. The short-circuit behavior will be presented. Both the simplified models and detailed models are used in the simulations and both symmetrical faults and unsymmetrical faults are discussed.

  6. Realistic fault modeling and quality test generation of combined delay faults

    E-Print Network [OSTI]

    Thadhlani, Ajaykumar A

    2001-01-01T23:59:59.000Z

    coupled lines. To cope up with these realistic testing problems, it is necessary to model the circuit defects by considering the capacitively coupling between lines. This needs a better fault model which can incorporate the local defects (such...

  7. Interruption Cost Estimate Calculator | Open Energy Information

    Open Energy Info (EERE)

    AFDC Printable Version Share this resource Send a link to EERE: Alternative Fuels Data Center Home Page to someone by E-mail Share EERE: Alternative Fuels Data Center Home Page on Facebook Tweet about EERE: Alternative Fuels Data Center Home Page on Twitter Bookmark EERE: Alternative Fuels Data Center Home Page onYou are now leaving Energy.gov You are now leaving Energy.gov You are8COaBulkTransmissionSitingProcess.pdfGetecGtelInterias Solar Energy Jump to:IES JumpUnion forInterruption Cost

  8. Passive fault current limiting device

    DOE Patents [OSTI]

    Evans, Daniel J. (Wheeling, IL); Cha, Yung S. (Darien, IL)

    1999-01-01T23:59:59.000Z

    A passive current limiting device and isolator is particularly adapted for use at high power levels for limiting excessive currents in a circuit in a fault condition such as an electrical short. The current limiting device comprises a magnetic core wound with two magnetically opposed, parallel connected coils of copper, a high temperature superconductor or other electrically conducting material, and a fault element connected in series with one of the coils. Under normal operating conditions, the magnetic flux density produced by the two coils cancel each other. Under a fault condition, the fault element is triggered to cause an imbalance in the magnetic flux density between the two coils which results in an increase in the impedance in the coils. While the fault element may be a separate current limiter, switch, fuse, bimetal strip or the like, it preferably is a superconductor current limiter conducting one-half of the current load compared to the same limiter wired to carry the total current of the circuit. The major voltage during a fault condition is in the coils wound on the common core in a preferred embodiment.

  9. Passive fault current limiting device

    DOE Patents [OSTI]

    Evans, D.J.; Cha, Y.S.

    1999-04-06T23:59:59.000Z

    A passive current limiting device and isolator is particularly adapted for use at high power levels for limiting excessive currents in a circuit in a fault condition such as an electrical short. The current limiting device comprises a magnetic core wound with two magnetically opposed, parallel connected coils of copper, a high temperature superconductor or other electrically conducting material, and a fault element connected in series with one of the coils. Under normal operating conditions, the magnetic flux density produced by the two coils cancel each other. Under a fault condition, the fault element is triggered to cause an imbalance in the magnetic flux density between the two coils which results in an increase in the impedance in the coils. While the fault element may be a separate current limiter, switch, fuse, bimetal strip or the like, it preferably is a superconductor current limiter conducting one-half of the current load compared to the same limiter wired to carry the total current of the circuit. The major voltage during a fault condition is in the coils wound on the common core in a preferred embodiment. 6 figs.

  10. Observability of Stuck-at-Faults with Differential Power Analysis

    E-Print Network [OSTI]

    Boyer, Edmond

    ,flottes,rouzeyre}@lirmm.fr Abstract In this paper we propose an innovative method to test integrated circuits based on the use of the current consumed by the circuit during net transitions, it does not require observing primary outputs of the circuit and allows the test of hard-to-observe faults. Conversely to Iddq, this technique is not sensible

  11. Fault Tolerance Techniques for Wireless Ad Hoc Sensor Networks Farinaz Koushanfar

    E-Print Network [OSTI]

    poten- tial to provide inexpensive and pervasive bridge between physical and computational worlds and actuators that have significantly higher fault rates than the traditional semiconductor integrated circuits

  12. Wind Power Plant Enhancement with a Fault-Current Limiter: Preprint

    SciTech Connect (OSTI)

    Muljadi, E.; Gevorgian, V.; DeLaRosa, F.

    2011-03-01T23:59:59.000Z

    This paper investigates the capability of a saturable core fault-current limiter to limit the short circuit current of different types of wind turbine generators.

  13. Microsoft Word - GroundFaultSAND-rev7-JJ.doc

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    to describe analytically without transcendental equations, but the use of computer circuit simulations can describe the behavior of a PV system for a wide variety of fault...

  14. Application of functional learning to ATPG and design verification for combinational circuits

    E-Print Network [OSTI]

    Mukherjee, Rajarshim

    1994-01-01T23:59:59.000Z

    to detect faults and in detecting redundant faults. Learning techniques have also been effectively applied to the problem of design verification for combinational circuits. This paper presents Functional Learning, a new method of learning, based...

  15. Arc fault detection system

    DOE Patents [OSTI]

    Jha, Kamal N. (Bethel Park, PA)

    1999-01-01T23:59:59.000Z

    An arc fault detection system for use on ungrounded or high-resistance-grounded power distribution systems is provided which can be retrofitted outside electrical switchboard circuits having limited space constraints. The system includes a differential current relay that senses a current differential between current flowing from secondary windings located in a current transformer coupled to a power supply side of a switchboard, and a total current induced in secondary windings coupled to a load side of the switchboard. When such a current differential is experienced, a current travels through a operating coil of the differential current relay, which in turn opens an upstream circuit breaker located between the switchboard and a power supply to remove the supply of power to the switchboard.

  16. Arc fault detection system

    DOE Patents [OSTI]

    Jha, K.N.

    1999-05-18T23:59:59.000Z

    An arc fault detection system for use on ungrounded or high-resistance-grounded power distribution systems is provided which can be retrofitted outside electrical switchboard circuits having limited space constraints. The system includes a differential current relay that senses a current differential between current flowing from secondary windings located in a current transformer coupled to a power supply side of a switchboard, and a total current induced in secondary windings coupled to a load side of the switchboard. When such a current differential is experienced, a current travels through a operating coil of the differential current relay, which in turn opens an upstream circuit breaker located between the switchboard and a power supply to remove the supply of power to the switchboard. 1 fig.

  17. Photovoltaic ground fault and blind spot electrical simulations.

    SciTech Connect (OSTI)

    Flicker, Jack David; Johnson, Jay

    2013-06-01T23:59:59.000Z

    Ground faults in photovoltaic (PV) systems pose a fire and shock hazard. To mitigate these risks, AC-isolated, DC grounded PV systems in the United States use Ground Fault Protection Devices (GFPDs), e.g., fuses, to de-energize the PV system when there is a ground fault. Recently the effectiveness of these protection devices has come under question because multiple fires have started when ground faults went undetected. In order to understand the limitations of fuse-based ground fault protection in PV systems, analytical and numerical simulations of different ground faults were performed. The numerical simulations were conducted with Simulation Program with Integrated Circuit Emphasis (SPICE) using a circuit model of the PV system which included the modules, wiring, switchgear, grounded or ungrounded components, and the inverter. The derivation of the SPICE model and the results of parametric fault current studies are provided with varying array topologies, fuse sizes, and fault impedances. Closed-form analytical approximations for GFPD currents from faults to the grounded current carrying conductor-known as %E2%80%9Cblind spot%E2%80%9D ground faults-are derived to provide greater understanding of the influence of array impedances on fault currents. The behavior of the array during various ground faults is studied for a range of ground fault fuse sizes to determine if reducing the size of the fuse improves ground fault detection sensitivity. The results of the simulations show that reducing the amperage rating of the protective fuse does increase fault current detection sensitivity without increasing the likelihood of nuisance trips to a degree. Unfortunately, this benefit reaches a limit as fuses become smaller and their internal resistance increases to the point of becoming a major element in the fault current circuit.

  18. IMPLEMENTATION OF PRECISE INTERRUPTS IN PIPELINED PROCESSORS James E. Smith

    E-Print Network [OSTI]

    Zhang, Zhongfei "Mark"

    is precise if the saved process state corresponds with the sequential model of program execution where one. When an interrupt occurs, the state of an interrupted process is typically saved by the hardware, registers, and memory. If the saved process state is consistent with the sequential architectural model

  19. Fault Current Calculation by The Least Squares Method Natthaphob Nimpitiwan, Student Member, IEEE, and Gerald T. Heydt, Fellow, IEEE

    E-Print Network [OSTI]

    OF FAULT CURRENT Circuit breaker capability and configuration of protective relays that were previously relays, and their coordination. Systems must be able to withstand a certain limit of faults which also

  20. Analysis of transmission system faults in the phase domain

    E-Print Network [OSTI]

    Zhu, Jun

    2004-11-15T23:59:59.000Z

    In order to maintain a continuous power suppply, nowadays relays in transmission systems are required to be able to deal with complicated faults involving non-conventional connections, which poses a challenge to the short circuit analysis...

  1. Induction Machine Fault Detection Enhancement Using a Stator Current High Resolution Spectrum

    E-Print Network [OSTI]

    Paris-Sud XI, Université de

    into stator winding short circuit, broken rotor bar, broken end-ring, rotor eccentricity, bearing faultsInduction Machine Fault Detection Enhancement Using a Stator Current High Resolution Spectrum El-Fault detection in squirrel cage induction machines based on stator current spectrum has been widely investi gated

  2. Fault Current Issues for Market Driven Power Systems with Distributed Generation

    E-Print Network [OSTI]

    are required for the selection of interruption devices, protective relays, and their coordination. Systems must Terms--Distributed / dispersed generation, power distri- bution, power system protection, fault in siting conventional generation ­ but, for whatever reason, protection engineers as well as transmission

  3. Back Fed Main Breakers with Ground-Fault Protection The NEC has had for many editions, a requirement (230.95) that solidly grounded

    E-Print Network [OSTI]

    Johnson, Eric E.

    Back Fed Main Breakers with Ground-Fault Protection The NEC has had for evaluating the backfeeding of the basic circuit breaker, most of the accessories

  4. Negotiating Task Interruptions with Virtual Agents for Health Behavior Change

    E-Print Network [OSTI]

    Bickmore, Timothy

    and chronic disease in the United States [18]. In addition, adherence to prescribed treatments, such as lack of physical activity and unhealthy dietary habits, are among the leading causes of death rate. However, as many recent studies in task interruption have shown, responsiveness

  5. Simulating Threshold Circuits by Majority Circuits \\Lambda

    E-Print Network [OSTI]

    Karpinski, Marek

    Simulating Threshold Circuits by Majority Circuits \\Lambda Mikael Goldmann y Numerical Analysis, and Kailath proved super­linear lower bounds on the number of wires in constant­depth majority circuits­size depth 2 majority circuit. In general we show that a polynomial­size, depth­ d threshold circuit can

  6. Exotic Options for Interruptible Electricity Supply Rajnish Kamat and Shmuel S. Oren

    E-Print Network [OSTI]

    California at Berkeley. University of

    as an interruptible service contract (see Chao and Wilson (1987)) involves giving firms a discount on the forward will call this contract an interruptible service contract with early notification. Another type of contract

  7. Slide 1

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    has required arc-fault circuit interrupters (AFCIs) to be incorporated into photovoltaic (PV) systems to prevent fires. Some manufacturers are designing AFCIs to consist of...

  8. Sandia Energy - EC Publications

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    has required arc-fault circuit interrupters (AFCIs) to be incorporated into photovoltaic (PV) systems to prevent fires. Some manufacturers are designing AFCIs to consist of...

  9. Exploring Interruption in HRI using Wizard of Oz Paul Saulnier, Ehud Sharlin, Saul Greenberg

    E-Print Network [OSTI]

    Greenberg, Saul

    experiments and should call for future research of interruption in human-robot interaction. II. DESCRIPTION of Oz (WoO) should interrupt humans in various social settings. While there is considerable work social HRI experiments as well as reflections on our future interruption HRI research Keywords

  10. Reversible harmless interruption of testicular blood supply in the ram

    SciTech Connect (OSTI)

    van Vliet, J.; De Ruiter-Bootsma, A.L.; Oei, Y.H.; Hoekstra, A.; De Rooij, D.G.; Wensing, C.J.

    1987-03-01T23:59:59.000Z

    An effective method of interrupting testicular blood flow temporarily and repeatedly in the ram has been developed. Blockade of flow has been achieved mechanically by an inflatable occluder placed around the testicular artery at the level of the spermatic cord. The effect of the blockade on total testicular blood supply was investigated using Doppler flowmetry and a percutaneous Xenon-133 injection method. With both approaches, the blood flow changes after inflation or deflation of the occluders could be estimated satisfactorily. A substantial decrease of testicular blood flow was achieved in eight of the 10 testes with inflated occluders. However, there were indications that in the remaining two testes blockade of the arterial flow was not complete. After deflation of the occluders, blood flow was restored rapidly and completely in all testes. Macro- and microscopic examinations revealed no long-term damage to the testis after blood flow interruptions lasting 30 or 60 minutes.

  11. Interruptible Power: An Economic Advantage to Industrial Users 

    E-Print Network [OSTI]

    Reynolds, S. D.; Gardner, J. R.

    1981-01-01T23:59:59.000Z

    Corp. 17,400 30,000 47,400 Monsanto Company 17,000 154,000 171,000 Pennwalt Corporation 75,000 30,000 105,000 SKW Alloys, Inc. 75,000 70,000 145,000 Stauffer Chemical Company 14,000 76,000 90,000 Total Interruptible 648,000 774 ESL-IE-81...

  12. Neural net application to transmission line fault detection and classification

    E-Print Network [OSTI]

    Rikalo, Igor

    1994-01-01T23:59:59.000Z

    . So far, several NN implementations for various fault diagnosis problems have been reported in the literature. A number of papers describing NN applications in pov er systems categorized in appropriate groups can be found in [19, 20]. 1. 3. Thesis... important issue for stable and reliable operation of pov;er systems. The main target of the fault analysis are circuit breaker and protection relay operations. The task of the analysis is to reach a conclusion about the current state of the electrical...

  13. High speed, long distance, data transmission multiplexing circuit

    DOE Patents [OSTI]

    Mariotti, Razvan (Boulder, CO)

    1991-01-01T23:59:59.000Z

    A high speed serial data transmission multiplexing circuit, which is operable to accurately transmit data over long distances (up to 3 Km), and to multiplex, select and continuously display real time analog signals in a bandwidth from DC to 100 Khz. The circuit is made fault tolerant by use of a programmable flywheel algorithm, which enables the circuit to tolerate one transmission error before losing synchronization of the transmitted frames of data. A method of encoding and framing captured and transmitted data is used which has a low overhead and prevents some particular transmitted data patterns from locking an included detector/decoder circuit.

  14. Stuck-at-fault test set compaction

    E-Print Network [OSTI]

    Vanfickell, Jason Michael

    2013-02-22T23:59:59.000Z

    of sltcp g(0. 5-ones~robo~, ~) Exc Bal, = 0. 25 ? of sites Figure 1. Formula for computation of the excitation balance Excitation balance is a metric computed for every detectable fault in the entire circuit. It is intended to provide a measure... Sigma ~ National Society of Collegiate Scholars Activities: ~ Texas A&M University Institute of Electrical and Electronic Engineers IT/Technology Chair and Webmaster, Fall 2003 ? Spring 2004 ~ Texas A&M University Student Engineers' Council...

  15. Reliability-yield allocation for semiconductor integrated circuits: modeling and optimization

    E-Print Network [OSTI]

    Ha, Chunghun

    2005-11-01T23:59:59.000Z

    This research develops yield and reliability models for fault-tolerant semiconductor integrated circuits and develops optimization algorithms that can be directly applied to these models. Since defects cause failures in microelectronics systems...

  16. Genetic Programming Approach for Fault Modeling of Electronic Hardware Ajith Abraham

    E-Print Network [OSTI]

    Fernandez, Thomas

    performance monitoring of electronic circuits and systems. Reliability modeling of electronic circuits can discussed in Section 2. This technique can be extended to simple electronic components and for complicatedGenetic Programming Approach for Fault Modeling of Electronic Hardware Ajith Abraham School

  17. High voltage fault current limiter having immersed phase coils

    DOE Patents [OSTI]

    Darmann, Francis Anthony

    2014-04-22T23:59:59.000Z

    A fault current limiter including: a ferromagnetic circuit formed from a ferromagnetic material and including at least a first limb, and a second limb; a saturation mechanism surrounding a limb for magnetically saturating the ferromagnetic material; a phase coil wound around a second limb; a dielectric fluid surrounding the phase coil; a gaseous atmosphere surrounding the saturation mechanism.

  18. Fault tolerant pulse synchronization 

    E-Print Network [OSTI]

    Deconda, Keerthi

    2009-05-15T23:59:59.000Z

    FFC n=4 orig alg n=4 ft alg n=7 orig alg n=7 ft alg n=10 orig alg n=10 ft alg 24 (a) n=4, f=1. (b) n=7, f=2. Fig. 5: Convergence Time with No Jump faults. 0 50 100 150 200 250 70 100 250 500 Tim e to co nv erg e FFC orig alg: no faults... orig alg: NoJump faults ft alg:NoJump faults 0 50 100 150 200 250 300 350 400 450 70 100 250 500 Tim e to co nv erg e FFC orig alg: no faults orig alg: NoJump faults ft alg:NoJump faults 25 (c) n=10, f=3. Fig. 5 (Continued) Fig. 5(a...

  19. Topological fault-tolerance in cluster state quantum computation

    E-Print Network [OSTI]

    Robert Raussendorf; Jim Harrington; Kovid Goyal

    2007-03-16T23:59:59.000Z

    We describe a fault-tolerant version of the one-way quantum computer using a cluster state in three spatial dimensions. Topologically protected quantum gates are realized by choosing appropriate boundary conditions on the cluster. We provide equivalence transformations for these boundary conditions that can be used to simplify fault-tolerant circuits and to derive circuit identities in a topological manner. The spatial dimensionality of the scheme can be reduced to two by converting one spatial axis of the cluster into time. The error threshold is 0.75% for each source in an error model with preparation, gate, storage and measurement errors. The operational overhead is poly-logarithmic in the circuit size.

  20. Topological fault-tolerance in cluster state quantum computation

    E-Print Network [OSTI]

    Raussendorf, R; Harrington, J; Goyal, Kovid; Harrington, Jim; Raussendorf, Robert

    2007-01-01T23:59:59.000Z

    We describe a fault-tolerant version of the one-way quantum computer using a cluster state in three spatial dimensions. Topologically protected quantum gates are realized by choosing appropriate boundary conditions on the cluster. We provide equivalence transformations for these boundary conditions that can be used to simplify fault-tolerant circuits and to derive circuit identities in a topological manner. The spatial dimensionality of the scheme can be reduced to two by converting one spatial axis of the cluster into time. The error threshold is 0.75% for each source in an error model with preparation, gate, storage and measurement errors. The operational overhead is poly-logarithmic in the circuit size.

  1. Testing tri-state and pass transistor circuit structures

    E-Print Network [OSTI]

    Parikh, Shaishav Shailesh

    2005-11-01T23:59:59.000Z

    will cause some lines in the circuit to float and take unknown values. A stuck-on control line can cause fighting when the two drivers connected to the same node drive different values. This thesis develops new gate level fault models and dynamic test...

  2. INSTRUCTIONS FOR PREPARATION OF PAPERS

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    PV arc-faults, the US National Electrical Code (NEC) 5 has required arc-fault circuit interrupters (AFCIs), for PV systems greater than 80V, since 2011. Underwriters...

  3. A Single Server Retrial Queue with Different Types of Server Interruptions

    E-Print Network [OSTI]

    Paris-Sud XI, Université de

    A Single Server Retrial Queue with Different Types of Server Interruptions Tewfik Kernane@gmail.com February 11, 2009 Abstract We consider a single server retrial queue with the server subject to interruptions and classical retrial policy for the access from the orbit to the server. We analyze

  4. Evolution of Drug-resistant Viral Populations during Interruption of Antiretroviral Therapy

    E-Print Network [OSTI]

    Ahlers, Guenter

    1 Evolution of Drug-resistant Viral Populations during Interruption of Antiretroviral Therapy Running title: Evolution and fitness of drug-resistant viruses Dongning Wang1 , Charles B. Hicks2 , Neela antiretroviral treatment (ART) interruption allows determination of the evolution of3 drug-resistant viruses

  5. Persuasion, Task Interruption and Health Regimen Timothy Bickmore, Daniel Mauer, Francisco Crespo, and Thomas Brown

    E-Print Network [OSTI]

    Bickmore, Timothy

    and unhealthy dietary habits, are among the leading causes of death and chronic disease in the United States [21 in a relatively high compliance rate. However, as many recent studies in task interruption have shown other factors such as the emotional state of the user [15] and the modality of the interruption [1]. We

  6. Fault simulation and test generation for small delay faults

    E-Print Network [OSTI]

    Qiu, Wangqi

    2007-04-25T23:59:59.000Z

    Delay faults are an increasingly important test challenge. Traditional delay fault models are incomplete in that they model only a subset of delay defect behaviors. To solve this problem, a more realistic delay fault model has been developed which...

  7. Symmetrical and Unsymmetrical Fault Currents of a Wind Power Plant: Preprint

    SciTech Connect (OSTI)

    Gevorgian, V.; Singh, M.; Muljadi, E.

    2011-12-01T23:59:59.000Z

    This paper investigates the short-circuit behavior of a wind power plant for different types of wind turbines. Both symmetrical faults and unsymmetrical faults are investigated. The size of wind power plants (WPPs) keeps getting bigger and bigger. The number of wind plants in the U.S. has increased very rapidly in the past 10 years. It is projected that in the U.S., the total wind power generation will reach 330 GW by 2030. As the importance of WPPs increases, planning engi-neers must perform impact studies used to evaluate short-circuit current (SCC) contribution of the plant into the transmission network under different fault conditions. This information is needed to size the circuit breakers, to establish the proper sys-tem protection, and to choose the transient suppressor in the circuits within the WPP. This task can be challenging to protec-tion engineers due to the topology differences between different types of wind turbine generators (WTGs) and the conventional generating units. This paper investigates the short-circuit behavior of a WPP for different types of wind turbines. Both symmetrical faults and unsymmetrical faults are investigated. Three different soft-ware packages are utilized to develop this paper. Time domain simulations and steady-state calculations are used to perform the analysis.

  8. Increasing fault resiliency in a message-passing environment.

    SciTech Connect (OSTI)

    Stearley, Jon R.; Riesen, Rolf E.; Laros, James H., III; Ferreira, Kurt Brian; Pedretti, Kevin Thomas Tauke; Oldfield, Ron A.; Kordenbrock, Todd (Hewlett-Packard Company); Brightwell, Ronald Brian

    2009-10-01T23:59:59.000Z

    Petaflops systems will have tens to hundreds of thousands of compute nodes which increases the likelihood of faults. Applications use checkpoint/restart to recover from these faults, but even under ideal conditions, applications running on more than 30,000 nodes will likely spend more than half of their total run time saving checkpoints, restarting, and redoing work that was lost. We created a library that performs redundant computations on additional nodes allocated to the application. An active node and its redundant partner form a node bundle which will only fail, and cause an application restart, when both nodes in the bundle fail. The goal of this library is to learn whether this can be done entirely at the user level, what requirements this library places on a Reliability, Availability, and Serviceability (RAS) system, and what its impact on performance and run time is. We find that our redundant MPI layer library imposes a relatively modest performance penalty for applications, but that it greatly reduces the number of applications interrupts. This reduction in interrupts leads to huge savings in restart and rework time. For large-scale applications the savings compensate for the performance loss and the additional nodes required for redundant computations.

  9. Onsite Backup Generation and Interruption Insurance for Electricity Distribution Author(s): Joseph A. Doucet and Shmuel S. Oren

    E-Print Network [OSTI]

    Oren, Shmuel S.

    Onsite Backup Generation and Interruption Insurance for Electricity Distribution Author(s): Joseph customerownedonsitebackupdecisionswillpre-emptthe utility'splan to mitigatecompensationpaymentsbyprovidingonsitebackup generation access to The Energy Journal. http://www.jstor.org #12;Onsite Backup Generation and Interruption

  10. Solar system fault detection

    DOE Patents [OSTI]

    Farrington, R.B.; Pruett, J.C. Jr.

    1984-05-14T23:59:59.000Z

    A fault detecting apparatus and method are provided for use with an active solar system. The apparatus provides an indication as to whether one or more predetermined faults have occurred in the solar system. The apparatus includes a plurality of sensors, each sensor being used in determining whether a predetermined condition is present. The outputs of the sensors are combined in a pre-established manner in accordance with the kind of predetermined faults to be detected. Indicators communicate with the outputs generated by combining the sensor outputs to give the user of the solar system and the apparatus an indication as to whether a predetermined fault has occurred. Upon detection and indication of any predetermined fault, the user can take appropriate corrective action so that the overall reliability and efficiency of the active solar system are increased.

  11. Charge regulation circuit

    DOE Patents [OSTI]

    Ball, Don G. (Livermore, CA)

    1992-01-01T23:59:59.000Z

    A charge regulation circuit provides regulation of an unregulated voltage supply in the range of 0.01%. The charge regulation circuit is utilized in a preferred embodiment in providing regulated voltage for controlling the operation of a laser.

  12. Worldwide reliability surveys of high voltage circuit breakers

    SciTech Connect (OSTI)

    Heising, C.R.

    1995-05-01T23:59:59.000Z

    This article reports on the results of two CIGRE 13.06 Working Group worldwide surveys of the reliability of high voltage circuit breakers, 63 kV and above. The first inquiry included 78,000 breaker-years of ``in service data`` from 102 utilities in 22 countries during the years 1974--1977 and included all interrupting technologies. The second inquiry included 70,708 breaker-years from 132 utilities in 22 countries for the years 1988--1991 and only included single-pressure SF6 breakers, because this is what most utilities are now buying. Thirty-one US utilities submitted data.

  13. Method for deposition of a conductor in integrated circuits

    DOE Patents [OSTI]

    Creighton, J.R.; Dominguez, F.; Johnson, A.W.; Omstead, T.R.

    1997-09-02T23:59:59.000Z

    A method is described for fabricating integrated semiconductor circuits and, more particularly, for the selective deposition of a conductor onto a substrate employing a chemical vapor deposition process. By way of example, tungsten can be selectively deposited onto a silicon substrate. At the onset of loss of selectivity of deposition of tungsten onto the silicon substrate, the deposition process is interrupted and unwanted tungsten which has deposited on a mask layer with the silicon substrate can be removed employing a halogen etchant. Thereafter, a plurality of deposition/etch back cycles can be carried out to achieve a predetermined thickness of tungsten. 2 figs.

  14. Method for deposition of a conductor in integrated circuits

    DOE Patents [OSTI]

    Creighton, J. Randall (Albuquerque, NM); Dominguez, Frank (Albuquerque, NM); Johnson, A. Wayne (Albuquerque, NM); Omstead, Thomas R. (Albuquerque, NM)

    1997-01-01T23:59:59.000Z

    A method is described for fabricating integrated semiconductor circuits and, more particularly, for the selective deposition of a conductor onto a substrate employing a chemical vapor deposition process. By way of example, tungsten can be selectively deposited onto a silicon substrate. At the onset of loss of selectivity of deposition of tungsten onto the silicon substrate, the deposition process is interrupted and unwanted tungsten which has deposited on a mask layer with the silicon substrate can be removed employing a halogen etchant. Thereafter, a plurality of deposition/etch back cycles can be carried out to achieve a predetermined thickness of tungsten.

  15. Piezoelectric drive circuit

    DOE Patents [OSTI]

    Treu, C.A. Jr.

    1999-08-31T23:59:59.000Z

    A piezoelectric motor drive circuit is provided which utilizes the piezoelectric elements as oscillators and a Meacham half-bridge approach to develop feedback from the motor ground circuit to produce a signal to drive amplifiers to power the motor. The circuit automatically compensates for shifts in harmonic frequency of the piezoelectric elements due to pressure and temperature changes. 7 figs.

  16. Piezoelectric drive circuit

    DOE Patents [OSTI]

    Treu, Jr., Charles A. (Raymore, MO)

    1999-08-31T23:59:59.000Z

    A piezoelectric motor drive circuit is provided which utilizes the piezoelectric elements as oscillators and a Meacham half-bridge approach to develop feedback from the motor ground circuit to produce a signal to drive amplifiers to power the motor. The circuit automatically compensates for shifts in harmonic frequency of the piezoelectric elements due to pressure and temperature changes.

  17. Development studies of a solid-state d.c. circuit breaker based on the GTO

    E-Print Network [OSTI]

    Kernaghan, William Henry

    1986-01-01T23:59:59.000Z

    by the arc, will ring with the circuit inductance and can produce transient recovery voltages up to twice the a. c. system voltage level. " This voltage can somewhat be controlled by switching in some resistance across the a. c. interrupter as illustrated... of anode voltage which in turn lessens the turn ? off losses of the GTO because high voltages are delayed until IA has decreased. This implies that the maximum controllable current increases as the 16 capacitance is increased. The snubber resistor must...

  18. Bridge Fault Simulation Strategies for CMOS Integrated Circuits Brian Chess

    E-Print Network [OSTI]

    Larrabee, Tracy

    , is more efficient---especially for larger cir­ cuits. I. Introduction Obtaining low IC defect levels

  19. Effect of Radiotherapy Interruptions on Survival in Medicare Enrollees With Local and Regional Head-and-Neck Cancer

    SciTech Connect (OSTI)

    Fesinmeyer, Megan Dann [Fred Hutchinson Cancer Research Center, Seattle, WA (United States); Mehta, Vivek [Swedish Medical Center, Seattle, WA (United States); Blough, David [Fred Hutchinson Cancer Research Center, Seattle, WA (United States); School of Pharmacy, University of Washington, Seattle, WA (United States); Tock, Lauri [Fred Hutchinson Cancer Research Center, Seattle, WA (United States); Ramsey, Scott D., E-mail: sramsey@fhcrc.or [Fred Hutchinson Cancer Research Center, Seattle, WA (United States); School of Pharmacy, University of Washington, Seattle, WA (United States)

    2010-11-01T23:59:59.000Z

    Purpose: To investigate whether interruptions in radiotherapy are associated with decreased survival in a population-based sample of head-and-neck cancer patients. Methods and Materials: Using the Surveillance, Epidemiology, and End Results-Medicare linked database we identified Medicare beneficiaries aged 66 years and older diagnosed with local-regional head-and-neck cancer during the period 1997-2003. We examined claims records of 3864 patients completing radiotherapy for the presence of one or more 5-30-day interruption(s) in therapy. We then performed Cox regression analyses to estimate the association between therapy interruptions and survival. Results: Patients with laryngeal tumors who experienced an interruption in radiotherapy had a 68% (95% confidence interval, 41-200%) increased risk of death, compared with patients with no interruptions. Patients with nasal cavity, nasopharynx, oral, salivary gland, and sinus tumors had similar associations between interruptions and increased risk of death, but these did not reach statistical significance because of small sample sizes. Conclusions: Treatment interruptions seem to influence survival time among patients with laryngeal tumors completing a full course of radiotherapy. At all head-and-neck sites, the association between interruptions and survival is sensitive to confounding by stage and other treatments. Further research is needed to develop methods to identify patients most susceptible to interruption-induced mortality.

  20. EC5135: Analog Electronic Circuits EC3102: Analog Circuits

    E-Print Network [OSTI]

    Krishnapura, Nagendra

    #12;Course prerequisites Circuit analysis Mesh, nodal analyses RLC, linear dependent sources Laplace and Kemmerly, Engineering Circuit Analysis, McGraw Hill, 6/e. B. P. Lathi, Linear Systems and Signals, Oxford Circuits EC3102: Analog Circuits #12;Course contents Nonlinear circuits-incremental analysis Obtaining

  1. Regenerative feedback resonant circuit

    DOE Patents [OSTI]

    Jones, A. Mark; Kelly, James F.; McCloy, John S.; McMakin, Douglas L.

    2014-09-02T23:59:59.000Z

    A regenerative feedback resonant circuit for measuring a transient response in a loop is disclosed. The circuit includes an amplifier for generating a signal in the loop. The circuit further includes a resonator having a resonant cavity and a material located within the cavity. The signal sent into the resonator produces a resonant frequency. A variation of the resonant frequency due to perturbations in electromagnetic properties of the material is measured.

  2. Remote reset circuit

    DOE Patents [OSTI]

    Gritzo, Russell E. (West Melbourne, FL)

    1987-01-01T23:59:59.000Z

    A remote reset circuit acts as a stand-alone monitor and controller by clocking in each character sent by a terminal to a computer and comparing it to a given reference character. When a match occurs, the remote reset circuit activates the system's hardware reset line. The remote reset circuit is hardware based centered around monostable multivibrators and is unaffected by system crashes, partial serial transmissions, or power supply transients.

  3. Fault tolerant linear actuator

    DOE Patents [OSTI]

    Tesar, Delbert

    2004-09-14T23:59:59.000Z

    In varying embodiments, the fault tolerant linear actuator of the present invention is a new and improved linear actuator with fault tolerance and positional control that may incorporate velocity summing, force summing, or a combination of the two. In one embodiment, the invention offers a velocity summing arrangement with a differential gear between two prime movers driving a cage, which then drives a linear spindle screw transmission. Other embodiments feature two prime movers driving separate linear spindle screw transmissions, one internal and one external, in a totally concentric and compact integrated module.

  4. Computer hardware fault administration

    DOE Patents [OSTI]

    Archer, Charles J. (Rochester, MN); Megerian, Mark G. (Rochester, MN); Ratterman, Joseph D. (Rochester, MN); Smith, Brian E. (Rochester, MN)

    2010-09-14T23:59:59.000Z

    Computer hardware fault administration carried out in a parallel computer, where the parallel computer includes a plurality of compute nodes. The compute nodes are coupled for data communications by at least two independent data communications networks, where each data communications network includes data communications links connected to the compute nodes. Typical embodiments carry out hardware fault administration by identifying a location of a defective link in the first data communications network of the parallel computer and routing communications data around the defective link through the second data communications network of the parallel computer.

  5. Circuit Theory for Analysis and Design of Spintronic Integrated Circuits

    E-Print Network [OSTI]

    Manipatruni, Sasikanth; Young, Ian A

    2011-01-01T23:59:59.000Z

    We present a theoretical and a numerical formalism for analysis and design of spintronic integrated circuits (SPINICs). The proposed formalism encompasses a generalized circuit theory for spintronic integrated circuits based on nanomagnetic dynamics and spin transport. We derive the circuit models for vector spin conduction in non-magnetic and magnetic components. We then propose an extension to the modified nodal analysis for the analysis of spin circuits. We demonstrate the applicability of the proposed theory using an example spin logic circuit.

  6. Compensated gain control circuit for buck regulator command charge circuit

    DOE Patents [OSTI]

    Barrett, David M. (Albuquerque, NM)

    1996-01-01T23:59:59.000Z

    A buck regulator command charge circuit includes a compensated-gain control signal for compensating for changes in the component values in order to achieve optimal voltage regulation. The compensated-gain control circuit includes an automatic-gain control circuit for generating a variable-gain control signal. The automatic-gain control circuit is formed of a precision rectifier circuit, a filter network, an error amplifier, and an integrator circuit.

  7. Compensated gain control circuit for buck regulator command charge circuit

    DOE Patents [OSTI]

    Barrett, D.M.

    1996-11-05T23:59:59.000Z

    A buck regulator command charge circuit includes a compensated-gain control signal for compensating for changes in the component values in order to achieve optimal voltage regulation. The compensated-gain control circuit includes an automatic-gain control circuit for generating a variable-gain control signal. The automatic-gain control circuit is formed of a precision rectifier circuit, a filter network, an error amplifier, and an integrator circuit. 5 figs.

  8. AC Circuits Magnetic flux

    E-Print Network [OSTI]

    Bertulani, Carlos A. - Department of Physics and Astronomy, Texas A&M University

    , i = 0 At t=, i =/R #12;Charging and discharging RL circuit Now move switch to position b so battery, B, in its central region Inductance, L is defined as Inductance per unit length of a solenoid in a circuit A changing current in a coil generates a self-induced emf, L in the coil Process is called self-induction

  9. Liquid detection circuit

    DOE Patents [OSTI]

    Regan, Thomas O. (North Aurora, IL)

    1987-01-01T23:59:59.000Z

    Herein is a circuit which is capable of detecting the presence of liquids, especially cryogenic liquids, and whose sensor will not overheat in a vacuum. The circuit parameters, however, can be adjusted to work with any liquid over a wide range of temperatures.

  10. Quantum Circuits Architecture

    E-Print Network [OSTI]

    Giulio Chiribella; Giacomo Mauro D'Ariano; Paolo Perinotti

    2007-12-09T23:59:59.000Z

    We present a method for optimizing quantum circuits architecture. The method is based on the notion of "quantum comb", which describes a circuit board in which one can insert variable subcircuits. The method allows one to efficiently address novel kinds of quantum information processing tasks, such as storing-retrieving, and cloning of channels.

  11. Fault Tolerant Quantum Filtering and Fault Detection for Quantum Systems

    E-Print Network [OSTI]

    Qing Gao; Daoyi Dong; Ian R. Petersen

    2015-04-26T23:59:59.000Z

    This paper aims to determine the fault tolerant quantum filter and fault detection equation for a class of open quantum systems coupled to laser fields and subject to stochastic faults. In order to analyze open quantum systems where the system dynamics involve both classical and quantum random variables, a quantum-classical probability space model is developed. Using a reference probability approach, a fault tolerant quantum filter and a fault detection equation are simultaneously derived for this class of open quantum systems. An example of two-level open quantum systems subject to Poisson-type faults is presented to illustrate the proposed method. These results have the potential to lead to a new fault tolerant control theory for quantum systems.

  12. Row fault detection system

    DOE Patents [OSTI]

    Archer, Charles Jens (Rochester, MN); Pinnow, Kurt Walter (Rochester, MN); Ratterman, Joseph D. (Rochester, MN); Smith, Brian Edward (Rochester, MN)

    2010-02-23T23:59:59.000Z

    An apparatus and program product check for nodal faults in a row of nodes by causing each node in the row to concurrently communicate with its adjacent neighbor nodes in the row. The communications are analyzed to determine a presence of a faulty node or connection.

  13. Row fault detection system

    DOE Patents [OSTI]

    Archer, Charles Jens (Rochester, MN); Pinnow, Kurt Walter (Rochester, MN); Ratterman, Joseph D. (Rochester, MN); Smith, Brian Edward (Rochester, MN)

    2012-02-07T23:59:59.000Z

    An apparatus, program product and method check for nodal faults in a row of nodes by causing each node in the row to concurrently communicate with its adjacent neighbor nodes in the row. The communications are analyzed to determine a presence of a faulty node or connection.

  14. Sensor readout detector circuit

    DOE Patents [OSTI]

    Chu, D.D.; Thelen, D.C. Jr.

    1998-08-11T23:59:59.000Z

    A sensor readout detector circuit is disclosed that is capable of detecting sensor signals down to a few nanoamperes or less in a high (microampere) background noise level. The circuit operates at a very low standby power level and is triggerable by a sensor event signal that is above a predetermined threshold level. A plurality of sensor readout detector circuits can be formed on a substrate as an integrated circuit (IC). These circuits can operate to process data from an array of sensors in parallel, with only data from active sensors being processed for digitization and analysis. This allows the IC to operate at a low power level with a high data throughput for the active sensors. The circuit may be used with many different types of sensors, including photodetectors, capacitance sensors, chemically-sensitive sensors or combinations thereof to provide a capability for recording transient events or for recording data for a predetermined period of time following an event trigger. The sensor readout detector circuit has applications for portable or satellite-based sensor systems. 6 figs.

  15. Nonlinear Circuit Analysis An Introduction 1. Why nonlinear circuits?

    E-Print Network [OSTI]

    Hart, Gus

    Nonlinear Circuit Analysis ­ An Introduction 1. Why nonlinear circuits? Electrical devices: the oscillator. 2. What is a nonlinear circuit? It is easy to understand the difference between a linear and a nonlinear circuit by looking at the difference between a linear and a nonlinear equation: y x ¡ 2 (1) y

  16. A Model for Human Interruptability: Experimental Evaluation and Automatic Estimation from Wearable Sensors

    E-Print Network [OSTI]

    A Model for Human Interruptability: Experimental Evaluation and Automatic Estimation from Wearable Sensors Nicky Kern, Stavros Antifakos, Bernt Schiele Perceptual Computing and Computer Vision ETH Zurich sensors. It is scalable for a large number of sensors, contexts, and situations and allows for online

  17. Targeting Mutant (V600E) B-Raf in Melanoma Interrupts Immunoediting of Leukocyte Functions and

    E-Print Network [OSTI]

    Dong, Cheng

    Targeting Mutant (V600E) B-Raf in Melanoma Interrupts Immunoediting of Leukocyte Functions and Melanoma Extravasation Shile Liang, 1 Arati Sharma, 3 Hsin-Hsin Peng, 2 Gavin Robertson, 3 Dermatology, The Pennsylvania State University College of Medicine; 6 The Foreman Foundation for Melanoma

  18. Career Interruptions: how do they impact pension rights? Karine Briard1

    E-Print Network [OSTI]

    Paris-Sud XI, Université de

    their professional trajectory due to unemployment, early retirement, part-time work, or inactivity. Little research is to analyze the question of career interruptions and to evaluate their impact on pension retirement for French, published in "The Geneva Papers on Risk and Insurance 36, 3 (2011) 440-457" #12;Introduction The retirement

  19. Estimating business and residential water supply interruption losses from catastrophic events

    E-Print Network [OSTI]

    Sunding, David

    . In particular, studies have focused on water supply, electric power, and transportation infrastructure [Chang and spatial extent, water supply infrastructure in many urban areas is particularly vulnerable to interruption and residential lifeline users. As a result, the total economic losses caused by infrastructure damage may be much

  20. Giant higher harmonic generation in mesoscopic metal wires and rings interrupted by tunnel junctions

    E-Print Network [OSTI]

    van Oudenaarden, Alexander

    Giant higher harmonic generation in mesoscopic metal wires and rings interrupted by tunnel 5046, 2600 GA Delft, The Netherlands Received 19 December 1997 Higher harmonic generation in mesoscopic is biased with a sinusoidal varying current, we observe giant higher harmon- ics in the conductance

  1. Predictable Interrupt Management for Real Time Kernels over conventional PC Hardware1

    E-Print Network [OSTI]

    Mejia-Alvarez, Pedro

    which this integrated model improves the traditional model. The design of a flexible and portable kernel-CONACyT 42151-Y, and CONACYT 42449-Y Mexico. Abstract In this paper we analyze the traditional model on real-time systems. As a result of this analysis, we propose a model that integrates interrupts

  2. A modified version of BILBO for faster testing of pipeline structure circuits

    E-Print Network [OSTI]

    Lee, Jungran

    1994-01-01T23:59:59.000Z

    are successfully used for detecting single stuck-at faults in a combinational circuit. By adding a few gates to a bidirectional multiple-input signature register, a multifunctional logic subsystem is obtained, which combines the advantages of builtin test and scan...

  3. Superconducting flux flow digital circuits

    DOE Patents [OSTI]

    Hietala, V.M.; Martens, J.S.; Zipperian, T.E.

    1995-02-14T23:59:59.000Z

    A NOR/inverter logic gate circuit and a flip flop circuit implemented with superconducting flux flow transistors (SFFTs) are disclosed. Both circuits comprise two SFFTs with feedback lines. They have extremely low power dissipation, very high switching speeds, and the ability to interface between Josephson junction superconductor circuits and conventional microelectronics. 8 figs.

  4. Stress and fault rock controls on fault zone hydrology, Coso...

    Open Energy Info (EERE)

    rock controls on fault zone hydrology, Coso geothermal field, CA Abstract In crystalline rock of the Coso Geothermal Field, CA, fractures are the primary source of permeability....

  5. Fault interaction near Hollister, California

    SciTech Connect (OSTI)

    Mavko, G.M.

    1982-09-10T23:59:59.000Z

    A numerical model is used to study fault stress slip near Hollister, California. The geometrically complex system of interacting faults, including the San Andreas, Calaveras, Sargent, and Busch faults, is approximated with a two-dimensional distribution of short planar fault segments in an elastic medium. The steady stress and slip rate are simulated by specifying frictional strength and stepping the remote stress ahead in time. The resulting computed fault stress is roughly proportional to the observed spatial density of small earthquakes, suggesting that the distinction between segments characterized by earthquakes and those with aseismic creep results, in part, from geometry. A nonsteady simulation is made by introducing, in addition, stress drops for individual moderate earthquakes. A close fit of observed creep with calculated slip on the Calaveras and San Andreas faults suggests that many changes in creep rate (averaged over several months) are caused by local moderate earthquakes. In particular, a 3-year creep lag preceding the August 6, 1979, Coyote Lake earthquake on the Calaveras fault seems to have been a direct result of the November 28, 1974, Thanksgiving Day earthquake on the Busch fault. Computed lags in slip rate preceding some other moderate earthquakes in the area are also due to earlier earthquakes. Although the response of the upper 1 km of the fault zone may cause some individual creep events and introduce delays in others, the long-term rate appears to reflect deep slip.

  6. Reversing-counterpulse repetitive-pulse inductive storage circuit

    DOE Patents [OSTI]

    Honig, Emanuel M. (Los Alamos, NM)

    1987-01-01T23:59:59.000Z

    A high-power reversing-counterpulse repetitive-pulse inductive storage and transfer circuit includes an opening switch, a main energy storage coil, a counterpulse capacitor and a small inductor. After counterpulsing the opening switch off, the counterpulse capacitor is recharged by the main energy storage coil before the load pulse is initiated. This gives the counterpulse capacitor sufficient energy for the next counterpulse operation, although the polarity of the capacitor's voltage must be reversed before that can occur. By using a current-zero switch as the counterpulse start switch, the capacitor is disconnected from the circuit (with a full charge) when the load pulse is initiated, preventing the capacitor from depleting its energy store by discharging through the load. After the load pulse is terminated by reclosing the main opening switch, the polarity of the counterpulse capacitor voltage is reversed by discharging the capacitor through a small inductor and interrupting the discharge current oscillation at zero current and peak reversed voltage. The circuit enables high-power, high-repetition-rate operation with reusable switches and features total control (pulse-to-pulse) over output pulse initiation, duration, repetition rate, and, to some extent, risetime.

  7. Reversing-counterpulse repetitive-pulse inductive storage circuit

    DOE Patents [OSTI]

    Honig, E.M.

    1987-02-10T23:59:59.000Z

    A high-power reversing-counterpulse repetitive-pulse inductive storage and transfer circuit includes an opening switch, a main energy storage coil, a counterpulse capacitor and a small inductor. After counterpulsing the opening switch off, the counterpulse capacitor is recharged by the main energy storage coil before the load pulse is initiated. This gives the counterpulse capacitor sufficient energy for the next counterpulse operation, although the polarity of the capacitor's voltage must be reversed before that can occur. By using a current-zero switch as the counterpulse start switch, the capacitor is disconnected from the circuit (with a full charge) when the load pulse is initiated, preventing the capacitor from depleting its energy store by discharging through the load. After the load pulse is terminated by reclosing the main opening switch, the polarity of the counterpulse capacitor voltage is reversed by discharging the capacitor through a small inductor and interrupting the discharge current oscillation at zero current and peak reversed voltage. The circuit enables high-power, high-repetition-rate operation with reusable switches and features total control (pulse-to-pulse) over output pulse initiation, duration, repetition rate, and, to some extent, risetime. 10 figs.

  8. Reversing-counterpulse repetitive-pulse inductive storage circuit

    DOE Patents [OSTI]

    Honig, E.M.

    1984-06-05T23:59:59.000Z

    A high power reversing-counterpulse repetitive-pulse inductive storage and transfer circuit includes an opening switch, a main energy storage coil, a counterpulse capacitor and a small inductor. After counterpulsing the opening switch off, the counterpulse capacitor is recharged by the main energy storage coil before the load pulse is initiated. This gives the counterpulse capacitor sufficient energy for the next counterpulse operation, although the polarity of the capacitor's voltage must be reversed before that can occur. By using a current-zero switch as the counterpulse start switch, the capacitor is disconnected from the circuit (with a full charge) when the load pulse is initiated, preventing the capacitor from depleting its energy store by discharging through the load. After the load pulse is terminated by reclosing the main opening switch, the polarity of the counterpulse capacitor voltage is reversed by discharging the capacitor through a small inductor and interrupting the discharge current oscillation at zero current and peak reversed voltage. The circuit enables high-power, high-repetition-rate operation with reusable switches and features total control (pulse-to-pulse) over output pulse initiation, duration, repetition rate, and, to some extent, risetime.

  9. Fault-tolerant quantum computing with color codes

    E-Print Network [OSTI]

    Andrew J. Landahl; Jonas T. Anderson; Patrick R. Rice

    2011-08-29T23:59:59.000Z

    We present and analyze protocols for fault-tolerant quantum computing using color codes. We present circuit-level schemes for extracting the error syndrome of these codes fault-tolerantly. We further present an integer-program-based decoding algorithm for identifying the most likely error given the syndrome. We simulated our syndrome extraction and decoding algorithms against three physically-motivated noise models using Monte Carlo methods, and used the simulations to estimate the corresponding accuracy thresholds for fault-tolerant quantum error correction. We also used a self-avoiding walk analysis to lower-bound the accuracy threshold for two of these noise models. We present and analyze two architectures for fault-tolerantly computing with these codes: one with 2D arrays of qubits are stacked atop each other and one in a single 2D substrate. Our analysis demonstrates that color codes perform slightly better than Kitaev's surface codes when circuit details are ignored. When these details are considered, we estimate that color codes achieve a threshold of 0.082(3)%, which is higher than the threshold of $1.3 \\times 10^{-5}$ achieved by concatenated coding schemes restricted to nearest-neighbor gates in two dimensions but lower than the threshold of 0.75% to 1.1% reported for the Kitaev codes subject to the same restrictions. Finally, because the behavior of our decoder's performance for two of the noise models we consider maps onto an order-disorder phase transition in the three-body random-bond Ising model in 2D and the corresponding random-plaquette gauge model in 3D, our results also answer the Nishimori conjecture for these models in the negative: the statistical-mechanical classical spin systems associated to the 4.8.8 color codes are counterintuitively more ordered at positive temperature than at zero temperature.

  10. Fault current limiter

    DOE Patents [OSTI]

    Darmann, Francis Anthony

    2013-10-08T23:59:59.000Z

    A fault current limiter (FCL) includes a series of high permeability posts for collectively define a core for the FCL. A DC coil, for the purposes of saturating a portion of the high permeability posts, surrounds the complete structure outside of an enclosure in the form of a vessel. The vessel contains a dielectric insulation medium. AC coils, for transporting AC current, are wound on insulating formers and electrically interconnected to each other in a manner such that the senses of the magnetic field produced by each AC coil in the corresponding high permeability core are opposing. There are insulation barriers between phases to improve dielectric withstand properties of the dielectric medium.

  11. Fault Current Limiters

    Broader source: Energy.gov (indexed) [DOE]

    AFDC Printable Version Share this resource Send a link to EERE: Alternative Fuels Data Center Home Page to someone by E-mail Share EERE: Alternative Fuels Data Center Home Page on Facebook Tweet about EERE: Alternative Fuels Data Center Home Page on Twitter Bookmark EERE: Alternative1 First Use of Energy for All Purposes (Fuel and Nonfuel), 2002; Level: National5Sales for4,645 3,625 1,006 492 742Energy Chinaof EnergyImpactOnSTATEMENT OF DAVID GEISEREnergy1DNVDOE'sUAfter 12Fault

  12. Observer-based fault detection for nuclear reactors

    E-Print Network [OSTI]

    Li, Qing, 1972-

    2001-01-01T23:59:59.000Z

    This is a study of fault detection for nuclear reactor systems. Basic concepts are derived from fundamental theories on system observers. Different types of fault- actuator fault, sensor fault, and system dynamics fault ...

  13. Method for preventing bitumen backflow in injection wells when steam injection is interrupted

    SciTech Connect (OSTI)

    Freeman, D.C.; Djabbarah, N.F.

    1990-04-24T23:59:59.000Z

    This patent describes a method for preventing viscous hydrocarbonaceous fluids from backflowing into a well upon interruption of a steamflood. It comprises: detecting a substantial reduction in steam injection pressure in at least one injection well via a pressure sensing device; and causing automatically a pressurized fluid to be injected into the injection well in response to the reduction in pressure which prevents viscous hydrocarbonaceous fluids from backflowing into the injection well.

  14. A hierarchical circuit extractor

    E-Print Network [OSTI]

    Ledbetter, William Burl

    1982-01-01T23:59:59.000Z

    Hierarchical Circuit Extractor (May 1982) William Burl Ledbetter Jr. , B. S. , Texas ASM University Co-Chairmen of Advisory Committee: Dr. Phil S. Noe and Dr. Noel R. Strader This thesi s describes the development of a hierarchical circuit extraction.... ACKNOWLEDGMENTS I would like to express my gratitude to Dr. N. R. Strader for his help in the preparation of this thesis and for the use of his rasteri zer in LEXTRACT. I also thank Dr. P. S. Noe, Dr. P. E. Allen, and Dr. W. M. Lively for serving on my...

  15. Electrical Circuit Tester

    DOE Patents [OSTI]

    Love, Frank (Amarillo, TX)

    2006-04-18T23:59:59.000Z

    An electrical circuit testing device is provided, comprising a case, a digital voltage level testing circuit with a display means, a switch to initiate measurement using the device, a non-shorting switching means for selecting pre-determined electrical wiring configurations to be tested in an outlet, a terminal block, a five-pole electrical plug mounted on the case surface and a set of adapters that can be used for various multiple-pronged electrical outlet configurations for voltages from 100 600 VAC from 50 100 Hz.

  16. Colorado Regional Faults

    SciTech Connect (OSTI)

    Hussein, Khalid

    2012-02-01T23:59:59.000Z

    Citation Information: Originator: Earth Science &Observation Center (ESOC), CIRES, University of Colorado at Boulder Originator: Colorado Geological Survey (CGS) Publication Date: 2012 Title: Regional Faults Edition: First Publication Information: Publication Place: Earth Science & Observation Center, Cooperative Institute for Research in Environmental Science, University of Colorado, Boulder Publisher: Earth Science &Observation Center (ESOC), CIRES, University of Colorado at Boulder Description: This layer contains the regional faults of Colorado Spatial Domain: Extent: Top: 4543192.100000 m Left: 144385.020000 m Right: 754585.020000 m Bottom: 4094592.100000 m Contact Information: Contact Organization: Earth Science &Observation Center (ESOC), CIRES, University of Colorado at Boulder Contact Person: Khalid Hussein Address: CIRES, Ekeley Building Earth Science & Observation Center (ESOC) 216 UCB City: Boulder State: CO Postal Code: 80309-0216 Country: USA Contact Telephone: 303-492-6782 Spatial Reference Information: Coordinate System: Universal Transverse Mercator (UTM) WGS’1984 Zone 13N False Easting: 500000.00000000 False Northing: 0.00000000 Central Meridian: -105.00000000 Scale Factor: 0.99960000 Latitude of Origin: 0.00000000 Linear Unit: Meter Datum: World Geodetic System 1984 (WGS ’984) Prime Meridian: Greenwich Angular Unit: Degree Digital Form: Format Name: Shape file

  17. Synchronized sampling improves fault location

    SciTech Connect (OSTI)

    Kezunovic, M. [Texas A and M Univ., College Station, TX (United States)] [Texas A and M Univ., College Station, TX (United States); Perunicic, B. [Lamar Univ., Beaumont, TX (United States)] [Lamar Univ., Beaumont, TX (United States)

    1995-04-01T23:59:59.000Z

    Transmission line faults must be located accurately to allow maintenance crews to arrive at the scene and repair the faulted section as soon as possible. Rugged terrain and geographical layout cause some sections of power transmission lines to be difficult to reach. In the past, a variety of fault location algorithms were introduced as either an add-on feature in protective relays or stand-alone implementation in fault locators. In both cases, the measurements of current and voltages were taken at one terminal of a transmission line only. Under such conditions, it may become difficult to determine the fault location accurately, since data from other transmission line ends are required for more precise computations. In the absence of data from the other end, existing algorithms have accuracy problems under several circumstances, such as varying switching and loading conditions, fault infeed from the other end, and random value of fault resistance. Most of the one-end algorithms were based on estimation of voltage and current phasors. The need to estimate phasors introduces additional difficulty in high-speed tripping situations where the algorithms may not be fast enough in determining fault location accurately before the current signals disappear due to the relay operation and breaker opening. This article introduces a unique concept of high-speed fault location that can be implemented either as a simple add-on to the digital fault recorders (DFRs) or as a stand-alone new relaying function. This advanced concept is based on the use of voltage and current samples that are synchronously taken at both ends of a transmission line. This sampling technique can be made readily available in some new DFR designs incorporating receivers for accurate sampling clock synchronization using the satellite Global Positioning System (GPS).

  18. Complicating Consent: A Study of the Rhetorical Strategies Employed to Interrupt Rape Myths in the Prosecutor v. Kunarac

    E-Print Network [OSTI]

    Shook, Lindsey

    2010-08-31T23:59:59.000Z

    The justices in the trial of the Prosecutor v. Kunarac were able to interrupt the rape myths that generally exist in rape trials by complicating the notion of consent. In this paper I argue that the justices de-naturalize ...

  19. Circuit breaker lockout device

    DOE Patents [OSTI]

    Kozlowski, Lawrence J. (New Kensington, PA); Shirey, Lawrence A. (North Huntingdon, PA)

    1992-01-01T23:59:59.000Z

    An improved lockout assembly for locking a circuit breaker in a selected off or on position is provided. The lockout assembly includes a lock block and a lock pin. The lock block has a hollow interior which fits over the free end of a switch handle of the circuit breaker. The lock block includes at least one hole that is placed in registration with a hole in the free end of the switch handle. A lock tab on the lock block serves to align and register the respective holes on the lock block and switch handle. A lock pin is inserted through the registered holes and serves to connect the lock block to the switch handle. Once the lock block and the switch handle are connected, the position of the switch handle is prevented from being changed by the lock tab bumping up against a stationary housing portion of the circuit breaker. When the lock pin installed, an apertured-end portion of the lock pin is in registration with another hole on the lock block. Then a special scissors conforming to O.S.H.A. regulations can be installed, with one or more padlocks, on the lockout assembly to prevent removal of the lock pin from the lockout assembly, thereby preventing removal of the lockout assembly from the circuit breaker.

  20. Circuit breaker lockout device

    SciTech Connect (OSTI)

    Kozlowski, L.J.; Shirey, L.A.

    1991-12-31T23:59:59.000Z

    An improved lockout assembly for locking a circuit breaker in a selected off or on position is provided. The lockout assembly includes a lock block and a lock pin. The lock block has a hollow interior which fits over the free end of a switch handle of the circuit breaker. The lock block includes at least one hole that is placed in registration with a hole in the free end of the switch handle. A lock tab on the lock block serves to align and register the respective holes on the lock block and switch handle. A lock pin is inserted through the registered holes and serves to connect the lock block to the switch handle. Once the lock block and the switch handle are connected, the position of the switch handle is prevented from being changed by the lock tab bumping up against a stationary housing portion of the circuit breaker. When the lock pin is installed, an apertured-end portion of the lock pin is in registration with another hole on the lock block. Then a special scissors conforming to O.S.H.A. regulations can be installed, with one or more padlocks, on the lockout assembly to prevent removal of the lock pin from the lockout assembly, thereby preventing removal of the lockout assembly from the circuit breaker.

  1. Circuit breaker lockout device

    DOE Patents [OSTI]

    Kozlowski, L.J.; Shirey, L.A.

    1992-11-24T23:59:59.000Z

    An improved lockout assembly for locking a circuit breaker in a selected off or on position is provided. The lockout assembly includes a lock block and a lock pin. The lock block has a hollow interior which fits over the free end of a switch handle of the circuit breaker. The lock block includes at least one hole that is placed in registration with a hole in the free end of the switch handle. A lock tab on the lock block serves to align and register the respective holes on the lock block and switch handle. A lock pin is inserted through the registered holes and serves to connect the lock block to the switch handle. Once the lock block and the switch handle are connected, the position of the switch handle is prevented from being changed by the lock tab bumping up against a stationary housing portion of the circuit breaker. When the lock pin installed, an apertured-end portion of the lock pin is in registration with another hole on the lock block. Then a special scissors conforming to O.S.H.A. regulations can be installed, with one or more padlocks, on the lockout assembly to prevent removal of the lock pin from the lockout assembly, thereby preventing removal of the lockout assembly from the circuit breaker. 2 figs.

  2. Bioluminescent bioreporter integrated circuit

    DOE Patents [OSTI]

    Simpson, Michael L. (Knoxville, TN); Sayler, Gary S. (Blaine, TN); Paulus, Michael J. (Knoxville, TN)

    2000-01-01T23:59:59.000Z

    Disclosed are monolithic bioelectronic devices comprising a bioreporter and an OASIC. These bioluminescent bioreporter integrated circuit are useful in detecting substances such as pollutants, explosives, and heavy-metals residing in inhospitable areas such as groundwater, industrial process vessels, and battlefields. Also disclosed are methods and apparatus for environmental pollutant detection, oil exploration, drug discovery, industrial process control, and hazardous chemical monitoring.

  3. Submission to International Journal of Control, Automation and Systems Vol. , No. , 1 Robust Fault Detection and Estimation for Descriptor Systems

    E-Print Network [OSTI]

    Paris-Sud XI, Université de

    in a large class of technical process like mechanical, electrical and chemical systems [3,17]. With regard of the proposed fault detection and estimation method is successfully applied to an electrical circuit. Keywords lead to significant performance degradation, serious system damages and even loss of human life

  4. Methods of fabricating applique circuits

    DOE Patents [OSTI]

    Dimos, Duane B. (Albuquerque, NM); Garino, Terry J. (Albuquerque, NM)

    1999-09-14T23:59:59.000Z

    Applique circuits suitable for advanced packaging applications are introduced. These structures are particularly suited for the simple integration of large amounts (many nanoFarads) of capacitance into conventional integrated circuit and multichip packaging technology. In operation, applique circuits are bonded to the integrated circuit or other appropriate structure at the point where the capacitance is required, thereby minimizing the effects of parasitic coupling. An immediate application is to problems of noise reduction and control in modern high-frequency circuitry.

  5. ECE 202: Circuit Theory Applications

    E-Print Network [OSTI]

    Schumacher, Russ

    : - Cadence - MATLAB IN OUT - Can analyze source-free RL, RC, and RLC circuits - Can calculate step response Numbers Algebra DC Circuit Analysis - Laplace transform - Bode plots - Complex response - Can calculate Filter Analysis Frequency Response and Filters AC Power Analysis AC Circuit Analysis Concepts

  6. High voltage MOSFET switching circuit

    DOE Patents [OSTI]

    McEwan, T.E.

    1994-07-26T23:59:59.000Z

    The problem of source lead inductance in a MOSFET switching circuit is compensated for by adding an inductor to the gate circuit. The gate circuit inductor produces an inductive spike which counters the source lead inductive drop to produce a rectangular drive voltage waveform at the internal gate-source terminals of the MOSFET. 2 figs.

  7. High voltage MOSFET switching circuit

    DOE Patents [OSTI]

    McEwan, Thomas E. (Livermore, CA)

    1994-01-01T23:59:59.000Z

    The problem of source lead inductance in a MOSFET switching circuit is compensated for by adding an inductor to the gate circuit. The gate circuit inductor produces an inductive spike which counters the source lead inductive drop to produce a rectangular drive voltage waveform at the internal gate-source terminals of the MOSFET.

  8. Automated Fault Location In Smart Distribution Systems 

    E-Print Network [OSTI]

    Lotfifard, Saeed

    2012-10-19T23:59:59.000Z

    ............................................................................................................................ 88 x LIST OF FIGURES Page Figure 1 Multiple possible fault location estimation for a fault at node A ........................ 7 Figure 2 Simple faulted network model [1] © [2011] IEEE ............................................ 40 Figure 3... Types C and D voltage sags for different phases [51] © [2003] IEEE .............. 42 Figure 4 Rf estimation procedure [1] © [2011] IEEE ...................................................... 45 Figure 5 Flow chart of the fault location algorithm [1...

  9. Hot Pot Detail - Evidence of Quaternary Faulting

    DOE Data Explorer [Office of Scientific and Technical Information (OSTI)]

    Lane, Michael

    Compilation of published data, field observations and photo interpretation relevant to Quaternary faulting at Hot Pot.

  10. Hot Pot Detail - Evidence of Quaternary Faulting

    SciTech Connect (OSTI)

    Lane, Michael

    2013-06-27T23:59:59.000Z

    Compilation of published data, field observations and photo interpretation relevant to Quaternary faulting at Hot Pot.

  11. Internal structure of the Kern Canyon Fault, California: a deeply exhumed strike-slip fault

    E-Print Network [OSTI]

    Neal, Leslie Ann

    2002-01-01T23:59:59.000Z

    Deformation and mineral alteration adjacent to a 2 km long segment of the Kern Canyon fault near Lake Isabella, California are studied to characterize the internal structure of the fault zone and to understand the development of fault structure...

  12. Variable timing circuit for motive power battery chargers

    SciTech Connect (OSTI)

    Lambert, F.J.; Bosack, D.J.; Johansen, D.K.

    1984-03-27T23:59:59.000Z

    A timing circuit for charging motive power batteries. The timing control circuit provides different times of charge in accordance with the time at which a predetermined voltage/current state of the battery is achieved. Control circuit cooperates with a controller in causing termination of the charging operation immediately upon reaching of the voltage/current state if this occurs in a first time slot of an initial control time period. The timing circuit provides an automatic finish time period of charge if the battery reaches the predetermined voltage/current state at some time during the initial control time period. The control includes a switch permitting the user to cause an automatic additional amount of charging upon completion of the normal charging cycle effected by the control, such as for effecting a weekend charge. The control further includes structure for terminating the charging operation in the event the battery being charged does not reach the predetermined voltage/current state at the end of a preselected maximum time. A signal light signals such a fault condition in the charging operation.

  13. Electric Power Interruption Cost Estimates for Individual Industries, Sectors, and U.S. Economy

    SciTech Connect (OSTI)

    Balducci, Patrick J.; Roop, Joseph M.; Schienbein, Lawrence A.; DeSteese, John G.; Weimar, Mark R.

    2002-02-27T23:59:59.000Z

    During the last 20 years, utilities and researchers have begun to understand the value in the collection and analysis of interruption cost data. The continued investigation of the monetary impact of power outages will facilitate the advancement of the analytical methods used to measure the costs and benefits from the perspective of the energy consumer. More in-depth analysis may be warranted because of the privatization and deregulation of power utilities, price instability in certain regions of the U.S. and the continued evolution of alternative auxiliary power systems.

  14. Fault-tolerant rotary actuator

    SciTech Connect (OSTI)

    Tesar, Delbert

    2006-10-17T23:59:59.000Z

    A fault-tolerant actuator module, in a single containment shell, containing two actuator subsystems that are either asymmetrically or symmetrically laid out is provided. Fault tolerance in the actuators of the present invention is achieved by the employment of dual sets of equal resources. Dual resources are integrated into single modules, with each having the external appearance and functionality of a single set of resources.

  15. Development of Characterization Technology for Fault Zone Hydrology

    E-Print Network [OSTI]

    Karasaki, Kenzi

    2010-01-01T23:59:59.000Z

    TECHNOLOGY FOR FAULT ZONE HYDROLOGY Kenzi Karasaki Lawrencefor characterizing the hydrology of fault zones, recognizingstructure of faults to hydrology, that it still may be

  16. active fault diagnosis: Topics by E-print Network

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Harrold, Mary Jean 453 Fault Tolerant Control with Additive Compensation for Faults in an Automotive Damper Physics Websites Summary: Fault Tolerant Control with Additive...

  17. Solid-state circuit breaker with current-limiting characteristic using a superconducting coil

    DOE Patents [OSTI]

    Boenig, H.J.

    1982-08-16T23:59:59.000Z

    A thyristor bridge interposes an ac source and a load. A series connected DC source and superconducting coil within the bridge biases the thyristors thereof so as to permit bidirectional ac current flow therethrough under normal operating conditions. Upon a fault condition a control circuit triggers the thyristors so as to reduce ac current flow therethrough to zero in less than two eyeles and to open the bridge thereafter. Upon a temporary overload condition the control circuit triggers the thyristors so as to limit ac current flow therethrough to an acceptable level.

  18. Base drive circuit

    DOE Patents [OSTI]

    Lange, A.C.

    1995-04-04T23:59:59.000Z

    An improved base drive circuit having a level shifter for providing bistable input signals to a pair of non-linear delays. The non-linear delays provide gate control to a corresponding pair of field effect transistors through a corresponding pair of buffer components. The non-linear delays provide delayed turn-on for each of the field effect transistors while an associated pair of transistors shunt the non-linear delays during turn-off of the associated field effect transistor. 2 figures.

  19. Base drive circuit

    DOE Patents [OSTI]

    Lange, Arnold C. (Livermore, CA)

    1995-01-01T23:59:59.000Z

    An improved base drive circuit (10) having a level shifter (24) for providing bistable input signals to a pair of non-linear delays (30, 32). The non-linear delays (30, 32) provide gate control to a corresponding pair of field effect transistors (100, 106) through a corresponding pair of buffer components (88, 94). The non-linear delays (30, 32) provide delayed turn-on for each of the field effect transistors (100, 106) while an associated pair of transistors (72, 80) shunt the non-linear delays (30, 32) during turn-off of the associated field effect transistor (100, 106).

  20. Threshold voltage extraction circuit

    E-Print Network [OSTI]

    Hoon, Siew Kuok

    2000-01-01T23:59:59.000Z

    to that of the saturation method. However, instead of fixing Vos ? Vos, the drain current is measured as a function of Vos while Vns is fixed at a constant low voltage of 100mV to ensure operation in the linear MOSFET region. Neglecting channel length modulation effect... transistors are layout next to the DUT of the NMOS and PMOS Vr extraction circuits respectively for extraction of Vr via graphical means. GRAPHICAL METHOD OF THE THRESHOLD-VOLTAGE MEASUREMENT Using the graphical method, the characteristics of 4n versus Vos...

  1. Condition Assessment and Fault Prognostics of Microelectromechanical Systems

    E-Print Network [OSTI]

    Paris-Sud XI, Université de

    monitoring, Condition assessment, Fault detection, Fault diagnostics, Fault prognostics. Corresponding, batteries, etc.) to complete machines (wind turbines, electrical motors, machining tools, etc.). SeveralCondition Assessment and Fault Prognostics of Microelectromechanical Systems K. Medjaher , H. Skima

  2. Enhancing the quantum efficiency of InGaN yellow-green light-emitting diodes by growth interruption

    SciTech Connect (OSTI)

    Du, Chunhua; Ma, Ziguang; Zhou, Junming; Lu, Taiping; Jiang, Yang; Zuo, Peng; Jia, Haiqiang; Chen, Hong, E-mail: hchen@iphy.ac.cn [Key Laboratory for Renewable Energy, Chinese Academy of Sciences, Beijing Key Laboratory for New Energy Materials and Devices, Beijing National Laboratory for Condense Matter Physics, Institute of Physics, Chinese Academy of Sciences, Beijing 100190 (China)

    2014-08-18T23:59:59.000Z

    We studied the effect of multiple interruptions during the quantum well growth on emission-efficiency enhancement of InGaN-based yellow-green light emitting diodes on c-plane sapphire substrate. The output power and dominant wavelength at 20?mA are 0.24 mW and 556.3?nm. High resolution x-ray diffraction, photoluminescence, and electroluminescence measurements demonstrate that efficiency enhancement could be partially attributed to crystal quality improvement of the active region resulted from reduced In clusters and relevant defects on the surface of InGaN layer by introducing interruptions. The less tilted energy band in the quantum well is also caused by the decrease of In-content gradient along c-axis resulted from In segregation during the interruptions, which increases spatial overlap of electron-hole wavefunction and thus the internal quantum efficiency. The latter also leads to smaller blueshift of dominant wavelength with current increasing.

  3. Thvenin's Theorem Linear two-terminal circuit

    E-Print Network [OSTI]

    Kozick, Richard J.

    Thévenin's Theorem Linear two-terminal circuit can be replaced by an equivalent circuit composed at terminals with allResistance at terminals with all independent circuit sources set to zero #12;Norton's Theorem Linear two-terminal circuit can be replaced by an equivalentbe replaced by an equivalent circuit

  4. Jitter compensation circuit

    DOE Patents [OSTI]

    Sullivan, J.S.; Ball, D.G.

    1997-09-09T23:59:59.000Z

    The instantaneous V{sub co} signal on a charging capacitor is sampled and the charge voltage on capacitor C{sub o} is captured just prior to its discharge into the first stage of magnetic modulator. The captured signal is applied to an averaging circuit with a long time constant and to the positive input terminal of a differential amplifier. The averaged V{sub co} signal is split between a gain stage (G = 0.975) and a feedback stage that determines the slope of the voltage ramp applied to the high speed comparator. The 97.5% portion of the averaged V{sub co} signal is applied to the negative input of a differential amplifier gain stage (G = 10). The differential amplifier produces an error signal by subtracting 97.5% of the averaged V{sub co} signal from the instantaneous value of sampled V{sub co} signal and multiplying the difference by ten. The resulting error signal is applied to the positive input of a high speed comparator. The error signal is then compared to a voltage ramp that is proportional to the averaged V{sub co} values squared divided by the total volt-second product of the magnetic compression circuit. 11 figs.

  5. Jitter compensation circuit

    DOE Patents [OSTI]

    Sullivan, James S. (Livermore, CA); Ball, Don G. (Livermore, CA)

    1997-01-01T23:59:59.000Z

    The instantaneous V.sub.co signal on a charging capacitor is sampled and the charge voltage on capacitor C.sub.o is captured just prior to its discharge into the first stage of magnetic modulator. The captured signal is applied to an averaging circuit with a long time constant and to the positive input terminal of a differential amplifier. The averaged V.sub. co signal is split between a gain stage (G=0.975) and a feedback stage that determines the slope of the voltage ramp applied to the high speed comparator. The 97.5% portion of the averaged V.sub.co signal is applied to the negative input of a differential amplifier gain stage (G=10). The differential amplifier produces an error signal by subtracting 97.5% of the averaged V.sub.co signal from the instantaneous value of sampled V.sub.co signal and multiplying the difference by ten. The resulting error signal is applied to the positive input of a high speed comparator. The error signal is then compared to a voltage ramp that is proportional to the averaged V.sub.co values squared divided by the total volt-second product of the magnetic compression circuit.

  6. Sensor Fault Detection and Isolation System

    E-Print Network [OSTI]

    Yang, Cheng-Ken

    2014-08-01T23:59:59.000Z

    The purpose of this research is to develop a Fault Detection and Isolation (FDI) system which is capable to diagnosis multiple sensor faults in nonlinear cases. In order to lead this study closer to real world applications in oil industries...

  7. A Rectilinear-Monotone Polygonal Fault Block Model for Fault-Tolerant Minimal Routing

    E-Print Network [OSTI]

    Wang, Dajin

    ]. In rectangular model, all faulty nodes are grouped in dis- jointed, rectangular areas, called fault blocksA Rectilinear-Monotone Polygonal Fault Block Model for Fault-Tolerant Minimal Routing in Mesh Dajin Wang, Member, IEEE Abstract--We propose a new fault block model, Minimal-Connected-Component (MCC

  8. Thvenin Emitter Circuit The Thvenin equivalent circuit seen looking into the emitter is useful in calculating

    E-Print Network [OSTI]

    Leach Jr.,W. Marshall

    voltage ve(oc) to the short-circuit emitter current. The circuit for calculating the short-circuit currentThévenin Emitter Circuit The Thévenin equivalent circuit seen looking into the emitter is useful. With the emitter open circuited, we denote the emitter voltage by ve(oc). The voltage source in the Thévenin

  9. Using Fault Model Enforcement to Improve Availability

    E-Print Network [OSTI]

    instead that a new approach, called fault model enforcement, that maps actual faults to expected faults on a constellation of interconnected systems--a typical example is cluster-based systems [4]. Traditional database centers around a set of closely guarded racks and data closets woven together by intricate networks

  10. Using Fault Model Enforcement to Improve Availability

    E-Print Network [OSTI]

    Martin, Richard P.

    that a new approach, called fault model enforcement, that maps actual faults to expected faults on a constellation of interconnected systems--a typical example is cluster-based systems [4]. Traditional database centers around a set of closely guarded racks and data closets woven together by intricate networks

  11. Demultiplexer circuit for neural stimulation

    DOE Patents [OSTI]

    Wessendorf, Kurt O; Okandan, Murat; Pearson, Sean

    2012-10-09T23:59:59.000Z

    A demultiplexer circuit is disclosed which can be used with a conventional neural stimulator to extend the number of electrodes which can be activated. The demultiplexer circuit, which is formed on a semiconductor substrate containing a power supply that provides all the dc electrical power for operation of the circuit, includes digital latches that receive and store addressing information from the neural stimulator one bit at a time. This addressing information is used to program one or more 1:2.sup.N demultiplexers in the demultiplexer circuit which then route neural stimulation signals from the neural stimulator to an electrode array which is connected to the outputs of the 1:2.sup.N demultiplexer. The demultiplexer circuit allows the number of individual electrodes in the electrode array to be increased by a factor of 2.sup.N with N generally being in a range of 2-4.

  12. Quantum Computation Beyond the Circuit Model

    E-Print Network [OSTI]

    Stephen P. Jordan

    2008-09-13T23:59:59.000Z

    The quantum circuit model is the most widely used model of quantum computation. It provides both a framework for formulating quantum algorithms and an architecture for the physical construction of quantum computers. However, several other models of quantum computation exist which provide useful alternative frameworks for both discovering new quantum algorithms and devising new physical implementations of quantum computers. In this thesis, I first present necessary background material for a general physics audience and discuss existing models of quantum computation. Then, I present three results relating to various models of quantum computation: a scheme for improving the intrinsic fault tolerance of adiabatic quantum computers using quantum error detecting codes, a proof that a certain problem of estimating Jones polynomials is complete for the one clean qubit complexity class, and a generalization of perturbative gadgets which allows k-body interactions to be directly simulated using 2-body interactions. Lastly, I discuss general principles regarding quantum computation that I learned in the course of my research, and using these principles I propose directions for future research.

  13. Photoconductive circuit element reflectometer

    DOE Patents [OSTI]

    Rauscher, Christen (Alexandria, VA)

    1990-01-01T23:59:59.000Z

    A photoconductive reflectometer for characterizing semiconductor devices at millimeter wavelength frequencies where a first photoconductive circuit element (PCE) is biased by a direct current voltage source and produces short electrical pulses when excited into conductance by short first laser light pulses. The electrical pulses are electronically conditioned to improve the frequency related amplitude characteristics of the pulses which thereafter propagate along a transmission line to a device under test. Second PCEs are connected along the transmission line to sample the signals on the transmission line when excited into conductance by short second laser light pulses, spaced apart in time a variable period from the first laser light pulses. Electronic filters connected to each of the second PCEs act as low-pass filters and remove parasitic interference from the sampled signals and output the sampled signals in the form of slowed-motion images of the signals on the transmission line.

  14. Photoconductive circuit element reflectometer

    DOE Patents [OSTI]

    Rauscher, C.

    1987-12-07T23:59:59.000Z

    A photoconductive reflectometer for characterizing semiconductor devices at millimeter wavelength frequencies where a first photoconductive circuit element (PCE) is biased by a direct current voltage source and produces short electrical pulses when excited into conductance by short first laser light pulses. The electrical pulses are electronically conditioned to improve the frequency related amplitude characteristics of the pulses which thereafter propagate along a transmission line to a device under test. Second PCEs are connected along the transmission line to sample the signals on the transmission line when excited into conductance by short second laser light pulses, spaced apart in time a determinable period from the first laser light pulses. Electronic filters connected to each of the second PCEs act as low-pass filters and remove parasitic interference from the sampled signals and output the sampled signals in the form of slowed-motion images of the signals on the transmission line. 4 figs.

  15. Electrolytic Hydrogen Evolution in DMFCs Induced by Oxygen Interruptions and Its Effect on Cell Performance

    E-Print Network [OSTI]

    Zhao, Tianshou

    - tem optimization and reliable operation of the fuel cell. Gas evolu- tion on the anode of a DMFC under flow field of a liquid-feed direct methanol fuel cell DMFC under open-circuit conditions after methanol fuel cells DMFCs are considered as one of the most competitive candidates for the future power

  16. Cell boundary fault detection system

    DOE Patents [OSTI]

    Archer, Charles Jens (Rochester, MN); Pinnow, Kurt Walter (Rochester, MN); Ratterman, Joseph D. (Rochester, MN); Smith, Brian Edward (Rochester, MN)

    2011-04-19T23:59:59.000Z

    An apparatus and program product determine a nodal fault along the boundary, or face, of a computing cell. Nodes on adjacent cell boundaries communicate with each other, and the communications are analyzed to determine if a node or connection is faulty.

  17. Software Fault Diagnosis Peter Zoeteweij

    E-Print Network [OSTI]

    Zoeteweij, Peter

    Lab, Faculty of Electrical Engineering, Mathematics, and Computer Science, Delft University-to-day basis is constantly growing. Combined with a practically constant rate of faults per line of code in the software development cycle, which aim at exposing such discrepancies. In this context, automated diagnosis

  18. Development of a bridge fault extractor tool

    E-Print Network [OSTI]

    Bhat, Nandan D.

    2005-02-17T23:59:59.000Z

    as interlayer faults. An example of an intralayer fault is a bridge between two adjacent metal1 lines. An example of an interlayer fault is a short between overlapping polysilicon and metal1 lines. The rest of this thesis is organized as follows: Chapter 2... between two adjacent 6 metal1 lines. An example of an interlayer fault is a short between overlapping polysilicon and metal1 lines. A recent survey of fault extractors describes their different features [15]. Some tools such as VLASIC [16] attempt...

  19. The Kinematic Wave Equation (KWE) In Tuesday's interrupted lecture we derived the Kinematic Wave Equation (KWE) for a density

    E-Print Network [OSTI]

    Gibbon, J. D.

    The Kinematic Wave Equation (KWE) In Tuesday's interrupted lecture we derived the Kinematic Wave refer to partial derivatives. Kinematic waves occur when we take Q = Q(), in which case t + c()x = 0 (2) where the propagation velocity is c() = dQ/d. (2) is called the Kinematic Wave Equation (KWE). We wish

  20. Counterpulse railgun energy recovery circuit

    DOE Patents [OSTI]

    Honig, E.M.

    1984-09-28T23:59:59.000Z

    The invention presented relates to a high-power pulsing circuit and more particularly to a repetitive pulse inductive energy storage and transfer circuit for an electromagnetic launcher. In an electromagnetic launcher such as a railgun for propelling a projectile at high velocity, a counterpulse energy recovery circuit is employed to transfer stored inductive energy from a source inductor to the railgun inductance to propel the projectile down the railgun. Switching circuitry and an energy transfer capacitor are used to switch the energy back to the source inductor in readiness for a repetitive projectile propelling cycle.

  1. Overpulse railgun energy recovery circuit

    DOE Patents [OSTI]

    Honig, E.M.

    1984-09-28T23:59:59.000Z

    The invention presented relates to a high-power pulsing circuit and more particularly to a repetitive pulse inductive energy storage and transfer circuit for an electromagnetic launcher. In an electromagnetic launcher such as a railgun for propelling a projectile at high velocity, an overpulse energy recovery circuit is employed to transfer stored inductive energy from a source inductor to the railgun inductance to propel the projectile down the railgun. Switching circuitry and an energy transfer capacitor are used to switch the energy back to the source inductor in readiness for a repetitive projectile propelling cycle.

  2. Hygroscopic Fine Mode Particle Deposition on Electronic Circuits and Resulting Degradation of Circuit Performance: An Experimental Study

    E-Print Network [OSTI]

    Litvak, A.

    2011-01-01T23:59:59.000Z

    electronic components, circuits, and spacing between adjacent conductors continues to get smaller ; degradation of circuit reliability

  3. 916 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 16, NO. 8, AUGUST 1997 On the Quality of Accumulator-Based

    E-Print Network [OSTI]

    Chakrabarty, Krishnendu

    , AUGUST 1997 On the Quality of Accumulator-Based Compaction of Test Responses Krishnendu Chakrabarty, Member, IEEE, and John P. Hayes, Fellow, IEEE Abstract--The accumulator-based compaction (ABC) technique uses an accumulator to generate a composite fault signature for a circuit under test. The error

  4. The detection of high impedance faults using random fault behavior

    E-Print Network [OSTI]

    Carswell, Patrick Wayne

    1988-01-01T23:59:59.000Z

    In response to an Electric Power Research Institute (EPRI) request for pro- posed solutions for the detection of high impedance faults, the Hughes Aircraft Corporation developed a detection technique based solely on the level of the third harmonic current... for proposed solutions from EPRI that brought the Hughes technique, Power Technologies Incorporated (PTI) proposed a technique which statistically monitors the first, third, and fifth harmonics of current to make a, determination as to the presence of a high...

  5. Restoration and testing of an HTS fault current controller

    SciTech Connect (OSTI)

    Waynert, J. A. (Joseph A.); Boenig, H. (Heinrich E.); Mielke, C. H. (Charles H.); Willis, J. O. (Jeffrey O.); Burley, B. L. (Burt L.)

    2002-01-01T23:59:59.000Z

    A three-phase, 1200 A, 12.5 kV fault current controller using three HTS 4 mH coils, was built by industry and tested in 1999 at the Center Substation of Southern California Edison in Norwalk, CA. During the testing, it appeared that each of the three single-phase units had experienced a voltage breakdown, one externally and two internally. Los Alamos National Laboratory (LANL) was asked by DOE to restore the operation of the fault current controller provided the HTS coils had not been damaged during the initial substation tests. When the internally-failed coil vacuum vessels were opened it became evident that in these two vessels, a flashover had occurred at the high voltage bus section leading to the terminals of the superconducting coil. An investigation into the failure mechanism resulted in six possible causes for the flashover. Based on these causes, the high voltage bus was completely redesigned. Single-phase tests were successfully performed on the modified unit at a 13.7 kV LANL substation. This paper presents the postulated voltage flashover failure mechanisms, the new high voltage bus design which mitigates the failure mechanisms, the sequence of tests used to validate the new design, and finally, the results of variable load and short-circuit tests with the single-phase unit operating on the LANL 13.7 kV substation.

  6. Development of secondary faults between en echelon, oblique-slip faults: examples from basement controlled, small-fault systems in the Llano Uplift of central Texas

    E-Print Network [OSTI]

    Hedgcoxe, Howard Reiffert

    1987-01-01T23:59:59.000Z

    correspond to the NE trending set of faults and the secondary antithetic faults corre- spond to the N to NNE set (Figure 12). Fractures, represented by the dashed lines in Figure 12, occur in direct association with the primary and secondary faults...DEVELOPMENT OF SECONDARY FAULTS BETWEEN EN ECHELON, OBLIQUE-SLIP FAULTS: EXAMPLES FROM BASEMENT CONTROLLED, SMALL-FAULT SYSTEMS IN THE LLANO UPLIFT OF CENTRAL TEXAS A Thesis by HOWARD REIFFERT HEDGCOXE Submitted to the Graduate College...

  7. Tunable circuit for tunable capacitor devices

    SciTech Connect (OSTI)

    Rivkina, Tatiana; Ginley, David S.

    2006-09-19T23:59:59.000Z

    A tunable circuit (10) for a capacitively tunable capacitor device (12) is provided. The tunable circuit (10) comprises a tunable circuit element (14) and a non-tunable dielectric element (16) coupled to the tunable circuit element (16). A tunable capacitor device (12) and a method for increasing the figure of merit in a tunable capacitor device (12) are also provided.

  8. Electronic circuit implementation of chaos synchronization

    E-Print Network [OSTI]

    Ravi Ranjan; Shivshankar Mishra; Suneel Madhekar

    2012-07-20T23:59:59.000Z

    In this paper, an electronic circuit implementation of a robustly chaotic two-dimensional map is presented. Two such electronic circuits are realized. One of the circuits is configured as the driver and the other circuit is configured as the driven system. Synchronization of chaos between the driver and the driven system is demonstrated.

  9. NPTEL Syllabus Basic Electrical Circuits -Video course

    E-Print Network [OSTI]

    Krishnapura, Nagendra

    with an introduction to basic linear elements used in electrical circuits. Mesh and node analysis for systematic analysis of large circuits will be studied. Fundamental circuit theorems and their use in analysis steady state analysis for simple analysis of such circuits will be studied. The concepts of power

  10. Reverse engineering of integrated circuits

    DOE Patents [OSTI]

    Chisholm, Gregory H. (Shorewood, IL); Eckmann, Steven T. (Colorado Springs, CO); Lain, Christopher M. (Pittsburgh, PA); Veroff, Robert L. (Albuquerque, NM)

    2003-01-01T23:59:59.000Z

    Software and a method therein to analyze circuits. The software comprises several tools, each of which perform particular functions in the Reverse Engineering process. The analyst, through a standard interface, directs each tool to the portion of the task to which it is most well suited, rendering previously intractable problems solvable. The tools are generally used iteratively to produce a successively more abstract picture of a circuit, about which incomplete a priori knowledge exists.

  11. Fault Current Contribution from Single-Phase PV Inverters

    SciTech Connect (OSTI)

    Keller, J.; Kroposki, B.; Bravo, R.; Robles, S.

    2011-01-01T23:59:59.000Z

    A significant increase in photovoltaic (PV) system installations is expected to come on line in the near future and as the penetration level of PV increases, the effect of PV may no longer be considered minimal. One of the most important attributions of additional PV is what effect this may have on protection systems. Protection engineers design protection systems to safely eliminate faults from the electric power system. One of the new technologies recently introduced into the electric power system are distributed energy resources (DER). Currently, inverter-based DER contributes very little to the power balance on all but a few utility distribution systems. As DER become prevalent in the distribution system, equipment rating capability and coordination of protection systems merit a closer investigation. A collaborative research effort between the National Renewable Energy Laboratory (NREL) and Southern California Edison (SCE) involved laboratory short-circuit testing single-phase (240 VAC) residential type (between 1.5 and 7kW) inverters. This paper will reveal test results obtained from these short-circuit tests.

  12. Fault tolerant, low voltage SRAM design

    E-Print Network [OSTI]

    Sinangil, Yildiz

    2010-01-01T23:59:59.000Z

    Scaling of process technologies has made power management a significant concern for circuit designers. Moreover, denser integration and shrinking geometries also have a negative impact on circuit reliability. Therefore, ...

  13. Fault prophet : a fault injection tool for large scale computer systems

    E-Print Network [OSTI]

    Tchwella, Tal

    2014-01-01T23:59:59.000Z

    In this thesis, I designed and implemented a fault injection tool, to study the impact of soft errors for large scale systems. Fault injection is used as a mechanism to simulate soft errors, measure the output variability ...

  14. Collateral damage: Evolution with displacement of fracture distribution and secondary fault strands in fault damage zones

    E-Print Network [OSTI]

    Savage, Heather M.; Brodsky, Emily E.

    2011-01-01T23:59:59.000Z

    E. McCallum (1999), Reservoir damage around faults: OutcropSkar (2005), Controls on damage zone asymmetry of a normal2007), The evolution of the damage zone with fault growth in

  15. The effects of lithology and initial fault angle in physical models of fault-propagation folds

    E-Print Network [OSTI]

    McLain, Christopher Thomas

    2001-01-01T23:59:59.000Z

    Experimentally deformed physical rock models are used to examine the effects of changing mechanical stratigraphy and initial fault angle on the development of fault-propagation folds over a flat-ramp-flat thrust geometry. This study also...

  16. Collateral damage: Evolution with displacement of fracture distribution and secondary fault strands in fault damage zones

    E-Print Network [OSTI]

    Savage, Heather M.; Brodsky, Emily E.

    2011-01-01T23:59:59.000Z

    8 m fault 14 m fault Lonewolf Wadi Araba Carboneras Caletasiltstone, conglomerate Wadi As Sir Limestone gneiss schistFaulkner et al. , 2003], and Wadi Araba [Du Bernard et al. ,

  17. Fault-tolerant dynamic task graph scheduling

    SciTech Connect (OSTI)

    Kurt, Mehmet C.; Krishnamoorthy, Sriram; Agrawal, Kunal; Agrawal, Gagan

    2014-11-16T23:59:59.000Z

    In this paper, we present an approach to fault tolerant execution of dynamic task graphs scheduled using work stealing. In particular, we focus on selective and localized recovery of tasks in the presence of soft faults. We elicit from the user the basic task graph structure in terms of successor and predecessor relationships. The work stealing-based algorithm to schedule such a task graph is augmented to enable recovery when the data and meta-data associated with a task get corrupted. We use this redundancy, and the knowledge of the task graph structure, to selectively recover from faults with low space and time overheads. We show that the fault tolerant design retains the essential properties of the underlying work stealing-based task scheduling algorithm, and that the fault tolerant execution is asymptotically optimal when task re-execution is taken into account. Experimental evaluation demonstrates the low cost of recovery under various fault scenarios.

  18. Automated Fault Location In Smart Distribution Systems

    E-Print Network [OSTI]

    Lotfifard, Saeed

    2012-10-19T23:59:59.000Z

    Quality Meters (PQM), are installed to capture harmonics and certain disturbances for analyzing the power quality indices. Digital Protective Relays are utilized to detect occurrence of the faults and isolate faulted section as fast as possible. Digital... Protective Relays) use synchronous methods [28]. Therefore, if the available data is provided by RTUs, fault location methods that operate based on direct comparison of the input samples cannot be 17 utilized. However, if the data could be gathered from...

  19. Detachment Faulting & Geothermal Resources - Pearl Hot Spring...

    Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

    Faulting & Geothermal Resources - Pearl Hot Spring, NV Conducting a 3D Converted Shear Wave Project to Reduce Exploration Risk at Wister, CA Crump Geyser: High Precision...

  20. Towards Fault-Tolerant Digital Microfluidic Lab-on-Chip: Defects, Fault Modeling, Testing, and Reconfiguration

    E-Print Network [OSTI]

    Chakrabarty, Krishnendu

    Towards Fault-Tolerant Digital Microfluidic Lab-on-Chip: Defects, Fault Modeling, Testing, NC 27708, USA Abstract Dependability is an important attribute for microfluidic lab-on-chip devices microfluidic lab-on-chip systems. Defects are related to logical fault models that can be viewed not only

  1. Contribution of Identified Active Faults to Near Fault Seismic Hazard in the Flinders Ranges

    E-Print Network [OSTI]

    Sandiford, Mike

    Somerville1 , Peggy Quijada1 , Hong Kie Thio1 , Mike Sandiford2 and Mark Quigley2 1. URS Corporation estimates of fault slip rate from Quigley et al. (2006) to quantify the seismic activity rate on the faults of these models was used in conjunction with the active fault model. Quigley et al. (2006) identified a system

  2. A fault location approach for fuzzy fault section estimation on radial distribution feeders

    E-Print Network [OSTI]

    Andoh, Kwame Sarpong

    2000-01-01T23:59:59.000Z

    was involved in the fault was evaluated using the event-phase possibility values and line section phase topology information. The fault distance algorithm was used to eliminate sections of the feeder that were not likely to be possible faulted section...

  3. Shallow faults mapped with seismic reflections: Lost River Fault, Idaho

    E-Print Network [OSTI]

    Mubarik, Ali; Miller, Richard D.; Steeples, Don W.

    1991-09-01T23:59:59.000Z

    stations 132 and 160. Total bedrock dis?lace- ment interpreted along this seismic survey line is approxa- mately 6 m, representing 4 to 6 times more displacement than is observed on either the common offset refraction section or at the surface..., vol. A, U.S. Geological Survey Open-file Report 85-290, 182-194, 1985. Crone, A. J., and M. N. Macbette, Surface faulting accompa- nying the Borah Peak earthquake, central Idaho, Geology, 12, 664-667, 1984. Crone, A. J., M. N. Macbette, M. G...

  4. Earthquake behavior and structure of oceanic transform faults

    E-Print Network [OSTI]

    Roland, Emily Carlson

    2012-01-01T23:59:59.000Z

    Oceanic transform faults that accommodate strain at mid-ocean ridge offsets represent a unique environment for studying fault mechanics. Here, I use seismic observations and models to explore how fault structure affects ...

  5. Low-cost motor drive embedded fault diagnosis systems

    E-Print Network [OSTI]

    Akin, Bilal

    2009-05-15T23:59:59.000Z

    Electric motors are used widely in industrial manufacturing plants. Bearing faults, insulation faults, and rotor faults are the major causes of electric motor failures. Based on the line current analysis, this dissertation mainly deals with the low...

  6. Circuits & Systems Test Circuits for Characterization of Process, Device, and Interconnect Variation ................................................................................. CS.1

    E-Print Network [OSTI]

    Reif, Rafael

    Circuits & Systems Test Circuits for Characterization of Process, Device, and Interconnect................................................................................................. CS.2 45nm Direct-battery DC-DC Converter for Mobile Applications

  7. Fault-tolerant quantum computation

    E-Print Network [OSTI]

    Shor, P W

    1996-01-01T23:59:59.000Z

    Recently, it was realized that use of the properties of quantum mechanics might speed up certain computations dramatically. Interest in quantum computation has since been growing. One of the main difficulties of realizing quantum computation is that decoherence tends to destroy the information in a superposition of states in a quantum computer, thus making long computations impossible. A futher difficulty is that inaccuracies in quantum state transformations throughout the computation accumulate, rendering the output of long computations unreliable. It was previously known that a quantum circuit with t gates could tolerate O(1/t) amounts of inaccuracy and decoherence per gate. We show, for any quantum computation with t gates, how to build a polynomial size quantum circuit that can tolerate O(1/(log t)^c) amounts of inaccuracy and decoherence per gate, for some constant c. We do this by showing how to compute using quantum error correcting codes. These codes were previously known to provide resistance to erro...

  8. Nuclear sensor signal processing circuit

    DOE Patents [OSTI]

    Kallenbach, Gene A. (Bosque Farms, NM); Noda, Frank T. (Albuquerque, NM); Mitchell, Dean J. (Tijeras, NM); Etzkin, Joshua L. (Albuquerque, NM)

    2007-02-20T23:59:59.000Z

    An apparatus and method are disclosed for a compact and temperature-insensitive nuclear sensor that can be calibrated with a non-hazardous radioactive sample. The nuclear sensor includes a gamma ray sensor that generates tail pulses from radioactive samples. An analog conditioning circuit conditions the tail-pulse signals from the gamma ray sensor, and a tail-pulse simulator circuit generates a plurality of simulated tail-pulse signals. A computer system processes the tail pulses from the gamma ray sensor and the simulated tail pulses from the tail-pulse simulator circuit. The nuclear sensor is calibrated under the control of the computer. The offset is adjusted using the simulated tail pulses. Since the offset is set to zero or near zero, the sensor gain can be adjusted with a non-hazardous radioactive source such as, for example, naturally occurring radiation and potassium chloride.

  9. Vertically Integrated Circuits at Fermilab

    SciTech Connect (OSTI)

    Deptuch, Grzegorz; Demarteau, Marcel; Hoff, James; Lipton, Ronald; Shenai, Alpana; Trimpl, Marcel; Yarema, Raymond; Zimmerman, Tom; /Fermilab

    2009-01-01T23:59:59.000Z

    The exploration of the vertically integrated circuits, also commonly known as 3D-IC technology, for applications in radiation detection started at Fermilab in 2006. This paper examines the opportunities that vertical integration offers by looking at various 3D designs that have been completed by Fermilab. The emphasis is on opportunities that are presented by through silicon vias (TSV), wafer and circuit thinning and finally fusion bonding techniques to replace conventional bump bonding. Early work by Fermilab has led to an international consortium for the development of 3D-IC circuits for High Energy Physics. The consortium has submitted over 25 different designs for the Fermilab organized MPW run organized for the first time.

  10. Off-fault Damage Associated with a Localized Bend in the North Branch San Gabriel Fault, California

    E-Print Network [OSTI]

    Becker, Andrew 1987-

    2012-08-15T23:59:59.000Z

    Structures within very large displacement, mature fault zones, such as the North Branch San Gabriel Fault (NBSGF), are the product of a complex combination of processes. Off-fault damage within a damage zone and first-order geometric asperities...

  11. Improving Distribution System Reliability Through Risk-base Doptimization of Fault Management and Improved Computer-based Fault Location

    E-Print Network [OSTI]

    Dong, Yimai

    2013-11-07T23:59:59.000Z

    )’s regulation on power quality. Optimization in fault management tasks has the potential of improving system reliability by reducing the duration and scale of outages caused by faults through fast fault isolation and service restoration. The research reported...

  12. Evaluation of faulting characteristics and ground acceleration associated with recent movement along the Meers Fault, Southwestern Oklahoma

    E-Print Network [OSTI]

    Burrell, Richard Dennis

    1997-01-01T23:59:59.000Z

    Recent studies have shown that a 27 km section of the Meers Fault was reactivated during Holocene time. Although these studies have proven the occurrence of recent fault activity, many basic characteristics of the faulting remain unresolved...

  13. An algorithm for faulted phase and feeder selection under high impedance fault conditions

    E-Print Network [OSTI]

    Benner, Carl Lee

    1988-01-01T23:59:59.000Z

    proximate lines served by the same substation. Because of this signal propagation, a fault will be detected simultaneously on the faulted line and possibly several other lines served by the substation. Since it would not be plausible for a utility company... to deenergize the entire area served by a substation due to a high impedance fault on one lateral, a technique is needed to discriminate the faulted line from neighboring healthy feeders and healthy phases of the faulted feeder. Such a technique would also...

  14. active fault segments: Topics by E-print Network

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Fault activation Kuzmanov, Georgi 140 Early stage evolution of growth faults: 3D seismic insights from the Levant Basin, Eastern Mediterranean Materials Science Websites...

  15. Modeling and Measurement Constraints in Fault Diagnostics for HVAC Systems

    E-Print Network [OSTI]

    Najafi, Massieh

    2010-01-01T23:59:59.000Z

    in Fault Diagnostics for HVAC Systems Massieh Najafi 1 ,tools for determining HVAC diagnostics, methods todetect faults in HVAC systems are still generally

  16. Fault-tolerant TCP mechanisms 

    E-Print Network [OSTI]

    Satapati, Suresh Kumar

    2000-01-01T23:59:59.000Z

    point (TSAPs). In BSD, a service access point is a TCP socket identified by an IP address and port number, A TCP based fault-tolerant service is realized by replicating a server program onto one or more hosts and by having all replicas bind... backup sends the SEQUENCE NUMBER of the segment it recently sent. Since the primary server doesn't exist, the client does not acknowledge. The TCP on backup server keeps retransmitting the same segment, which can be counted to initiate a...

  17. Fault Controlled | Open Energy Information

    Open Energy Info (EERE)

    AFDC Printable Version Share this resource Send a link to EERE: Alternative Fuels Data Center Home Page to someone by E-mail Share EERE: Alternative Fuels Data Center Home Page on Facebook Tweet about EERE: Alternative Fuels Data Center Home Page on Twitter Bookmark EERE: Alternative Fuels Data Center Home Page onYou are now leaving Energy.gov You are now leaving Energy.gov You are beingZealand JumpConceptual Model,DOEHazelPennsylvania: EnergyExolisFairway,FarmersFastcap SystemsShear Zone:Fault

  18. Fermionic Models with Superconducting Circuits

    E-Print Network [OSTI]

    U. Las Heras; L. García-Álvarez; A. Mezzacapo; E. Solano; L. Lamata

    2015-03-31T23:59:59.000Z

    We propose a method for the efficient quantum simulation of fermionic systems with superconducting circuits. It consists in the suitable use of Jordan-Wigner mapping, Trotter decomposition, and multiqubit gates, be with the use of a quantum bus or direct capacitive couplings. We apply our method to the paradigmatic cases of 1D and 2D Fermi-Hubbard models, involving couplings with nearest and next-nearest neighbours. Furthermore, we propose an optimal architecture for this model and discuss the benchmarking of the simulations in realistic circuit quantum electrodynamics setups.

  19. Fermionic Models with Superconducting Circuits

    E-Print Network [OSTI]

    U. Las Heras; L. García-Álvarez; A. Mezzacapo; E. Solano; L. Lamata

    2014-11-10T23:59:59.000Z

    We propose a method for the efficient quantum simulation of fermionic systems with superconducting circuits. It consists in the suitable use of Jordan-Wigner mapping, Trotter decomposition, and multiqubit gates, be with the use of a quantum bus or direct capacitive couplings. We apply our method to the paradigmatic cases of 1D and 2D Fermi-Hubbard models, involving couplings with nearest and next-nearest neighbours. Furthermore, we propose an optimal architecture for this model and discuss the benchmarking of the simulations in realistic circuit quantum electrodynamics setups.

  20. Spatial analysis of hypocenter to fault relationships for determining fault process zone width in Japan.

    SciTech Connect (OSTI)

    Arnold, Bill Walter; Roberts, Barry L.; McKenna, Sean Andrew; Coburn, Timothy C. (Abilene Christian University, Abilene, TX)

    2004-09-01T23:59:59.000Z

    Preliminary investigation areas (PIA) for a potential repository of high-level radioactive waste must be evaluated by NUMO with regard to a number of qualifying factors. One of these factors is related to earthquakes and fault activity. This study develops a spatial statistical assessment method that can be applied to the active faults in Japan to perform such screening evaluations. This analysis uses the distribution of seismicity near faults to define the width of the associated process zone. This concept is based on previous observations of aftershock earthquakes clustered near active faults and on the assumption that such seismic activity is indicative of fracturing and associated impacts on bedrock integrity. Preliminary analyses of aggregate data for all of Japan confirmed that the frequency of earthquakes is higher near active faults. Data used in the analysis were obtained from NUMO and consist of three primary sources: (1) active fault attributes compiled in a spreadsheet, (2) earthquake hypocenter data, and (3) active fault locations. Examination of these data revealed several limitations with regard to the ability to associate fault attributes from the spreadsheet to locations of individual fault trace segments. In particular, there was no direct link between attributes of the active faults in the spreadsheet and the active fault locations in the GIS database. In addition, the hypocenter location resolution in the pre-1983 data was less accurate than for later data. These pre-1983 hypocenters were eliminated from further analysis.

  1. Physiochemical Evidence of Faulting Processes and Modeling of Fluid in Evolving Fault Systems in Southern California

    SciTech Connect (OSTI)

    Boles, James [Professor

    2013-05-24T23:59:59.000Z

    Our study targets recent (Plio-Pleistocene) faults and young (Tertiary) petroleum fields in southern California. Faults include the Refugio Fault in the Transverse Ranges, the Ellwood Fault in the Santa Barbara Channel, and most recently the Newport- Inglewood in the Los Angeles Basin. Subsurface core and tubing scale samples, outcrop samples, well logs, reservoir properties, pore pressures, fluid compositions, and published structural-seismic sections have been used to characterize the tectonic/diagenetic history of the faults. As part of the effort to understand the diagenetic processes within these fault zones, we have studied analogous processes of rapid carbonate precipitation (scaling) in petroleum reservoir tubing and manmade tunnels. From this, we have identified geochemical signatures in carbonate that characterize rapid CO2 degassing. These data provide constraints for finite element models that predict fluid pressures, multiphase flow patterns, rates and patterns of deformation, subsurface temperatures and heat flow, and geochemistry associated with large fault systems.

  2. Optimized Fault Location Final Project Report

    E-Print Network [OSTI]

    Engineering Research Center Optimized Fault Location Concurrent Technologies Corporation Final Project Report by the Concurrent Technologies Corporation (CTC) and the Power Systems Engineering Research Center (PSERC). NeitherOptimized Fault Location Final Project Report Power Systems Engineering Research Center A National

  3. Sensor Fault Diagnosis Using Principal Component Analysis 

    E-Print Network [OSTI]

    Sharifi, Mahmoudreza

    2010-07-14T23:59:59.000Z

    The purpose of this research is to address the problem of fault diagnosis of sensors which measure a set of direct redundant variables. This study proposes: 1. A method for linear senor fault diagnosis 2. An analysis of isolability and detectability...

  4. Sensor Fault Diagnosis Using Principal Component Analysis

    E-Print Network [OSTI]

    Sharifi, Mahmoudreza

    2010-07-14T23:59:59.000Z

    The purpose of this research is to address the problem of fault diagnosis of sensors which measure a set of direct redundant variables. This study proposes: 1. A method for linear senor fault diagnosis 2. An analysis of isolability and detectability...

  5. INDUCTION MOTOR FAULT DIAGNOSTIC AND MONITORING METHODS

    E-Print Network [OSTI]

    Povinelli, Richard J.

    INDUCTION MOTOR FAULT DIAGNOSTIC AND MONITORING METHODS by Aderiano M. da Silva, B.S. A Thesis;i Abstract Induction motors are used worldwide as the "workhorse" in industrial applications material. However, induction motor faults can be detected in an initial stage in order to prevent

  6. Self-triggering superconducting fault current limiter

    DOE Patents [OSTI]

    Yuan, Xing (Albany, NY); Tekletsadik, Kasegn (Rexford, NY)

    2008-10-21T23:59:59.000Z

    A modular and scaleable Matrix Fault Current Limiter (MFCL) that functions as a "variable impedance" device in an electric power network, using components made of superconducting and non-superconducting electrically conductive materials. The matrix fault current limiter comprises a fault current limiter module that includes a superconductor which is electrically coupled in parallel with a trigger coil, wherein the trigger coil is magnetically coupled to the superconductor. The current surge doing a fault within the electrical power network will cause the superconductor to transition to its resistive state and also generate a uniform magnetic field in the trigger coil and simultaneously limit the voltage developed across the superconductor. This results in fast and uniform quenching of the superconductors, significantly reduces the burnout risk associated with non-uniformity often existing within the volume of superconductor materials. The fault current limiter modules may be electrically coupled together to form various "n" (rows).times."m" (columns) matrix configurations.

  7. Post regulation circuit with energy storage

    DOE Patents [OSTI]

    Ball, Don G. (Livermore, CA); Birx, Daniel L. (Oakley, CA); Cook, Edward G. (Livermore, CA)

    1992-01-01T23:59:59.000Z

    A charge regulation circuit provides regulation of an unregulated voltage supply and provides energy storage. The charge regulation circuit according to the present invention provides energy storage without unnecessary dissipation of energy through a resistor as in prior art approaches.

  8. Circuit Optimization Using Efficient Parallel Pattern Search

    E-Print Network [OSTI]

    Narasimhan, Srinath S.

    2011-08-08T23:59:59.000Z

    Circuit optimization is extremely important in order to design today's high performance integrated circuits. As systems become more and more complex, traditional optimization techniques are no longer viable due to the complex and simulation...

  9. The Starr fault system of southeastern Ohio

    SciTech Connect (OSTI)

    Brannock, M.C. (Qauker State Corp., Belpre, OH (United States))

    1993-08-01T23:59:59.000Z

    The Starr fault system is a series of east-west-trending faults located in southeastern Ohio. This fault system was discovered by mapping the anomalous sedimentary sequence of the [open quotes]Big Lime[close quotes]. The Big Lime is a driller's term for the stratigraphic section that includes the Lower Devonian Onondaga through Middle Silurian Lockport formations. The use of trend-surface analysis identified the probable fault orientation, which was then verified by seismic. The system is a series of high-angle faults, originating in the Precambrian, that occur along a narrow corridor traversing several townships. Analysis of the sedimentary section preserved by faulting indicates fault movement after the deposition of the Bass Island Formation, which was followed by a regional unconformity that removed the Bass Islands and a part of the upper Salina Formation. The Onondaga subsequently was deposited, masking fault movement evidence in the shallower formations. Some minor movement occurred later, as evidenced by the expansion in the Devonian shale sequence. The geometry of the fault system and other data suggest a pattern similar to the Albio-Scipio field of southern Michigan. A group of wells were drilled to test the Ordovician Trenton and Black River formations to determine the existence of secondary dolomite, which could be a potential reservoir. Secondary dolomite was encountered, but no commercial hydrocarbons were found in either the Trenton or Black River. Other formations produced hydrocarbons and water from fractured zones that were not known for this behavior. Other probable fault systems in southern Ohio, identified by using the same mapping techniques, may provide deeper targets for future drilling.

  10. 20Engineering Gene Circuits: Foundations

    E-Print Network [OSTI]

    You, Lingchong

    ................................................................. 20-363 20.2 Designing Gene Circuits............................................. 20-364 Modeling characterized as ``robustness.'' Based on extensive studies over the last several decades, much engineered switches [11­14], oscillators [15,16], logic gates [17­19], metabolic control [20], reengineered

  11. ECE 2100 Circuit Analysis NAME: ________________________________________________

    E-Print Network [OSTI]

    Miller, Damon A.

    ECE 2100 Circuit Analysis Fall 2011 Exam #1 NAME Schematics drawn using LTspice IV (linear.com). Some problems might be adapted from the course text Schematics drawn using LTspice IV (linear.com). Some problems might be adapted from the course text

  12. Analysis and design of reliable nanometer circuits

    E-Print Network [OSTI]

    Zhao, Chong

    2007-01-01T23:59:59.000Z

    methodology is the key first step toward design of low-cost, highly robust nanometer circuit systems. Soft

  13. Circuit Quantum Electrodynamics with Electrons on Helium

    E-Print Network [OSTI]

    Circuit Quantum Electrodynamics with Electrons on Helium A Dissertation Presented to the Faculty Fragner All rights reserved. ii #12;Abstract Circuit Quantum Electrodynamics with Electrons on Helium helium. Such a system represents a solid-state, electrical circuit analog of atomic cavity QED in which

  14. Voltage, energy and power in electric circuits

    E-Print Network [OSTI]

    Berzins, M.

    Voltage, energy and power in electric circuits Science teaching unit #12;Disclaimer The Department-2008DVD-EN Voltage, energy and power in electric circuits #12;#12;© Crown copyright 2008 1The National Strategies | Secondary Voltage, energy and power in electric circuits 00094-2008DVD-EN Contents Voltage

  15. access circuit design: Topics by E-print Network

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    7 Multilayer Ceramic Integrated Circuits (MCICs) Technology and Passive Circuit Design Computer Technologies and Information Sciences Websites Summary: Multilayer Ceramic...

  16. Maze Solving Automatons for Self-Healing of Open Interconnects: Modular Add-on for Circuit Boards

    E-Print Network [OSTI]

    Aswathi Nair; Karthik Raghunandan; Vaddi Yaswanth; Sreelal Shridharan; Sanjiv Sambandan

    2014-12-30T23:59:59.000Z

    We present the circuit board integration of a self-healing mechanism to repair open faults. The electric field driven mechanism physically restores fractured interconnects in electronic circuits and has the ability to solve mazes. The repair is performed by conductive particles dispersed in an insulating fluid. We demonstrate the integration of the healing module onto printed circuit boards and the ability of maze solving. We model and perform experiments on the influence of the geometry of the conductive particles as well as the terminal impedances of the route on the healing efficiency. The typical heal rate is 10 $\\mu$m/s with healed route having resistance of 100 $\\Omega$ to 20 k$\\Omega$ depending on the materials and concentrations used.

  17. A method for finding the statically sensitized critical path in VLSI circuits

    E-Print Network [OSTI]

    Sen, Anindita

    1995-01-01T23:59:59.000Z

    is not to eliminate the false paths but to identify the critical path. Here, instead of starting with a path list and examining one path at a time from this list, they start at a PI with a logic value of 0 or 1 and try to get to the PO of the longest sensitizable... propagate an event from a PI to a PO in the presence of sn input vector. In order to activate a fault the test generation algorithms have to find an input vector that sets a specified line in a circuit to the desired value. This is an instance...

  18. Fault-Tolerant CCM Middleware for Embedded Adaptive Dependability (MEAD)

    E-Print Network [OSTI]

    Narasimhan, Priya

    Fault-Tolerant CCM Middleware for Embedded Adaptive Dependability (MEAD) Real-Time Fault Narasimhan Carnegie Mellon University CCM Workshop, Nashville, TN December 10, 2003 #12;12/11/2003 Page 2 Model precursor to a real-time fault tolerant CCM ­ Real-Time Fault Tolerant CORBA Standard RFP launched

  19. Fault-tolerant quantum computation

    E-Print Network [OSTI]

    Peter W. Shor

    1997-03-05T23:59:59.000Z

    Recently, it was realized that use of the properties of quantum mechanics might speed up certain computations dramatically. Interest in quantum computation has since been growing. One of the main difficulties of realizing quantum computation is that decoherence tends to destroy the information in a superposition of states in a quantum computer, thus making long computations impossible. A futher difficulty is that inaccuracies in quantum state transformations throughout the computation accumulate, rendering the output of long computations unreliable. It was previously known that a quantum circuit with t gates could tolerate O(1/t) amounts of inaccuracy and decoherence per gate. We show, for any quantum computation with t gates, how to build a polynomial size quantum circuit that can tolerate O(1/(log t)^c) amounts of inaccuracy and decoherence per gate, for some constant c. We do this by showing how to compute using quantum error correcting codes. These codes were previously known to provide resistance to errors while storing and transmitting quantum data.

  20. Mechanical Models of Fault-Related Folding

    SciTech Connect (OSTI)

    Johnson, A. M.

    2003-01-09T23:59:59.000Z

    The subject of the proposed research is fault-related folding and ground deformation. The results are relevant to oil-producing structures throughout the world, to understanding of damage that has been observed along and near earthquake ruptures, and to earthquake-producing structures in California and other tectonically-active areas. The objectives of the proposed research were to provide both a unified, mechanical infrastructure for studies of fault-related foldings and to present the results in computer programs that have graphical users interfaces (GUIs) so that structural geologists and geophysicists can model a wide variety of fault-related folds (FaRFs).

  1. 1166 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 5, MAY 2005 Design Analysis and Circuit Enhancements for

    E-Print Network [OSTI]

    Long, Stephen I.

    1166 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 5, MAY 2005 Design Analysis and Circuit from the layout in an analysis, see [6]. A. Open Circuit Time Constants The method of open circuit time finds exactly the value of for a linear circuit (corre- sponding to the dominant pole in the circuit

  2. Delta connected resonant snubber circuit

    DOE Patents [OSTI]

    Lai, J.S.; Peng, F.Z.; Young, R.W. Sr.; Ott, G.W. Jr.

    1998-01-20T23:59:59.000Z

    A delta connected, resonant snubber-based, soft switching, inverter circuit achieves lossless switching during dc-to-ac power conversion and power conditioning with minimum component count and size. Current is supplied to the resonant snubber branches solely by the dc supply voltage through the main inverter switches and the auxiliary switches. Component count and size are reduced by use of a single semiconductor switch in the resonant snubber branches. Component count is also reduced by maximizing the use of stray capacitances of the main switches as parallel resonant capacitors. Resonance charging and discharging of the parallel capacitances allows lossless, zero voltage switching. In one embodiment, circuit component size and count are minimized while achieving lossless, zero voltage switching within a three-phase inverter. 36 figs.

  3. Ionization tube simmer current circuit

    DOE Patents [OSTI]

    Steinkraus, Jr., Robert F. (Livermore, CA)

    1994-01-01T23:59:59.000Z

    A highly efficient flash lamp simmer current circuit utilizes a fifty percent duty cycle square wave pulse generator to pass a current over a current limiting inductor to a full wave rectifier. The DC output of the rectifier is then passed over a voltage smoothing capacitor through a reverse current blocking diode to a flash lamp tube to sustain ionization in the tube between discharges via a small simmer current. An alternate embodiment of the circuit combines the pulse generator and inductor in the form of an FET off line square wave generator with an impedance limited step up output transformer which is then applied to the full wave rectifier as before to yield a similar simmer current.

  4. Delta connected resonant snubber circuit

    DOE Patents [OSTI]

    Lai, Jih-Sheng (Knoxville, TN); Peng, Fang Zheng (Oak Ridge, TN); Young, Sr., Robert W. (Oak Ridge, TN); Ott, Jr., George W. (Knoxville, TN)

    1998-01-01T23:59:59.000Z

    A delta connected, resonant snubber-based, soft switching, inverter circuit achieves lossless switching during dc-to-ac power conversion and power conditioning with minimum component count and size. Current is supplied to the resonant snubber branches solely by the dc supply voltage through the main inverter switches and the auxiliary switches. Component count and size are reduced by use of a single semiconductor switch in the resonant snubber branches. Component count is also reduced by maximizing the use of stray capacitances of the main switches as parallel resonant capacitors. Resonance charging and discharging of the parallel capacitances allows lossless, zero voltage switching. In one embodiment, circuit component size and count are minimized while achieving lossless, zero voltage switching within a three-phase inverter.

  5. Ionization tube simmer current circuit

    DOE Patents [OSTI]

    Steinkraus, R.F. Jr.

    1994-12-13T23:59:59.000Z

    A highly efficient flash lamp simmer current circuit utilizes a fifty percent duty cycle square wave pulse generator to pass a current over a current limiting inductor to a full wave rectifier. The DC output of the rectifier is then passed over a voltage smoothing capacitor through a reverse current blocking diode to a flash lamp tube to sustain ionization in the tube between discharges via a small simmer current. An alternate embodiment of the circuit combines the pulse generator and inductor in the form of an FET off line square wave generator with an impedance limited step up output transformer which is then applied to the full wave rectifier as before to yield a similar simmer current. 6 figures.

  6. Normalizer circuits and a Gottesman-Knill theorem for infinite-dimensional systems

    E-Print Network [OSTI]

    Juan Bermejo-Vega; Cedric Yen-Yu Lin; Maarten Van den Nest

    2015-01-20T23:59:59.000Z

    $\\textit{Normalizer circuits}$ [1,2] are generalized Clifford circuits that act on arbitrary finite-dimensional systems $\\mathcal{H}_{d_1}\\otimes ... \\otimes \\mathcal{H}_{d_n}$ with a standard basis labeled by the elements of a finite Abelian group $G=\\mathbb{Z}_{d_1}\\times... \\times \\mathbb{Z}_{d_n}$. Normalizer gates implement operations associated with the group $G$ and can be of three types: quantum Fourier transforms, group automorphism gates and quadratic phase gates. In this work, we extend the normalizer formalism [1,2] to infinite dimensions, by allowing normalizer gates to act on systems of the form $\\mathcal{H}_\\mathbb{Z}^{\\otimes a}$: each factor $\\mathcal{H}_\\mathbb{Z}$ has a standard basis labeled by $\\textit{integers}$ $\\mathbb{Z}$, and a Fourier basis labeled by $\\textit{angles}$, elements of the circle group $\\mathbb{T}$. Normalizer circuits become hybrid quantum circuits acting both on continuous- and discrete-variable systems. We show that infinite-dimensional normalizer circuits can be efficiently simulated classically with a generalized $\\textit{stabilizer formalism}$ for Hilbert spaces associated with groups of the form $\\mathbb{Z}^a\\times \\mathbb{T}^b \\times \\mathbb{Z}_{d_1}\\times...\\times \\mathbb{Z}_{d_n}$. We develop new techniques to track stabilizer-groups based on normal forms for group automorphisms and quadratic functions. We use our normal forms to reduce the problem of simulating normalizer circuits to that of finding general solutions of systems of mixed real-integer linear equations [3] and exploit this fact to devise a robust simulation algorithm: the latter remains efficient even in pathological cases where stabilizer groups become infinite, uncountable and non-compact. The techniques developed in this paper might find applications in the study of fault-tolerant quantum computation with superconducting qubits [4,5].

  7. Photoconductive circuit element pulse generator

    DOE Patents [OSTI]

    Rauscher, Christen (Alexandria, VA)

    1989-01-01T23:59:59.000Z

    A pulse generator for characterizing semiconductor devices at millimeter wavelength frequencies where a photoconductive circuit element (PCE) is biased by a direct current voltage source and produces short electrical pulses when excited into conductance by short laser light pulses. The electrical pulses are electronically conditioned to improve the frequency related amplitude characteristics of the pulses which thereafter propagate along a transmission line to a device under test.

  8. Monolithic readout circuits for RHIC

    SciTech Connect (OSTI)

    O`Connor, P.; Harder, J. [Brookhaven National Laboratory, Upton, NY (United States)

    1991-12-31T23:59:59.000Z

    Several CMOS ASICs have been developed for a proposed RHIC experiment. This paper discusses why ASIC implementation was chosen for certain functions, circuit specifications and the design techniques used to meet them, and results of simulations and early prototypes. By working closely together from an early stage in the planning process, in-house ASIC designers and detector and data acquisition experimenters can achieve optimal use of this important technology.

  9. Counterpulse railgun energy recovery circuit

    DOE Patents [OSTI]

    Honig, Emanuel M. (Los Alamos, NM)

    1986-01-01T23:59:59.000Z

    In an electromagnetic launcher such as a railgun for propelling a projectile at high velocity, a counterpulse energy recovery circuit is employed to transfer stored inductive energy from a source inductor to the railgun inductance to propel the projectile down the railgun. Switching circuitry and an energy transfer capacitor are used to switch the energy back to the source inductor in readiness for a repetitive projectile propelling cycle.

  10. Overpulse railgun energy recovery circuit

    DOE Patents [OSTI]

    Honig, Emanuel M. (Los Alamos, NM)

    1989-01-01T23:59:59.000Z

    In an electromagnetic launcher such as a railgun for propelling a projectile at high velocity, an overpulse energy recovery circuit is employed to transfer stored inductive energy from a source inductor to the railgun inductance to propel the projectile down the railgun. Switching circuitry and an energy transfer capacitor are used to switch the energy back to the source inductor in readiness for a repetitive projectile propelling cycle.

  11. Online circuit breaker monitoring system

    E-Print Network [OSTI]

    Djekic, Zarko

    2008-10-10T23:59:59.000Z

    of Department, Costas N. Georghiades December 2007 Major Subject: Electrical Engineering iii ABSTRACT Online Circuit Breaker Monitoring System. (December 2007) Zarko Djekic, B.S., University of Novi Sad, Serbia Chair of Advisory..., this work would not be possible. I would also like to thank the members of my committee, Dr. Chanan Singh, Dr. Sunil Khatri and Dr. William Lively for their advice and patience. Special thanks also go to Center Point Energy personnel Don Sevcik and John...

  12. Online circuit breaker monitoring system

    E-Print Network [OSTI]

    Djekic, Zarko

    2009-05-15T23:59:59.000Z

    of Department, Costas N. Georghiades December 2007 Major Subject: Electrical Engineering iii ABSTRACT Online Circuit Breaker Monitoring System. (December 2007) Zarko Djekic, B.S., University of Novi Sad, Serbia Chair of Advisory..., this work would not be possible. I would also like to thank the members of my committee, Dr. Chanan Singh, Dr. Sunil Khatri and Dr. William Lively for their advice and patience. Special thanks also go to Center Point Energy personnel Don Sevcik and John...

  13. Wind Power Plant Short Circuit Current Contribution for Different Fault and Wind Turbine Topologies: Preprint

    SciTech Connect (OSTI)

    Gevorgian, V.; Muljadi, E.

    2010-10-01T23:59:59.000Z

    This paper presents simulation results for SC current contribution for different types of WTGs obtained through transient and steady-state computer simulation software.

  14. Communication delay analysis of fault-tolerant pipelined circuit switching in torus

    E-Print Network [OSTI]

    Safaei, F.; Khonsari, A.; Ould-Khaoua, M.

    Safaei,F. Khonsari,A. Ould-Khaoua,M. Journal of Computer and System Sciences, to appear, 2008, ISSN: 0022-0000. Elsevier Science

  15. Structure of the eastern Red Rocks and Wind Ridge thrust faults, Wyoming: how a thrust fault gains displacement along strike 

    E-Print Network [OSTI]

    Huntsman, Brent Stanley

    1983-01-01T23:59:59.000Z

    OF FIELD MAPPING Methods . Thrust Faults . The Wind Ridge Thrust Fault System The Red Rocks Thrust Fault System CLAY MODEL STUDIES Purpose and Description Model Results DISCUSSION OF RESULTS Kinematics of the Red Rocks Thrust Fault Termination... . Kinematics of the Southern Wind Ridge Thrust Fault . . . A Conceptual Model of the Red Rocks Thrust Fault Termination Implications of the Red Rocks Fault Termination . . . . . . Page V1 V11 1X X1 X11 7 9 17 18 18 21 24 27 35 35 38 49 49...

  16. Fault Tolerant Control using Cartesian Genetic Programming

    E-Print Network [OSTI]

    Fernandez, Thomas

    Fault Tolerant Control using Cartesian Genetic Programming Yoshikazu Hirayama University of York]: Robotics-- Sensors; F.2.2 [Analysis of Algorithms and Problem Complexity]: Nonnumerical Algorithms and Problems General Terms Algorithms, Reliability Keywords cartesian genetic programming, evolutionary

  17. Microscopic feather fractures in the faulting process

    E-Print Network [OSTI]

    Conrad, Robert Eugene

    1974-01-01T23:59:59.000Z

    . Naximum compressive stress trajectories in a photoelastic model are shown by solid lines. Short lines are drawn on isoclinics in crossed polarized light at 10' intervals of rotation. Load axis is N-S. stress (o'I) trajectories curve near the fault..., maximum compressive stress, trajectories to a two dimensional during sliding along (dashed lines) in a cylindrical specimen reduced elastic problem. (b) Expected ol trajectories a fault. crack by shear along the crack surfaces (Bieniawski, 1967...

  18. Fault Detection of Broken Rotor Bars in Induction Motor using a Global Fault Index

    E-Print Network [OSTI]

    Boyer, Edmond

    in induction motor. Stator voltage and current in an induction motor were measured and employed for computation of the input power of one stator phase. Waveforms of the instantaneous power and line current were subsequently-known that interruptions of a manufacturing process due to a mechanical problem induces a serious financial loss

  19. Cluster-based architecture for fault-tolerant quantum computation

    E-Print Network [OSTI]

    Keisuke Fujii; Katsuji Yamamoto

    2009-12-28T23:59:59.000Z

    We present a detailed description of an architecture for fault-tolerant quantum computation, which is based on the cluster model of encoded qubits. In this cluster-based architecture, concatenated computation is implemented in a quite different way from the usual circuit-based architecture where physical gates are recursively replaced by logical gates with error-correction gadgets. Instead, some relevant cluster states, say fundamental clusters, are recursively constructed through verification and postselection in advance for the higher-level one-way computation, which namely provides error-precorrection of gate operations. A suitable code such as the Steane seven-qubit code is adopted for transversal operations. This concatenated construction of verified fundamental clusters has a simple transversal structure of logical errors, and achieves a high noise threshold ~ 3 % for computation by using appropriate verification procedures. Since the postselection is localized within each fundamental cluster with the help of deterministic bare controlled-Z gates without verification, divergence of resources is restrained, which reconciles postselection with scalability.

  20. Fault Detection and Load Distribution for the Wind Farm Challenge

    SciTech Connect (OSTI)

    Borchehrsen, Anders B.; Larsen, Jesper A.; Stoustrup, Jakob

    2014-08-24T23:59:59.000Z

    In this paper a fault detection system and a fault tolerant controller for a wind farm model. The wind farm model used is the one proposed as a public challenge. In the model three types of faults are introduced to a wind farm consisting of nine turbines. A fault detection system designed, by taking advantage of the fact that within a wind farm several wind turbines will be operating under all most identical conditions. The turbines are then grouped, and then turbines within each group are used to generate residuals for turbines in the group. The generated residuals are then evaluated using dynamical cumulative sum. The designed fault detection system is cable of detecting all three fault types occurring in the model. But there is room for improving the fault detection in some areas. To take advantage of the fault detection system a fault tolerant controller for the wind farm has been designed. The fault tolerant controller is a dispatch controller which is estimating the possible power at each individual turbine and then setting the reference accordingly. The fault tolerant controller has been compared to a reference controller. And the comparison shows that the fault tolerant controller performance better in all measures. The fault detection and a fault tolerant controller has been designed, and based on the simulated results the overall performance of the wind farm is improved on all measures. Thereby this is a step towards improving the overall performance of current and future wind farms.

  1. Collateral damage: Evolution with displacement of fracture distribution and secondary fault strands in fault

    E-Print Network [OSTI]

    Savage, Heather M.

    Collateral damage: Evolution with displacement of fracture distribution and secondary fault strands in fault damage zones Heather M. Savage1,2 and Emily E. Brodsky1 Received 22 April 2010; revised 10 of fracture distributions as a function of displacement to determine whether damage around small and large

  2. Fault-tolerant Sensor Network based on Fault Evaluation Matrix and Compensation for Intermittent Observation

    E-Print Network [OSTI]

    Fault-tolerant Sensor Network based on Fault Evaluation Matrix and Compensation for Intermittent-tolerant sensor network configuration problem for a target navigation. A sensor network system consists of many sensor nodes and its network connections. Each sensor node can exchange information by wireless

  3. Measuring and Modeling Fault Density for Plume-Fault Encounter Probability Estimation

    SciTech Connect (OSTI)

    Jordan, P.D.; Oldenburg, C.M.; Nicot, J.-P.

    2011-05-15T23:59:59.000Z

    Emission of carbon dioxide from fossil-fueled power generation stations contributes to global climate change. Storage of this carbon dioxide within the pores of geologic strata (geologic carbon storage) is one approach to mitigating the climate change that would otherwise occur. The large storage volume needed for this mitigation requires injection into brine-filled pore space in reservoir strata overlain by cap rocks. One of the main concerns of storage in such rocks is leakage via faults. In the early stages of site selection, site-specific fault coverages are often not available. This necessitates a method for using available fault data to develop an estimate of the likelihood of injected carbon dioxide encountering and migrating up a fault, primarily due to buoyancy. Fault population statistics provide one of the main inputs to calculate the encounter probability. Previous fault population statistics work is shown to be applicable to areal fault density statistics. This result is applied to a case study in the southern portion of the San Joaquin Basin with the result that the probability of a carbon dioxide plume from a previously planned injection had a 3% chance of encountering a fully seal offsetting fault.

  4. Different Factors Affecting Short Circuit Behavior of a Wind Power Plant

    SciTech Connect (OSTI)

    Muljadi, E.; Samaan, Nader A.; Gevorgian, Vahan; Li, Jun; Pasupulati, Subbaiah

    2013-01-31T23:59:59.000Z

    A wind power plant consists of a large number of turbines interconnected by underground cable. A pad-mount transformer at each turbine steps up the voltage from generating voltage (690 V) to a medium voltage (34.5 kV). All turbines in the plant are connected to the substation transformer where the voltage is stepped up to the transmission level. An important aspect of wind power plant (WPP) impact studies is to evaluate the short-circuit (SC) current contribution of the plant into the transmission network under different fault conditions. This task can be challenging to protection engineers due to the topology differences between different types of wind turbine generators (WTGs) and the conventional generating units. This paper investigates the short circuit behavior of a wind power plant for different types of faults. The impact of wind turbine types, the transformer configuration, and the reactive compensation capacitor will be investigated. The voltage response at different buses will be observed. Finally, the SC line currents will be presented along with its symmetrical components.

  5. Different Factors Affecting Short Circuit Behavior of a Wind Power Plant

    SciTech Connect (OSTI)

    Muljadi, E.; Samaan, Nader A.; Gevorgian, Vahan; Li, Jun; Pasupulati, Subbaiah

    2010-12-21T23:59:59.000Z

    A wind power plant consists of a large number of turbines interconnected by underground cable. A pad-mount transformer at each turbine steps up the voltage from generating voltage (690 V) to a medium voltage (34.5 kV). All turbines in the plant are connected to the substation transformer where the voltage is stepped up to the transmission level. An important aspect of wind power plant (WPP) impact studies is to evaluate the short-circuit (SC) current contribution of the plant into the transmission network under different fault conditions. This task can be challenging to protection engineers due to the topology differences between different types of wind turbine generators (WTGs) and the conventional generating units. This paper investigates the short circuit behavior of a wind power plant for different types of faults. The impact of wind turbine types, the transformer configuration, and the reactive compensation capacitor will be investigated. The voltage response at different buses will be observed. Finally, the SC line currents will be presented along with its symmetrical components.

  6. Monitoring transients in low inductance circuits

    DOE Patents [OSTI]

    Guilford, R.P.; Rosborough, J.R.

    1985-10-21T23:59:59.000Z

    The instant invention relates to methods of and apparatus for monitoring transients in low inductance circuits and to a probe utilized to practice said method and apparatus. More particularly, the instant invention relates to methods of and apparatus for monitoring low inductance circuits, wherein the low inductance circuits include a pair of flat cable transmission lines. The instant invention is further directed to a probe for use in monitoring pairs of flat cable transmission lines.

  7. An experimental study of some ferroresonant circuits

    E-Print Network [OSTI]

    Rose, Price Duane

    1959-01-01T23:59:59.000Z

    many helpful suggestions during the course of this work. CONTENTS Pa'ge PART I ? GENERAL Introduction Circuit Arrangements Studied Method of Approach PART II SERIES FERRORESONANT CIRCUITS Reaction to Variation of Source Voltage Effect of Non...-linear Resistance Reaction to Variation of Switch-Closing Time 13 Method Used to Close the Switch 13 Experimental Results 19 Effect of Residual Magnetism 22 PART III ? SERIES-PARALLEL FERRORESONANT CIRCUITS Reaction to Variation of Source Voltage 30 Reaction...

  8. Locally Advanced Stage IV Squamous Cell Carcinoma of the Head and Neck: Impact of Pre-Radiotherapy Hemoglobin Level and Interruptions During Radiotherapy

    SciTech Connect (OSTI)

    Rades, Dirk [Department of Radiation Oncology, University Hospital Schleswig-Holstein, Campus Luebeck, Luebeck (Germany); Department of Radiation Oncology, University Medical Center Hamburg-Eppendorf, Hamburg (Germany)], E-mail: Rades.Dirk@gmx.net; Stoehr, Monika [Department of Radiation Oncology, University Hospital Schleswig-Holstein, Campus Luebeck, Luebeck (Germany); Kazic, Nadja [Department of Radiation Oncology, University Hospital Sarajevo, Sarajevo(Bosnia and Herzegowina); Hakim, Samer G. [Department of Oral and Maxillofacial Surgery, University Hospital Schleswig-Holstein, Campus Luebeck, Luebeck (Germany); Walz, Annette [Department of Head and Neck Surgery, University Hospital Schleswig-Holstein, Campus Luebeck, Luebeck (Germany); Schild, Steven E. [Department of Radiation Oncology, Mayo Clinic Scottsdale, AZ (United States); Dunst, Juergen [Department of Radiation Oncology, University Hospital Schleswig-Holstein, Campus Luebeck, Luebeck (Germany)

    2008-03-15T23:59:59.000Z

    Purpose: Stage IV head and neck cancer patients carry a poor prognosis. Clear understanding of prognostic factors can help to optimize care for the individual patient. This study investigated 11 potential prognostic factors including pre-radiotherapy hemoglobin level and interruptions during radiotherapy for overall survival (OS), metastases-free survival (MFS), and locoregional control (LC) after radiochemotherapy. Methods and Materials: Eleven factors were investigated in 153 patients receiving radiochemotherapy for Stage IV squamous cell head and neck cancer: age, gender, Karnofsky performance score (KPS), tumor site, grading, T stage, N stage, pre-radiotherapy hemoglobin level, surgery, chemotherapy type, and interruptions during radiotherapy >1 week. Results: On multivariate analysis, improved OS was associated with KPS 90-100 (relative risk [RR], 2.36; 95% confidence interval [CI], 1.20-4.93; p = .012), hemoglobin {>=}12 g/dL (RR, 1.88; 95% CI, 1.01-3.53; p = .048), and no radiotherapy interruptions (RR, 2.59; 95% CI, 1.15-5.78; p = .021). Improved LC was significantly associated with lower T stage (RR, 2.17; 95% CI, 1.16-4.63; p = .013), hemoglobin {>=}12 g/dL (RR, 4.12; 95% CI, 1.92-9.09; p < .001), surgery (RR, 2.67; 95% CI, 1.28-5.88; p = .008), and no radiotherapy interruptions (RR, 3.32; 95% CI, 1.26-8.79; p = .015). Improved MFS was associated with KPS 90-100 (RR, 3.41; 95% CI, 1.46-8.85; p = .012). Conclusions: Significant predictors for outcome in Stage IV head and neck cancer were performance status, stage, surgery, pre-radiotherapy hemoglobin level, and interruptions during radiotherapy >1 week. It appears important to avoid anemia and radiotherapy interruptions to achieve the best treatment results.

  9. Printed circuit dispersive transmission line

    DOE Patents [OSTI]

    Ikezi, H.; Lin-Liu, Y.R.; DeGrassie, J.S.

    1991-08-27T23:59:59.000Z

    A printed circuit dispersive transmission line structure is disclosed comprising an insulator, a ground plane formed on one surface of the insulator, a first transmission line formed on a second surface of the insulator, and a second transmission line also formed on the second surface of the insulator and of longer length than the first transmission line and periodically intersecting the first transmission line. In a preferred embodiment, the transmission line structure exhibits highly dispersive characteristics by designing the length of one of the transmission line between two adjacent periodic intersections to be longer than the other. 5 figures.

  10. Polysilicon photoconductor for integrated circuits

    DOE Patents [OSTI]

    Hammond, R.B.; Bowman, D.R.

    1989-04-11T23:59:59.000Z

    A photoconductive element of polycrystalline silicon is provided with intrinsic response time which does not limit overall circuit response. An undoped polycrystalline silicon layer is deposited by LPCVD to a selected thickness on silicon dioxide. The deposited polycrystalline silicon is then annealed at a selected temperature and for a time effective to obtain crystal sizes effective to produce an enhanced current output. The annealed polycrystalline layer is subsequently exposed and damaged by ion implantation to a damage factor effective to obtain a fast photoconductive response. 6 figs.

  11. Circuit analysis of quantum measurement

    E-Print Network [OSTI]

    Yuji Kurotani; Masahito Ueda

    2006-09-08T23:59:59.000Z

    We develop a circuit theory that enables us to analyze quantum measurements on a two-level system and on a continuous-variable system on an equal footing. As a measurement scheme applicable to both systems, we discuss a swapping state measurement which exchanges quantum states between the system and the measuring apparatus before the apparatus meter is read out. This swapping state measurement has an advantage in gravitational-wave detection over contractive state measurement in that the postmeasurement state of the system can be set to a prescribed one, regardless of the outcome of the measurement.

  12. Hybrid stretchable circuits on silicone substrate

    SciTech Connect (OSTI)

    Robinson, A., E-mail: adam.1.robinson@nokia.com; Aziz, A., E-mail: a.aziz1@lancaster.ac.uk [Nanoscience Centre, University of Cambridge, Cambridge CB01FF (United Kingdom); Liu, Q.; Suo, Z. [School of Engineering and Applied Sciences and Kavli Institute for Bionano Science and Technology, Harvard University, Cambridge, Massachusetts 02138 (United States); Lacour, S. P., E-mail: stephanie.lacour@epfl.ch [Centre for Neuroprosthetics and Laboratory for Soft Bioelectronics Interfaces, School of Engineering, Ecole Polytechnique Fédérale de Lausanne, Lausanne 1015 (Switzerland)

    2014-04-14T23:59:59.000Z

    When rigid and stretchable components are integrated onto a single elastic carrier substrate, large strain heterogeneities appear in the vicinity of the deformable-non-deformable interfaces. In this paper, we report on a generic approach to manufacture hybrid stretchable circuits where commercial electronic components can be mounted on a stretchable circuit board. Similar to printed circuit board development, the components are electrically bonded on the elastic substrate and interconnected with stretchable electrical traces. The substrate—a silicone matrix carrying concentric rigid disks—ensures both the circuit elasticity and the mechanical integrity of the most fragile materials.

  13. Faulted joints: kinematics, displacementlength scaling relations and criteria for their identication

    E-Print Network [OSTI]

    Engelder, Terry

    and kinematics based on two sets of joints, pinnate joints and fault striations, reveal that some mesoscale faults (i.e., faults without linked fault segments) at the mesoscale: ªneoformed faultsº which form

  14. Microfracture fabric of the Punchbowl fault zone, San Andreas System, California

    E-Print Network [OSTI]

    Wilson, Jennifer Elizabeth

    1999-01-01T23:59:59.000Z

    The origin of fault zone structure is not completely understood. On the basis of mechanistic models of faulting, the characteristic internal structure of faults may largely be established early during growth of the fault, or it may develop...

  15. Robust Condition Monitoring and Fault Diagnosis of Variable Speed Induction Motor Drives

    E-Print Network [OSTI]

    Choi, Seungdeog

    2012-02-14T23:59:59.000Z

    The main types of faults studied in the literature are commonly categorized as electrical faults and mechanical faults. In addition to well known faults, the performance of a diagnostic algorithm and its operational reliability in harsh environments...

  16. A Hybrid Model Based and Statistical Fault Diagnosis System for Industrial Process

    E-Print Network [OSTI]

    Lin, Chen-Han

    2014-11-21T23:59:59.000Z

    This thesis presents a hybrid model based and statistical fault diagnosis system, which applied on the nonlinear three-tank model. The purpose of fault diagnosis is generating and analyzing the residual to find out the fault occurrence. This fault...

  17. Step Response of an RLC Circuit ECE 2100 Circuit Analysis Laboratory

    E-Print Network [OSTI]

    Miller, Damon A.

    Step Response of an RLC Circuit ECE 2100 Circuit Analysis Laboratory updated 8 January 2008 Pre of a function generator. As in the RC step response lab, this voltage source will be used to apply a voltage step to the RLC circuit. 1. Find , 0, d, and vC(t) for R1=750, 2450, and 3550. Use a table to present

  18. ENGR 201 Electrical Fundamentals I Catalog Description: Analysis of linear circuits. Circuit laws and theorems. DC response of

    E-Print Network [OSTI]

    ENGR 201 ­ Electrical Fundamentals I Catalog Description: Analysis of linear circuits. Circuit laws and laws · Methods of analysis (e.g., nodal, mesh) · Circuit theorems · Operational amplifiers · Capacitors, and apply these for the analysis of dc circuits (ABET outcomes: A, e, m) 4. Analyze circuits made up

  19. Synthesis and evaluation of fault-tolerant quantum computer architectures

    E-Print Network [OSTI]

    Cross, Andrew W. (Andrew William), 1979-

    2005-01-01T23:59:59.000Z

    Fault-tolerance is the cornerstone of practical, large-scale quantum computing, pushed into its prominent position with heroic theoretical efforts. The fault-tolerance threshold, which is the component failure probability ...

  20. FEATURE BASED HANDLING OF SURFACE FAULTS IN COMPACT DISC PLAYERS

    E-Print Network [OSTI]

    Wickerhauser, M. Victor

    two photo detectors. The distances are the distance from the actual position of the OPU such surface faults. The core idea is not to rely on sensor information during the fault. The sensor signals

  1. Observations on the capability of the Criner fault, southern Oklahoma

    E-Print Network [OSTI]

    Williamson, Shawn Collin

    1996-01-01T23:59:59.000Z

    of the present study suggest that the Criner fault is an old tectonic feature with a deceptively youthful geomorphic appearance. Differential erosion has likely exhumed the Criner fault-line scarp in the resistant Ordovician limestone of the Criner Hills...

  2. Design and analysis of a fault tolerant network processor

    E-Print Network [OSTI]

    Desai, Shaishav A

    1998-01-01T23:59:59.000Z

    This thesis investigates the effect of transient faults on a processor and proposes on-chip fault tolerant design techniques to improve its reliability. The target processor is a general 32-bit, four stage pipeline, dual context RISC style design...

  3. Frictional properties of faults: from observation on the

    E-Print Network [OSTI]

    Winfree, Erik

    Frictional properties of faults: from observation on the Longitudinal Valley Fault, Taiwan myself lucky to do what I love and to wake up every day, happy and excited about the day to come

  4. East-west faults due to planetary contraction

    E-Print Network [OSTI]

    Beuthe, Mikael

    2010-01-01T23:59:59.000Z

    Contraction, expansion and despinning have been common in the past evolution of Solar System bodies. These processes deform the lithosphere until it breaks along faults. The type and orientation of faults are usually determined under the assumption of a constant lithospheric thickness, but lithospheric thinning can occur at the equator or at the poles due either to latitudinal variation in solar insolation or to localized tidal dissipation. Using thin elastic shells with variable thickness, I show that the equatorial thinning of the lithosphere transforms the homogeneous and isotropic fault pattern caused by contraction/expansion into a pattern of faults striking east-west, preferably formed in the equatorial region. By contrast, lithospheric thickness variations only weakly affect the despinning faulting pattern consisting of equatorial strike-slip faults and polar normal faults. If contraction is added to despinning, the despinning pattern first shifts to thrust faults striking north-south and then to thrus...

  5. New approach to the fault location problem using synchronized sampling

    E-Print Network [OSTI]

    Mrkic, Jasna

    1994-01-01T23:59:59.000Z

    This thesis presents a new approach to solving the problem of fault location on a transmission line using synchronized data from both ends of the line. The synchronized phase voltage and current samples taken during the fault transient are used...

  6. VCSEL fault location apparatus and method

    DOE Patents [OSTI]

    Keeler, Gordon A. (Albuquerque, NM); Serkland, Darwin K. (Albuquerque, NM)

    2007-05-15T23:59:59.000Z

    An apparatus for locating a fault within an optical fiber is disclosed. The apparatus, which can be formed as a part of a fiber-optic transmitter or as a stand-alone instrument, utilizes a vertical-cavity surface-emitting laser (VCSEL) to generate a test pulse of light which is coupled into an optical fiber under test. The VCSEL is subsequently reconfigured by changing a bias voltage thereto and is used as a resonant-cavity photodetector (RCPD) to detect a portion of the test light pulse which is reflected or scattered from any fault within the optical fiber. A time interval .DELTA.t between an instant in time when the test light pulse is generated and the time the reflected or scattered portion is detected can then be used to determine the location of the fault within the optical fiber.

  7. Protection from ground faults in the stator winding of generators at power plants in the Siberian networks

    SciTech Connect (OSTI)

    Vainshtein, R. A., E-mail: vra@tpu.ru [Tomsk Polytechnical University (Russian Federation); Lapin, V. I. [ODU Sibiri (Integrated Dispatcher Control for Siberia), branch of JSC 'SO EES' (Russian Federation); Naumov, A. M.; Doronin, A. V. [JSC NPP 'EKRA' (Russian Federation); Yudin, S. M. [Tomsk Polytechnical University (Russian Federation)

    2010-05-15T23:59:59.000Z

    The experience of many years of experience in developing and utilization of ground fault protection in the stator winding of generators in the Siberian networks is generalized. The main method of protection is to apply a direct current or an alternating current with a frequency of 25 Hz to the primary circuits of the stator. A direct current is applied to turbo generators operating in a unit with a transformer without a resistive coupling to the external grid or to other generators. Applying a 25 Hz control current is appropriate for power generation systems with compensation of a capacitive short circuit current to ground. This method forms the basis for protection of generators operating on busbars, hydroelectric generators with a neutral grounded through an arc-suppression reactor, including in consolidated units with generators operating in parallel on a single low-voltage transformer winding.

  8. Entropy production by simple electrical circuits

    E-Print Network [OSTI]

    E. N. Miranda; S. Nikolskaia

    2012-08-13T23:59:59.000Z

    The entropy production by simple electrical circuits (R, RC, RL) is analyzed. It comes out that the entropy production is minimal, in agreement with a well known theorem due to Prigogine. In this way, it is wrong a recent result by Zupanovic, Juretic and Botric (Physica Review E 70, 056198) who claimed that the entropy production in simple electrical circuits is a maximum

  9. The Design of Integrated Circuits to Observe

    E-Print Network [OSTI]

    Harrison, Reid R.

    -limited application. KEYWORDS | Amplifiers; analog integrated circuits; biomedical signal processing; low must have its own dedicated low-noise amplifier. Although it is tempting to imagine using an analog revealed significant circuit design chal- lenges. Weak neural signals must be amplified and filtered using

  10. LABORATORY II ENERGY AND ELECTRIC CIRCUITS

    E-Print Network [OSTI]

    Minnesota, University of

    LABORATORY II ENERGY AND ELECTRIC CIRCUITS Lab II - 1 It is often useful to study physical. An electric circuit illustrates how energy can be transformed within a system, transferred to different parts it is the electric charge that transports the energy from one place in the system to another

  11. Experimental characterization of faults on low-voltage systems

    E-Print Network [OSTI]

    Ahmed, Jubayer

    1992-01-01T23:59:59.000Z

    was to simulate a con- trolled arcing fault. Hence, the arcgap was maintained constant for a particular test. A tungsten welding rod was used as the electrode because it does not melt easily. This test was performed on a. single-phase system with 240 volts... better understanding of the problem. These arcing faults and high impedance and incipient faults constitute the previously mentioned low-current faults. Journal model is IEEE Transactions on Power Delivery. Although these problems have been...

  12. Fault seal analysis of Okan and Meren fields, Nigeria

    SciTech Connect (OSTI)

    Eisenberg, R.A. [Chevron Petroleum Technology Co., La Habra, CA (United States); Brenneman, R.J. [Chevron Overseas Petroleum Co., San Ramon, CA (United States); Adeogba, A.A. [Chevron Nigeria Ltd., Lagos (Nigeria)

    1995-08-01T23:59:59.000Z

    The sealing capacity and the dynamic seal behavior of faults between juxtaposed reservoirs were analyzed for Okan and Meren fields, offshore Nigeria. In both fields correlations were found between reservoir performance, juxtaposed fluid types, oil geochemistry, interpreted fluid contact relationships, fault sealing/leaking condition, and calculated smear gouge ratios. Integration of these data has been invaluable in quantifying fault seal risk and may effect depletion strategies for fault-juxtaposed reservoirs within these fields. Fault plane sections defined reservoir juxtapositions and aided visualization of potential cross-fault spill points. Smear gouge ratios calculated from E-logs were used to estimate the composition of fault-gouge materials between the juxtaposed reservoirs. These tools augmented interpretation of seal/nonseal character based on fluid contact relationships in proved reservoirs and, in addition, were used to quantify fault seal risk of untested fault-dependent closures in Okan. The results of these analyses were then used to interpret production-induced fault seal breakdown within the G-sands and also to risk seal integrity of fault dependent closures within the untested O-sands in an adjacent, upthrown fault block. Within this fault block the presence of potential fault intersection leak points and large areas of sand/sand juxtaposition with high smear gouge ratios (low sealing potential) limits potential reserves within the O-sand package. In Meren Field the E- and G-sands are juxtaposed, on different pressure decline, geochemically distinct, and are characterized by low smear gouge ratios. In contrast, specific G- and H-sands, juxtaposed across the same fault, contain similar OOWCs and are characterized by high smear gouge ratios. The cross-sealing and/or cross-leaking nature of compartment boundaries at Meren is related to fault displacement variation and the composition of displaced stratigraphy.

  13. Detachment Faulting & Geothermal Resources- Pearl Hot Spring, NV

    Broader source: Energy.gov [DOE]

    Detachment Faulting & Geothermal Resources - Pearl Hot Spring, NV presentation at the April 2013 peer review meeting held in Denver, Colorado.

  14. Understanding Fault Characteristics of Inverter-Based Distributed Energy Resources

    SciTech Connect (OSTI)

    Keller, J.; Kroposki, B.

    2010-01-01T23:59:59.000Z

    This report discusses issues and provides solutions for dealing with fault current contributions from inverter-based distributed energy resources.

  15. Reusable vibration resistant integrated circuit mounting socket

    DOE Patents [OSTI]

    Evans, Craig N. (Irwin, PA)

    1995-01-01T23:59:59.000Z

    This invention discloses a novel form of socket for integrated circuits to be mounted on printed circuit boards. The socket uses a novel contact which is fabricated out of a bimetallic strip with a shape which makes the end of the strip move laterally as temperature changes. The end of the strip forms a barb which digs into an integrated circuit lead at normal temperatures and holds it firmly in the contact, preventing loosening and open circuits from vibration. By cooling the contact containing the bimetallic strip the barb end can be made to release so that the integrated circuit lead can be removed from the socket without damage either to the lead or to the socket components.

  16. Experimental wrench faulting at confining pressure

    E-Print Network [OSTI]

    Bartlett, Wendy Louise

    1980-01-01T23:59:59.000Z

    along the precut, resembling the "flower or palm tree" structure noted by Sylvester and Smith (1976), in the Salton Sea area, California. The bounding fault above the down-dropped block dips at a lower angle to the forcing block-veneer interface than..., the oeometries, ori- gins, and sequence of development of structural elements comprising the fault zones. Specimens (2. 8 or 3. 4 x 3. 4 x 9. 4 cm) are loaded parallel to their longest dimension, at an average displacement rate -3 -1 of 7. 3 x 10 cm sec...

  17. Sequential power-up circuit

    DOE Patents [OSTI]

    Kronberg, J.W.

    1992-06-02T23:59:59.000Z

    A sequential power-up circuit for starting several electrical load elements in series to avoid excessive current surge, comprising a voltage ramp generator and a set of voltage comparators, each comparator having a different reference voltage and interfacing with a switch that is capable of turning on one of the load elements. As the voltage rises, it passes the reference voltages one at a time and causes the switch corresponding to that voltage to turn on its load element. The ramp is turned on and off by a single switch or by a logic-level electrical signal. The ramp rate for turning on the load element is relatively slow and the rate for turning the elements off is relatively fast. Optionally, the duration of each interval of time between the turning on of the load elements is programmable. 2 figs.

  18. UNSUPERVISED CLUSTERING FOR FAULT DIAGNOSIS IN NUCLEAR POWER PLANT COMPONENTS

    E-Print Network [OSTI]

    Boyer, Edmond

    1 UNSUPERVISED CLUSTERING FOR FAULT DIAGNOSIS IN NUCLEAR POWER PLANT COMPONENTS Piero Baraldi1 of prototypical behaviors. Its performance is tested with respect to an artificial case study and then applied on transients originated by different faults in the pressurizer of a nuclear power reactor. Key Words: Fault

  19. On Distributed Fault-Tolerant Detection in Wireless Sensor Networks

    E-Print Network [OSTI]

    Huang, Yinlun

    On Distributed Fault-Tolerant Detection in Wireless Sensor Networks Xuanwen Luo, Student Member problems for distributed fault-tolerant detection in wireless sensor networks: 1) how to address both it possible to perform energy- efficient fault-tolerant detection in a wireless sensor network. Index Terms

  20. Outlier Detection Rules for Fault Detection in Solar Photovoltaic Arrays

    E-Print Network [OSTI]

    Lehman, Brad

    , MPPT of the PV inverters, high fault impedance, or degradation of solar cells [1]. Without proper fault Abstract-- Solar photovoltaic (PV) arrays are unique power sources that may have uncleared fault current when utilizing conventional overcurrent protection devices. To monitor the PV operation and detect

  1. A Parametric Spectral Estimator for Faults Detection in Induction Machines

    E-Print Network [OSTI]

    Boyer, Edmond

    since their frequency resolution is limited and additional post-processing algorithms are required of bearing faults. Index Terms--Induction machine, faults detection, bearing faults, stator current that avoids the use of extra sensors since the stator currents are usually available and inexpensive

  2. RIS-M-2311 AUTOMATIC FAULT TREE CONSTRUCTION WITH RIKKE

    E-Print Network [OSTI]

    RISØ-M-2311 AUTOMATIC FAULT TREE CONSTRUCTION WITH RIKKE A COMPENDIUM OF EXAMPLES, VOLUME I BASIC MODELS J.R. Taylor Abstract. Examples of automatically constructed fault trees are given. In this first are intended to illustrate the prin- ciples of fault tree construction using the RIKKE failure analysis system

  3. Ris-M-2311 AUTOMATIC FAULT TREE CONSTRUCTION WITH RIKKE

    E-Print Network [OSTI]

    Risø-M-2311 Vol. 2 AUTOMATIC FAULT TREE CONSTRUCTION WITH RIKKE A COMPENDIUM OF EXAMPLES. VOLUME 2. CONTROL AND SAFETY LOOPS. J.R. Taylor Abstract. This second volume describes the construction of fault In this volume, examples of HIKKE fault tree construction including loops are given. The principles involved were

  4. Statistical estimation of multiple faults in aircraft gas turbine engines

    E-Print Network [OSTI]

    Ray, Asok

    415 Statistical estimation of multiple faults in aircraft gas turbine engines S Sarkar, C Rao of multiple faults in aircraft gas-turbine engines, based on a statistical pattern recognition tool called commercial aircraft engine. Keywords: aircraft propulsion, gas turbine engines, multiple fault estimation

  5. Identifying Security Fault Reports via Text Mining Michael Gegick, 2

    E-Print Network [OSTI]

    Young, R. Michael

    Identifying Security Fault Reports via Text Mining 1 Michael Gegick, 2 Pete Rotella, 1 Tao Xie 1 contains fault reports (FRs) collected from various sources such as development teams, test teams, and end-users. Software or security engineers manually analyze the FRs to label the subset of FRs that are security fault

  6. Diverse neural net solutions to a fault diagnosis problem \\Lambda

    E-Print Network [OSTI]

    Sharkey, Amanda

    Abstract The development of a neural net system for fault diagnosis in a mar­ ine diesel engine system solution to a problem of fault diagnosis in a four­stroke marine diesel engine; that of early to recognise faults in simulated data from a diesel engine; specifically to classify combustion condition

  7. active snubber circuit: Topics by E-print Network

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Circuits Engineering Websites Summary: Transition Density, A New Measure of Activity in Digital Circuits Farid N. Najm Semiconductor Process & Design Center Texas Instruments...

  8. atmospheric electric circuit: Topics by E-print Network

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Berkeley, California of a satisfactory circuit. The topology comprises the gross number of components in the circuit, the type of each Fernandez, Thomas 59 ENG 2MM3...

  9. atmospheric electrical circuit: Topics by E-print Network

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Berkeley, California of a satisfactory circuit. The topology comprises the gross number of components in the circuit, the type of each Fernandez, Thomas 59 ENG 2MM3...

  10. Buford Major Rehabilitation Study (1996) and 11th Circuit Hydropower...

    Office of Environmental Management (EM)

    Buford Major Rehabilitation Study (1996) and 11th Circuit Hydropower Report (June 2012) Comparison The rehab study is compared to the 11th Circuit Hydropower Report for capacity...

  11. An algorithm for faulted phase and feeder selection under high impedance fault conditions 

    E-Print Network [OSTI]

    Benner, Carl Lee

    1988-01-01T23:59:59.000Z

    . One method based on increases in third and fifth harmonic symmetrical current components under high impedance fault conditions has been proposed by Balser et. Journal model is IEEE Transactions on Power Delivery. al, of Power Technologies Inc [1...

  12. Seismoelectric Imaging of a Shallow Fault System Employing Fault Guided Waves

    E-Print Network [OSTI]

    Cohrs, Frelynn Joseph Reese

    2012-07-16T23:59:59.000Z

    Independent sets of reflection seismic and seismoelectric data were collected, processed, and interpreted with the aim of generating and studying guided waves within a fault zone. While seismic surveys have recently been utilized to investigate...

  13. Clay fabric intensity in natural and artificial fault gouges: Implications for brittle fault zone processes and sedimentary

    E-Print Network [OSTI]

    Clay fabric intensity in natural and artificial fault gouges: Implications for brittle fault zone processes and sedimentary basin clay fabric evolution Samuel H. Haines,1 Ben A. van der Pluijm,1 Matt J intensity measurements using X-ray texture goniometry on 22 natural clay-rich fault gouges from low

  14. We develop a microprocessor design that tolerates hard faults, including fabrication defects and in-field faults,

    E-Print Network [OSTI]

    Sorin, Daniel J.

    1 Abstract We develop a microprocessor design that tolerates hard faults, including fabrication defects and in-field faults, by leveraging existing microprocessor redundancy. To do this, we must: detect FDUs with hard faults. In our reliable microprocessor design, we use DIVA dynamic verification

  15. Thermal anomaly near the Aigio fault, Gulf of Corinth, Greece, maybe due to convection below the fault

    E-Print Network [OSTI]

    Thermal anomaly near the Aigio fault, Gulf of Corinth, Greece, maybe due to convection below intersecting the active Aigio fault, Corinth Rift, Greece. The heat flow is 53 mW/m2 , indicating of Corinth, Greece, maybe due to convection below the fault, Geophys. Res. Lett., 34, L06314, doi:10

  16. Fault Tolerant CORBASpecification, OMG document: ptc/20000404

    E-Print Network [OSTI]

    Roma "La Sapienza", Università di

    Fault Tolerant CORBASpecification, V1.0 OMG document: ptc/2000­04­04 replaces draft adopted specification ptc/2000­03­04 and submission document orbos/00­01­19 This document is an OMG Final Adopted in the finalization phase. Comments on the content of this document are welcomed, and should be directed to issues

  17. All row, planar fault detection system

    DOE Patents [OSTI]

    Archer, Charles Jens; Pinnow, Kurt Walter; Ratterman, Joseph D; Smith, Brian Edward

    2013-07-23T23:59:59.000Z

    An apparatus, program product and method for detecting nodal faults may simultaneously cause designated nodes of a cell to communicate with all nodes adjacent to each of the designated nodes. Furthermore, all nodes along the axes of the designated nodes are made to communicate with their adjacent nodes, and the communications are analyzed to determine if a node or connection is faulty.

  18. Multi-directional fault detection system

    DOE Patents [OSTI]

    Archer, Charles Jens (Rochester, MN); Pinnow, Kurt Walter (Rochester, MN); Ratterman, Joseph D. (Rochester, MN); Smith, Brian Edward (Rochester, MN)

    2010-11-23T23:59:59.000Z

    An apparatus, program product and method checks for nodal faults in a group of nodes comprising a center node and all adjacent nodes. The center node concurrently communicates with the immediately adjacent nodes in three dimensions. The communications are analyzed to determine a presence of a faulty node or connection.

  19. Multi-directional fault detection system

    DOE Patents [OSTI]

    Archer, Charles Jens; Pinnow, Kurt Walter; Ratterman, Joseph D.; Smith, Brian Edward

    2010-06-29T23:59:59.000Z

    An apparatus, program product and method checks for nodal faults in a group of nodes comprising a center node and all adjacent nodes. The center node concurrently communicates with the immediately adjacent nodes in three dimensions. The communications are analyzed to determine a presence of a faulty node or connection.

  20. Global Trajectory Planning for Fault Tolerant Manipulators

    E-Print Network [OSTI]

    . Khosla Department of Electrical and Computer Engineering and The Robotics Institute, Carnegie Mellon attribute of robot manipulators in a growing range of applications such as space missions, nuclear waste retrieval, and medical robot­ ics. This trend has spawned a research effort in fault toler­ ant robotics

  1. Fault-tolerant, Universal Adiabatic Quantum Computation

    E-Print Network [OSTI]

    Ari Mizel

    2014-03-30T23:59:59.000Z

    Quantum computation has revolutionary potential for speeding computational tasks such as factoring and simulating quantum systems, but the task of constructing a quantum computer is daunting. Adiabatic quantum computation and other ``hands-off" approaches relieve the need for rapid, precise pulsing to control the system, inspiring at least one high-profile effort to realize a hands-off quantum computing device. But is hands-off incompatible with fault-tolerant? Concerted effort and many innovative ideas have not resolved this question but have instead deepened it, linking it to fundamental problems in quantum complexity theory. Here we present a hands-off approach that is provably (a) capable of scalable universal quantum computation in a non-degenerate ground state and (b) fault-tolerant against an analogue of the usual local stochastic fault model. A satisfying physical and numerical argument indicates that (c) it is also fault-tolerant against thermal excitation below a threshold temperature independent of the computation size.

  2. 54 MAY | 2012 Gearbox Fault Detection

    E-Print Network [OSTI]

    Kusiak, Andrew

    , research in fault identification and condition monitoring is war- ranted. In this study, detecting wind of a test wind turbine. The gearbox was retested at the Dynamometer Test Facility (DTF) at NREL. To retest the gearbox, the complete nacelle, and the drive train of the test wind turbine were installed at the DTF

  3. Fault-tolerant quantum computation by anyons

    E-Print Network [OSTI]

    A. Yu. Kitaev

    1997-07-09T23:59:59.000Z

    A two-dimensional quantum system with anyonic excitations can be considered as a quantum computer. Unitary transformations can be performed by moving the excitations around each other. Measurements can be performed by joining excitations in pairs and observing the result of fusion. Such computation is fault-tolerant by its physical nature.

  4. Fault-Tolerant Spanners: Better and Simpler

    E-Print Network [OSTI]

    Dinitz, Michael

    2011-01-01T23:59:59.000Z

    A natural requirement of many distributed structures is fault-tolerance: after some failures, whatever remains from the structure should still be effective for whatever remains from the network. In this paper we examine spanners of general graphs that are tolerant to vertex failures, and significantly improve their dependence on the number of faults $r$, for all stretch bounds. For stretch $k \\geq 3$ we design a simple transformation that converts every $k$-spanner construction with at most $f(n)$ edges into an $r$-fault-tolerant $k$-spanner construction with at most $O(r^3 \\log n) \\cdot f(2n/r)$ edges. Applying this to standard greedy spanner constructions gives $r$-fault tolerant $k$-spanners with $\\tilde O(r^{2} n^{1+\\frac{2}{k+1}})$ edges. The previous construction by Chechik, Langberg, Peleg, and Roddity [STOC 2009] depends similarly on $n$ but exponentially on $r$ (approximately like $k^r$). For the case $k=2$ and unit-length edges, an $O(r \\log n)$-approximation algorithm is known from recent work of D...

  5. Coordinated Fault Tolerance for High-Performance Computing

    SciTech Connect (OSTI)

    Dongarra, Jack; Bosilca, George; et al.

    2013-04-08T23:59:59.000Z

    Our work to meet our goal of end-to-end fault tolerance has focused on two areas: (1) improving fault tolerance in various software currently available and widely used throughout the HEC domain and (2) using fault information exchange and coordination to achieve holistic, systemwide fault tolerance and understanding how to design and implement interfaces for integrating fault tolerance features for multiple layers of the software stack—from the application, math libraries, and programming language runtime to other common system software such as jobs schedulers, resource managers, and monitoring tools.

  6. Efficient quantum circuits for arbitrary sparse unitaries

    SciTech Connect (OSTI)

    Jordan, Stephen P. [Institute for Quantum Information, Caltech, Pasadena, California 91125 (United States); Wocjan, Pawel [School of Electrical Engineering and Computer Science, University of Central Florida, Orlando, Florida 32816 (United States)

    2009-12-15T23:59:59.000Z

    Arbitrary exponentially large unitaries cannot be implemented efficiently by quantum circuits. However, we show that quantum circuits can efficiently implement any unitary provided it has at most polynomially many nonzero entries in any row or column, and these entries are efficiently computable. One can formulate a model of computation based on the composition of sparse unitaries which includes the quantum Turing machine model, the quantum circuit model, anyonic models, permutational quantum computation, and discrete time quantum walks as special cases. Thus, we obtain a simple unified proof that these models are all contained in BQP. Furthermore, our general method for implementing sparse unitaries simplifies several existing quantum algorithms.

  7. Overload protection circuit for output driver

    DOE Patents [OSTI]

    Stewart, Roger G. (Neshanic Station, NJ)

    1982-05-11T23:59:59.000Z

    A protection circuit for preventing excessive power dissipation in an output transistor whose conduction path is connected between a power terminal and an output terminal. The protection circuit includes means for sensing the application of a turn on signal to the output transistor and the voltage at the output terminal. When the turn on signal is maintained for a period of time greater than a given period without the voltage at the output terminal reaching a predetermined value, the protection circuit decreases the turn on signal to, and the current conduction through, the output transistor.

  8. Design Robustness Analysis of Neuromorphic Circuits

    E-Print Network [OSTI]

    Bashaireh, Ahmad

    2014-04-23T23:59:59.000Z

    tasks such as pattern recognition. Few attempts have been made to investigate the effect of silicon failures beyond the circuit level. In this thesis, a method is proposed to evaluate the impact of process and environmental variations on the overall...

  9. Analog circuit for controlling acoustic transducer arrays

    DOE Patents [OSTI]

    Drumheller, Douglas S. (Cedar Crest, NM)

    1991-01-01T23:59:59.000Z

    A simplified ananlog circuit is presented for controlling electromechanical transducer pairs in an acoustic telemetry system. The analog circuit of this invention comprises a single electrical resistor which replaces all of the digital components in a known digital circuit. In accordance with this invention, a first transducer in a transducer pair of array is driven in series with the resistor. The voltage drop across this resistor is then amplified and used to drive the second transducer. The voltage drop across the resistor is proportional and in phase with the current to the transducer. This current is approximately 90 degrees out of phase with the driving voltage to the transducer. This phase shift replaces the digital delay required by the digital control circuit of the prior art.

  10. Analysis and Design of Resilient VLSI Circuits

    E-Print Network [OSTI]

    Garg, Rajesh

    2010-07-14T23:59:59.000Z

    (or error caused by radiation particle strikes) have become an increasingly troublesome issue for memory arrays as well as combinational logic circuits. Also, in the DSM era, process variations are increasing at an alarming rate, making it more...

  11. Generating Circuit Tests by Exploiting Designed Behavior

    E-Print Network [OSTI]

    Shirley, Mark Harper

    1988-12-01T23:59:59.000Z

    This thesis describes two programs for generating tests for digital circuits that exploit several kinds of expert knowledge not used by previous approaches. First, many test generation problems can be solved efficiently ...

  12. Microelectronic Devices and Circuits - 2006 Electronic Edition

    E-Print Network [OSTI]

    Fonstad, Clifton

    2006-10-01T23:59:59.000Z

    Combining semiconductor device physics and modeling with electronic circuit analysis and practice in a single sophomore/junior level microelectronics course, this textbook offers an integrated approach so students can truly ...

  13. Carbon nanotube synthesis for integrated circuit interconnects

    E-Print Network [OSTI]

    Nessim, Gilbert Daniel

    2009-01-01T23:59:59.000Z

    Based on their properties, carbon nanotubes (CNTs) have been identified as ideal replacements for copper interconnects in integrated circuits given their higher current density, inertness, and higher resistance to ...

  14. Analysis of neural circuits in vitro

    E-Print Network [OSTI]

    Wang, Jennifer Lynn

    2010-01-01T23:59:59.000Z

    This thesis is a collection of manuscripts addressing connectivity of neural circuits in cultured hippocampal neurons. These studies begin with an investigation of dopaminergic modulation of excitatory synapses in small ...

  15. Flexible Electronics: Materials, Circuits, and Design Methodology

    E-Print Network [OSTI]

    Kim, Chris H.

    Electronics: Today Display Solar cell Battery 4 #12;Next Generation Flexible Electronics Problem: Traumatic system Proposed EEG system Electrode sheet Flexible electronics ... ... ... Next Generation FlexibleFlexible Electronics: Materials, Circuits, and Design Methodology Chris H. Kim Dept. of Electrical

  16. Differential transimpedance amplifier circuit for correlated differential amplification

    DOE Patents [OSTI]

    Gresham, Christopher A. (Albuquerque, NM); Denton, M. Bonner (Tucson, AZ); Sperline, Roger P. (Tucson, AZ)

    2008-07-22T23:59:59.000Z

    A differential transimpedance amplifier circuit for correlated differential amplification. The amplifier circuit increase electronic signal-to-noise ratios in charge detection circuits designed for the detection of very small quantities of electrical charge and/or very weak electromagnetic waves. A differential, integrating capacitive transimpedance amplifier integrated circuit comprising capacitor feedback loops performs time-correlated subtraction of noise.

  17. Triple effect absorption chiller utilizing two refrigeration circuits

    DOE Patents [OSTI]

    DeVault, Robert C. (Knoxville, TN)

    1988-01-01T23:59:59.000Z

    A triple effect absorption method and apparatus having a high coefficient of performance. Two single effect absorption circuits are combined with heat exchange occurring between a condenser and absorber of a high temperature circuit, and a generator of a low temperature circuit. The evaporators of both the high and low temperature circuits provide cooling to an external heat load.

  18. Foundations for a Circuit Complexity Theory of Sensory Processing

    E-Print Network [OSTI]

    Maass, Wolfgang

    bounds, in particular with linear or almost linear total wire length. 1 Introduction Circuit complexity interest in neuromorphicengineering, especially analog VLSI, and the analysis of neural circuits mathematical analysis of such circuits. The standard mathematical approach is to model such circuits

  19. Challenges for Qualitative Electrical Reasoning in Automotive Circuit Simulation

    E-Print Network [OSTI]

    Snooke, Neal

    Challenges for Qualitative Electrical Reasoning in Automotive Circuit Simulation Neal Snooke it to be used for applications on realistic automotive circuits. The type of circuits for which it is most automotive circuits with more complex overall behaviour can be approximated using this type of modelling

  20. Electrochemically controlled charging circuit for storage batteries

    DOE Patents [OSTI]

    Onstott, E.I.

    1980-06-24T23:59:59.000Z

    An electrochemically controlled charging circuit for charging storage batteries is disclosed. The embodiments disclosed utilize dc amplification of battery control current to minimize total energy expended for charging storage batteries to a preset voltage level. The circuits allow for selection of Zener diodes having a wide range of reference voltage levels. Also, the preset voltage level to which the storage batteries are charged can be varied over a wide range.

  1. Equivalent Circuit Modeling of Hysteresis Motors

    SciTech Connect (OSTI)

    Nitao, J J; Scharlemann, E T; Kirkendall, B A

    2009-08-31T23:59:59.000Z

    We performed a literature review and found that many equivalent circuit models of hysteresis motors in use today are incorrect. The model by Miyairi and Kataoka (1965) is the correct one. We extended the model by transforming it to quadrature coordinates, amenable to circuit or digital simulation. 'Hunting' is an oscillatory phenomenon often observed in hysteresis motors. While several works have attempted to model the phenomenon with some partial success, we present a new complete model that predicts hunting from first principles.

  2. Fault-tolerant logical gates in quantum error-correcting codes

    E-Print Network [OSTI]

    Fernando Pastawski; Beni Yoshida

    2014-08-07T23:59:59.000Z

    Recently, Bravyi and K\\"onig have shown that there is a tradeoff between fault-tolerantly implementable logical gates and geometric locality of stabilizer codes. They consider locality-preserving operations which are implemented by a constant depth geometrically local circuit and are thus fault-tolerant by construction. In particular, they shown that, for local stabilizer codes in D spatial dimensions, locality preserving gates are restricted to a set of unitary gates known as the D-th level of the Clifford hierarchy. In this paper, we elaborate this idea and provide several extensions and applications of their characterization in various directions. First, we present a new no-go theorem for self-correcting quantum memory. Namely, we prove that a three-dimensional stabilizer Hamiltonian with a locality-preserving implementation of a non-Clifford gate cannot have a macroscopic energy barrier. Second, we prove that the code distance of a D-dimensional local stabilizer code with non-trivial locality-preserving m-th level Clifford logical gate is upper bounded by $O(L^{D+1-m})$. For codes with non-Clifford gates (m>2), this improves the previous best bound by Bravyi and Terhal. Third we prove that a qubit loss threshold of codes with non-trivial transversal m-th level Clifford logical gate is upper bounded by 1/m. As such, no family of fault-tolerant codes with transversal gates in increasing level of the Clifford hierarchy may exist. This result applies to arbitrary stabilizer and subsystem codes, and is not restricted to geometrically-local codes. Fourth we extend the result of Bravyi and K\\"onig to subsystem codes. A technical difficulty is that, unlike stabilizer codes, the so-called union lemma does not apply to subsystem codes. This problem is avoided by assuming the presence of error threshold in a subsystem code, and the same conclusion as Bravyi-K\\"onig is recovered.

  3. Norton Collector Circuit The Norton equivalent circuit seen looking into the collector can be used to solve for the

    E-Print Network [OSTI]

    Leach Jr.,W. Marshall

    Norton Collector Circuit The Norton equivalent circuit seen looking into the collector can be used with Thévenin sources connected to its base and emitter. With the collector grounded, the col- lector current is called the short-circuit output current or ic(sc). The current source in the Norton collector circuit has

  4. Completing fault models for abductive diagnosis

    SciTech Connect (OSTI)

    Knill, E. (Los Alamos National Lab., NM (United States)); Cox, P.T.; Pietrzykowski, T. (Technical Univ., NS (Canada))

    1992-11-05T23:59:59.000Z

    In logic-based diagnosis, the consistency-based method is used to determine the possible sets of faulty devices. If the fault models of the devices are incomplete or nondeterministic, then this method does not necessarily yield abductive explanations of system behavior. Such explanations give additional information about faulty behavior and can be used for prediction. Unfortunately, system descriptions for the consistency-based method are often not suitable for abductive diagnosis. Methods for completing the fault models for abductive diagnosis have been suggested informally by Poole and by Cox et al. Here we formalize these methods by introducing a standard form for system descriptions. The properties of these methods are determined in relation to consistency-based diagnosis and compared to other ideas for integrating consistency-based and abductive diagnosis.

  5. Undulator Hall Air Temperature Fault Scenarios

    SciTech Connect (OSTI)

    Sevilla, J.; Welch, J.; /SLAC; ,

    2010-11-17T23:59:59.000Z

    Recent experience indicates that the LCLS undulator segments must not, at any time following tuning, be allowed to change temperature by more than about {+-}2.5 C or the magnetic center will irreversibly shift outside of acceptable tolerances. This vulnerability raises a concern that under fault conditions the ambient temperature in the Undulator Hall might go outside of the safe range and potentially could require removal and retuning of all the segments. In this note we estimate changes that can be expected in the Undulator Hall air temperature for three fault scenarios: (1) System-wide power failure; (2) Heating Ventilation and Air Conditioning (HVAC) system shutdown; and (3) HVAC system temperature regulation fault. We find that for either a system-wide power failure or an HVAC system shutdown (with the technical equipment left on), the short-term temperature changes of the air would be modest due to the ability of the walls and floor to act as a heat ballast. No action would be needed to protect the undulator system in the event of a system-wide power failure. Some action to adjust the heat balance, in the case of the HVAC power failure with the equipment left on, might be desirable but is not required. On the other hand, a temperature regulation failure of the HVAC system can quickly cause large excursions in air temperature and prompt action would be required to avoid damage to the undulator system.

  6. Chapter 54. Superconducting Circuits and Quantum Computing Superconducting Circuits and Quantum Computing

    E-Print Network [OSTI]

    Chapter 54. Superconducting Circuits and Quantum Computing 54-1 Superconducting Circuits. William D. Oliver (MIT Lincoln Laboratory Senior Staff Member, RLE affiliate) Overview: Superconducting computer. Our qubit species of choice is the superconducting persistent-current (PC) qubit (also known

  7. Pressure test data reveal reservoir barriers/faults

    SciTech Connect (OSTI)

    Hurd, J.D.

    1984-07-30T23:59:59.000Z

    A review of transient pressure test data from an oil reservoir in Libya indicated not only the suspected fault barriers, but also the non-sealing portions of the faults. Extensive seismic data indicated much faulting, and directional trends had been interpreted to be generally northwest-southeast. The reservoir is a heterogeneous dolomite with average permeability of 40 to 50 md and contains neither natural fractures not stratification. Vertical displacement (throw) of each fault block is indicated to be within the range of the dolomite thickness, i.e., 40 to 180 ft. Therefore, when the fault throw is greater than reservoir thickness there is sealing, and when the throw is less than reservoir thickness the faults are non-sealing.

  8. Fibre bundle framework for unitary quantum fault tolerance

    E-Print Network [OSTI]

    Daniel Gottesman; Lucy Liuxuan Zhang

    2013-09-26T23:59:59.000Z

    We introduce a differential geometric framework for describing families of quantum error-correcting codes and for understanding quantum fault tolerance. This work unifies the notion of topological fault tolerance with fault tolerance in other kinds of quantum error-correcting codes. In particular, we use fibre bundles with a natural flat projective connection to study the transformation of codewords under unitary fault-tolerant evolutions. We show that the fault-tolerant logical operations are given by the monodromy group for either of two bundles, both of which have flat projective connections. As concrete realizations of the general framework, we construct the bundles explicitly for two examples of fault-tolerant families of operations, the qudit transversal gates and the string operators in the toric code.

  9. Similarity Matching Techniques for Fault Diagnosis in Automotive Infotainment Electronics

    E-Print Network [OSTI]

    Kabir, Mashud

    2009-01-01T23:59:59.000Z

    Fault diagnosis has become a very important area of research during the last decade due to the advancement of mechanical and electrical systems in industries. The automobile is a crucial field where fault diagnosis is given a special attention. Due to the increasing complexity and newly added features in vehicles, a comprehensive study has to be performed in order to achieve an appropriate diagnosis model. A diagnosis system is capable of identifying the faults of a system by investigating the observable effects (or symptoms). The system categorizes the fault into a diagnosis class and identifies a probable cause based on the supplied fault symptoms. Fault categorization and identification are done using similarity matching techniques. The development of diagnosis classes is done by making use of previous experience, knowledge or information within an application area. The necessary information used may come from several sources of knowledge, such as from system analysis. In this paper similarity matching tec...

  10. Investigation of the Meers fault in southwestern Oklahoma

    SciTech Connect (OSTI)

    Luza, K.V.; Madole, R.F.; Crone, A.J.

    1987-08-01T23:59:59.000Z

    The Meers fault is part of a major system of NW-trending faults that form the boundary between the Wichita Mountains and the Anadarko basin in southwestern Oklahoma. A portion of the Meers fault is exposed at the surface in northern Comanche County and strikes approximately N. 60/sup 0/ W. where it offsets Permian conglomerate and shale for at least 26 km. The scarp on the fault is consistently down to the south, with a maximum relief of 5 m near the center of the fault trace. Quaternary stratigraphic relationships and 10 /sup 14/C age dates constrain the age of the last movement of the Meers fault. The last movement postdates the Browns Creek Alluvium, late Pleistocene to early Holocene, and predates the East Cache Alluvium, 100 to 800 yr B.P. Fan alluvium, produced by the last fault movement, buried a soil that dates between 1400 and 1100 yr B.P. Two trenches excavated across the scarp near Canyon Creek document the near-surface deformation and provide some general information on recurrence. Trench 1 was excavated in the lower Holocene part of the Browns Creek Alluvium, and trench 2 was excavated in unnamed gravels thought to be upper Pleistocene. Flexing and warping was the dominant mode of deformation that produced the scarp. The stratigraphy in both trenches indicates one surface-faulting event, which implies a lengthy recurrence interval for surface faulting on this part of the fault. Organic-rich material from two samples that postdate the last fault movement yielded /sup 14/C ages between 1600 and 1300 yr B.P. These dates are in excellent agreement with the dates obtained from soils buried by the fault-related fan alluvium.

  11. A Turing Machine Resisting Isolated Bursts Of Faults

    E-Print Network [OSTI]

    Capuni, Ilir

    2012-01-01T23:59:59.000Z

    We consider computations of a Turing machine under noise that causes consecutive violations of the machine's transition function. Given a constant upper bound B on the size of bursts of faults, we construct a Turing machine M(B) subject to faults that can simulate any fault-free machine under the condition that bursts are not closer to each other than V for an appropriate V = O(B^2).

  12. Dual circuit embossed sheet heat transfer panel

    DOE Patents [OSTI]

    Morgan, G.D.

    1984-02-21T23:59:59.000Z

    A heat transfer panel provides redundant cooling for fusion reactors or the like environment requiring low-mass construction. Redundant cooling is provided by two independent cooling circuits, each circuit consisting of a series of channels joined to inlet and outlet headers. The panel comprises a welded joinder of two full-size and two much smaller partial-size sheets. The first full-size sheet is embossed to form first portions of channels for the first and second circuits, as well as a header for the first circuit. The second full-sized sheet is then laid over and welded to the first full-size sheet. The first and second partial-size sheets are then overlaid on separate portions of the second full-sized sheet, and are welded thereto. The first and second partial-sized sheets are embossed to form inlet and outlet headers, which communicate with channels of the second circuit through apertures formed in the second full-sized sheet. 6 figs.

  13. Lookout device for high voltage circuit breaker

    SciTech Connect (OSTI)

    Kozlowski, L.J.; Shirey, L.A.

    1991-12-31T23:59:59.000Z

    An improved lockout assembly is provided for a circuit breaker to lock the switch handle into a selected switch position. The lockout assembly includes two main elements, each having a respective foot for engaging a portion of the upper housing wall of the circuit breaker. The first foot is inserted into a groove in the upper housing wall, and the second foot is inserted into an adjacent aperture (e.g., a slot) in the upper housing wall. The first foot is slid under and into engagement with a first portion, and the second foot is slid under and into engagement with a second portion of the upper housing wall. At the same time the respective two feet are placed in engagement with the respective portions of the upper housing wall, two holes, one on each of the respective two main elements of the assembly, are placed in registration; and a locking device, such as a special scissors equipped with a padlock, is installed through the registered holes to secure the lockout assembly on the circuit breaker. When the lockout assembly of the invention is secured on the circuit breaker, the switch handle of the circuit breaker is locked into the selected switch position and prevented from being switched to another switch position.

  14. Lockout device for high voltage circuit breaker

    DOE Patents [OSTI]

    Kozlowski, L.J.; Shirey, L.A.

    1993-01-26T23:59:59.000Z

    An improved lockout assembly is provided for a circuit breaker to lock the switch handle into a selected switch position. The lockout assembly includes two main elements, each having a respective foot for engaging a portion of the upper housing wall of the circuit breaker. The first foot is inserted into a groove in the upper housing wall, and the second foot is inserted into an adjacent aperture (e.g., a slot) in the upper housing wall. The first foot is slid under and into engagement with a first portion, and the second foot is slid under and into engagement with a second portion of the upper housing wall. At the same time the respective two feet are placed in engagement with the respective portions of the upper housing wall, two holes, one on each of the respective two main elements of the assembly, are placed in registration; and a locking device, such as a special scissors equipped with a padlock, is installed through the registered holes to secure the lockout assembly on the circuit breaker. When the lockout assembly of the invention is secured on the circuit breaker, the switch handle of the circuit breaker is locked into the selected switch position and prevented from being switched to another switch position.

  15. Lockout device for high voltage circuit breaker

    SciTech Connect (OSTI)

    Kozlowski, Lawrence J. (New Kensington, PA); Shirey, Lawrence A. (North Huntingdon, PA)

    1993-01-01T23:59:59.000Z

    An improved lockout assembly is provided for a circuit breaker to lock the switch handle into a selected switch position. The lockout assembly includes two main elements, each having a respective foot for engaging a portion of the upper housing wall of the circuit breaker. The first foot is inserted into a groove in the upper housing wall, and the second foot is inserted into an adjacent aperture (e.g., a slot) in the upper housing wall. The first foot is slid under and into engagement with a first portion, and the second foot is slid under and into engagement with a second portion of the upper housing wall. At the same time the repsective two feet are placed in engagement with the respective portions of the upper housing wall, two holes, one on each of the respective two main elements of the assembly, are placed in registration; and a locking device, such as a special scissors equipped with a padlock, is installed through the registered holes to secure the lockout assembly on the circuit breaker. When the lockout assembly of the invention is secured on the circuit breaker, the switch handle of the circuit breaker is locked into the selected switch position and prevented from being switched to another switch position.

  16. An analysis of reversible multiplier circuits

    E-Print Network [OSTI]

    Anindita Banerjee; Anirban Pathak

    2009-07-20T23:59:59.000Z

    Multiplier circuits play an important role in reversible computation, which is helpful in diverse areas such as low power CMOS design, optical computing, DNA computing and bioinformatics. Here we propose a new reversible multiplier circuit with optimized hardware complexity. The optimized multiplier circuit is compared with the earlier proposals. We have shown that the quantum cost of earlier proposals can be further reduced with the help of existing local optimization algorithms (e.g. template matching, moving rule and deletion rule). A systematic protocol for reduction of quantum cost has been proposed. It has also been shown that the advantage in gate count obtained in some of the earlier proposals by introduction of new reversible gates is an artifact and if it is allowed then every circuit block can be reduced to a single gate. Further, it is shown that the 4x4 reversible gates proposed for designing of a component of multiplier circuit (full adder) is neither unique nor special and many such 4x4 gates may be proposed. As example three such new gates have been presented here and it is shown that the proposed gates are universal. It is also shown that the total cost of our design is minimum.

  17. On the Synthesis of Sequential Reversible Circuit

    E-Print Network [OSTI]

    Anindita Banerjee; Anirban Pathak

    2007-07-28T23:59:59.000Z

    Reversible circuits for SR flip flop, JK flip flop, D flip flop, T flip flop, Master Slave D flip flop and Master Slave JK flip flop have been provided with three different logical approaches. All the circuits have been optimized with the help of existing local optimization algorithms (e.g. template matching, moving rule and deletion rule) and the optimized sequential circuits have been compared with the earlier proposals for the same. It has been shown that the present proposals have lower gate complexities and lower number of garbage bits compared to the earlier proposals. It has also been shown that the advantage in gate count obtained in some of the earlier proposals by introduction of New gates is an \\textcolor{black}{artifact} and if it is allowed then every circuit block (unless there is a measurement) can be reduced to a single gate. Further, it is shown that a reversible flip flop can be constructed even without a feedback. In this context, some important conceptual issues related to the designing and optimization of sequential reversible circuits have also been addressed.

  18. Upper crustal faulting in an obliquely extending orogen, structural...

    Open Energy Info (EERE)

    faulting in an obliquely extending orogen, structural control on permeability and production in the Coso Geothermal Field, eastern California Jump to: navigation, search OpenEI...

  19. Active Fault Controls At High-Temperature Geothermal Sites- Prospectin...

    Open Energy Info (EERE)

    the level of unrecognized active faults present in these areas. Analysis of low-sun-angle aerial photography acquired over the Needle Rocks, Astor Pass, Empire, and Lee...

  20. Fault-tolerant distributed transactions for partitioned OLTP databases

    E-Print Network [OSTI]

    Jones, Evan P. C. (Evan Philip Charles), 1981-

    2012-01-01T23:59:59.000Z

    This thesis presents Dtxn, a fault-tolerant distributed transaction system designed specifically for building online transaction processing (OLTP) databases. Databases have traditionally been designed as general purpose ...

  1. atera fault central: Topics by E-print Network

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    deformation and creep along the central section of the North Anatolian Fault (Turkey): InSAR observations Geosciences Websites Summary: Interseismic deformation and creep...

  2. Checksum-Based Fault Tolerance for LU Factorization

    E-Print Network [OSTI]

    Davies, Teresa

    2014-01-01T23:59:59.000Z

    study of failures in high-performance computing systems. InFault tolerant high performance computing by a codingfor large-scale high- performance computing. In 2012

  3. PV Arc Fault Detector Challenges Due to Module Frequency Response...

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    This poster does not contain any proprietary or confidential information. Introduction PV system arc faults have led to a number of rooftop fires which have caused significant...

  4. Dating of major normal fault systems using thermochronology-...

    Open Energy Info (EERE)

    faults, timing of ductile mylonite formation and passage of rocks through the crystal-plastic to brittle transition, and multiple events of extensional unroofing. Here we...

  5. MICRO-SEISMICITY, FAULT STRUCTURE AND HYDRAULIC COMPARTMENTALIZATION...

    Open Energy Info (EERE)

    GETHERMAL FIELD, CALIFORNIA Jump to: navigation, search OpenEI Reference LibraryAdd to library Conference Proceedings: MICRO-SEISMICITY, FAULT STRUCTURE AND HYDRAULIC...

  6. PHOTOVOLTAIC DC ARC FAULT DETECTOR TESTING AT SANDIA NATIONAL

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    PHOTOVOLTAIC DC ARC FAULT DETECTOR TESTING AT SANDIA NATIONAL LABORATORIES Jay Johnson 1 , Birger Pahl 2 , Charles Luebke 2 , Tom Pier 2 , Theodore Miller 3 , Jason Strauch 1 ,...

  7. Fault tolerant Quantum Information Processing with Holographic control

    E-Print Network [OSTI]

    G. A. Paz-Silva; G. K. Brennen; J. Twamley

    2010-08-10T23:59:59.000Z

    We present a fault-tolerant semi-global control strategy for universal quantum computers. We show that N-dimensional array of qubits where only (N-1)-dimensional addressing resolution is available is compatible with fault-tolerant universal quantum computation. What is more, we show that measurements and individual control of qubits are required only at the boundaries of the fault-tolerant computer, i.e. holographic fault-tolerant quantum computation. Our model alleviates the heavy physical conditions on current qubit candidates imposed by addressability requirements and represents an option to improve their scalability.

  8. Fault Tolerant Evaluation of Continuous Selection Queries over Sensor Data

    E-Print Network [OSTI]

    Lazaridis, Iosif; Han, Qi; Mehrotra, Sharad; Venkatasubramanian, Nalini

    2009-01-01T23:59:59.000Z

    Evaluation of Continuous Selection Queries over Sensor Dataevaluation of continuous selection queries (CSQs) over sensor-sensor suffices and there is no Fault Tolerant Evaluation of

  9. Aksaray And Ecemis Faults - Diapiric Salt Relationships- Relevance...

    Open Energy Info (EERE)

    Aksaray And Ecemis Faults - Diapiric Salt Relationships- Relevance To The Hydrocarbon Exploration In The Tuz Golu (Salt Lake) Basin, Central Anatolia, Turkey Jump to: navigation,...

  10. Wrench faulting and cavity concentration ; Dollarhide Field, Andrews County, Texas

    E-Print Network [OSTI]

    Dygert, Todd Charles

    1992-01-01T23:59:59.000Z

    structure map for the Devonian horizon 20 7. Seismic time slice taken at 1010 ms 8. Seismic line 190 9. Seismic line 108 10. Seismic line 40 22 25 27 11. Cross-sectional view of a wrench fault 31 12. Pure shear fault model for strike- slip.... The Clearfork horizon was mapped first since it was shallow, strong and continuous. The faults and Devonian horizon were interpreted simultaneously, Adjacent lines were interpreted together throughout the survey to insure consistent fault and horizon picks...

  11. Effects of Volcanism, Crustal Thickness, and Large Scale Faulting...

    Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

    of Volcanism, Crustal Thickness, and Large Scale Faulting on the Development and Evolution of Geothermal Systems: Collaborative Project in Chile Effects of Volcanism, Crustal...

  12. automatic fault management: Topics by E-print Network

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Software Fault Diagnosis by Exploiting Application Signatures Xiaoning Ding - The Ohio - The Ohio State University ABSTRACT Application problem diagnosis in complex...

  13. automatic fault tree: Topics by E-print Network

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Software Fault Diagnosis by Exploiting Application Signatures Xiaoning Ding - The Ohio - The Ohio State University ABSTRACT Application problem diagnosis in complex...

  14. automatical adaptive fault: Topics by E-print Network

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Software Fault Diagnosis by Exploiting Application Signatures Xiaoning Ding - The Ohio - The Ohio State University ABSTRACT Application problem diagnosis in complex...

  15. Recent earthquake sequences at Coso: Evidence for conjugate faulting...

    Open Energy Info (EERE)

    of faulting along conjugate planes. We present results from analyzing an earthquake sequence occurring in 1998 and compare it with a similar sequence that occurred in 1996. The...

  16. Post-Cretaceous faulting at head of Mississippi embayment

    SciTech Connect (OSTI)

    Nelson, W.J. (Illinois State Geological Survey, Champaign, IL (United States)); Harrison, R.W. (Geological Survey, Reston, VA (United States))

    1993-03-01T23:59:59.000Z

    Recent mapping in southernmost Illinois and southeastern Missouri has revealed numerous faults that displace Cretaceous and Tertiary strata. Units as young as the Pliocene-Pleistocene( ) Mounds Gravel are deformed; some faults possibly displace Quaternary sediments. The faults strike northeast, dip nearly vertically, and exhibit characteristics of dextral strike-slip. Pull-apart grabens occur along right-stepping fault strands, they contain chaotically jumbled blocks of Paleozoic, Cretaceous and Tertiary rocks downdropped as much as 800 m relative to wall rocks. Faults at the head of the Mississippi embayment probably originated during Cambrian rifting (Reelfoot rift) and have a long, complex history of reactivation under different stress fields. Some faults are on strike with faults in the New Madrid seismic zone. Kinematics of post-Cretaceous displacements fit the contemporary stress regime of ENE-WSW compression. Similar fault orientations and kinematics, as well as close proximity, suggest a close link between faulting at the head of the embayment and ongoing tectonism in the New Madrid seismic zone.

  17. Recurrent faulting and petroleum accumulation, Cat Creek Anticline, central Montana

    SciTech Connect (OSTI)

    Nelson, W.J. (Illinois State Geological Survey, Champaign (United States))

    1991-06-01T23:59:59.000Z

    The Cat Creek anticline, scene of central Montana's first significant oil discovery, is underlain by a south-dipping high-angle fault (Cat Creek fault) that has undergone several episodes of movement with opposite sense of displacement. Borehole data suggest that the Cat Creek fault originated as a normal fault during Proterozoic rifting concurrent with deposition of the Belt Supergroup. Reverse faulting took place in Late Cambrian time, and again near the end of the Devonian Period. The Devonian episode, coeval with the Antler orogeny, raised the southern block several hundred feet. The southern block remained high through Meramecian time, then began to subside. Post-Atokan, pre-Middle Jurassic normal faulting lowered the southern block as much as 1,500 ft. During the Laramide orogeny (latest Cretaceous-Eocene) the Cat Creek fault underwent as much as 4,000 ft of reverse displacement and a comparable amount of left-lateral displacement. The Cat Creek anticline is a fault-propagation fold; en echelon domes and listric normal faults developed along its crest in response to wrenching. Oil was generated mainly in organic-rich shales of the Heath Formation (upper Chesterian Series) and migrated upward along tectonic fractures into Pennsylvanian, Jurassic, and Cretaceous reservoir rocks in structural traps in en echelon domes. Production has been achieved only from those domes where structural closure was retained from Jurassic through Holocene time.

  18. Direct dating of Eocene reverse faulting in northeastern Tibet using Ar-dating of fault clays and low-temperature thermochronometry

    E-Print Network [OSTI]

    Direct dating of Eocene reverse faulting in northeastern Tibet using Ar-dating of fault clays fault of northeastern Tibet by dating several size fractions of fault gouge clay that represent variable Ma and continued until at least Middle Miocene time and that authigenic clay growth occurred

  19. Evaluation of faulting characteristics and ground acceleration associated with recent movement along the Meers Fault, Southwestern Oklahoma 

    E-Print Network [OSTI]

    Burrell, Richard Dennis

    1997-01-01T23:59:59.000Z

    Exposures. 14 Diagram illustrating the effects of the Meers Fault scarp on stream channel pathways. 16 Tors on the western side of Elk Mountain, 17 Tors in Wichita Mountains known as Twin Rocks . . . 10 Tor Analysis Log utilized during fteld... and the adjacent petroleum rich Anadarko Basin. Moody and Hill (1956) identified the presence of a scarp along a section of the Meers Fault which deforms Quaternary deposits during a study of wrench fault tectonics. However, it was not until further observations...

  20. Treanmission Line Fault Location using Interoperability and Integration of Data and Model 

    E-Print Network [OSTI]

    Dutta, Papiya

    2014-01-10T23:59:59.000Z

    , classify and locate transmission line faults using synchronous samples of voltages and currents captured during fault transients from both ends of the transmission line of interest. The method is tested for several faults simulated on IEEE 118 bus test...

  1. Fault tolerant control of homopolar magnetic bearings and circular sensor arrays 

    E-Print Network [OSTI]

    Li, Ming-Hsiu

    2006-04-12T23:59:59.000Z

    Fault tolerant control can accommodate the component faults in a control system such as sensors, actuators, plants, etc. This dissertation presents two fault tolerant control schemes to accommodate the failures of power ...

  2. A Comparison of Fault Detection Methods For a Transcritical Refrigeration System

    E-Print Network [OSTI]

    Janecke, Alex Karl

    2012-10-19T23:59:59.000Z

    pairings of four faults: over/undercharge, evaporator fouling, gas cooler fouling, and compressor valve leakage. This technique allows for low cost measurement and independent detection of individual faults even when multiple faults are present. Results...

  3. Early Holocene and Late Pleistocene slip rates of the southern Dead Sea Fault determined from 10

    E-Print Network [OSTI]

    Klinger, Yann

    sites located along the Wadi Araba Fault (WAF) segment of the Dead Sea Fault are targeted on the DSF, focusing on the Wadi Araba Fault (WAF) segment (Figure 1b). The WAF strikes N12°E for about 160

  4. Data-Based Monitoring and Fault-Tolerant Control of Nonlinear Processes

    E-Print Network [OSTI]

    Chilin, David

    2012-01-01T23:59:59.000Z

    with a fault in the heat input/removal actuator to vessel 2with a fault in the heat input/removal actuator to vessel 2with a fault in the heat input/removal actuator to vessel 2

  5. Lithium Circuit Test Section Design and Fabrication

    SciTech Connect (OSTI)

    Godfroy, Thomas; Garber, Anne; Martin, James [NASA Marshall Space Flight Center, Nuclear Systems Engineering Analysis, Huntsville, Alabama 35812 (United States)

    2006-01-20T23:59:59.000Z

    The Early Flight Fission -- Test Facilities (EFF-TF) team has designed and built an actively pumped lithium flow circuit. Modifications were made to a circuit originally designed for NaK to enable the use of lithium that included application specific instrumentation and hardware. Component scale freeze/thaw tests were conducted to both gain experience with handling and behavior of lithium in solid and liquid form and to supply anchor data for a Generalized Fluid System Simulation Program (GFSSP) model that was modified to include the physics for freeze/thaw transitions. Void formation was investigated. The basic circuit components include: reactor segment, lithium to gas heat exchanger, electromagnetic (EM) liquid metal pump, load/drain reservoir, expansion reservoir, instrumentation, and trace heaters. This paper discusses the overall system design and build and the component testing findings.

  6. Package for integrated optic circuit and method

    DOE Patents [OSTI]

    Kravitz, Stanley H. (26 Aspen Rd., Placitas, NM 87043); Hadley, G. Ronald (6012 Annapolis NE., Albuquerque, NM 87111); Warren, Mial E. (3825 Mary Ellen NE., Albuquerque, NM 87111); Carson, Richard F. (1036 Jewel Pl. NE., Albuquerque, NM 87123); Armendariz, Marcelino G. (1023 Oro Real NE., Albuquerque, NM 87123)

    1998-01-01T23:59:59.000Z

    A structure and method for packaging an integrated optic circuit. The package comprises a first wall having a plurality of microlenses formed therein to establish channels of optical communication with an integrated optic circuit within the package. A first registration pattern is provided on an inside surface of one of the walls of the package for alignment and attachment of the integrated optic circuit. The package in one embodiment may further comprise a fiber holder for aligning and attaching a plurality of optical fibers to the package and extending the channels of optical communication to the fibers outside the package. In another embodiment, a fiber holder may be used to hold the fibers and align the fibers to the package. The fiber holder may be detachably connected to the package.

  7. Radiation-hardened transistor and integrated circuit

    DOE Patents [OSTI]

    Ma, Kwok K. (Albuquerque, NM)

    2007-11-20T23:59:59.000Z

    A composite transistor is disclosed for use in radiation hardening a CMOS IC formed on an SOI or bulk semiconductor substrate. The composite transistor has a circuit transistor and a blocking transistor connected in series with a common gate connection. A body terminal of the blocking transistor is connected only to a source terminal thereof, and to no other connection point. The blocking transistor acts to prevent a single-event transient (SET) occurring in the circuit transistor from being coupled outside the composite transistor. Similarly, when a SET occurs in the blocking transistor, the circuit transistor prevents the SET from being coupled outside the composite transistor. N-type and P-type composite transistors can be used for each and every transistor in the CMOS IC to radiation harden the IC, and can be used to form inverters and transmission gates which are the building blocks of CMOS ICs.

  8. Electronic circuit for measuring series connected electrochemical cell voltages

    DOE Patents [OSTI]

    Ashtiani, Cyrus N. (West Bloomfield, MI); Stuart, Thomas A. (Toledo, OH)

    2000-01-01T23:59:59.000Z

    An electronic circuit for measuring voltage signals in an energy storage device is disclosed. The electronic circuit includes a plurality of energy storage cells forming the energy storage device. A voltage divider circuit is connected to at least one of the energy storage cells. A current regulating circuit is provided for regulating the current through the voltage divider circuit. A voltage measurement node is associated with the voltage divider circuit for producing a voltage signal which is proportional to the voltage across the energy storage cell.

  9. Circuit breaker monitoring application using wireless communication

    E-Print Network [OSTI]

    Ved, Nitin

    2007-04-25T23:59:59.000Z

    synchronizes recorded data to a global time standard enabling system-wide applications to use the recorded data. ? Ease of installation: The circuit breaker monitoring system can be installed at a substation within minutes by one or two personnel. The system... is powered by a 130V DC source, usually a battery in the substation control house, called the supply volt- age. All elements of the circuit are connected between the positive and the negative terminals of the supply voltage.Another voltage source called...

  10. Electronic Circuit Realization of the Logistic Map

    E-Print Network [OSTI]

    Madhekar Suneel

    2006-03-11T23:59:59.000Z

    An electronic circuit realization of the logistic difference equation is presented using analog electronics. The behavior of the realized system is evaluated against computer simulations of the same. The circuit is found to exhibit the entire range of dynamics of the logistic equation: fixed points, periodicity, period doubling, chaos and intermittency. Quantitative measurements of the dynamics of the realized system are presented and are found to be in good agreement with the theoretical values. Some possible applications of such a realization are briefly discussed.

  11. Research on Fault Analysis and Fault-Tolerant Control of EV/HEV Powertrain

    E-Print Network [OSTI]

    Brest, Université de

    power industries, interests in diagnostics and fault-tolerant control of nuclear power plants have been industrial systems. To achieve these goals, monitoring and supervision are embedded in the electrical energy, FTC has been implemented in sensible applications such as aerospace, nuclear power, automotive

  12. Efficient Fault Tolerance: an Approach to Deal with Transient Faults in Multiprocessor Architectures

    E-Print Network [OSTI]

    Firenze, Università degli Studi di

    , 36, 56126 Pisa, Italy ** IEI/CNR, Via S. Maria, 46, 56126 Pisa, Italy Abstract Dynamic error, while making efficient use of the available resources. To this end, dynamic error processing must is integrated with a mechanism for dynamic error processing in a complete fault tolerance strategy. Reliability

  13. A core-based assessment of the spatial relationship of small faults associated with a basement-controlled, large normal fault in the Hickory Sandstone

    E-Print Network [OSTI]

    Graff, Mitchell C

    2006-10-30T23:59:59.000Z

    Measures of Small Faults??????????????? Page iii v vi viii xiv 1 3 3 5 7 10 10 10 12 14 18 20 26 28 vii 4. ESTIMATING SMALL FAULT DISPLACEMENT USING FAULT GOUGE THICKNESS AND PROTOLITH TEXTURE??????????... 4.1 Previous Work... is proportional to mean?????????????????????. 26 Combined scatterplot of faults with known gouge thickness versus known displacement and faults with known gouge thickness versus estimated displacement????????????????????. Page 37 38 39 40 43 45 47 48...

  14. Fault Analysis at a Wind Power Plant for One Year of Observation: Preprint

    SciTech Connect (OSTI)

    Muljadi, E.; Mills, Z.; Foster, R.; Conto, J.; Ellis, A.

    2008-07-01T23:59:59.000Z

    This paper analyzes the fault characteristics observed at a wind power plant, and the behavior of the wind power plant under fault events.

  15. SciTech Connect: Development of Asset Fault Signatures for Prognostic...

    Office of Scientific and Technical Information (OSTI)

    Development of Asset Fault Signatures for Prognostic and Health Management in the Nuclear Industry Citation Details In-Document Search Title: Development of Asset Fault Signatures...

  16. Automatic Fault Characterization via Abnormality-Enhanced Classification

    SciTech Connect (OSTI)

    Bronevetsky, G; Laguna, I; de Supinski, B R

    2010-12-20T23:59:59.000Z

    Enterprise and high-performance computing systems are growing extremely large and complex, employing hundreds to hundreds of thousands of processors and software/hardware stacks built by many people across many organizations. As the growing scale of these machines increases the frequency of faults, system complexity makes these faults difficult to detect and to diagnose. Current system management techniques, which focus primarily on efficient data access and query mechanisms, require system administrators to examine the behavior of various system services manually. Growing system complexity is making this manual process unmanageable: administrators require more effective management tools that can detect faults and help to identify their root causes. System administrators need timely notification when a fault is manifested that includes the type of fault, the time period in which it occurred and the processor on which it originated. Statistical modeling approaches can accurately characterize system behavior. However, the complex effects of system faults make these tools difficult to apply effectively. This paper investigates the application of classification and clustering algorithms to fault detection and characterization. We show experimentally that naively applying these methods achieves poor accuracy. Further, we design novel techniques that combine classification algorithms with information on the abnormality of application behavior to improve detection and characterization accuracy. Our experiments demonstrate that these techniques can detect and characterize faults with 65% accuracy, compared to just 5% accuracy for naive approaches.

  17. The northwest extension of the Meers Fault in southwestern Oklahoma

    E-Print Network [OSTI]

    Cetin, Hasan

    1991-01-01T23:59:59.000Z

    + t '+ + + ~et t 30 mt ~ 39 ~ 40 mt ~ 49 a 50 mt 59 060 m& 69 O20 mts29 26 26 ASZ ? ANNA SEISMIC ZONE ES ? ENOLA SWARM KRF ? KENTUCKY RIVER FAULT MF ? MEERS FAULT MU ? MONROE UPLIFT NM ? NEW MADRID NU ? NEMAHA UPLIFT PSD ? PIERRE, SOUTH DAKOTA WVF...

  18. An Information Flow Model of Fault Detection Margaret C. Thompson ?

    E-Print Network [OSTI]

    Massachusetts at Amherst, University of

    not be practical. Nonethe­ less, Relay provides insight into testing and fault de­ tection and suggests an approach and Computer Science Amherst, MA 01003 University of California Irvine, CA 92717 Abstract Relay is a model of how a fault causes a failure on execution of some test datum. This process begins with introduction

  19. Fault Tolerant Oxygen Control of a Diesel Engine Air System

    E-Print Network [OSTI]

    Paris-Sud XI, Université de

    Fault Tolerant Oxygen Control of a Diesel Engine Air System Rainer Nitsche Matthias Bitzer control problem of a Diesel engine air system having a jammed Exhaust Gas Recirculation (EGR) valve of the air system. Keywords: Fault tolerant control, Diesel engine, Air system, Model-based trajectory

  20. All-to-all sequenced fault detection system

    DOE Patents [OSTI]

    Archer, Charles Jens (Rochester, MN); Pinnow, Kurt Walter (Rochester, MN); Ratterman, Joseph D. (Rochester, MN); Smith, Brian Edward (Rochester, MN)

    2010-11-02T23:59:59.000Z

    An apparatus, program product and method enable nodal fault detection by sequencing communications between all system nodes. A master node may coordinate communications between two slave nodes before sequencing to and initiating communications between a new pair of slave nodes. The communications may be analyzed to determine the nodal fault.

  1. Fault Detection, Identification and Accommodation for an Electro-hydraulic

    E-Print Network [OSTI]

    Yao, Bin

    Fault Detection, Identification and Accommodation for an Electro-hydraulic System: An Adaptive in electro-hydraulic systems. It is well known fact that any realistic model of a hydraulic system suffers, such a scheme becomes a natural choice for designing robust fault detection algorithms for electro-hydraulic

  2. Stator current demodulation for induction machine rotor faults diagnosis

    E-Print Network [OSTI]

    Boyer, Edmond

    with emphasis on stator current processing [1], [2]. It has been proven that mechanical and electrical faultsStator current demodulation for induction machine rotor faults diagnosis El Houssin El Bouchikhi of the stator currents. Hence, demodulation of the stator currents is of high interest for induction machines

  3. Fuzzy Pattern Recognition Based Fault Diagnosis Rafik Bensaadi1

    E-Print Network [OSTI]

    Boyer, Edmond

    Fuzzy Pattern Recognition Based Fault Diagnosis Rafik Bensaadi1 , Leïla H. Mouss1 , Mohamed D in this paper the design of a Fuzzy Pattern Recognition System (FPRS) that solves, in real time, the main. Keywords: Diagnosis, fault detection, pattern recognition, fuzzy control, conjugate gradients, complex

  4. Symbolic identification for fault detection in aircraft gas turbine engines

    E-Print Network [OSTI]

    Ray, Asok

    Symbolic identification for fault detection in aircraft gas turbine engines S Chakraborty, S Sarkar and computationally inexpensive technique of component-level fault detection in aircraft gas-turbine engines identification, gas turbine engines, language-theoretic analysis 1 INTRODUCTION The propulsion system of modern

  5. Online Fault Detection and Tolerance for Photovoltaic Energy Harvesting Systems

    E-Print Network [OSTI]

    Pedram, Massoud

    and weather conditions (e.g., clouds), and the output power of PV systems is directly dependent on solar and mitigate the output power shortage under low levels of solar irradiance. Moreover, PV panels exhibit highly fault detection and tolerance. Our fault detection and tolerance technique reduces output power

  6. Triassic/Jurassic faulting patterns of Conecuh Ridge, southwest Alabama

    SciTech Connect (OSTI)

    Hutley, J.K.

    1985-02-01T23:59:59.000Z

    Two major fault systems influenced Jurassic structure and deposition on the Conecuh Ridge, southwest Alabama. Identification and dating of these fault systems are based on seismic-stratigraphic interpretation of a 7-township grid in Monroe and Conecuh Counties. Relative time of faulting is determined by fault geometry and by formation isopachs and isochrons. Smackover and Norphlet Formations, both Late Jurassic in age, are mappable seismic reflectors and are thus reliable for seismicstratigraphic dating. The earlier of the 2 fault systems is a series of horsts and grabens that trends northeast-southwest and is Late Triassic to Early Jurassic in age. The system formed in response to tensional stress associated with the opening of the Atlantic Ocean. The resulting topography was a series of northeast-southwest-trending ridges. Upper Triassic Eagle Mills and Jurassic Werner Formations were deposited in the grabens. The later fault system is also a series of horsts and grabens trending perpendicular to the first. This system was caused by tensional stress related to a pulse in the opening of the Gulf of Mexico. Faulting began in Early Jurassic and continued into Late Jurassic, becoming progressively younger basinward. At the basin margin, faulting produced a very irregular shoreline. Submerged horst blocks became centers for shoaling or carbonate buildups. Today, these blocks are exploration targets in southwest Alabama.

  7. Using Reinforcement Learning for Proactive Network Fault Management

    E-Print Network [OSTI]

    Shayman, Mark A.

    fault management demands intelligent man­ agement actions be taken by central manager or remote agents.g., alarms) which appear sequentially. For example, on the manager's side, polling devices randomly (orUsing Reinforcement Learning for Proactive Network Fault Management Qiming He, Mark A. Shayman

  8. Diagonal quantum circuits: their computational power and applications

    E-Print Network [OSTI]

    Yoshifumi Nakata; Mio Murao

    2014-08-04T23:59:59.000Z

    Diagonal quantum circuits are quantum circuits comprising only diagonal gates in the computational basis. In spite of a classical feature of diagonal quantum circuits in the sense of commutativity of all gates, their computational power is highly likely to outperform classical one and they are exploited for applications in quantum informational tasks. We review computational power of diagonal quantum circuits and their applications. We focus on the computational power of instantaneous quantum polynomial-time (IQP) circuits, which are a special type of diagonal quantum circuits. We then review an approximate generation of random states as an application of diagonal quantum circuits, where random states are an ensemble of pure states uniformly distributed in a Hilbert space. We also present a thermalizing algorithm of classical Hamiltonians by using diagonal quantum circuits. These applications are feasible to be experimentally implemented by current technology due to a simple and robust structure of diagonal gates.

  9. Regulation of mammalian neuronal circuit development by CPG 15

    E-Print Network [OSTI]

    Leslie, Jennifer H

    2012-01-01T23:59:59.000Z

    The orderly assembly of neuronal circuits is specified by developmental programs of gene expression, however, the final stage in circuit development, maturation and refinement of specific synaptic connections, is strongly ...

  10. accurate analog circuits: Topics by E-print Network

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    The total size of each centroid circuit is 160m x 160m in a standard 1.2-m CMOS process. Paul M. Furth; Natalie Clark 1998-01-01 6 Low voltage analog circuit design...

  11. analog circuits macromodel: Topics by E-print Network

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    The total size of each centroid circuit is 160m x 160m in a standard 1.2-m CMOS process. Paul M. Furth; Natalie Clark 1998-01-01 7 Low voltage analog circuit design...

  12. analog linear circuits: Topics by E-print Network

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    The total size of each centroid circuit is 160m x 160m in a standard 1.2-m CMOS process. Paul M. Furth; Natalie Clark 1998-01-01 10 Low voltage analog circuit design...

  13. A Taxonomy of Rerouting in Circuit-Switched Networks

    E-Print Network [OSTI]

    Wong, Eric Wing-Ming

    A Taxonomy of Rerouting in Circuit-Switched Networks Eric W. M. Wong and Andy K. M. Chan, City presents a taxonomy of rerouting in circuit- switched networks showing the various ways rerouting can

  14. 6.301 Solid-State Circuits, Spring 2003

    E-Print Network [OSTI]

    Roberge, James

    This course covers analog circuit analysis and design, focusing on the tools and methods necessary for the creative design of useful circuits using active devices. The class stresses insight and intuition, applied to the ...

  15. Cryogenic direct current superconducting quantum interference device readout circuit

    E-Print Network [OSTI]

    Le Roy, Robert J.

    Cryogenic direct current superconducting quantum interference device readout circuit Michael Mück SQUID readout circuit, which can be operated at liquid helium temperatures. Although room electronics, and feedback coil as short as possible to minimize phase shifts and time delays. Cooling

  16. Protecting Circuits from Computationally Bounded and Noisy Leakage

    E-Print Network [OSTI]

    Faust, Sebastian

    Physical computational devices leak side-channel information that may, and often does, reveal secret internal states. We present a general transformation that compiles any circuit into a circuit with the same functionality ...

  17. IMPACT OF DYNAMIC VOLTAGE SCALING (DVS) ON CIRCUIT OPTIMIZATION

    E-Print Network [OSTI]

    Esquit Hernandez, Carlos A.

    2010-01-16T23:59:59.000Z

    Circuit designers perform optimization procedures targeting speed and power during the design of a circuit. Gate sizing can be applied to optimize for speed, while Dual-VT and Dynamic Voltage Scaling (DVS) can be applied to optimize for leakage...

  18. IMPACT OF DYNAMIC VOLTAGE SCALING (DVS) ON CIRCUIT OPTIMIZATION 

    E-Print Network [OSTI]

    Esquit Hernandez, Carlos A.

    2010-01-16T23:59:59.000Z

    Circuit designers perform optimization procedures targeting speed and power during the design of a circuit. Gate sizing can be applied to optimize for speed, while Dual-VT and Dynamic Voltage Scaling (DVS) can be applied ...

  19. Development of Hydrologic Characterization Technology of Fault Zones

    SciTech Connect (OSTI)

    Karasaki, Kenzi; Onishi, Tiemi; Wu, Yu-Shu

    2008-03-31T23:59:59.000Z

    Through an extensive literature survey we find that there is very limited amount of work on fault zone hydrology, particularly in the field using borehole testing. The common elements of a fault include a core, and damage zones. The core usually acts as a barrier to the flow across it, whereas the damage zone controls the flow either parallel to the strike or dip of a fault. In most of cases the damage zone isthe one that is controlling the flow in the fault zone and the surroundings. The permeability of damage zone is in the range of two to three orders of magnitude higher than the protolith. The fault core can have permeability up to seven orders of magnitude lower than the damage zone. The fault types (normal, reverse, and strike-slip) by themselves do not appear to be a clear classifier of the hydrology of fault zones. However, there still remains a possibility that other additional geologic attributes and scaling relationships can be used to predict or bracket the range of hydrologic behavior of fault zones. AMT (Audio frequency Magneto Telluric) and seismic reflection techniques are often used to locate faults. Geochemical signatures and temperature distributions are often used to identify flow domains and/or directions. ALSM (Airborne Laser Swath Mapping) or LIDAR (Light Detection and Ranging) method may prove to be a powerful tool for identifying lineaments in place of the traditional photogrammetry. Nonetheless not much work has been done to characterize the hydrologic properties of faults by directly testing them using pump tests. There are some uncertainties involved in analyzing pressure transients of pump tests: both low permeability and high permeability faults exhibit similar pressure responses. A physically based conceptual and numerical model is presented for simulating fluid and heat flow and solute transport through fractured fault zones using a multiple-continuum medium approach. Data from the Horonobe URL site are analyzed to demonstrate the proposed approach and to examine the flow direction and magnitude on both sides of a suspected fault. We describe a strategy for effective characterization of fault zone hydrology. We recommend conducting a long term pump test followed by a long term buildup test. We do not recommend isolating the borehole into too many intervals. We do recommend ensuring durability and redundancy for long term monitoring.

  20. Count-doubling time safety circuit

    DOE Patents [OSTI]

    Rusch, Gordon K. (Downers Grove, IL); Keefe, Donald J. (Lemont, IL); McDowell, William P. (Downers Grove, IL)

    1981-01-01T23:59:59.000Z

    There is provided a nuclear reactor count-factor-increase time monitoring circuit which includes a pulse-type neutron detector, and means for counting the number of detected pulses during specific time periods. Counts are compared and the comparison is utilized to develop a reactor scram signal, if necessary.

  1. An intuitive approach to quantum circuit simulation

    E-Print Network [OSTI]

    Sensarn, Steven

    2013-02-22T23:59:59.000Z

    for beginners in the field. A student may better understand an algorithm by visualizing each step and observing the state of the system over time. While there are many representations of a quantum algorithm, perhaps the most intuitive is the quantum circuit...

  2. Quantum computer of wire circuit architecture

    E-Print Network [OSTI]

    S. A. Moiseev; F. F. Gubaidullin; S. N. Andrianov

    2010-01-07T23:59:59.000Z

    First solid state quantum computer was built using transmons (cooper pair boxes). The operation of the computer is limited because of using a number of the rigit cooper boxes working with fixed frequency at temperatures of superconducting material. Here, we propose a novel architecture of quantum computer based on a flexible wire circuit of many coupled quantum nodes containing controlled atomic (molecular) ensembles. We demonstrate wide opportunities of the proposed computer. Firstly, we reveal a perfect storage of external photon qubits to multi-mode quantum memory node and demonstrate a reversible exchange of the qubits between any arbitrary nodes. We found optimal parameters of atoms in the circuit and self quantum modes for quantum processing. The predicted perfect storage has been observed experimentally for microwave radiation on the lithium phthalocyaninate molecule ensemble. Then also, for the first time we show a realization of the efficient basic two-qubit gate with direct coupling of two arbitrary nodes by using appropriate atomic frequency shifts in the circuit nodes. Proposed two-qubit gate runs with a speed drastically accelerated proportionally to the number of atoms in the node. The direct coupling and accelerated two-qubit gate can be realized for large number of the circuit nodes. Finally, we describe two and three-dimensional scalable architectures that pave the road to construction of universal multi-qubit quantum computer operating at room temperatures.

  3. Dendritic processing within olfactory bulb circuits

    E-Print Network [OSTI]

    Betz, William J.

    Dendritic processing within olfactory bulb circuits Nathan E. Schoppa1 and Nathan N. Urban2 1 of the olfactory bulb. How- ever, the mechanisms by which this map is transformed into an odor code by the bulb circuitry remain unclear. Recent physiological studies in bulb slices have ident- ified several synaptic

  4. Bioluminescent bioreporter integrated circuit detection methods

    DOE Patents [OSTI]

    Simpson, Michael L.; Paulus, Michael J.; Sayler, Gary S.; Applegate, Bruce M.; Ripp, Steven A.

    2005-06-14T23:59:59.000Z

    Disclosed are monolithic bioelectronic devices comprising a bioreporter and an OASIC. These bioluminescent bioreporter integrated circuit are useful in detecting substances such as pollutants, explosives, and heavy-metals residing in inhospitable areas such as groundwater, industrial process vessels, and battlefields. Also disclosed are methods and apparatus for detection of particular analytes, including ammonia and estrogen compounds.

  5. ECE 2100 Circuit Analysis Spring 2011

    E-Print Network [OSTI]

    Miller, Damon A.

    ECE 2100 Circuit Analysis Spring 2011 Exam #1 NAME analysis. #12;© 2011 Damon A. Miller Schematics drawn using LTspice IV (linear.com). Some problems might Schematics drawn using LTspice IV (linear.com). Some problems might be adapted from the course text

  6. Analysis of S-Circuit Uncertainty

    E-Print Network [OSTI]

    Ahmed, Taahir

    2011-08-08T23:59:59.000Z

    INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 viii LIST OF FIGURES FIGURE Page 1 Explanatory figures for Donald?s s-circuit example. . . . . . . . . . . . . 9 2 A representational s... Digraph representations of Donald?s beacon-compass reconfiguration and beacon-only reconfiguration. . . . . . . . . . . . . . . . . . . . . . . . . 30 8 The hardware implementations of the beacon emitter and receiver. . . . . 33 9 The hardware...

  7. Dual-circuit segmented rail phased induction motor

    DOE Patents [OSTI]

    Marder, Barry M. (Albuquerque, NM); Cowan, Jr., Maynard (Albuquerque, NM)

    2002-01-01T23:59:59.000Z

    An improved linear motor utilizes two circuits, rather that one circuit and an opposed plate, to gain efficiency. The powered circuit is a flat conductive coil. The opposed segmented rail circuit is either a plurality of similar conductive coils that are shorted, or a plurality of ladders formed of opposed conductive bars connected by a plurality of spaced conductors. In each embodiment, the conductors are preferably cables formed from a plurality of intertwined insulated wires to carry current evenly.

  8. Trust in analog : analog circuit techniques for reducing the risk of malicious circuits and software

    E-Print Network [OSTI]

    Kuznetsov, Eugene

    2011-01-01T23:59:59.000Z

    Malicious circuits and software present a significant security risk, especially in control applications. This work is concerned with increasing the trustworthiness of control circuitry by reducing its complexity. The ...

  9. Circuit design for embedded memory in low-power integrated circuits

    E-Print Network [OSTI]

    Qazi, Masood

    2012-01-01T23:59:59.000Z

    This thesis explores the challenges for integrating embedded static random access memory (SRAM) and non-volatile memory-based on ferroelectric capacitor technology-into lowpower integrated circuits. First considered is the ...

  10. EEE 334 Circuits II (4) [F, S] Course (Catalog) description

    E-Print Network [OSTI]

    Zhang, Junshan

    : EEE334 contributes to engineering science through linear and non-linear circuit analysis, problem Prerequisites by Topic: Circuits I Course Objectives: Application of electric network theory to analysis and design of the fundamental non- linear circuits of transistor electronics. Course Outcomes: 1. Apply

  11. Foundations for a Circuit Complexity Theory of Sensory Processing

    E-Print Network [OSTI]

    Maass, Wolfgang

    with linear or almost linear total wire length. 1 Introduction Circuit complexity theory is a classical area in neuromorphic engineering, especially analog VLSI, and the analysis of neural circuits in biological organisms modules'' (i.e., as gates) in our complexity analysis. #12; plexity measures in traditional circuit

  12. Timed Verification of the Generic Architecture of a Memory Circuit

    E-Print Network [OSTI]

    Encrenaz-Tiphène, Emmanuelle

    #cient linear constraints relating the delays of the internal gates of the circuit to the exter­ nal delays on the reachability analysis of a timed model of the circuit (with additional abstract interpretation techniques [10Timed Verification of the Generic Architecture of a Memory Circuit Using Parametric Timed Automata

  13. Verification of the Generic Architecture of a Memory Circuit

    E-Print Network [OSTI]

    Encrenaz-Tiphène, Emmanuelle

    -Cortadella's parametric method for verifying asynchronous circuits, we formally derive a set of linear constraints of sufficient linear constraints relating the delays of the internal gates of the circuit to the external delays on the reachability analysis of a timed model of the circuit (with additional abstract interpretation techniques [11

  14. Circuit Complexity and Multiplicative Complexity of Boolean Functions

    E-Print Network [OSTI]

    no example of an explicit function requiring super linear circuit size. Moreover, only a few proofs of linear (usually by a long case analysis) that for any circuit computing this function setting some variablesCircuit Complexity and Multiplicative Complexity of Boolean Functions Arist Kojevnikov1

  15. Boullier The fault zone geology 1 Fault zone geology: lessons from drilling through the Nojima and 1

    E-Print Network [OSTI]

    Paris-Sud XI, Université de

    drilling through the Nojima and 1 Chelungpu faults 2 3 Anne-Marie Boullier 4-Marie.Boullier@obs.ujf-grenoble.fr 8 9 Abstract 10 Several drilling projects have been conducted through significant topics 32 for future research, one of which was "fault zone drilling

  16. Boullier The fault zone geology 1 Fault zone geology: lessons from drilling through the Nojima and 1

    E-Print Network [OSTI]

    Boyer, Edmond

    drilling through the Nojima and 1 Chelungpu faults 2 3 Anne-Marie Boullier 4-Marie.Boullier@obs.ujf-grenoble.fr 8 9 Abstract 10 Several drilling projects have been conducted through was "fault zone drilling combined with surface-based 33 geophysical and geological

  17. Rupture Dynamics of Strike-Slip Faults with Stepovers: From Conceptually Simplified to Realistically Complex Fault Systems

    E-Print Network [OSTI]

    Liu, Zaifeng

    2014-05-05T23:59:59.000Z

    , the Aksay double-bend in the Altyn Tagh fault, and its ability to stop the dynamic rupture. A detailed parameter-space study has been performed in the simplified model. From the single fault test, I find that the Positive Coulomb Stress (PCS) region...

  18. Feb. 11, 2008 Advanced Fault Tolerance Solutions for High Performance Computing 1/47 Advanced Fault Tolerance Solutions

    E-Print Network [OSTI]

    Engelmann, Christian

    Feb. 11, 2008 Advanced Fault Tolerance Solutions for High Performance Computing 1/47 RAS RAS Advanced Fault Tolerance Solutions for High Performance Computing Christian Engelmann Oak Ridge National Solutions for High Performance Computing 2/47 · Nation's largest energy laboratory · Nation's largest

  19. Acceleration and evolution of faults: An example from the Hunter MountainPanamint Valley fault zone, Eastern California

    E-Print Network [OSTI]

    Amelung, Falk

    : R.D. van der Hilst Keywords: geodesy fault evolution InSAR rock mechanics Western United States assumes a monotonic increase in slip rate with time as the fault matures and straightens. The rate. However, before this can be realized, we need to better understand the various sources for discrepancies

  20. Detection and removal of functional redundancy in multi-level logic circuits

    E-Print Network [OSTI]

    Dorsey, David Michael

    2013-02-22T23:59:59.000Z

    circuit. This research will focus on finding non-traditional methods for minimizing multi-level logic circuits....

  1. Advanced Non-Krylov Subspace Model Order Reduction Techniques for Interconnect Circuits

    E-Print Network [OSTI]

    Yan, Boyuan

    2009-01-01T23:59:59.000Z

    Freund. Efficient linear circuit analysis by Pade approxima-for reduced order analysis of linear circuit with multiple

  2. High density printed electrical circuit board card connection system

    DOE Patents [OSTI]

    Baumbaugh, Alan E. (Aurora, IL)

    1997-01-01T23:59:59.000Z

    A zero insertion/extraction force printed circuit board card connection system comprises a cam-operated locking mechanism disposed along an edge portion of the printed circuit board. The extrusions along the circuit board mate with an extrusion fixed to the card cage having a plurality of electrical connectors. The card connection system allows the connectors to be held away from the circuit board during insertion/extraction and provides a constant mating force once the circuit board is positioned. The card connection system provides a simple solution to the need for a greater number of electrical signal connections.

  3. Development of Characterization Technology for Fault Zone Hydrology

    SciTech Connect (OSTI)

    Karasaki, Kenzi; Onishi, Tiemi; Gasperikova, Erika; Goto, Junichi; Tsuchi, Hiroyuki; Miwa, Tadashi; Ueta, Keiichi; Kiho, Kenzo; MIyakawa, Kimio

    2010-08-06T23:59:59.000Z

    Several deep trenches were cut, and a number of geophysical surveys were conducted across the Wildcat Fault in the hills east of Berkeley, California. The Wildcat Fault is believed to be a strike-slip fault and a member of the Hayward Fault System, with over 10 km of displacement. So far, three boreholes of ~;; 150m deep have been core-drilled and borehole geophysical logs were conducted. The rocks are extensively sheared and fractured; gouges were observed at several depths and a thick cataclasitic zone was also observed. While confirming some earlier, published conclusions from shallow observations about Wildcat, some unexpected findings were encountered. Preliminary analysis indicates that Wildcat near the field site consists of multiple faults. The hydraulic test data suggest the dual properties of the hydrologic structure of the fault zone. A fourth borehole is planned to penetrate the main fault believed to lie in-between the holes. The main philosophy behind our approach for the hydrologic characterization of such a complex fractured system is to let the system take its own average and monitor a long term behavior instead of collecting a multitude of data at small length and time scales, or at a discrete fracture scale and to ?up-scale,? which is extremely tenuous.

  4. Opportunistic Transient-Fault Detection Mohamed A. Gomaa and T. N. Vijaykumar

    E-Print Network [OSTI]

    Vijaykumar, T. N.

    Opportunistic Transient-Fault Detection Mohamed A. Gomaa and T. N. Vijaykumar School of Electrical susceptibility of microprocessors to transient faults. Most current proposals for transient-fault detection use redundancy by exploiting reuse's implicit redundancy within the main thread for fault detection with vir

  5. Analysis of the growth of strike-slip faults using effective medium theory

    SciTech Connect (OSTI)

    Aydin, A.; Berryman, J.G.

    2009-10-15T23:59:59.000Z

    Increases in the dimensions of strike-slip faults including fault length, thickness of fault rock and the surrounding damage zone collectively provide quantitative definition of fault growth and are commonly measured in terms of the maximum fault slip. The field observations indicate that a common mechanism for fault growth in the brittle upper crust is fault lengthening by linkage and coalescence of neighboring fault segments or strands, and fault rock-zone widening into highly fractured inner damage zone via cataclastic deformation. The most important underlying mechanical reason in both cases is prior weakening of the rocks surrounding a fault's core and between neighboring fault segments by faulting-related fractures. In this paper, using field observations together with effective medium models, we analyze the reduction in the effective elastic properties of rock in terms of density of the fault-related brittle fractures and fracture intersection angles controlled primarily by the splay angles. Fracture densities or equivalent fracture spacing values corresponding to the vanishing Young's, shear, and quasi-pure shear moduli were obtained by extrapolation from the calculated range of these parameters. The fracture densities or the equivalent spacing values obtained using this method compare well with the field data measured along scan lines across the faults in the study area. These findings should be helpful for a better understanding of the fracture density/spacing distribution around faults and the transition from discrete fracturing to cataclastic deformation associated with fault growth and the related instabilities.

  6. Potential-induced degradation in solar cells: Electronic structure and diffusion mechanism of sodium in stacking faults of silicon

    SciTech Connect (OSTI)

    Ziebarth, Benedikt, E-mail: Benedikt.Ziebarth@iwm.fraunhofer.de; Gumbsch, Peter [Fraunhofer Institut für Werkstoffmechanik IWM, Wöhlerstr. 11, 79108 Freiburg (Germany); Karlsruher Institut für Technologie, Institut für Ausgewandte Materialien (IAM-ZBS), Engelbert-Arnold-Str. 4, 76131 Karlsruhe (Germany); Mrovec, Matous; Elsässer, Christian [Fraunhofer Institut für Werkstoffmechanik IWM, Wöhlerstr. 11, 79108 Freiburg (Germany)

    2014-09-07T23:59:59.000Z

    Sodium decorated stacking faults (SFs) were recently identified as the primary cause of potential-induced degradation in silicon (Si) solar-cells due to local electrical short-circuiting of the p-n junctions. In the present study, we investigate these defects by first principles calculations based on density functional theory in order to elucidate their structural, thermodynamic, and electronic properties. Our calculations show that the presence of sodium (Na) atoms leads to a substantial elongation of the Si-Si bonds across the SF, and the coverage and continuity of the Na layer strongly affect the diffusion behavior of Na within the SF. An analysis of the electronic structure reveals that the presence of Na in the SF gives rise to partially occupied defect levels within the Si band gap that participate in electrical conduction along the SF.

  7. Locating hardware faults in a parallel computer

    DOE Patents [OSTI]

    Archer, Charles J.; Megerian, Mark G.; Ratterman, Joseph D.; Smith, Brian E.

    2010-04-13T23:59:59.000Z

    Locating hardware faults in a parallel computer, including defining within a tree network of the parallel computer two or more sets of non-overlapping test levels of compute nodes of the network that together include all the data communications links of the network, each non-overlapping test level comprising two or more adjacent tiers of the tree; defining test cells within each non-overlapping test level, each test cell comprising a subtree of the tree including a subtree root compute node and all descendant compute nodes of the subtree root compute node within a non-overlapping test level; performing, separately on each set of non-overlapping test levels, an uplink test on all test cells in a set of non-overlapping test levels; and performing, separately from the uplink tests and separately on each set of non-overlapping test levels, a downlink test on all test cells in a set of non-overlapping test levels.

  8. Steps toward fault-tolerant quantum chemistry.

    SciTech Connect (OSTI)

    Taube, Andrew Garvin

    2010-05-01T23:59:59.000Z

    Developing quantum chemistry programs on the coming generation of exascale computers will be a difficult task. The programs will need to be fault-tolerant and minimize the use of global operations. This work explores the use a task-based model that uses a data-centric approach to allocate work to different processes as it applies to quantum chemistry. After introducing the key problems that appear when trying to parallelize a complicated quantum chemistry method such as coupled-cluster theory, we discuss the implications of that model as it pertains to the computational kernel of a coupled-cluster program - matrix multiplication. Also, we discuss the extensions that would required to build a full coupled-cluster program using the task-based model. Current programming models for high-performance computing are fault-intolerant and use global operations. Those properties are unsustainable as computers scale to millions of CPUs; instead one must recognize that these systems will be hierarchical in structure, prone to constant faults, and global operations will be infeasible. The FAST-OS HARE project is introducing a scale-free computing model to address these issues. This model is hierarchical and fault-tolerant by design, allows for the clean overlap of computation and communication, reducing the network load, does not require checkpointing, and avoids the complexity of many HPC runtimes. Development of an algorithm within this model requires a change in focus from imperative programming to a data-centric approach. Quantum chemistry (QC) algorithms, in particular electronic structure methods, are an ideal test bed for this computing model. These methods describe the distribution of electrons in a molecule, which determine the properties of the molecule. The computational cost of these methods is high, scaling quartically or higher in the size of the molecule, which is why QC applications are major users of HPC resources. The complexity of these algorithms means that MPI alone is insufficient to achieve parallel scaling; QC developers have been forced to use alternative approaches to achieve scalability and would be receptive to radical shifts in the programming paradigm. Initial work in adapting the simplest QC method, Hartree-Fock, to this the new programming model indicates that the approach is beneficial for QC applications. However, the advantages to being able to scale to exascale computers are greatest for the computationally most expensive algorithms; within QC these are the high-accuracy coupled-cluster (CC) methods. Parallel coupledcluster programs are available, however they are based on the conventional MPI paradigm. Much of the effort is spent handling the complicated data dependencies between the various processors, especially as the size of the problem becomes large. The current paradigm will not survive the move to exascale computers. Here we discuss the initial steps toward designing and implementing a CC method within this model. First, we introduce the general concepts behind a CC method, focusing on the aspects that make these methods difficult to parallelize with conventional techniques. Then we outline what is the computational core of the CC method - a matrix multiply - within the task-based approach that the FAST-OS project is designed to take advantage of. Finally we outline the general setup to implement the simplest CC method in this model, linearized CC doubles (LinCC).

  9. Self field triggered superconducting fault current limiter

    DOE Patents [OSTI]

    Tekletsadik, Kasegn D. (Rexford, NY)

    2008-02-19T23:59:59.000Z

    A superconducting fault current limiter array with a plurality of superconductor elements arranged in a meanding array having an even number of supconductors parallel to each other and arranged in a plane that is parallel to an odd number of the plurality of superconductors, where the odd number of supconductors are parallel to each other and arranged in a plane that is parallel to the even number of the plurality of superconductors, when viewed from a top view. The even number of superconductors are coupled at the upper end to the upper end of the odd number of superconductors. A plurality of lower shunt coils each coupled to the lower end of each of the even number of superconductors and a plurality of upper shunt coils each coupled to the upper end of each of the odd number of superconductors so as to generate a generally orthoganal uniform magnetic field during quenching using only the magenetic field generated by the superconductors.

  10. A Docking Casette For Printed Circuit Boards

    DOE Patents [OSTI]

    Barringer, Dennis R. (Wallkill, NY); Seminaro, Edward J. (Milton, NY); Toffler, Harold M. (Newburgh, NY)

    2003-08-19T23:59:59.000Z

    A docking apparatus for printed circuit boards including a cassette housing, having a housing base, a housing cover and a housing wall, wherein the housing base and the housing wall are disposed relative to each other so as to define a housing cavity for containing a printed circuit board and wherein the housing wall includes a cable opening disposed so as to be communicated with the housing cavity, a linkage mechanism, wherein the linkage mechanism includes an engagement configuration and a disengagement configuration and wherein the linkage mechanism is disposed so as to be associated with the cassette housing and a housing bezel, wherein the housing bezel is disposed relative to the cassette housing so as to be associated with the cable opening.

  11. TRIAC/SCR proportional control circuit

    DOE Patents [OSTI]

    Hughes, Wallace J. (Boston Lake, NY)

    1999-01-01T23:59:59.000Z

    A power controller device which uses a voltage-to-frequency converter in conjunction with a zero crossing detector to linearly and proportionally control AC power being supplied to a load. The output of the voltage-to frequency converter controls the "reset" input of a R-S flip flop, while an "0" crossing detector controls the "set" input. The output of the flip flop triggers a monostable multivibrator controlling the SCR or TRIAC firing circuit connected to the load. Logic gates prevent the direct triggering of the multivibrator in the rare instance where the "reset" and "set" inputs of the flip flop are in coincidence. The control circuit can be supplemented with a control loop, providing compensation for line voltage variations.

  12. TRIAC/SCR proportional control circuit

    DOE Patents [OSTI]

    Hughes, W.J.

    1999-04-06T23:59:59.000Z

    A power controller device is disclosed which uses a voltage-to-frequency converter in conjunction with a zero crossing detector to linearly and proportionally control AC power being supplied to a load. The output of the voltage-to frequency converter controls the ``reset`` input of a R-S flip flop, while an ``0`` crossing detector controls the ``set`` input. The output of the flip flop triggers a monostable multivibrator controlling the SCR or TRIAC firing circuit connected to the load. Logic gates prevent the direct triggering of the multivibrator in the rare instance where the ``reset`` and ``set`` inputs of the flip flop are in coincidence. The control circuit can be supplemented with a control loop, providing compensation for line voltage variations. 9 figs.

  13. Fault-tree construction and calculations on a microcomputer

    E-Print Network [OSTI]

    Beckmann, Jeffery Linn

    1985-01-01T23:59:59.000Z

    Figure 17 - Program Overview Screen Figure 18 ? Main Menu Screen Figure 19 ? Invalid Command Screen Figure 20 - First Usage of Disk Screen Figure 21 ? Fault-tree Name Screen Figure 22 - Invalid Fault-tree Name Screen Fi gure 23 ? TOP EVENT Label... to do? Fi gure 19. Inval i d Command Screen 53 CREATE - This command allows the user to build a new fault tree. After a CREATE command is entered, the system wi 1 1 display the screen in Figure 20. This question is asked in order to determine...

  14. Visualization of stacking faults in fcc crystals in plastic deformations

    E-Print Network [OSTI]

    Takeshi Kawasaki; Akira Onuki

    2011-11-27T23:59:59.000Z

    Using molecular dynamics simulation, we investigate the dynamics of stacking faults in fcc crystals in uniaxial stretching in a Lennard-Jones binary mixture composed of 4096 particles in three dimensions. We visualize stacking faults using a disorder variable $D_j(t)$ for each particle $j$ constructed from local bond order parameters based on spherical harmonics (Steinhardt order parameters). Also introducing a method of bond breakage, we examine how stacking faults are formed and removed by collective particle motions. These processes are relevant in plasticity of fcc crystals.

  15. Fault-tree construction and calculations on a microcomputer 

    E-Print Network [OSTI]

    Beckmann, Jeffery Linn

    1985-01-01T23:59:59.000Z

    Figure 17 - Program Overview Screen Figure 18 ? Main Menu Screen Figure 19 ? Invalid Command Screen Figure 20 - First Usage of Disk Screen Figure 21 ? Fault-tree Name Screen Figure 22 - Invalid Fault-tree Name Screen Fi gure 23 ? TOP EVENT Label... to do? Fi gure 19. Inval i d Command Screen 53 CREATE - This command allows the user to build a new fault tree. After a CREATE command is entered, the system wi 1 1 display the screen in Figure 20. This question is asked in order to determine...

  16. Quantum Heat Engines Using Superconducting Quantum Circuits

    E-Print Network [OSTI]

    H. T. Quan; Y. D. Wang; Yu-xi Liu; C. P. Sun; Franco Nori

    2006-09-14T23:59:59.000Z

    We propose a quantum analog of the internal combustion engine used in most cars. Specifically, we study how to implement the Otto-type quantum heat engine (QHE) with the assistance of a Maxwell's demon. Three steps are required: thermalization, quantum measurement, and quantum feedback controlled by the Maxwell demon. We derive the positive-work condition of this composite QHE. Our QHE can be constructed using superconducting quantum circuits. We explicitly demonstrate the essential role of the demon in this macroscopic QHE.

  17. Dynamic leakage of faults during differential depletion: Theory, models, and examples from the Niger delta

    SciTech Connect (OSTI)

    Watts, N.L.; Kaars Sijpestein, C.H.; Osai, L.N.; Okoli, O.C. (Shell Petroleum Development Co. of Nigeria, Lagos (Nigeria))

    1991-08-01T23:59:59.000Z

    Previous studies of fault sealing have addressed possible fault leakage during secondary migration due to the effects of increased hydrocarbon-water capillary pressure, fracturing, or small-scale incremental fault movements. Of equal importance to production geologists is the failure and leakage of faults during field development due to differential depletion of adjacent fault blocks. This paper examines the unique problems associated with this dynamic leakage of faults. It is theoretically shown that the fault sealing mechanism, and the extent of the seal, directly influences the failure process which in turn results in a variety of favorable and unfavorable effects on field development. The qualitative models give considerable insight into such aspects as oil-column expansion and resaturation losses, interfault block aquifer support (with important implications to material balance calculations), possible leakage or spillage of oil across faults, and potential fault failure during (re)injection projects. Examples of dynamic fault leakage are presented from selected fields of the Niger delta.

  18. Progress in radiation immune thermionic integrated circuits

    SciTech Connect (OSTI)

    Lynn, D.K.; McCormick, J.B. (comps.)

    1985-08-01T23:59:59.000Z

    This report describes the results of a program directed at evaluating the thermionic integrated circuit (TIC) technology for applicability to military systems. Previous programs under the sponsorship of the Department of Energy, Office of Basic Energy Sciences, have developed an initial TIC technology base and demonstrated operation in high-temperature and high-radiation environments. The program described in this report has two parts: (1) a technical portion in which experiments and analyses were conducted to refine perceptions of near-term as well as ultimate performance levels of the TIC technology and (2) an applications portion in which the technical conclusions were to be evaluated against potential military applications. This report draws several conclusions that strongly suggest that (1) useful radiation-hard/high-temperature operable integrated circuits can be developed using the TIC technology; (2) because of their ability to survive and operate in hostile environments, a variety of potential military applications have been projected for this technology; and (3) based on the above two conclusions, an aggressive TIC development program should be initiated to provide the designers of future systems with integrated circuits and devices with the unique features of the TICs.

  19. Base drive and overlap protection circuit

    DOE Patents [OSTI]

    Gritter, David J. (Southfield, MI)

    1983-01-01T23:59:59.000Z

    An inverter (34) which provides power to an A. C. machine (28) is controlled by a circuit (36) employing PWM control strategy whereby A. C. power is supplied to the machine at a preselectable frequency and preselectable voltage. This is accomplished by the technique of waveform notching in which the shapes of the notches are varied to determine the average energy content of the overall waveform. Through this arrangement, the operational efficiency of the A. C. machine is optimized. The control circuit includes a microcomputer and memory element which receive various parametric inputs and calculate optimized machine control data signals therefrom. The control data is asynchronously loaded into the inverter through an intermediate buffer (38). A base drive and overlap protection circuit is included to insure that both transistors of a complimentary pair are not conducting at the same time. In its preferred embodiment, the present invention is incorporated within an electric vehicle (10) employing a 144 VDC battery pack (32) and a three-phase induction motor (18).

  20. IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, VOL. 3, NO. 4, AUGUST 2009 241 Fault Modeling and Functional Test Methods

    E-Print Network [OSTI]

    Chakrabarty, Krishnendu

    and Functional Test Methods for Digital Microfluidic Biochips Tao Xu, Student Member, IEEE, and Krishnendu detect and locate defect sites on a microfluidic array, they cannot be used to ensure correct operation of functional units). In this paper, we introduce the concept of functional testing of microfluidic biochips. We

  1. Bridging faults in CMOS circuits which are non-Iddq testable and their effect on delay testing

    E-Print Network [OSTI]

    Tu, Gao

    1997-01-01T23:59:59.000Z

    for at speed voltage domain tests are discussed and compared with other testing methods. SPICE level 3 simulations using a technology file provided by Hewlett Packard have verified the observations made in this thesis....

  2. Qualitative reasoning about fault effects in electrical cir-cuits has reached a level of achievement which allows it to

    E-Print Network [OSTI]

    Hamburg,.Universität

    - stance, the FLAME system (Pugh and Snooke 1996) per- forms failure mode and effects analysis (FMEA) is employed for automated FMEA and diagnosis guidelines generation for mechatronic car subsystems

  3. Automated transmission line fault analysis using synchronized sampling at two ends

    SciTech Connect (OSTI)

    Kezunovic, M. [Texas A and M Univ., College Station, TX (United States)] [Texas A and M Univ., College Station, TX (United States); Perunicic, B. [Lamar Univ., Beaumont, TX (United States)] [Lamar Univ., Beaumont, TX (United States)

    1996-02-01T23:59:59.000Z

    This paper introduces a new approach to fault analysis using synchronized sampling. A digital fault recorder with Global Positioning System (GPS) satellite receiver is the source of data for this approach. Fault analysis functions, such as fault detection, classification and location are implemented for a transmission line using synchronized samples from two ends of a line. This technique can be extremely fast, selective and accurate, providing fault analysis performance that can not easily be matched by other known techniques.

  4. Automated transmission line fault analysis using synchronized sampling at two ends

    SciTech Connect (OSTI)

    Kezunovic, M. [Texas A and M Univ., College Station, TX (United States); Perunicic, B. [Lamar Univ., Beaumont, TX (United States)

    1995-12-31T23:59:59.000Z

    This paper introduces a new approach to fault analysis using synchronized sampling. A digital fault recorder with Global Positioning System (GPS) satellite receiver is the source of data for this approach. Fault analysis functions, such as fault detection, classification and location are implemented for a transmission line using synchronized samples from two ends of a line. This technique can be extremely fast, selective and accurate, providing fault analysis performance that can not easily be matched by other known techniques.

  5. C-testability of a ripple carry adder under multiple faults

    E-Print Network [OSTI]

    Bommena, Manoher V.

    1992-01-01T23:59:59.000Z

    . Fault Types IV FAULT SIMULATION AND EXPERIMENT . A. Physical Line Fault Simulation . 1. Layout 2. Simulation B. Functional Fault Simulation and Experiment . 1. Probability of Un-detection 2. Efficiency of the Test Vectors and Reduced Test V... RESULTS VI CONCLUSIONS AND RECOMMENDATIONS 9 10 12 18 18 19 22 27 27 Set . 30 REFERENCES 41 APPENDIX A APPENDIX B . Page APPENDIX C . I. IST OF TABLES TABLE Page I Expressions from the physical line fault simulation stage 24 II...

  6. anatolian fault zone: Topics by E-print Network

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    across the Mudurnu segment of the North Anatolian Fault Zone (NAFZ) in northwestern Turkey Ben-Zion, Yehuda 2 Velocity contrast across the 1944 rupture zone of the North...

  7. An information model for inter-organizational fault Patricia Marcu

    E-Print Network [OSTI]

    in the IT Infrastructure Library (ITIL) [2] and related frameworks in the area of IT service management (ITSM). But since ITIL and the related ITSM frameworks do not consider specific aspects of inter- organizational (fault

  8. Melt generation, crystallization, and extraction beneath segmented oceanic transform faults

    E-Print Network [OSTI]

    Gregg, Patricia M.

    We examine mantle melting, fractional crystallization, and melt extraction beneath fast slipping, segmented oceanic transform fault systems. Three-dimensional mantle flow and thermal structures are calculated using a ...

  9. Non-intrusive fault detection in reciprocating compressors

    E-Print Network [OSTI]

    Schantz, Christopher James

    2011-01-01T23:59:59.000Z

    This thesis presents a set of techniques for non-intrusive sensing and fault detection in reciprocating compressors driven by induction motors. The procedures developed here are "non-intrusive" because they rely only on ...

  10. andreas fault system: Topics by E-print Network

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    system Sontag, Eduardo 23 The San Andreas Fault In The San Francisco Bay Area, California: A Geology Fieldtrip Guidebook To Selected Stops On Public Lands CiteSeer Summary:...

  11. Detecting and tolerating Byzantine faults in database systems

    E-Print Network [OSTI]

    Vandiver, Benjamin Mead, 1978-

    2008-01-01T23:59:59.000Z

    This thesis describes the design, implementation, and evaluation of a replication scheme to handle Byzantine faults in transaction processing database systems. The scheme compares answers from queries and updates on multiple ...

  12. Detecting and Tolerating Byzantine Faults in Database Systems

    E-Print Network [OSTI]

    Vandiver, Benjamin Mead

    2008-06-30T23:59:59.000Z

    This thesis describes the design, implementation, and evaluation of a replication scheme to handle Byzantine faults in transaction processing database systems. The scheme compares answers from queries and updates on multiple ...

  13. Cryptic Faulting and Multi-Scale Geothermal Fluid Connections...

    Open Energy Info (EERE)

    from Mt Resistivity Surveying Jump to: navigation, search OpenEI Reference LibraryAdd to library Conference Paper: Cryptic Faulting and Multi-Scale Geothermal Fluid Connections in...

  14. Intersecting Fault Trends and Crustal-Scale Fluid Pathways Below...

    Open Energy Info (EERE)

    3d Magnetotelluric Surveying Jump to: navigation, search OpenEI Reference LibraryAdd to library Conference Paper: Intersecting Fault Trends and Crustal-Scale Fluid Pathways Below...

  15. STRESS AND FAULTING IN THE COSO GEOTHERMAL FIELD: UPDATE AND...

    Open Energy Info (EERE)

    THE EAST FLANK AND COSO WASH Jump to: navigation, search OpenEI Reference LibraryAdd to library Conference Proceedings: STRESS AND FAULTING IN THE COSO GEOTHERMAL FIELD: UPDATE...

  16. arcing fault fires: Topics by E-print Network

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    stacking faults at a production-rate of few gmin. A guideline for controlling the number of layers of such FLG has also been suggested. Karmakar, Soumen; Lalla, Niranjan P;...

  17. assembly line fault: Topics by E-print Network

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    of fault data to verify that all elements of the protection system Siegel, Mel 190 Bucket brigades on in-tree assembly networks John J. Bartholdi III a,*, Donald D. Eisenstein...

  18. Microgrid Fault Protection Based on Symmetrical and Differential Current Components

    E-Print Network [OSTI]

    Microgrid Fault Protection Based on Symmetrical and Differential Current Components Prepared.........................................................................................8 2. AEP CERTS MICROGRID .........................................................................9 ........................................................................67 #12;3 Index of Figures Figure 1: Schematic representation of the AEP CERTS microgrid

  19. Characteristics of Wind Turbines Under Normal and Fault Conditions: Preprint

    SciTech Connect (OSTI)

    Muljadi, E.; Butterfield, C. P.; Parsons, B.; Ellis, A.

    2007-02-01T23:59:59.000Z

    This paper investigates the characteristics of a variable-speed wind turbine connected to a stiff or weak grid under normal and fault conditions and the role of reactive power compensation.

  20. Fault Tolerant WideArea Parallel Computing Jon B. Weissman

    E-Print Network [OSTI]

    Weissman, Jon

    hosts go down and get rebooted, and network faults where links go down. A single monolithic solu­ tion not fit their assumptions, the maxim ``pay for what you need'' has been proposed as a guiding principle

  1. Faults as potential hydrocarbon barriers, Arroyo Grande, California

    E-Print Network [OSTI]

    Switek, Daniel Paul

    1994-01-01T23:59:59.000Z

    Faulting in a sandstone introduces properties which are different from the country rock. Previous work has shown that these new properties can significantly impede the flow of hydrocarbons through the country rock. This thesis seeks to analyze...

  2. Robust model-based fault diagnosis for chemical process systems

    E-Print Network [OSTI]

    Rajaraman, Srinivasan

    2006-08-16T23:59:59.000Z

    Fault detection and diagnosis have gained central importance in the chemical process industries over the past decade. This is due to several reasons, one of them being that copious amount of data is available from a large number of sensors...

  3. Controls on Fault-Hosted Fluid Flow: Preliminary Results from...

    Open Energy Info (EERE)

    Geothermal Field, CA Jump to: navigation, search OpenEI Reference LibraryAdd to library Conference Proceedings: Controls on Fault-Hosted Fluid Flow: Preliminary Results from the...

  4. analysis fault reactivation: Topics by E-print Network

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    23 24 25 Next Page Last Page Topic Index 81 System level Analysis of Fault Effect in an Automotive Environment CiteSeer Summary: In the last years, new requirements in terms of...

  5. Understanding Fault Characteristics And Sediment Depth For Geothermal...

    Open Energy Info (EERE)

    of primarily E-W directed extension along N-NNW striking normal faults. Water well drilling on the eastern slopes of the Wassuk Range, west of the city of Hawthorne, Nevada...

  6. Robust model-based fault diagnosis for chemical process systems 

    E-Print Network [OSTI]

    Rajaraman, Srinivasan

    2006-08-16T23:59:59.000Z

    Fault detection and diagnosis have gained central importance in the chemical process industries over the past decade. This is due to several reasons, one of them being that copious amount of data is available from a large ...

  7. Identifying Efficiency Degrading Faults in Split Air Conditioning Systems

    E-Print Network [OSTI]

    Terrill, T. J.; Brown, M. L.; Cheyne, R. W. Jr.; Cousins, A. J.; Daniels, B. P.; Erb, K. L.; Garcia, P. A.; Leutermann, M. J.; Nel, A. J.; Robert, C. L.; Widger, S. B.; Williams, A. G.; Rasmussen, B. P.

    2013-01-01T23:59:59.000Z

    Studies estimate that as much as 50% of packaged air conditioning systems operate in faulty conditions that degrade system efficiency. Common faults include: under- and over-charged systems (too much or too little refrigerant), faulty expansions...

  8. Capacitive charge generation apparatus and method for testing circuits

    DOE Patents [OSTI]

    Cole, E.I. Jr.; Peterson, K.A.; Barton, D.L.

    1998-07-14T23:59:59.000Z

    An electron beam apparatus and method for testing a circuit are disclosed. The electron beam apparatus comprises an electron beam incident on an outer surface of an insulating layer overlying one or more electrical conductors of the circuit for generating a time varying or alternating current electrical potential on the surface; and a measurement unit connected to the circuit for measuring an electrical signal capacitively coupled to the electrical conductors to identify and map a conduction state of each of the electrical conductors, with or without an electrical bias signal being applied to the circuit. The electron beam apparatus can further include a secondary electron detector for forming a secondary electron image for registration with a map of the conduction state of the electrical conductors. The apparatus and method are useful for failure analysis or qualification testing to determine the presence of any open-circuits or short-circuits, and to verify the continuity or integrity of electrical conductors buried below an insulating layer thickness of 1-100 {micro}m or more without damaging or breaking down the insulating layer. The types of electrical circuits that can be tested include integrated circuits, multi-chip modules, printed circuit boards and flexible printed circuits. 7 figs.

  9. Capacitive charge generation apparatus and method for testing circuits

    DOE Patents [OSTI]

    Cole, Jr., Edward I. (Albuquerque, NM); Peterson, Kenneth A. (Albuquerque, NM); Barton, Daniel L. (Albuquerque, NM)

    1998-01-01T23:59:59.000Z

    An electron beam apparatus and method for testing a circuit. The electron beam apparatus comprises an electron beam incident on an outer surface of an insulating layer overlying one or more electrical conductors of the circuit for generating a time varying or alternating current electrical potential on the surface; and a measurement unit connected to the circuit for measuring an electrical signal capacitively coupled to the electrical conductors to identify and map a conduction state of each of the electrical conductors, with or without an electrical bias signal being applied to the circuit. The electron beam apparatus can further include a secondary electron detector for forming a secondary electron image for registration with a map of the conduction state of the electrical conductors. The apparatus and method are useful for failure analysis or qualification testing to determine the presence of any open-circuits or short-circuits, and to verify the continuity or integrity of electrical conductors buried below an insulating layer thickness of 1-100 .mu.m or more without damaging or breaking down the insulating layer. The types of electrical circuits that can be tested include integrated circuits, multi-chip modules, printed circuit boards and flexible printed circuits.

  10. Two Similarity Measure Approaches to Whole Building Fault Diagnosis

    E-Print Network [OSTI]

    Lin, G.; Claridge, D.

    2012-01-01T23:59:59.000Z

    consumption in buildings using similarity measures. The method is referred to as the cosine similarity method if cosine similarity is adopted and is referred to as the Euclidean distance similarity method if Euclidean distance similarity is implemented.... Fig. 1 Block diagram for diagnosing abnormal energy consumption Step 1: Reference Control Change Library Determination Whole building fault diagnosis is different from component level fault diagnosis. It can only give a general clue, for example...

  11. Mechanical properties and fabric of the Punchbowl fault zone, California

    E-Print Network [OSTI]

    Chester, Frederick Michael

    1983-01-01T23:59:59.000Z

    MECHANICAL PROPERIIES AND FABRIC OF THE PUiVCHBOlv'L FAULT ZONE, CALIFORNIA A Thesis by FREDERICK MICHAEL CHESTER Subm-', tted to the Graduate College of Texas ABM University in partial fulfillment of the requirements for the degree... of MASTER OF SCIENCE December 1983 Major Subject: Geology MECHANICAL PROPERTIES AND FABRIC OF THE PUNCHBOWL FAULT ZONE, CALIFORNIA A Thesis by FREDERICK MICHAEL CHESTER Approved as to sty1e and content by: on . . an airman o ommittee) Me1vin edman...

  12. Analysis of faults using gravity methods in Mason County, Texas

    E-Print Network [OSTI]

    Milligan, Michael Glen

    1992-01-01T23:59:59.000Z

    Committee: Dr. D. A. Fahlquist Dr. B. Johnson The objective of this study is to determine the applicability of gravity profiling methods for determining the location and throw of a series of faults related to a structural graben in northern Mason County... profiles. For two faults with the best geologic control, the best-fit gravity models compared favorably with the the geologic model constructed by Randolph (1991) on the basis of surface mapping, structural control and well control. The gravity models...

  13. The application of satellite time references to HVDC fault location

    SciTech Connect (OSTI)

    Dewe, M.B.; Sankar, S.; Arrillaga, J. (Univ. of Canterbury, Christchurch (New Zealand))

    1993-07-01T23:59:59.000Z

    An HVdc fault location scheme is described which relies on very precise detection of the time of arrival of fault created surges at both ends of the line. Such detection is achieved by a very accurate data acquisition and processing system combined with the time reference signals provided by a global positioning system receiver. Extensive digital simulation is carried out to determine the voltage and current waveforms, to identify the main sources of error and suggest possible compensation techniques.

  14. Occupancy Based Fault Detection on Building Level - a Feasibility Study

    E-Print Network [OSTI]

    Tuip, B.; Houten, M.; Trcka, M.; Hensen, M.

    2010-01-01T23:59:59.000Z

    -going commissioning and fault detection and diagnostics (FDD) has been performed to improve the current situation of building problems by comparing measured building performance with design predictions [Portland 2003]. For fault detection, different methods... conference on building commissioning, Portland Energy Conservation. Portland. 2003. Methods for automated and continuous commissioning of building systems. US department of commerce, Portland energy conservation inc. Schijndel, A.W.M. van, 2008...

  15. A DC-81-indole conjugate agent suppresses melanoma A375 cell migration partially via interrupting VEGF production and stromal cell-derived factor-1{alpha}-mediated signaling

    SciTech Connect (OSTI)

    Hsieh, Ming-Chu [Graduate Institute of Pharmacy, Faculty of Pharmacy, Kaohsiung Medical University, Kaohsiung, Taiwan (China); Hu, Wan-Ping [Department of Biotechnology, College of Life Science, Kaohsiung Medical University, Kaohsiung, Taiwan (China); Yu, Hsin-Su [Department of Dermatology, College of Medicine, Kaohsiung Medical University, Kaohsiung, Taiwan (China); Wu, Wen-Chuan [Department of Ophthalmology, College of Medicine, Kaohsiung Medical University, Kaohsiung, Taiwan (China); Chang, Long-Sen [Institute of Biomedical Sciences, National Sun Yat-Sen University, Kaohsiung, Taiwan (China); Kao, Ying-Hsien, E-mail: danyhkao@gmail.com [Department of Medical Research, E-DA Hospital, I-Shou University, Kaohsiung, Taiwan (China); Wang, Jeh-Jeng, E-mail: jjwang@kmu.edu.tw [Graduate Institute of Pharmacy, Faculty of Pharmacy, Kaohsiung Medical University, Kaohsiung, Taiwan (China); Department of Medicinal and Applied Chemistry, Kaohsiung Medical University, Kaohsiung, Taiwan (China)

    2011-09-01T23:59:59.000Z

    Pyrrolo[2,1-c][1,4]benzodiazepine (PBD) chemicals are antitumor antibiotics inhibiting nucleic acid synthesis. An indole carboxylate-PBD hybrid with six-carbon spacer structure (IN6CPBD) has been previously demonstrated to induce melanoma cell apoptosis and reduce metastasis in mouse lungs. This study aimed at investigating the efficacy of the other hybrid compound with four-carbon spacer (IN4CPBD) and elucidating its anti-metastatic mechanism. Human melanoma A375 cells with IN4CPBD treatment underwent cytotoxicity and apoptosis-associated assays. Transwell migration assay, Western blotting, and ELISA were used for mechanistic study. IN4CPBD exhibited potent melanoma cytotoxicity through interrupting G1/S cell cycle progression, increasing DNA fragmentation and hypodipoidic DNA contents, and reducing mitochondrial membrane potential. Caspase activity elevation suggested that both intrinsic and extrinsic pathways were involved in IN4CPBD-induced melanoma apoptosis. IN4CPBD up-regulated p53 and p21, thereby concomitantly derailing the equilibrium between Bcl-2 and Bax levels. Transwell migration assay demonstrated that stromal cell-derived factor-1{alpha} (SDF-1{alpha}) stimulated A375 cell motility, while kinase inhibitors treatment confirmed that Rho/ROCK, Akt, ERK1/2, and p38 MAPK pathways were involved in SDF-1{alpha}-enhanced melanoma migration. IN4CPBD not only abolished the SDF-1{alpha}-enhanced chemotactic motility but also suppressed constitutive MMP-9 and VEGF expression. Mechanistically, IN4CPBD down-regulated Akt, ERK1/2, and p38 MAPK total proteins and MYPT1 phosphorylation. In conclusion, beyond the fact that IN4CPBD induces melanoma cell apoptosis at cytotoxic dose, the interruption in the VEGF expression and the SDF-1{alpha}-related signaling at cytostatic dose may partially constitute the rationale for its in vivo anti-metastatic potency. - Research Highlights: > A novel carboxylate-PBD hybrid as anti-melanoma drug. > IN4CPBD interrupts melanoma cell cycle progression and induces apoptosis. > IN4CPBD suppresses SDF-1{alpha}-enhanced signaling and melanoma migration. > IN4CPBD abolishes angiogenic factor production and chemotactic effect of SDF-1{alpha}. > This drug is clinically applicable to melanoma therapy.

  16. Microcomputer applications of, and modifications to, the modular fault trees

    SciTech Connect (OSTI)

    Zimmerman, T.L.; Graves, N.L.; Payne, A.C. Jr.; Whitehead, D.W. [Sandia National Labs., Albuquerque, NM (United States)] [Sandia National Labs., Albuquerque, NM (United States)

    1994-10-01T23:59:59.000Z

    The LaSalle Probabilistic Risk Assessment was the first major application of the modular logic fault trees after the IREP program. In the process of performing the analysis, many errors were discovered in the fault tree modules that led to difficulties in combining the modules to form the final system fault trees. These errors are corrected in the revised modules listed in this report. In addition, the application of the modules in terms of editing them and forming them into the system fault trees was inefficient. Originally, the editing had to be done line by line and no error checking was performed by the computer. This led to many typos and other logic errors in the construction of the modular fault tree files. Two programs were written to help alleviate this problem: (1) MODEDIT - This program allows an operator to retrieve a file for editing, edit the file for the plant specific application, perform some general error checking while the file is being modified, and store the file for later use, and (2) INDEX - This program checks that the modules that are supposed to form one fault tree all link up appropriately before the files are,loaded onto the mainframe computer. Lastly, the modules were not designed for relay type logic common in BWR designs but for solid state type logic. Some additional modules were defined for modeling relay logic, and an explanation and example of their use are included in this report.

  17. The San Andreas Fault System Paul Withers Wallace RE, The San Andreas Fault System, California, USGS Professional Paper 1515,

    E-Print Network [OSTI]

    Withers, Paul

    mainland Mexico. The San Andreas fault is commonly referred to as the boundary between the Pacific is correlated with the local geological setting. CO2 lubrication, #12;increased pore pressure, and decreased

  18. Abstract--A method for fault detection and isolation is proposed and applied to inverter faults in multi-phase drives. An

    E-Print Network [OSTI]

    Boyer, Edmond

    energy source, a five- leg inverter and a five-phase star-connected PMSM. It has to be noticed that all-magnet synchronous machine (PMSM) drive. The faults under consideration are: open-phase faults and open-switch faults

  19. Solid-State Fault Current Limiter Development : Design and Testing Update of a 15kV SSCL Power Stack

    SciTech Connect (OSTI)

    Dr. Ram Adapa; Mr. Dante Piccone

    2012-04-30T23:59:59.000Z

    ABSTRACT The Solid-State Fault Current Limiter (SSCL) is a promising technology that can be applied to utility power delivery systems to address the problem of increasing fault currents associated with load growth. As demand continues to grow, more power is added to utility system either by increasing generator capacity or by adding distributed generators, resulting in higher available fault currents, often beyond the capabilities of the present infrastructure. The SSCL is power-electronics based equipment designed to work with the present utility system to address this problem. The SSCL monitors the line current and dynamically inserts additional impedance into the line in the event of a fault being detected. The SSCL is based on a modular design and can be configured for 5kV through 69kV systems at nominal current ratings of 1000A to 4000A. Results and Findings This report provides the final test results on the development of 15kV class SSCL single phase power stack. The scope of work included the design of the modular standard building block sub-assemblies, the design and manufacture of the power stack and the testing of the power stack for the key functional tests of continuous current capability and fault current limiting action. Challenges and Objectives Solid-State Current Limiter technology impacts a wide spectrum of utility engineering and operating personnel. It addresses the problems associated with load growth both at Transmission and Distribution class networks. The design concept is pioneering in terms of developing the most efficient and compact power electronics equipment for utility use. The initial test results of the standard building blocks are promising. The independent laboratory tests of the power stack are promising. However the complete 3 phase system needs rigorous testing for performance and reliability. Applications, Values, and Use The SSCL is an intelligent power-electronics device which is modular in design and can provide current limiting or current interrupting capabilities. It can be applied to variety of applications from distribution class to transmission class power delivery grids and networks. It can also be applied to single major commercial and industrial loads and distributed generator supplies. The active switching of devices can be further utilized for protection of substation transformers. The stress on the system can be reduced substantially improving the life of the power system. It minimizes the voltage sag by speedy elimination of heavy fault currents and promises to be an important element of the utility power system. DOE Perspective This development effort is now focused on a 15kV system. This project will help mitigate the challenges of increasing available fault current. DOE has made a major contribution in providing a cost effective SSCL designed to integrate seamlessly into the Transmission and Distribution networks of today and the future. Approach SSCL development program for a 69kV SSCL was initiated which included the use of the Super GTO advanced semiconductor device which won the 2007 R&D100 Award. In the beginning, steps were identified to accomplish the economically viable design of a 69kV class Solid State Current Limiter that is extremely reliable, cost effective, and compact enough to be applied in urban transmission. The prime thrust in design and development was to encompass the 1000A and the 3000A ratings and provide a modular design to cover the wide range of applications. The focus of the project was then shifted to a 15kV class SSCL. The specifications for the 15kV power stack are reviewed. The design changes integrated into the 15kV power stack are discussed. In this Technical Update the complete project is summarized followed by a detailed test report. The power stack independent high voltage laboratory test requirements and results are presented. Keywords Solid State Current Limiter, SSCL, Fault Current Limiter, Fault Current Controller, Power electronics controller, Intelligent power-electronics Device, IED

  20. An experimental analogue for memristor based Chua's circuit

    E-Print Network [OSTI]

    R. Jothimurugan; K. Thamilmaran; Ronilson Rocha

    2014-08-21T23:59:59.000Z

    This paper presents the dynamics of a practical equivalent of a smooth memristor oscillator derived from Chua's circuit. This approach replaces the conventional Chua's diode by a flux controlled memristor with negative conductance. The central idea is to design a practical memristor based circuit using electronic analogy in order to bypass problems related to the realization of memristor equivalents. The amplitude and the frequency of the oscillations are previously defined in the circuit design. The result is a robust and flexible circuit without inductors, which is able to reproduce a rich variety of dynamical behaviors. The proposed analogue circuit is successfully designed and implemented, producing experimental time series, phase portraits, and power spectra, which are corroborated by numerical simulations. The "0-1 test" is also performed in order to verify the regular and chaotic dynamics on the proposed analogue circuit.