National Library of Energy BETA

Sample records for fault circuit interrupt

  1. QUANTIFYING PHOTOVOLTAIC FIRE DANGER REDUCTION WITH ARC-FAULT CIRCUIT INTERRUPTERS

    E-Print Network [OSTI]

    QUANTIFYING PHOTOVOLTAIC FIRE DANGER REDUCTION WITH ARC-FAULT CIRCUIT INTERRUPTERS Kenneth M, shock hazards, and cause system downtime in photovoltaic (PV) systems. The 2011 National Electrical Code

  2. Apparatus for and method of testing an electrical ground fault circuit interrupt device

    DOE Patents [OSTI]

    Andrews, L.B.

    1998-08-18

    An apparatus for testing a ground fault circuit interrupt device includes a processor, an input device connected to the processor for receiving input from an operator, a storage media connected to the processor for storing test data, an output device connected to the processor for outputting information corresponding to the test data to the operator, and a calibrated variable load circuit connected between the processor and the ground fault circuit interrupt device. The ground fault circuit interrupt device is configured to trip a corresponding circuit breaker. The processor is configured to receive signals from the calibrated variable load circuit and to process the signals to determine a trip threshold current and/or a trip time. A method of testing the ground fault circuit interrupt device includes a first step of providing an identification for the ground fault circuit interrupt device. Test data is then recorded in accordance with the identification. By comparing test data from an initial test with test data from a subsequent test, a trend of performance for the ground fault circuit interrupt device is determined. 17 figs.

  3. Apparatus for and method of testing an electrical ground fault circuit interrupt device

    DOE Patents [OSTI]

    Andrews, Lowell B. (2181-13th Ave. SW., Largo, FL 34640)

    1998-01-01

    An apparatus for testing a ground fault circuit interrupt device includes a processor, an input device connected to the processor for receiving input from an operator, a storage media connected to the processor for storing test data, an output device connected to the processor for outputting information corresponding to the test data to the operator, and a calibrated variable load circuit connected between the processor and the ground fault circuit interrupt device. The ground fault circuit interrupt device is configured to trip a corresponding circuit breaker. The processor is configured to receive signals from the calibrated variable load circuit and to process the signals to determine a trip threshold current and/or a trip time. A method of testing the ground fault circuit interrupt device includes a first step of providing an identification for the ground fault circuit interrupt device. Test data is then recorded in accordance with the identification. By comparing test data from an initial test with test data from a subsequent test, a trend of performance for the ground fault circuit interrupt device is determined.

  4. 1. Detect ground faults in PV arrays mounted on the roofs of 2. Interrupt the fault current

    E-Print Network [OSTI]

    Johnson, Eric E.

    1. Detect ground faults in PV arrays mounted on the roofs of dwellings 2. Interrupt the fault current 3. Indicate that a ground fault had occurred 4. Disconnect the faulted part of the PV array 5. "Crowbar" (short-circuit) the PV array The original GFPD prototype was developed in two versions that were

  5. Development of a Hydrologic Characterization Technology for Fault Zones Final Report

    E-Print Network [OSTI]

    Karasaki, Kenzi

    2014-01-01

    times by triggering a GFCI (Ground Fault Circuit Interrupt).time, rain caused a GFCI (ground fault circuit interrupt),

  6. Hybrid high direct current circuit interrupter

    DOE Patents [OSTI]

    Rockot, J.H.; Mikesell, H.E.; Jha, K.N.

    1998-08-11

    A device and a method are disclosed for interrupting very high direct currents (greater than 100,000 amperes) and simultaneously blocking high voltages (greater than 600 volts). The device utilizes a mechanical switch to carry very high currents continuously with low loss and a silicon controlled rectifier (SCR) to bypass the current around the mechanical switch while its contacts are separating. A commutation circuit, connected in parallel with the SCR, turns off the SCR by utilizing a resonant circuit to divert the SCR current after the switch opens. 7 figs.

  7. Hybrid high direct current circuit interrupter

    DOE Patents [OSTI]

    Rockot, Joseph H. (N. Huntingdon, PA); Mikesell, Harvey E. (McMurray, PA); Jha, Kamal N. (Bethel Park, PA)

    1998-01-01

    A device and a method for interrupting very high direct currents (greater than 100,000 amperes) and simultaneously blocking high voltages (greater than 600 volts). The device utilizes a mechanical switch to carry very high currents continuously with low loss and a silicon controlled rectifier (SCR) to bypass the current around the mechanical switch while its contacts are separating. A commutation circuit, connected in parallel with the SCR, turns off the SCR by utilizing a resonant circuit to divert the SCR current after the switch opens.

  8. Adjustable direct current and pulsed circuit fault current limiter

    DOE Patents [OSTI]

    Boenig, Heinrich J.; Schillig, Josef B.

    2003-09-23

    A fault current limiting system for direct current circuits and for pulsed power circuit. In the circuits, a current source biases a diode that is in series with the circuits' transmission line. If fault current in a circuit exceeds current from the current source biasing the diode open, the diode will cease conducting and route the fault current through the current source and an inductor. This limits the rate of rise and the peak value of the fault current.

  9. A Compiler for Fault-Tolerant High Level Quantum Circuits

    E-Print Network [OSTI]

    Alexandru Paler; Ilia Polian; Kae Nemoto; Simon J. Devitt

    2015-09-07

    Fault-tolerant quantum error correction is an absolute necessity for any quantum architecture destined to tackle interesting, large-scale quantum algorithms. The theoretical formalism of quantum error correction codes, fault-tolerant circuit constructions, gate decompositions and relevant optimisations have been well founded for nearly two decades. However, at this point we still do not have a reliable compiler to adapt a high level circuit description to a fully fault-tolerant, error corrected description. There are many technical hurdles to this, including dynamic circuit constructions that occur due to teleportation protocols necessary to achieve fault-tolerance with commonly used error correction codes. We combine multiple results to develop a package that takes any high level quantum circuit consisting of CNOT, Toffoli, Controlled-$\\sqrt{X}$ and arbitrary single qubit rotations and converts it to a equivalent quantum circuit employing ancillary protocols needed for fault-tolerant error correction. We call this representation the (I)initialisation, (C)NOT, (M)measurement representation (ICM) and consists of an initialisation layer of qubits into one of four distinct states, a massive array of CNOT operations that implement the relevant algorithmic decompositions and fault-tolerant ancillary protocols and a series of time ordered $X$- and $Z$-basis measurements. Our package will output either a standard circuit description or a canonical geometric structure that represents its implementation for topological quantum codes that can be further optimised and implemented on actual quantum hardware.

  10. Fault current limiter and alternating current circuit breaker

    DOE Patents [OSTI]

    Boenig, H.J.

    1998-03-10

    A solid-state circuit breaker and current limiter are disclosed for a load served by an alternating current source having a source impedance, the solid-state circuit breaker and current limiter comprising a thyristor bridge interposed between the alternating current source and the load, the thyristor bridge having four thyristor legs and four nodes, with a first node connected to the alternating current source, and a second node connected to the load. A coil is connected from a third node to a fourth node, the coil having an impedance of a value calculated to limit the current flowing therethrough to a predetermined value. Control means are connected to the thyristor legs for limiting the alternating current flow to the load under fault conditions to a predetermined level, and for gating the thyristor bridge under fault conditions to quickly reduce alternating current flowing therethrough to zero and thereafter to maintain the thyristor bridge in an electrically open condition preventing the alternating current from flowing therethrough for a predetermined period of time. 9 figs.

  11. Fault current limiter and alternating current circuit breaker

    DOE Patents [OSTI]

    Boenig, Heinrich J. (Los Alamos, NM)

    1998-01-01

    A solid-state circuit breaker and current limiter for a load served by an alternating current source having a source impedance, the solid-state circuit breaker and current limiter comprising a thyristor bridge interposed between the alternating current source and the load, the thyristor bridge having four thyristor legs and four nodes, with a first node connected to the alternating current source, and a second node connected to the load. A coil is connected from a third node to a fourth node, the coil having an impedance of a value calculated to limit the current flowing therethrough to a predetermined value. Control means are connected to the thyristor legs for limiting the alternating current flow to the load under fault conditions to a predetermined level, and for gating the thyristor bridge under fault conditions to quickly reduce alternating current flowing therethrough to zero and thereafter to maintain the thyristor bridge in an electrically open condition preventing the alternating current from flowing therethrough for a predetermined period of time.

  12. A Smart Algorithm for the Diagnosis of Short-Circuit Faults in a Photovoltaic Generator

    E-Print Network [OSTI]

    Paris-Sud XI, Université de

    A Smart Algorithm for the Diagnosis of Short-Circuit Faults in a Photovoltaic Generator Wail Rezgui observations distributed over classes is used for simulation purposes. Keywords--Photovoltaic generator, SVM, k-NN, short-circuit fault, smart classification, linear programming. NOMENCLATURE PV = Photovoltaic; SVM

  13. CREATING DYNAMIC EQUIVALENT PV CIRCUIT MODELS WITH IMPEDANCE SPECTROSCOPY FOR ARC FAULT MODELING

    E-Print Network [OSTI]

    CREATING DYNAMIC EQUIVALENT PV CIRCUIT MODELS WITH IMPEDANCE SPECTROSCOPY FOR ARC FAULT MODELING ® (NEC® ) requires new photovoltaic (PV) systems on or penetrating a building to include a listed arc of the arcing frequencies through PV components despite the potential for modules and other PV components

  14. Use of inverse time, adjustable instantaneous pickup circuit breakers for short circuit and ground fault protection of energy efficient motors

    SciTech Connect (OSTI)

    Heath, D.W.; Bradfield, H.L.

    1995-12-31

    Many energy efficient low voltage motors exhibit first half cycle instantaneous inrush current values greater than the National Electrical Code`s 13 times motor full load amperes maximum permissible setting for instantaneous trip circuit breakers. The alternate use of an inverse time circuit breaker could lead to inadequate protection if the breaker does not have adjustable instantaneous settings. Recent innovations in digital solid state trip unit technology have made available an inverse time, adjustable instantaneous trip circuit breaker in 15A to 150A ratings. This allows the instantaneous pickup to be adjusted to a value slightly above motor inrush so that low level faults will be cleared instantaneously while avoiding nuisance tripping at startup. Applications, settings and comparisons are discussed.

  15. Modeling quantum noise for efficient testing of fault-tolerant circuits

    E-Print Network [OSTI]

    Easwar Magesan; Daniel Puzzuoli; Christopher E. Granade; David G. Cory

    2012-06-23

    Understanding fault-tolerant properties of quantum circuits is important for the design of large-scale quantum information processors. In particular, simulating properties of encoded circuits is a crucial tool for investigating the relationships between the noise model, encoding scheme, and threshold value. For general circuits and noise models, these simulations quickly become intractable in the size of the encoded circuit. We introduce methods for approximating a noise process by one which allows for efficient Monte Carlo simulation of properties of encoded circuits. The approximations are as close to the original process as possible without overestimating their ability to preserve quantum information, a key property for obtaining more honest estimates of threshold values. We numerically illustrate the method with various physically relevant noise models.

  16. Fault modeling, delay evaluation and path selection for delay test under process variation in nano-scale VLSI circuits 

    E-Print Network [OSTI]

    Lu, Xiang

    2006-04-12

    Delay test in nano-scale VLSI circuits becomes more difficult with shrinking technology feature sizes and rising clock frequencies. In this dissertation, we study three challenging issues in delay test: fault modeling, ...

  17. Creating dynamic equivalent PV circuit models with impedance spectroscopy for arc-fault modeling.

    SciTech Connect (OSTI)

    Johnson, Jay Dean; Kuszmaul, Scott S.; Strauch, Jason E.; Schoenwald, David Alan

    2011-06-01

    Article 690.11 in the 2011 National Electrical Code{reg_sign} (NEC{reg_sign}) requires new photovoltaic (PV) systems on or penetrating a building to include a listed arc fault protection device. Currently there is little experimental or empirical research into the behavior of the arcing frequencies through PV components despite the potential for modules and other PV components to filter or attenuate arcing signatures that could render the arc detector ineffective. To model AC arcing signal propagation along PV strings, the well-studied DC diode models were found to inadequately capture the behavior of high frequency arcing signals. Instead dynamic equivalent circuit models of PV modules were required to describe the impedance for alternating currents in modules. The nonlinearities present in PV cells resulting from irradiance, temperature, frequency, and bias voltage variations make modeling these systems challenging. Linearized dynamic equivalent circuits were created for multiple PV module manufacturers and module technologies. The equivalent resistances and capacitances for the modules were determined using impedance spectroscopy with no bias voltage and no irradiance. The equivalent circuit model was employed to evaluate modules having irradiance conditions that could not be measured directly with the instrumentation. Although there was a wide range of circuit component values, the complex impedance model does not predict filtering of arc fault frequencies in PV strings for any irradiance level. Experimental results with no irradiance agree with the model and show nearly no attenuation for 1 Hz to 100 kHz input frequencies.

  18. Low Insertion HVDC Circuit Breaker: Magnetically Pulsed Hybrid Breaker for HVDC Power Distribution Protection

    SciTech Connect (OSTI)

    2012-01-09

    GENI Project: General Atomics is developing a direct current (DC) circuit breaker that could protect the grid from faults 100 times faster than its alternating current (AC) counterparts. Circuit breakers are critical elements in any electrical system. At the grid level, their main function is to isolate parts of the grid where a fault has occurred—such as a downed power line or a transformer explosion—from the rest of the system. DC circuit breakers must interrupt the system during a fault much faster than AC circuit breakers to prevent possible damage to cables, converters and other grid-level components. General Atomics’ high-voltage DC circuit breaker would react in less than 1/1,000th of a second to interrupt current during a fault, preventing potential hazards to people and equipment.

  19. ECE 586 Fault Detection in Digital Circuits Lecture 19 Design for Testability I

    E-Print Network [OSTI]

    Wang, Jia

    be converted into costs associated with the testing process. Cost of test pattern generation. Cost of fault simulation and generation of fault location information. Cost of test equipment. Cost of testing process;Motivation Test generation is complicated. Test complexity can be converted into costs associated

  20. Ensemble Dependent Matrix Methodology for Probabilistic-Based Fault-tolerant Nanoscale Circuit Design

    E-Print Network [OSTI]

    Wu, An-Yeu "Andy"

    Electrical and Computer Engineering Department, University of Alberta, Canada *Graduate Institute of Electronics Engineering, and Department of Electrical Engineering, National Taiwan University, Taiwan Abstract tools development and to optimize nanoscale circuit and system design. In this paper, we show

  1. Fault Locating, Prediction and Protection (FLPPS)

    SciTech Connect (OSTI)

    Yinger, Robert, J.; Venkata, S., S.; Centeno, Virgilio

    2010-09-30

    One of the main objectives of this DOE-sponsored project was to reduce customer outage time. Fault location, prediction, and protection are the most important aspects of fault management for the reduction of outage time. In the past most of the research and development on power system faults in these areas has focused on transmission systems, and it is not until recently with deregulation and competition that research on power system faults has begun to focus on the unique aspects of distribution systems. This project was planned with three Phases, approximately one year per phase. The first phase of the project involved an assessment of the state-of-the-art in fault location, prediction, and detection as well as the design, lab testing, and field installation of the advanced protection system on the SCE Circuit of the Future located north of San Bernardino, CA. The new feeder automation scheme, with vacuum fault interrupters, will limit the number of customers affected by the fault. Depending on the fault location, the substation breaker might not even trip. Through the use of fast communications (fiber) the fault locations can be determined and the proper fault interrupting switches opened automatically. With knowledge of circuit loadings at the time of the fault, ties to other circuits can be closed automatically to restore all customers except the faulted section. This new automation scheme limits outage time and increases reliability for customers. The second phase of the project involved the selection, modeling, testing and installation of a fault current limiter on the Circuit of the Future. While this project did not pay for the installation and testing of the fault current limiter, it did perform the evaluation of the fault current limiter and its impacts on the protection system of the Circuit of the Future. After investigation of several fault current limiters, the Zenergy superconducting, saturable core fault current limiter was selected for installation. Because of some testing problems with the Zenergy fault current limiter, installation was delayed until early 2009 with it being put into operation on March 6, 2009. A malfunction of the FCL controller caused the DC power supply to the superconducting magnet to be turned off. This inserted the FCL impedance into the circuit while it was in normal operation causing a voltage resonance condition. While these voltages never reached a point where damage would occur on customer equipment, steps were taken to insure this would not happen again. The FCL was reenergized with load on December 18, 2009. A fault was experienced on the circuit with the FCL in operation on January 14, 2010. The FCL operated properly and reduced the fault current by about 8%, what was expected from tests and modeling. As of the end of the project, the FCL was still in operation on the circuit. The third phase of the project involved the exploration of several advanced protection ideas that might be at a state where they could be applied to the Circuit of the Future and elsewhere in the SCE electrical system. Based on the work done as part of the literature review and survey, as well as a number of internal meetings with engineering staff at SCE, a number of ideas were compiled. These ideas were then evaluated for applicability and ability to be applied on the Circuit of the Future in the time remaining for the project. Some of these basic ideas were implemented on the circuit including measurement of power quality before and after the FCL. It was also decided that we would take what was learned as part of the Circuit of the Future work and extend it to the next generation circuit protection for SCE. Also at this time, SCE put in a proposal to the DOE for the Irvine Smart Grid Demonstration using ARRA funding. SCE was successful in obtaining funding for this proposal, so it was felt that exploration of new protection schemes for this Irvine Smart Grid Demonstration would be a good use of the project resources. With this in mind, a protection system that uses fault interrupting switches, hi

  2. Fault finder

    DOE Patents [OSTI]

    Bunch, Richard H. (1614 NW. 106th St., Vancouver, WA 98665)

    1986-01-01

    A fault finder for locating faults along a high voltage electrical transmission line. Real time monitoring of background noise and improved filtering of input signals is used to identify the occurrence of a fault. A fault is detected at both a master and remote unit spaced along the line. A master clock synchronizes operation of a similar clock at the remote unit. Both units include modulator and demodulator circuits for transmission of clock signals and data. All data is received at the master unit for processing to determine an accurate fault distance calculation.

  3. Experiments of a twenty cell PEFC operating under fault conditions with diode by-pass circuit for uninterrupted power delivery

    E-Print Network [OSTI]

    Boyer, Edmond

    behaviour of a 500W, twenty cell Polymer Electrolyte Fuel Cell (PEFC) stack operated under fault condition-up that reproduces the electrical coupling in series of two fuel cells. The results allow the evaluation of the by the capability of the reverse diode to electrically isolate a fuel cell stack under fault. The proposed

  4. Commutation circuit for an HVDC circuit breaker

    DOE Patents [OSTI]

    Premerlani, W.J.

    1981-11-10

    A commutation circuit for a high voltage DC circuit breaker incorporates a resistor capacitor combination and a charging circuit connected to the main breaker, such that a commutating capacitor is discharged in opposition to the load current to force the current in an arc after breaker opening to zero to facilitate arc interruption. In a particular embodiment, a normally open commutating circuit is connected across the contacts of a main DC circuit breaker to absorb the inductive system energy trapped by breaker opening and to limit recovery voltages to a level tolerable by the commutating circuit components. 13 figs.

  5. Accurate resistive bridge fault modeling, simulation, and test generation 

    E-Print Network [OSTI]

    Sar-Dessai, Vijay Ramesh

    1999-01-01

    Resistive bridging faults in CMOS combinational circuits are studied in this work. Bridging faults are modeled using HSPICE circuit simulation of the various types of bridging faults that can occur in CMOS combinational ...

  6. Interrupted polysilanes useful as photoresists

    DOE Patents [OSTI]

    Zeigler, John M. (2208 Lester Dr, NE., Albuquerque, NM 87112)

    1988-01-01

    Polysilane polymers in which the Si backbone is interrupted by atoms such as O, Ge, Sn, P, etc., are useful photoresists especially in the solvent development mode.

  7. Interrupted polysilanes useful as photoresists

    DOE Patents [OSTI]

    Zeigler, J.M.

    1988-08-02

    Polysilane polymers in which the Si backbone is interrupted by atoms such as O, Ge, Sn, P, etc., are useful photoresists especially in the solvent development mode.

  8. Design of a Universal Logic Block for Fault-Tolerant Realization of any Logic Operation in Trapped-Ion Quantum Circuits

    E-Print Network [OSTI]

    Hadi Goudarzi; Mohammad Javad Dousti; Alireza Shafaei; Massoud Pedram

    2015-01-12

    This paper presents a physical mapping tool for quantum circuits, which generates the optimal Universal Logic Block (ULB) that can perform any logical fault-tolerant (FT) quantum operations with the minimum latency. The operation scheduling, placement, and qubit routing problems tackled by the quantum physical mapper are highly dependent on one another. More precisely, the scheduling solution affects the quality of the achievable placement solution due to resource pressures that may be created as a result of operation scheduling whereas the operation placement and qubit routing solutions influence the scheduling solution due to resulting distances between predecessor and current operations, which in turn determines routing latencies. The proposed flow for the quantum physical mapper captures these dependencies by applying (i) a loose scheduling step, which transforms an initial quantum data flow graph into one that explicitly captures the no-cloning theorem of the quantum computing and then performs instruction scheduling based on a modified force-directed scheduling approach to minimize the resource contention and quantum circuit latency, (ii) a placement step, which uses timing-driven instruction placement to minimize the approximate routing latencies while making iterative calls to the aforesaid force-directed scheduler to correct scheduling levels of quantum operations as needed, and (iii) a routing step that finds dynamic values of routing latencies for the qubits. In addition to the quantum physical mapper, an approach is presented to determine the single best ULB size for a target quantum circuit by examining the latency of different FT quantum operations mapped onto different ULB sizes and using information about the occurrence frequency of operations on critical paths of the target quantum algorithm to weigh these latencies.

  9. Global interrupt and barrier networks

    DOE Patents [OSTI]

    Blumrich, Matthias A. (Ridgefield, CT); Chen, Dong (Croton-On-Hudson, NY); Coteus, Paul W. (Yorktown Heights, NY); Gara, Alan G. (Mount Kisco, NY); Giampapa, Mark E (Irvington, NY); Heidelberger, Philip (Cortlandt Manor, NY); Kopcsay, Gerard V. (Yorktown Heights, NY); Steinmacher-Burow, Burkhard D. (Mount Kisco, NY); Takken, Todd E. (Mount Kisco, NY)

    2008-10-28

    A system and method for generating global asynchronous signals in a computing structure. Particularly, a global interrupt and barrier network is implemented that implements logic for generating global interrupt and barrier signals for controlling global asynchronous operations performed by processing elements at selected processing nodes of a computing structure in accordance with a processing algorithm; and includes the physical interconnecting of the processing nodes for communicating the global interrupt and barrier signals to the elements via low-latency paths. The global asynchronous signals respectively initiate interrupt and barrier operations at the processing nodes at times selected for optimizing performance of the processing algorithms. In one embodiment, the global interrupt and barrier network is implemented in a scalable, massively parallel supercomputing device structure comprising a plurality of processing nodes interconnected by multiple independent networks, with each node including one or more processing elements for performing computation or communication activity as required when performing parallel algorithm operations. One multiple independent network includes a global tree network for enabling high-speed global tree communications among global tree network nodes or sub-trees thereof. The global interrupt and barrier network may operate in parallel with the global tree network for providing global asynchronous sideband signals.

  10. Pulsed interrupter and method of operation

    DOE Patents [OSTI]

    Drake, Joel Lawton; Kratz, Robert

    2015-06-09

    Some embodiments provide interrupter systems comprising: a first electrode; a second electrode; a piston movably located at a first position and electrically coupled with the first and second electrodes establishing a closed state, the piston comprises an electrical conductor that couples with the first and second electrodes providing a conductive path; an electromagnetic launcher configured to, when activated, induce a magnetic field pulse causing the piston to move away from the electrical coupling with the first and second electrodes establishing an open circuit between the first and second electrodes; and a piston control system comprising a piston arresting system configured to control a deceleration of the piston following the movement of the piston induced by the electromagnetic launcher such that the piston is not in electrical contact with at least one of the first electrode and the second electrode when in the open state.

  11. High temperature superconducting fault current limiter

    DOE Patents [OSTI]

    Hull, J.R.

    1997-02-04

    A fault current limiter for an electrical circuit is disclosed. The fault current limiter includes a high temperature superconductor in the electrical circuit. The high temperature superconductor is cooled below its critical temperature to maintain the superconducting electrical properties during operation as the fault current limiter. 15 figs.

  12. High temperature superconducting fault current limiter

    DOE Patents [OSTI]

    Hull, John R. (Hinsdale, IL)

    1997-01-01

    A fault current limiter (10) for an electrical circuit (14). The fault current limiter (10) includes a high temperature superconductor (12) in the electrical circuit (14). The high temperature superconductor (12) is cooled below its critical temperature to maintain the superconducting electrical properties during operation as the fault current limiter (10).

  13. Assisting interruption recovery in mission control operations

    E-Print Network [OSTI]

    Wan, Jordan (Jordan X.)

    2007-01-01

    Frequent interruptions are commonplace in modem work environments. The negative impacts of interruptions are well documented and include increased task completion and error rates in individual task activities, as well as ...

  14. Fault Models for Quantum Mechanical Switching Networks

    E-Print Network [OSTI]

    Jacob Biamonte; Jeff S. Allen; Marek A. Perkowski

    2010-01-19

    The difference between faults and errors is that, unlike faults, errors can be corrected using control codes. In classical test and verification one develops a test set separating a correct circuit from a circuit containing any considered fault. Classical faults are modelled at the logical level by fault models that act on classical states. The stuck fault model, thought of as a lead connected to a power rail or to a ground, is most typically considered. A classical test set complete for the stuck fault model propagates both binary basis states, 0 and 1, through all nodes in a network and is known to detect many physical faults. A classical test set complete for the stuck fault model allows all circuit nodes to be completely tested and verifies the function of many gates. It is natural to ask if one may adapt any of the known classical methods to test quantum circuits. Of course, classical fault models do not capture all the logical failures found in quantum circuits. The first obstacle faced when using methods from classical test is developing a set of realistic quantum-logical fault models. Developing fault models to abstract the test problem away from the device level motivated our study. Several results are established. First, we describe typical modes of failure present in the physical design of quantum circuits. From this we develop fault models for quantum binary circuits that enable testing at the logical level. The application of these fault models is shown by adapting the classical test set generation technique known as constructing a fault table to generate quantum test sets. A test set developed using this method is shown to detect each of the considered faults.

  15. Realistic fault modeling and quality test generation of combined delay faults 

    E-Print Network [OSTI]

    Thadhlani, Ajaykumar A

    2001-01-01

    With increasing operating speed and shrinking technology, timing defects in integrated circuits are becoming increasingly important. The well established stuck-at-fault model is not sufficient because it is a static fault model and does not account...

  16. 906 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 27, NO. 5, MAY 2008 Fault-Tolerant Distributed Deployment of

    E-Print Network [OSTI]

    Carloni, Luca

    platform, i.e., the controller. Control theorists design the control laws to be robust with respect of the target platform and the fault model, designers can rely on the synthesis of the low-level fault studies from the automotive industry: a steer-by-wire system from General Motors and a drive

  17. Avoiding and Managing Interruptions of Electric Service Under an Interruptible Contract or Tariff 

    E-Print Network [OSTI]

    Evans, G. W.

    1995-01-01

    the customer to verify, after the fact, that an actual interruption could not have been avoided. The industrial should have the right to verify that the utility made every reasonable effort to avoid the interruption. Hourly generation data, load data...

  18. EXOTIC OPTIONS FOR INTERRUPTIBLE ELECTRICITY SUPPLY CONTRACTS

    E-Print Network [OSTI]

    deregulated electricity markets have shown very little demand elasticity. Price spikes have reached $7000EXOTIC OPTIONS FOR INTERRUPTIBLE ELECTRICITY SUPPLY CONTRACTS RAJNISH KAMAT and SHMUEL S. OREN of financial contracts for the supply and procurement of interruptible electricity service. While the contract

  19. Accelerated Life Testing of PV Arc-Fault Detectors Jay Johnson, Michael Neilsen, Paul Vianco, N. Rob Sorensen,

    E-Print Network [OSTI]

    interrupters (AFCIs) to be incorporated into photovoltaic (PV) systems to prevent fires. Some manufacturers-fault prevention devices. Index Terms -- photovoltaic systems, arc-fault detectors, accelerated life testing on the photovoltaic (PV) system. While there has been extensive work to create functionally robust arc-fault detectors

  20. ALS Beamline Design Requirements - Revision 1

    E-Print Network [OSTI]

    Heimann, Phil

    2010-01-01

    be protected by a ground fault circuit interrupter (GFCI).The ALS routinely installs GFCI at convenient locations

  1. Interruptions : using activity transitions to trigger proactive messages

    E-Print Network [OSTI]

    Ho, Joyce (Joyce Carmen)

    2004-01-01

    The proliferation of mobile devices and their tendency to present information proactively has led to an increase in device generated interruptions experienced by users. These interruptions are not confined to a particular ...

  2. Short-Circuit Modeling of a Wind Power Plant: Preprint

    SciTech Connect (OSTI)

    Muljadi, E.; Gevorgian, V.

    2011-03-01

    This paper investigates the short-circuit behavior of a WPP for different types of wind turbines. The short-circuit behavior will be presented. Both the simplified models and detailed models are used in the simulations and both symmetrical faults and unsymmetrical faults are discussed.

  3. Observability of Stuck-at-Faults with Differential Power Analysis

    E-Print Network [OSTI]

    Boyer, Edmond

    ,flottes,rouzeyre}@lirmm.fr Abstract In this paper we propose an innovative method to test integrated circuits based on the use of the current consumed by the circuit during net transitions, it does not require observing primary outputs of the circuit and allows the test of hard-to-observe faults. Conversely to Iddq, this technique is not sensible

  4. Arc fault detection system

    DOE Patents [OSTI]

    Jha, Kamal N. (Bethel Park, PA)

    1999-01-01

    An arc fault detection system for use on ungrounded or high-resistance-grounded power distribution systems is provided which can be retrofitted outside electrical switchboard circuits having limited space constraints. The system includes a differential current relay that senses a current differential between current flowing from secondary windings located in a current transformer coupled to a power supply side of a switchboard, and a total current induced in secondary windings coupled to a load side of the switchboard. When such a current differential is experienced, a current travels through a operating coil of the differential current relay, which in turn opens an upstream circuit breaker located between the switchboard and a power supply to remove the supply of power to the switchboard.

  5. Arc fault detection system

    DOE Patents [OSTI]

    Jha, K.N.

    1999-05-18

    An arc fault detection system for use on ungrounded or high-resistance-grounded power distribution systems is provided which can be retrofitted outside electrical switchboard circuits having limited space constraints. The system includes a differential current relay that senses a current differential between current flowing from secondary windings located in a current transformer coupled to a power supply side of a switchboard, and a total current induced in secondary windings coupled to a load side of the switchboard. When such a current differential is experienced, a current travels through a operating coil of the differential current relay, which in turn opens an upstream circuit breaker located between the switchboard and a power supply to remove the supply of power to the switchboard. 1 fig.

  6. Wind Power Plant Enhancement with a Fault-Current Limiter: Preprint

    SciTech Connect (OSTI)

    Muljadi, E.; Gevorgian, V.; DeLaRosa, F.

    2011-03-01

    This paper investigates the capability of a saturable core fault-current limiter to limit the short circuit current of different types of wind turbine generators.

  7. Microsoft Word - GroundFaultSAND-rev7-JJ.doc

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    to describe analytically without transcendental equations, but the use of computer circuit simulations can describe the behavior of a PV system for a wide variety of fault...

  8. Application of functional learning to ATPG and design verification for combinational circuits 

    E-Print Network [OSTI]

    Mukherjee, Rajarshim

    1994-01-01

    to detect faults and in detecting redundant faults. Learning techniques have also been effectively applied to the problem of design verification for combinational circuits. This paper presents Functional Learning, a new method of learning, based...

  9. Realization of User Level Fault Tolerant Policy Management through a Holistic Approach for Fault Correlation

    SciTech Connect (OSTI)

    Park, Byung H [ORNL; Naughton, III, Thomas J [ORNL; Agarwal, Pratul K [ORNL; Bernholdt, David E [ORNL; Geist, Al [ORNL; Tippens, Jennifer L [ORNL

    2011-01-01

    Many modern scientific applications, which are designed to utilize high performance parallel com- puters, occupy hundreds of thousands of computational cores running for days or even weeks. Since many scien- tists compete for resources, most supercomputing centers practice strict scheduling policies and perform meticulous accounting on their usage. Thus computing resources and time assigned to a user is considered invaluable. However, most applications are not well prepared for un- foreseeable faults, still relying on primitive fault tolerance techniques. Considering that ever-plunging mean time to interrupt (MTTI) is making scientific applications more vulnerable to faults, it is increasingly important to provide users not only an improved fault tolerant environment, but also a framework to support their own fault tolerance policies so that their allocation times can be best utilized. This paper addresses a user level fault tolerance policy management based on a holistic approach to digest and correlate fault related information. It introduces simple semantics with which users express their policies on faults, and illustrates how event correlation techniques can be applied to manage and determine the most preferable user policies. The paper also discusses an implementation of the framework using open source software, and demonstrates, as an example, how a molecular dynamics simulation application running on the institutional cluster at Oak Ridge National Laboratory benefits from it.

  10. NREL: Awards and Honors - Current Interrupt Charging Algorithm...

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Current Interrupt Charging Algorithm for Lead-Acid Batteries Developers: Matthew A. Keyser, Ahmad A. Pesaran, and Mark M. Mihalic, National Renewable Energy Laboratory; Robert F....

  11. IMPLEMENTATION OF PRECISE INTERRUPTS IN PIPELINED PROCESSORS James E. Smith

    E-Print Network [OSTI]

    Zhang, Zhongfei "Mark"

    is precise if the saved process state corresponds with the sequential model of program execution where one. When an interrupt occurs, the state of an interrupted process is typically saved by the hardware, registers, and memory. If the saved process state is consistent with the sequential architectural model

  12. Servicing a globally broadcast interrupt signal in a multi-threaded computer

    DOE Patents [OSTI]

    Attinella, John E.; Davis, Kristan D.; Musselman, Roy G.; Satterfield, David L.

    2015-12-29

    Methods, apparatuses, and computer program products for servicing a globally broadcast interrupt signal in a multi-threaded computer comprising a plurality of processor threads. Embodiments include an interrupt controller indicating in a plurality of local interrupt status locations that a globally broadcast interrupt signal has been received by the interrupt controller. Embodiments also include a thread determining that a local interrupt status location corresponding to the thread indicates that the globally broadcast interrupt signal has been received by the interrupt controller. Embodiments also include the thread processing one or more entries in a global interrupt status bit queue based on whether global interrupt status bits associated with the globally broadcast interrupt signal are locked. Each entry in the global interrupt status bit queue corresponds to a queued global interrupt.

  13. Understanding the Cost of Power Interruptions to U.S. Electricity...

    Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

    Understanding the Cost of Power Interruptions to U.S. Electricity Consumers Understanding the Cost of Power Interruptions to U.S. Electricity Consumers The massive electric power...

  14. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 12, NO. 3, MARCH 2004 299 Trading Off Transient Fault Tolerance and Power

    E-Print Network [OSTI]

    Tessier, Russell

    Trading Off Transient Fault Tolerance and Power Consumption in Deep Submicron (DSM) VLSI Circuits Atul Abstract--High fault tolerance for transient faults and low- power consumption are key objectives, defibrillators, and other electronic gadgets must not only be designed for fault tolerance but also for ultra-low-power

  15. Back Fed Main Breakers with Ground-Fault Protection The NEC has had for many editions, a requirement (230.95) that solidly grounded

    E-Print Network [OSTI]

    Johnson, Eric E.

    Back Fed Main Breakers with Ground-Fault Protection The NEC has had for evaluating the backfeeding of the basic circuit breaker, most of the accessories

  16. Simulating Threshold Circuits by Majority Circuits \\Lambda

    E-Print Network [OSTI]

    Karpinski, Marek

    Simulating Threshold Circuits by Majority Circuits \\Lambda Mikael Goldmann y Numerical Analysis, and Kailath proved super­linear lower bounds on the number of wires in constant­depth majority circuits­size depth 2 majority circuit. In general we show that a polynomial­size, depth­ d threshold circuit can

  17. Federated Testbed Circuits

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Testbed Circuits Network R&D Overview Experimental Network Testbeds 100G SDN Testbed Dark Fiber Testbed Federated Testbed Circuits Test Circuit Service Performance (perfSONAR)...

  18. Neural net application to transmission line fault detection and classification 

    E-Print Network [OSTI]

    Rikalo, Igor

    1994-01-01

    . So far, several NN implementations for various fault diagnosis problems have been reported in the literature. A number of papers describing NN applications in pov er systems categorized in appropriate groups can be found in [19, 20]. 1. 3. Thesis... important issue for stable and reliable operation of pov;er systems. The main target of the fault analysis are circuit breaker and protection relay operations. The task of the analysis is to reach a conclusion about the current state of the electrical...

  19. Natural Convective Heat Transfer from Interrupted Rectangular Fins

    E-Print Network [OSTI]

    Bahrami, Majid

    industrial applications to cool electronic, power electronic, telecommunications, and automotive components. Those components might be either high-power semiconductor devices, e.g., diodes, thyristors, IGBTs on geometrical parameters for interrupted walls is presented using a blending technic for two asymptotes

  20. Negotiating Task Interruptions with Virtual Agents for Health Behavior Change

    E-Print Network [OSTI]

    Bickmore, Timothy

    and chronic disease in the United States [18]. In addition, adherence to prescribed treatments, such as lack of physical activity and unhealthy dietary habits, are among the leading causes of death rate. However, as many recent studies in task interruption have shown, responsiveness

  1. Optimal fault location 

    E-Print Network [OSTI]

    Knezev, Maja

    2008-10-10

    sequence of events newly obtained recording belongs. Software prototype of the proposed automated fault location analysis is developed using Java programming language. Fault location analysis is automatically triggered by appearance of new event files in a...

  2. High speed, long distance, data transmission multiplexing circuit

    DOE Patents [OSTI]

    Mariotti, Razvan (Boulder, CO)

    1991-01-01

    A high speed serial data transmission multiplexing circuit, which is operable to accurately transmit data over long distances (up to 3 Km), and to multiplex, select and continuously display real time analog signals in a bandwidth from DC to 100 Khz. The circuit is made fault tolerant by use of a programmable flywheel algorithm, which enables the circuit to tolerate one transmission error before losing synchronization of the transmitted frames of data. A method of encoding and framing captured and transmitted data is used which has a low overhead and prevents some particular transmitted data patterns from locking an included detector/decoder circuit.

  3. Resistive Bridge Fault Modeling,Simulationand Test Generation Vijay R. Sar-Dessai

    E-Print Network [OSTI]

    Walker, Duncan M. "Hank"

    Resistive Bridge Fault Modeling,Simulationand Test Generation Vijay R. Sar-Dessai Intel Corporation.sar-dessai@intel.com Abstract In this work' we develop models of resistive bridging faults and study thefault coverage on ISCAS85 circuits of different test sets using resistive and zero-ohm bridges at different supply voltages

  4. Exploring Interruption in HRI using Wizard of Oz Paul Saulnier, Ehud Sharlin, Saul Greenberg

    E-Print Network [OSTI]

    Greenberg, Saul

    experiments and should call for future research of interruption in human-robot interaction. II. DESCRIPTION of Oz (WoO) should interrupt humans in various social settings. While there is considerable work social HRI experiments as well as reflections on our future interruption HRI research Keywords

  5. High voltage fault current limiter having immersed phase coils

    DOE Patents [OSTI]

    Darmann, Francis Anthony

    2014-04-22

    A fault current limiter including: a ferromagnetic circuit formed from a ferromagnetic material and including at least a first limb, and a second limb; a saturation mechanism surrounding a limb for magnetically saturating the ferromagnetic material; a phase coil wound around a second limb; a dielectric fluid surrounding the phase coil; a gaseous atmosphere surrounding the saturation mechanism.

  6. Ris-M-2311 AUTOMATIC FAULT TREE CONSTRUCTION WITH RIKKE

    E-Print Network [OSTI]

    evaluated and listed. The cut sets were evaluated using FAUNET and the FAUNET interface programs included order. During evaluation of the HI fault tree an interesting effect was observed. The shut off valve circuit with cross coupling to two gas flow sensors. The sensors are represented by the "load" components

  7. High-capacity single-pressure SF/sub 6/ interrupters. Final report

    SciTech Connect (OSTI)

    Rostron, J R; Berkebile, L E; Spindle, H E

    1983-05-01

    The object of this project was to design and develop a high-voltage, single-pressure, SF/sub 6/ interrupter with an interrupting capability of 120 kA at 145 kV with a continuous current rating of 5000 A and an interrupting time of 1.5 cycles or less. A second objective of 100 kA at 242 kV was added during the project. Mathematical models were used to extrapolate design requirements from existing data for 63 and 80 kA. Two model puffers, one liquid and the other gas, were designed and tested to obtain data at 100 kA. An interrupter, optimized on the basis of total prospective breaker cost, was designed using the mathematical models. A study was made of the construction materials to operate under the high-stress conditions in this interrupter. Existing high-speed movies of high-current arcs under double-flow conditions were analyzed to obtain more information for modeling the interrupter. The optimized interrupter design was built and tested. The interrupting capability confirmed calculations of predicted performance near current zero; however, the dielectric strength after interrupting these high-current arcs was not adequate for the 145-kV or the 242-kV ratings. The dielectric strength was reduced by hot gases flowing out of the interrupter. Valuable data have been obtained for modeling the SF/sub 6/ puffer interrupter for high currents.

  8. Preventing Electrical Shock 

    E-Print Network [OSTI]

    Smith, David

    2004-09-16

    Fault Circuit Interrupters (GFCI), fuses and circuit breakers, grounding, and polarization. Ground fault circuit interrupters (GFCI) protect against electrocution by monitoring the current fl ow to an electrical device and comparing it to the amount... of current fl owing back, thus detecting if some current is fl owing back through the ground through a path other than the wire. A GFCI recognizes these ?ground faults? and stops current from fl owing in the circuit. There are three types of GFCIs: ? GFCI...

  9. Fault simulation and test generation for small delay faults 

    E-Print Network [OSTI]

    Qiu, Wangqi

    2007-04-25

    Delay faults are an increasingly important test challenge. Traditional delay fault models are incomplete in that they model only a subset of delay defect behaviors. To solve this problem, a more realistic delay fault model has been developed which...

  10. Solar system fault detection

    DOE Patents [OSTI]

    Farrington, R.B.; Pruett, J.C. Jr.

    1984-05-14

    A fault detecting apparatus and method are provided for use with an active solar system. The apparatus provides an indication as to whether one or more predetermined faults have occurred in the solar system. The apparatus includes a plurality of sensors, each sensor being used in determining whether a predetermined condition is present. The outputs of the sensors are combined in a pre-established manner in accordance with the kind of predetermined faults to be detected. Indicators communicate with the outputs generated by combining the sensor outputs to give the user of the solar system and the apparatus an indication as to whether a predetermined fault has occurred. Upon detection and indication of any predetermined fault, the user can take appropriate corrective action so that the overall reliability and efficiency of the active solar system are increased.

  11. Solar system fault detection

    DOE Patents [OSTI]

    Farrington, Robert B. (Wheatridge, CO); Pruett, Jr., James C. (Lakewood, CO)

    1986-01-01

    A fault detecting apparatus and method are provided for use with an active solar system. The apparatus provides an indication as to whether one or more predetermined faults have occurred in the solar system. The apparatus includes a plurality of sensors, each sensor being used in determining whether a predetermined condition is present. The outputs of the sensors are combined in a pre-established manner in accordance with the kind of predetermined faults to be detected. Indicators communicate with the outputs generated by combining the sensor outputs to give the user of the solar system and the apparatus an indication as to whether a predetermined fault has occurred. Upon detection and indication of any predetermined fault, the user can take appropriate corrective action so that the overall reliability and efficiency of the active solar system are increased.

  12. Cost of Power Interruptions to Electricity Consumers in the United States (U.S.)

    E-Print Network [OSTI]

    Hamachi LaCommare, Kristina; Eto, Joseph H.

    2006-01-01

    Mean Reliability Event Data SAIDI Trimmed Mean (StandardEEI Annual Report c a b SAIFI SAIDI MAIFI Source: EPRI 2003Interruption Duration Index (SAIDI) and System Average

  13. Symmetrical and Unsymmetrical Fault Currents of a Wind Power Plant: Preprint

    SciTech Connect (OSTI)

    Gevorgian, V.; Singh, M.; Muljadi, E.

    2011-12-01

    This paper investigates the short-circuit behavior of a wind power plant for different types of wind turbines. Both symmetrical faults and unsymmetrical faults are investigated. The size of wind power plants (WPPs) keeps getting bigger and bigger. The number of wind plants in the U.S. has increased very rapidly in the past 10 years. It is projected that in the U.S., the total wind power generation will reach 330 GW by 2030. As the importance of WPPs increases, planning engi-neers must perform impact studies used to evaluate short-circuit current (SCC) contribution of the plant into the transmission network under different fault conditions. This information is needed to size the circuit breakers, to establish the proper sys-tem protection, and to choose the transient suppressor in the circuits within the WPP. This task can be challenging to protec-tion engineers due to the topology differences between different types of wind turbine generators (WTGs) and the conventional generating units. This paper investigates the short-circuit behavior of a WPP for different types of wind turbines. Both symmetrical faults and unsymmetrical faults are investigated. Three different soft-ware packages are utilized to develop this paper. Time domain simulations and steady-state calculations are used to perform the analysis.

  14. Transient fault modeling and fault injection simulation 

    E-Print Network [OSTI]

    Yuan, Xuejun

    1996-01-01

    An accurate transient fault model is presented in this thesis. A 7-term exponential current upset model is derived from the results of a device-level, 3-dimensional, single-event-upset simulation. A curve-fitting algorithm is used to extract...

  15. 2566 IEEE TRANSACTIONS ON PLASMA SCIENCE, VOL. 36, NO. 5, OCTOBER 2008 Quantitative Analysis of Gas Circuit Breaker

    E-Print Network [OSTI]

    Basse, Nils Plesner

    2566 IEEE TRANSACTIONS ON PLASMA SCIENCE, VOL. 36, NO. 5, OCTOBER 2008 Quantitative Analysis of Gas-circuit current interruption performance. In this paper, we study a single arc discharge both using measurements in the heating volume created by radiative ablation of the Polytetrafluoroethylene nozzles surrounding the arc

  16. The Cost of Interrupted Work: More Speed and Stress Gloria Mark

    E-Print Network [OSTI]

    Madiraju, Praveen

    , systems might be designed to help colleagues gear their interruptions to others so as match the context discuss implications for how system design can support interrupted work. Author Keywords Multi as the task at-hand are beneficial, then this has important implications for system design. For example

  17. A Statistical Method for Extracting Uninterrupted and Interrupted Collocations from Very Large Corpora

    E-Print Network [OSTI]

    A Statistical Method for Extracting Uninterrupted and Interrupted Collocations from Very Large-gram of m'bitrary N can be applied to the extraction of uninterrupted collocations. But this method posed by the proposal of a method that enable to extract interrupted collocations. The new methods are applied

  18. Persuasion, Task Interruption and Health Regimen Timothy Bickmore, Daniel Mauer, Francisco Crespo, and Thomas Brown

    E-Print Network [OSTI]

    Bickmore, Timothy

    and unhealthy dietary habits, are among the leading causes of death and chronic disease in the United States [21 in a relatively high compliance rate. However, as many recent studies in task interruption have shown other factors such as the emotional state of the user [15] and the modality of the interruption [1]. We

  19. Bridge Fault Simulation Strategies for CMOS Integrated Circuits Brian Chess

    E-Print Network [OSTI]

    Larrabee, Tracy

    , is more efficient---especially for larger cir­ cuits. I. Introduction Obtaining low IC defect levels

  20. Charge regulation circuit

    DOE Patents [OSTI]

    Ball, Don G. (Livermore, CA)

    1992-01-01

    A charge regulation circuit provides regulation of an unregulated voltage supply in the range of 0.01%. The charge regulation circuit is utilized in a preferred embodiment in providing regulated voltage for controlling the operation of a laser.

  1. An efficient logic fault diagnosis framework based on effect-cause approach 

    E-Print Network [OSTI]

    Wu, Lei

    2009-05-15

    analysis. Guided-probe analysis employed a physical voltage probe and feedback from an analysis algorithm to intelligently select accessible circuit nodes for evaluation [5]. Two examples were Western Electric Company?s DORA [11] and an early approach... the cost of simulating each of these faults can be expensive, especially if the simulation considers electrical effects. All of the above bridging fault diagnosis techniques are based on the cause-effect approach. Venkataraman and Fuchs presented a...

  2. Piezoelectric drive circuit

    DOE Patents [OSTI]

    Treu, Jr., Charles A. (Raymore, MO)

    1999-08-31

    A piezoelectric motor drive circuit is provided which utilizes the piezoelectric elements as oscillators and a Meacham half-bridge approach to develop feedback from the motor ground circuit to produce a signal to drive amplifiers to power the motor. The circuit automatically compensates for shifts in harmonic frequency of the piezoelectric elements due to pressure and temperature changes.

  3. Piezoelectric drive circuit

    DOE Patents [OSTI]

    Treu, C.A. Jr.

    1999-08-31

    A piezoelectric motor drive circuit is provided which utilizes the piezoelectric elements as oscillators and a Meacham half-bridge approach to develop feedback from the motor ground circuit to produce a signal to drive amplifiers to power the motor. The circuit automatically compensates for shifts in harmonic frequency of the piezoelectric elements due to pressure and temperature changes. 7 figs.

  4. Automated Fault Location In Smart Distribution Systems 

    E-Print Network [OSTI]

    Lotfifard, Saeed

    2012-10-19

    of Energy (DOE) “Grid 2030” initiatives for grid modernization by improving reliability indices of the network. Improving customer average interruption duration index (CAIDI) and system average interruption duration index (SAIDI) are direct advantages...

  5. A method to determine fault vectors in 4H-SiC from stacking sequences observed on high resolution transmission electron microscopy images

    SciTech Connect (OSTI)

    Wu, Fangzhen; Wang, Huanhuan; Raghothamachar, Balaji; Dudley, Michael; Mueller, Stephan G.; Chung, Gil; Sanchez, Edward K.; Hansen, Darren; Loboda, Mark J.; Zhang, Lihua; Su, Dong; Kisslinger, Kim; Stach, Eric

    2014-09-14

    A new method has been developed to determine the fault vectors associated with stacking faults in 4H-SiC from their stacking sequences observed on high resolution TEM images. This method, analogous to the Burgers circuit technique for determination of dislocation Burgers vector, involves determination of the vectors required in the projection of the perfect lattice to correct the deviated path constructed in the faulted material. Results for several different stacking faults were compared with fault vectors determined from X-ray topographic contrast analysis and were found to be consistent. This technique is expected to applicable to all structures comprising corner shared tetrahedra.

  6. Method for deposition of a conductor in integrated circuits

    DOE Patents [OSTI]

    Creighton, J.R.; Dominguez, F.; Johnson, A.W.; Omstead, T.R.

    1997-09-02

    A method is described for fabricating integrated semiconductor circuits and, more particularly, for the selective deposition of a conductor onto a substrate employing a chemical vapor deposition process. By way of example, tungsten can be selectively deposited onto a silicon substrate. At the onset of loss of selectivity of deposition of tungsten onto the silicon substrate, the deposition process is interrupted and unwanted tungsten which has deposited on a mask layer with the silicon substrate can be removed employing a halogen etchant. Thereafter, a plurality of deposition/etch back cycles can be carried out to achieve a predetermined thickness of tungsten. 2 figs.

  7. The detection of high impedance faults using random fault behavior 

    E-Print Network [OSTI]

    Carswell, Patrick Wayne

    1988-01-01

    and cleared by conventional overcurrent devices. Examples of high impedance fault scenarios include broken conductors and grounded conductors as is the case with tree faults. Most high impedance fault situations occur on the power distribution system due... of the most promising proposals are presented and commented upon as to their weaknesses and limitations if implemented on an actual power distribution system. A new algorithm is developed which attempts to detect the presence of a high impedance fault...

  8. Abstract--The FREEDM grid utilizes solid state transformers (SST) and solid state fault interruption devices (FID) which may

    E-Print Network [OSTI]

    Kimball, Jonathan W.

    distributed generation and distributed energy storage devices (DESD) on the grid. Replacing conventional are 6.5kV silicon IGBT and 600V silicon IGBT respectively. The switching frequency of the high voltage silicon IGBT devices is 1 kHz, and the low voltage IGBT in the VSI switches is 15 kHz. Fig. 1. Solid state

  9. Fault tolerant linear actuator

    DOE Patents [OSTI]

    Tesar, Delbert

    2004-09-14

    In varying embodiments, the fault tolerant linear actuator of the present invention is a new and improved linear actuator with fault tolerance and positional control that may incorporate velocity summing, force summing, or a combination of the two. In one embodiment, the invention offers a velocity summing arrangement with a differential gear between two prime movers driving a cage, which then drives a linear spindle screw transmission. Other embodiments feature two prime movers driving separate linear spindle screw transmissions, one internal and one external, in a totally concentric and compact integrated module.

  10. Computer hardware fault administration

    DOE Patents [OSTI]

    Archer, Charles J. (Rochester, MN); Megerian, Mark G. (Rochester, MN); Ratterman, Joseph D. (Rochester, MN); Smith, Brian E. (Rochester, MN)

    2010-09-14

    Computer hardware fault administration carried out in a parallel computer, where the parallel computer includes a plurality of compute nodes. The compute nodes are coupled for data communications by at least two independent data communications networks, where each data communications network includes data communications links connected to the compute nodes. Typical embodiments carry out hardware fault administration by identifying a location of a defective link in the first data communications network of the parallel computer and routing communications data around the defective link through the second data communications network of the parallel computer.

  11. Electric Power Interruption Cost Estimates for Individual Industries, Sectors, and the U.S. Economy 

    E-Print Network [OSTI]

    Balducci, P. J.; Roop, J. M.; Schienbein, L. A.; DeSteese, J. G.; Weimar, M. R.

    2003-01-01

    . Interruption cost estimates are presented as a function of outage duration (e.g., 20 minutes, 1-hour, 3-hour), and are normalized in terms of dollars per peak kW....

  12. Performance Evaluation of Interrupt-Driven Kernels in Gigabit Networks K. Salah K. El-Badawi

    E-Print Network [OSTI]

    Salah, Khaled Hamed

    -Badawi Department of Information and Computer Science King Fahd University of Petroleum and Minerals Dhahran 31261 overhead and latency for handling incoming packets are low. However, interrupt overhead cost directly

  13. EC5135: Analog Electronic Circuits EC3102: Analog Circuits

    E-Print Network [OSTI]

    Krishnapura, Nagendra

    #12;Course prerequisites Circuit analysis Mesh, nodal analyses RLC, linear dependent sources Laplace and Kemmerly, Engineering Circuit Analysis, McGraw Hill, 6/e. B. P. Lathi, Linear Systems and Signals, Oxford Circuits EC3102: Analog Circuits #12;Course contents Nonlinear circuits-incremental analysis Obtaining

  14. Regenerative feedback resonant circuit

    SciTech Connect (OSTI)

    Jones, A. Mark; Kelly, James F.; McCloy, John S.; McMakin, Douglas L.

    2014-09-02

    A regenerative feedback resonant circuit for measuring a transient response in a loop is disclosed. The circuit includes an amplifier for generating a signal in the loop. The circuit further includes a resonator having a resonant cavity and a material located within the cavity. The signal sent into the resonator produces a resonant frequency. A variation of the resonant frequency due to perturbations in electromagnetic properties of the material is measured.

  15. Remote reset circuit

    DOE Patents [OSTI]

    Gritzo, Russell E. (West Melbourne, FL)

    1987-01-01

    A remote reset circuit acts as a stand-alone monitor and controller by clocking in each character sent by a terminal to a computer and comparing it to a given reference character. When a match occurs, the remote reset circuit activates the system's hardware reset line. The remote reset circuit is hardware based centered around monostable multivibrators and is unaffected by system crashes, partial serial transmissions, or power supply transients.

  16. Remote reset circuit

    DOE Patents [OSTI]

    Gritzo, R.E.

    1985-09-12

    A remote reset circuit acts as a stand-along monitor and controller by clocking in each character sent by a terminal to a computer and comparing it to a given reference character. When a match occurs, the remote reset circuit activates the system's hardware reset line. The remote reset circuit is hardware based centered around monostable multivibrators and is unaffected by system crashes, partial serial transmissions, or power supply transients. 4 figs.

  17. A hierarchical circuit extractor 

    E-Print Network [OSTI]

    Ledbetter, William Burl

    1982-01-01

    committee. V1 TABLE OF CONTENTS CHAPTER I INTRODUCTION II CIRCUIT EXTRACTION III HIERARCHICAL CIRCUIT EXTRACTION IV A HIERARCHICAL CIRCUIT EXTRACTOR V EVALUATION VI CONCLUSIONS REFERENCES APPENDIX A APPENDIX B VITA PAGE 12 16 29 39 43 44... 46 103 LIST OF FIGURES FIGURE I Symbolic Node Name Differentiation Z SIE Node Connectivity Algorithm 3 Sel ecti ve Interface Extr acti on Al gori thm 4 Checkplot of LEDRC 5 Extraction of LEDRC 6 Schematic of LEDRC . 7 Checkplot of LEDIN . 8...

  18. IEEE TRANSACTIONS LARGE SCALE INTEGRATION (VLSI) SYSTEMS, MARCH Trading Off Transient Fault Tolerance and Power

    E-Print Network [OSTI]

    Tessier, Russell

    tolerance also ultra­low­power consumption limited battery In paper, a highly accurate method estimating batteries their source power. limited battery the ability of replace recharge battery, circuits used. These errors called transient faults, or single­event upsets (SEU). event causing upset be an energetic nuclear

  19. Logic gates at the surface code threshold: Superconducting qubits poised for fault-tolerant quantum computing

    E-Print Network [OSTI]

    Martinis, John M.

    Logic gates at the surface code threshold: Superconducting qubits poised for fault-tolerant quantum circuits, and is compatible with microfabrication. For superconducting qubits the surface code7 99%. Here, we demonstrate a universal set of logic gates in a superconducting multi-qubit processor

  20. Circuit Theory for Analysis and Design of Spintronic Integrated Circuits

    E-Print Network [OSTI]

    Manipatruni, Sasikanth; Young, Ian A

    2011-01-01

    We present a theoretical and a numerical formalism for analysis and design of spintronic integrated circuits (SPINICs). The proposed formalism encompasses a generalized circuit theory for spintronic integrated circuits based on nanomagnetic dynamics and spin transport. We derive the circuit models for vector spin conduction in non-magnetic and magnetic components. We then propose an extension to the modified nodal analysis for the analysis of spin circuits. We demonstrate the applicability of the proposed theory using an example spin logic circuit.

  1. Compensated gain control circuit for buck regulator command charge circuit

    DOE Patents [OSTI]

    Barrett, David M. (Albuquerque, NM)

    1996-01-01

    A buck regulator command charge circuit includes a compensated-gain control signal for compensating for changes in the component values in order to achieve optimal voltage regulation. The compensated-gain control circuit includes an automatic-gain control circuit for generating a variable-gain control signal. The automatic-gain control circuit is formed of a precision rectifier circuit, a filter network, an error amplifier, and an integrator circuit.

  2. Compensated gain control circuit for buck regulator command charge circuit

    DOE Patents [OSTI]

    Barrett, D.M.

    1996-11-05

    A buck regulator command charge circuit includes a compensated-gain control signal for compensating for changes in the component values in order to achieve optimal voltage regulation. The compensated-gain control circuit includes an automatic-gain control circuit for generating a variable-gain control signal. The automatic-gain control circuit is formed of a precision rectifier circuit, a filter network, an error amplifier, and an integrator circuit. 5 figs.

  3. Quantum Circuits Architecture

    E-Print Network [OSTI]

    Giulio Chiribella; Giacomo Mauro D'Ariano; Paolo Perinotti

    2007-12-09

    We present a method for optimizing quantum circuits architecture. The method is based on the notion of "quantum comb", which describes a circuit board in which one can insert variable subcircuits. The method allows one to efficiently address novel kinds of quantum information processing tasks, such as storing-retrieving, and cloning of channels.

  4. LABORATORY V ELECTRIC CIRCUITS

    E-Print Network [OSTI]

    Minnesota, University of

    Lab V -1 LABORATORY V ELECTRIC CIRCUITS Electrical devices are the cornerstones of our modern world understanding of them. In the previous laboratory, you studied the behavior of electric fields and their effect successfully completing this laboratory, you should be able to: · apply the concept of circuit to any

  5. Approximate circuits for increased reliability

    DOE Patents [OSTI]

    Hamlet, Jason R.; Mayo, Jackson R.

    2015-12-22

    Embodiments of the invention describe a Boolean circuit having a voter circuit and a plurality of approximate circuits each based, at least in part, on a reference circuit. The approximate circuits are each to generate one or more output signals based on values of received input signals. The voter circuit is to receive the one or more output signals generated by each of the approximate circuits, and is to output one or more signals corresponding to a majority value of the received signals. At least some of the approximate circuits are to generate an output value different than the reference circuit for one or more input signal values; however, for each possible input signal value, the majority values of the one or more output signals generated by the approximate circuits and received by the voter circuit correspond to output signal result values of the reference circuit.

  6. Stress and fault rock controls on fault zone hydrology, Coso...

    Open Energy Info (EERE)

    fault zone hydrology, Coso geothermal field, CA Abstract In crystalline rock of the Coso Geothermal Field, CA, fractures are the primary source of permeability. At reservoir...

  7. Fault interaction near Hollister, California

    SciTech Connect (OSTI)

    Mavko, G.M.

    1982-09-10

    A numerical model is used to study fault stress slip near Hollister, California. The geometrically complex system of interacting faults, including the San Andreas, Calaveras, Sargent, and Busch faults, is approximated with a two-dimensional distribution of short planar fault segments in an elastic medium. The steady stress and slip rate are simulated by specifying frictional strength and stepping the remote stress ahead in time. The resulting computed fault stress is roughly proportional to the observed spatial density of small earthquakes, suggesting that the distinction between segments characterized by earthquakes and those with aseismic creep results, in part, from geometry. A nonsteady simulation is made by introducing, in addition, stress drops for individual moderate earthquakes. A close fit of observed creep with calculated slip on the Calaveras and San Andreas faults suggests that many changes in creep rate (averaged over several months) are caused by local moderate earthquakes. In particular, a 3-year creep lag preceding the August 6, 1979, Coyote Lake earthquake on the Calaveras fault seems to have been a direct result of the November 28, 1974, Thanksgiving Day earthquake on the Busch fault. Computed lags in slip rate preceding some other moderate earthquakes in the area are also due to earlier earthquakes. Although the response of the upper 1 km of the fault zone may cause some individual creep events and introduce delays in others, the long-term rate appears to reflect deep slip.

  8. Sensor readout detector circuit

    DOE Patents [OSTI]

    Chu, D.D.; Thelen, D.C. Jr.

    1998-08-11

    A sensor readout detector circuit is disclosed that is capable of detecting sensor signals down to a few nanoamperes or less in a high (microampere) background noise level. The circuit operates at a very low standby power level and is triggerable by a sensor event signal that is above a predetermined threshold level. A plurality of sensor readout detector circuits can be formed on a substrate as an integrated circuit (IC). These circuits can operate to process data from an array of sensors in parallel, with only data from active sensors being processed for digitization and analysis. This allows the IC to operate at a low power level with a high data throughput for the active sensors. The circuit may be used with many different types of sensors, including photodetectors, capacitance sensors, chemically-sensitive sensors or combinations thereof to provide a capability for recording transient events or for recording data for a predetermined period of time following an event trigger. The sensor readout detector circuit has applications for portable or satellite-based sensor systems. 6 figs.

  9. Nonlinear Circuit Analysis An Introduction 1. Why nonlinear circuits?

    E-Print Network [OSTI]

    Hart, Gus

    Nonlinear Circuit Analysis ­ An Introduction 1. Why nonlinear circuits? Electrical devices: the oscillator. 2. What is a nonlinear circuit? It is easy to understand the difference between a linear and a nonlinear circuit by looking at the difference between a linear and a nonlinear equation: y x ¡ 2 (1) y

  10. Fault current limiter

    DOE Patents [OSTI]

    Darmann, Francis Anthony

    2013-10-08

    A fault current limiter (FCL) includes a series of high permeability posts for collectively define a core for the FCL. A DC coil, for the purposes of saturating a portion of the high permeability posts, surrounds the complete structure outside of an enclosure in the form of a vessel. The vessel contains a dielectric insulation medium. AC coils, for transporting AC current, are wound on insulating formers and electrically interconnected to each other in a manner such that the senses of the magnetic field produced by each AC coil in the corresponding high permeability core are opposing. There are insulation barriers between phases to improve dielectric withstand properties of the dielectric medium.

  11. Fault Current Limiters

    Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

    AFDC Printable Version Share this resource Send a link to EERE: Alternative Fuels Data Center Home Page to someone by E-mail Share EERE: Alternative Fuels Data Center Home Page on Facebook Tweet about EERE: Alternative Fuels Data Center Home Page on Twitter Bookmark EERE: Alternative Fuels Data Center Home Page on Google Bookmark EERE: Alternative Fuels Data Center Home Page on Delicious Rank EERE:FinancingPetroleum12, 2015Executive Order14, 20111,FYDepartment of5 NovemberFarms to FuelFault

  12. Pipeline coating impedance effects on powerline fault current coupling

    SciTech Connect (OSTI)

    Dabkowski, J.

    1989-12-01

    Prior research leading to the development of predictive electromagnetic coupling computer codes has shown that the coating conductance is the principal factor in determining the response of a pipeline to magnetic induction from an overhead power transmission line. Under power line fault conditions, a high voltage may stress the coating causing a significant change in its conductance, and hence, the coupling response. Based upon laboratory experimentation and analysis, a model has been developed which allows prediction of the modified coating characteristics when subjected to high voltage during fault situations. Another program objective was the investigation of a method to determine the high voltage behavior of an existing coating from low voltage in situ field measurements. Such a method appeared conceptually feasible for non-porous coatings whose conductance is primarily a result of current leakage through existing holidays. However, limited testing has shown that difficulties in determining the steel-electrolyte capacitance limit the application of the method Methods for field measurement of the pipeline coating conductance were also studied for both dc ad ac signal excitation. Ac techniques offer the advantage that cathodic protection current interruption is not required, thus eliminating depolarization effects. However, ac field measurement techniques need additional refinement before these methods can be generally applied. 53 figs.

  13. Superconducting flux flow digital circuits

    DOE Patents [OSTI]

    Hietala, V.M.; Martens, J.S.; Zipperian, T.E.

    1995-02-14

    A NOR/inverter logic gate circuit and a flip flop circuit implemented with superconducting flux flow transistors (SFFTs) are disclosed. Both circuits comprise two SFFTs with feedback lines. They have extremely low power dissipation, very high switching speeds, and the ability to interface between Josephson junction superconductor circuits and conventional microelectronics. 8 figs.

  14. Superconducting flux flow digital circuits

    DOE Patents [OSTI]

    Hietala, Vincent M. (Placitas, NM); Martens, Jon S. (Sunnyvale, CA); Zipperian, Thomas E. (Albuquerque, NM)

    1995-01-01

    A NOR/inverter logic gate circuit and a flip flop circuit implemented with superconducting flux flow transistors (SFFTs). Both circuits comprise two SFFTs with feedback lines. They have extremely low power dissipation, very high switching speeds, and the ability to interface between Josephson junction superconductor circuits and conventional microelectronics.

  15. Colorado Regional Faults

    SciTech Connect (OSTI)

    Hussein, Khalid

    2012-02-01

    Citation Information: Originator: Earth Science &Observation Center (ESOC), CIRES, University of Colorado at Boulder Originator: Colorado Geological Survey (CGS) Publication Date: 2012 Title: Regional Faults Edition: First Publication Information: Publication Place: Earth Science & Observation Center, Cooperative Institute for Research in Environmental Science, University of Colorado, Boulder Publisher: Earth Science &Observation Center (ESOC), CIRES, University of Colorado at Boulder Description: This layer contains the regional faults of Colorado Spatial Domain: Extent: Top: 4543192.100000 m Left: 144385.020000 m Right: 754585.020000 m Bottom: 4094592.100000 m Contact Information: Contact Organization: Earth Science &Observation Center (ESOC), CIRES, University of Colorado at Boulder Contact Person: Khalid Hussein Address: CIRES, Ekeley Building Earth Science & Observation Center (ESOC) 216 UCB City: Boulder State: CO Postal Code: 80309-0216 Country: USA Contact Telephone: 303-492-6782 Spatial Reference Information: Coordinate System: Universal Transverse Mercator (UTM) WGS’1984 Zone 13N False Easting: 500000.00000000 False Northing: 0.00000000 Central Meridian: -105.00000000 Scale Factor: 0.99960000 Latitude of Origin: 0.00000000 Linear Unit: Meter Datum: World Geodetic System 1984 (WGS ’984) Prime Meridian: Greenwich Angular Unit: Degree Digital Form: Format Name: Shape file

  16. Optimized Fault Location Final Project Report

    E-Print Network [OSTI]

    Optimized Fault Location Final Project Report Power Systems Engineering Research Center A National Engineering Research Center Optimized Fault Location Concurrent Technologies Corporation Final Project Report

  17. Observer-based fault detection for nuclear reactors

    E-Print Network [OSTI]

    Li, Qing, 1972-

    2001-01-01

    This is a study of fault detection for nuclear reactor systems. Basic concepts are derived from fundamental theories on system observers. Different types of fault- actuator fault, sensor fault, and system dynamics fault ...

  18. System Calls and Interrupt Vectors in an Operating Systems Mark A. Holliday

    E-Print Network [OSTI]

    Holliday, Mark A.

    System Calls and Interrupt Vectors in an Operating Systems Course' Mark A. Holliday Western@wcu.edu Abstract The introductory operating systems course has a tendency to appear to the student as a disparate policies. We describe a sequence of material to cover early in the operating systems course that prevents

  19. A Model for Human Interruptability: Experimental Evaluation and Automatic Estimation from Wearable Sensors

    E-Print Network [OSTI]

    A Model for Human Interruptability: Experimental Evaluation and Automatic Estimation from Wearable Sensors Nicky Kern, Stavros Antifakos, Bernt Schiele Perceptual Computing and Computer Vision ETH Zurich sensors. It is scalable for a large number of sensors, contexts, and situations and allows for online

  20. An Adjustable Robust Optimization Approach to Scheduling of Continuous Industrial Processes Providing Interruptible Load

    E-Print Network [OSTI]

    Grossmann, Ignacio E.

    by reducing electricity consumption Also referred to as interruptible load Can be regarded as spinning as the maximum possible reduction in electricity consumption that can be requested by the grid operator for large industrial electricity consumers Target power consumption Minimum power consumption Time Power

  1. Predictable Interrupt Management for Real Time Kernels over conventional PC Hardware1

    E-Print Network [OSTI]

    Mejia-Alvarez, Pedro

    which this integrated model improves the traditional model. The design of a flexible and portable kernel-CONACyT 42151-Y, and CONACYT 42449-Y Mexico. Abstract In this paper we analyze the traditional model on real-time systems. As a result of this analysis, we propose a model that integrates interrupts

  2. Modeling and Analysis of Interrupt Disable-Enable Scheme K. Salah K. Elbadawi

    E-Print Network [OSTI]

    Salah, Khaled Hamed

    of Information and Computer Science King Fahd University of Petroleum and Minerals Dhahran 31261, Saudi Arabia be degraded due to interrupt overhead caused by heavy incoming traffic. One of the most popular solutions With almost all today's Gigabit NICs, an incoming packet gets transferred (or DMA'd) through the PCI bus from

  3. 562 IEEE TRANSACTIONS ON COMPUTERS, VOL. 31,NO. 5, MAY 1988 Implementing Precise Interrupts in Pipelined

    E-Print Network [OSTI]

    Lee, Hsien-Hsin "Sean"

    in pipelined processors. An interrupt is precise if the saved process state corresponds with a sequential model process is typically saved by the hardware, the software, or by a combinationof the two. The process state generally consists of the program counter, registers, and memory. If the saved process state is consistent

  4. Aging correlation functions of the interrupted fractional Fokker-Planck propagator

    E-Print Network [OSTI]

    Cao, Jianshu

    Aging correlation functions of the interrupted fractional Fokker-Planck propagator James B The authors explore aging in a general semi-Markov process with arbitrary waiting time distributions coordination, but one can generalize the construction to incorporate cutoffs in the aging of the system, i

  5. Throughput-Delay Analysis of Interrupt-Driven Kernels with DMA Enabled and Disabled in High-Speed Networks

    E-Print Network [OSTI]

    Salah, Khaled Hamed

    of Petroleum and Minerals Dhahran 31261, Saudi Arabia Email: {salah,elbadawi}@kfupm.edu.sa Abstract Interrupt incoming traffic. Under heavy network traffic, the system performance will be negatively affected due to interrupt overhead caused by the incoming traffic. In particular, excessive latency and significant

  6. The bridge-type fault current controller--a new facts controller

    SciTech Connect (OSTI)

    Boenig, Heinrich J.; Mielke, C. H. (Charles H.); Burley, B. L. (Burt L.); Chen, Hong; Waynert, J. A. (Joseph A.); Willis, J. O. (Jeffrey O.)

    2002-01-01

    The operation of a novel current controller, which can also function as a fault current limiter and as a solid-state ac circuit breaker, is presented. The controller, which consists of a thyristor bridge, an inductor, and an optional bias power supply, is installed in series with the voltage source and the load, For load current values smaller than a preset value, the inductor of the current controller presents no impedance to the ac current flow. For values higher than the preset current value, the inductor is switched automatically into the ac circuit and limits the amount of current flow. Theoretical results in the form of circuit simulations and experimental results with a single-phase unit, operating on a 13.7 kV three-phase system with peak short-circuit currents of 3140 Arms, are presented.

  7. Hot Pot Detail - Evidence of Quaternary Faulting

    DOE Data Explorer [Office of Scientific and Technical Information (OSTI)]

    Lane, Michael

    2013-06-27

    Compilation of published data, field observations and photo interpretation relevant to Quaternary faulting at Hot Pot.

  8. Hot Pot Detail - Evidence of Quaternary Faulting

    DOE Data Explorer [Office of Scientific and Technical Information (OSTI)]

    Lane, Michael

    Compilation of published data, field observations and photo interpretation relevant to Quaternary faulting at Hot Pot.

  9. Fault-tolerant TCP mechanisms 

    E-Print Network [OSTI]

    Satapati, Suresh Kumar

    2000-01-01

    While fault-tolerance is supported by a variety of critical services that can be accessed over the Internet, they are not robust in that they are oblivious of the impact of their tolerant mechanisms on the service they ...

  10. In the laboratory, workers may be exposed to electrical hazards including electric shock, arc blasts, electro-

    E-Print Network [OSTI]

    Johnson, Eric E.

    Make sure that any outlet near a sink or other water source is Ground-Fault Circuit Interrupter (GFCI) protected. If you have a GFCI, periodically test it by plugging something into it and pushing the "test

  11. Private Circuits II: Keeping Secrets in Tamperable Circuits

    E-Print Network [OSTI]

    Sahai, Amit

    Private Circuits II: Keeping Secrets in Tamperable Circuits Yuval Ishai , Manoj Prabhakaran , Amit completely free from tampering. We obtain the first feasibility results for such private circuits. Our main serious tampering and erase all data in the memory. In terms of the information available to the adversary

  12. Internal structure of the Kern Canyon Fault, California: a deeply exhumed strike-slip fault 

    E-Print Network [OSTI]

    Neal, Leslie Ann

    2002-01-01

    Deformation and mineral alteration adjacent to a 2 km long segment of the Kern Canyon fault near Lake Isabella, California are studied to characterize the internal structure of the fault zone and to understand the development of fault structure...

  13. Bioluminescent bioreporter integrated circuit

    DOE Patents [OSTI]

    Simpson, Michael L. (Knoxville, TN); Sayler, Gary S. (Blaine, TN); Paulus, Michael J. (Knoxville, TN)

    2000-01-01

    Disclosed are monolithic bioelectronic devices comprising a bioreporter and an OASIC. These bioluminescent bioreporter integrated circuit are useful in detecting substances such as pollutants, explosives, and heavy-metals residing in inhospitable areas such as groundwater, industrial process vessels, and battlefields. Also disclosed are methods and apparatus for environmental pollutant detection, oil exploration, drug discovery, industrial process control, and hazardous chemical monitoring.

  14. Circuit breaker lockout device

    DOE Patents [OSTI]

    Kozlowski, L.J.; Shirey, L.A.

    1992-11-24

    An improved lockout assembly for locking a circuit breaker in a selected off or on position is provided. The lockout assembly includes a lock block and a lock pin. The lock block has a hollow interior which fits over the free end of a switch handle of the circuit breaker. The lock block includes at least one hole that is placed in registration with a hole in the free end of the switch handle. A lock tab on the lock block serves to align and register the respective holes on the lock block and switch handle. A lock pin is inserted through the registered holes and serves to connect the lock block to the switch handle. Once the lock block and the switch handle are connected, the position of the switch handle is prevented from being changed by the lock tab bumping up against a stationary housing portion of the circuit breaker. When the lock pin installed, an apertured-end portion of the lock pin is in registration with another hole on the lock block. Then a special scissors conforming to O.S.H.A. regulations can be installed, with one or more padlocks, on the lockout assembly to prevent removal of the lock pin from the lockout assembly, thereby preventing removal of the lockout assembly from the circuit breaker. 2 figs.

  15. Circuit breaker lockout device

    DOE Patents [OSTI]

    Kozlowski, Lawrence J. (New Kensington, PA); Shirey, Lawrence A. (North Huntingdon, PA)

    1992-01-01

    An improved lockout assembly for locking a circuit breaker in a selected off or on position is provided. The lockout assembly includes a lock block and a lock pin. The lock block has a hollow interior which fits over the free end of a switch handle of the circuit breaker. The lock block includes at least one hole that is placed in registration with a hole in the free end of the switch handle. A lock tab on the lock block serves to align and register the respective holes on the lock block and switch handle. A lock pin is inserted through the registered holes and serves to connect the lock block to the switch handle. Once the lock block and the switch handle are connected, the position of the switch handle is prevented from being changed by the lock tab bumping up against a stationary housing portion of the circuit breaker. When the lock pin installed, an apertured-end portion of the lock pin is in registration with another hole on the lock block. Then a special scissors conforming to O.S.H.A. regulations can be installed, with one or more padlocks, on the lockout assembly to prevent removal of the lock pin from the lockout assembly, thereby preventing removal of the lockout assembly from the circuit breaker.

  16. Circuit breaker lockout device

    SciTech Connect (OSTI)

    Kozlowski, L.J.; Shirey, L.A.

    1991-12-31

    An improved lockout assembly for locking a circuit breaker in a selected off or on position is provided. The lockout assembly includes a lock block and a lock pin. The lock block has a hollow interior which fits over the free end of a switch handle of the circuit breaker. The lock block includes at least one hole that is placed in registration with a hole in the free end of the switch handle. A lock tab on the lock block serves to align and register the respective holes on the lock block and switch handle. A lock pin is inserted through the registered holes and serves to connect the lock block to the switch handle. Once the lock block and the switch handle are connected, the position of the switch handle is prevented from being changed by the lock tab bumping up against a stationary housing portion of the circuit breaker. When the lock pin is installed, an apertured-end portion of the lock pin is in registration with another hole on the lock block. Then a special scissors conforming to O.S.H.A. regulations can be installed, with one or more padlocks, on the lockout assembly to prevent removal of the lock pin from the lockout assembly, thereby preventing removal of the lockout assembly from the circuit breaker.

  17. LABORATORY IV ELECTRIC CIRCUITS

    E-Print Network [OSTI]

    Minnesota, University of

    LABORATORY IV ELECTRIC CIRCUITS Lab IV - 1 In the first laboratory, you studied the behavior of conservation. OBJECTIVES After successfully completing this laboratory, you should be able to: · Apply that you will be doing these laboratory problems before your lecturer addresses this material. The purpose

  18. Automatic sweep circuit

    DOE Patents [OSTI]

    Keefe, Donald J. (Lemont, IL)

    1980-01-01

    An automatically sweeping circuit for searching for an evoked response in an output signal in time with respect to a trigger input. Digital counters are used to activate a detector at precise intervals, and monitoring is repeated for statistical accuracy. If the response is not found then a different time window is examined until the signal is found.

  19. Methods of fabricating applique circuits

    DOE Patents [OSTI]

    Dimos, Duane B. (Albuquerque, NM); Garino, Terry J. (Albuquerque, NM)

    1999-09-14

    Applique circuits suitable for advanced packaging applications are introduced. These structures are particularly suited for the simple integration of large amounts (many nanoFarads) of capacitance into conventional integrated circuit and multichip packaging technology. In operation, applique circuits are bonded to the integrated circuit or other appropriate structure at the point where the capacitance is required, thereby minimizing the effects of parasitic coupling. An immediate application is to problems of noise reduction and control in modern high-frequency circuitry.

  20. High voltage MOSFET switching circuit

    DOE Patents [OSTI]

    McEwan, Thomas E. (Livermore, CA)

    1994-01-01

    The problem of source lead inductance in a MOSFET switching circuit is compensated for by adding an inductor to the gate circuit. The gate circuit inductor produces an inductive spike which counters the source lead inductive drop to produce a rectangular drive voltage waveform at the internal gate-source terminals of the MOSFET.

  1. High voltage MOSFET switching circuit

    DOE Patents [OSTI]

    McEwan, T.E.

    1994-07-26

    The problem of source lead inductance in a MOSFET switching circuit is compensated for by adding an inductor to the gate circuit. The gate circuit inductor produces an inductive spike which counters the source lead inductive drop to produce a rectangular drive voltage waveform at the internal gate-source terminals of the MOSFET. 2 figs.

  2. Cost of Power Interruptions to Electricity Consumers in the UnitedStates (U.S.)

    SciTech Connect (OSTI)

    Hamachi LaCommare, Kristina; Eto, Joseph H.

    2006-02-16

    The massive electric power blackout in the northeastern U.S.and Canada on August 14-15, 2003 catalyzed discussions about modernizingthe U.S. electricity grid. Industry sources suggested that investments of$50 to $100 billion would be needed. This work seeks to better understandan important piece of information that has been missing from thesediscussions: What do power interruptions and fluctuations in powerquality (power-quality events) cost electricity consumers? We developed abottom-up approach for assessing the cost to U.S. electricity consumersof power interruptions and power-quality events (referred to collectivelyas "reliability events"). The approach can be used to help assess thepotential benefits of investments in improving the reliability of thegrid. We developed a new estimate based on publicly availableinformation, and assessed how uncertainties in these data affect thisestimate using sensitivity analysis.

  3. Sandia Energy - PV Arc-Fault and Ground Fault Detection and Mitigation...

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Program Home Stationary Power Energy Conversion Efficiency Solar Energy Photovoltaics PV Systems Reliability PV Arc-Fault and Ground Fault Detection and Mitigation Program PV...

  4. Transition-fault test generation 

    E-Print Network [OSTI]

    Cobb, Bradley Douglas

    2013-02-22

    After an integrated circuit is manufactured, it must be tested to insure that it is not defective. Specifically, timing defects are becoming increasingly important to detect because of the decreasing process geometries and increasing clock rates...

  5. Sensor Fault Detection and Isolation System 

    E-Print Network [OSTI]

    Yang, Cheng-Ken

    2014-08-01

    The purpose of this research is to develop a Fault Detection and Isolation (FDI) system which is capable to diagnosis multiple sensor faults in nonlinear cases. In order to lead this study closer to real world applications ...

  6. Boullier The fault zone geology 1 Fault zone geology: lessons from drilling through the Nojima and 1

    E-Print Network [OSTI]

    Boyer, Edmond

    Boullier The fault zone geology 1 Fault zone geology: lessons from active faults with the aim of 11 learning about the geology of the fault all 18 their objectives, have still contributed to a better geological

  7. Sequential circuit design for radiation hardened multiple voltage integrated circuits

    DOE Patents [OSTI]

    Clark, Lawrence T. (Phoenix, AZ); McIver, III, John K. (Albuquerque, NM)

    2009-11-24

    The present invention includes a radiation hardened sequential circuit, such as a bistable circuit, flip-flop or other suitable design that presents substantial immunity to ionizing radiation while simultaneously maintaining a low operating voltage. In one embodiment, the circuit includes a plurality of logic elements that operate on relatively low voltage, and a master and slave latches each having storage elements that operate on a relatively high voltage.

  8. Solid-state circuit breaker with current-limiting characteristic using a superconducting coil

    DOE Patents [OSTI]

    Boenig, H.J.

    1982-08-16

    A thyristor bridge interposes an ac source and a load. A series connected DC source and superconducting coil within the bridge biases the thyristors thereof so as to permit bidirectional ac current flow therethrough under normal operating conditions. Upon a fault condition a control circuit triggers the thyristors so as to reduce ac current flow therethrough to zero in less than two eyeles and to open the bridge thereafter. Upon a temporary overload condition the control circuit triggers the thyristors so as to limit ac current flow therethrough to an acceptable level.

  9. Solid-state circuit breaker with current limiting characteristic using a superconducting coil

    DOE Patents [OSTI]

    Boenig, Heinrich J. (Los Alamos, NM)

    1984-01-01

    A thyristor bridge interposes an ac source and a load. A series connected DC source and superconducting coil within the bridge biases the thyristors thereof so as to permit bidirectional ac current flow therethrough under normal operating conditions. Upon a fault condition a control circuit triggers the thyristors so as to reduce ac current flow therethrough to zero in less than two cycles and to open the bridge thereafter. Upon a temporary overload condition the control circuit triggers the thyristors so as to limit ac current flow therethrough to an acceptable level.

  10. Test Circuit Service

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    AFDC Printable Version Share this resource Send a link to EERE: Alternative Fuels Data Center Home Page to someone by E-mail Share EERE: Alternative Fuels Data Center Home Page on Facebook Tweet about EERE: Alternative Fuels Data Center Home Page on Twitter Bookmark EERE: Alternative Fuels Data Center Homesum_a_epg0_fpd_mmcf_m.xls" ,"Available from WebQuantity ofkandz-cm11 Outreach Home RoomPreservationBio-Inspired Solar FuelTechnologyTel: Name: Rm. Tel:Test Circuit Service Network

  11. Electric Power Interruption Cost Estimates for Individual Industries, Sectors, and U.S. Economy

    SciTech Connect (OSTI)

    Balducci, Patrick J.; Roop, Joseph M.; Schienbein, Lawrence A.; DeSteese, John G.; Weimar, Mark R.

    2002-02-27

    During the last 20 years, utilities and researchers have begun to understand the value in the collection and analysis of interruption cost data. The continued investigation of the monetary impact of power outages will facilitate the advancement of the analytical methods used to measure the costs and benefits from the perspective of the energy consumer. More in-depth analysis may be warranted because of the privatization and deregulation of power utilities, price instability in certain regions of the U.S. and the continued evolution of alternative auxiliary power systems.

  12. Understanding the cost of power interruptions to U.S. electricity consumers

    SciTech Connect (OSTI)

    LaCommare, Kristina Hamachi; Eto, Joseph H.

    2004-09-01

    The massive electric power blackout in the northeastern United States and Canada on August 14-15, 2003 resulted in the U.S. electricity system being called ''antiquated'' and catalyzed discussions about modernizing the grid. Industry sources suggested that investments of $50 to $100 billion would be needed. This report seeks to quantify an important piece of information that has been missing from these discussions: how much do power interruptions and fluctuations in power quality (power-quality events) cost U.S. electricity consumers? Accurately estimating this cost will help assess the potential benefits of investments in improving the reliability of the grid. We develop a comprehensive end-use framework for assessing the cost to U.S. electricity consumers of power interruptions and power-quality events (referred to collectively as ''reliability events''). The framework expresses these costs as a function of: (1) Number of customers by type in a region; (2) Frequency and type of reliability events experienced annually (including both power interruptions and power-quality events) by these customers; (3) Cost of reliability events; and (4) Vulnerability of customers to these events. The framework is designed so that its cost estimate can be improved as additional data become available. Using our framework, we estimate that the national cost of power interruptions is about $80 billion annually, based on the best information available in the public domain. However, there are large gaps in and significant uncertainties about the information currently available. Notably, we were not able to develop an estimate of power-quality events. Sensitivity analysis of some of these uncertainties suggests that the total annual cost could range from less than $30 billion to more than $130 billion. Because of this large range and the enormous cost of the decisions that may be based on this estimate, we encourage policy makers, regulators, and industry to jointly under take the comparatively modest-cost improvements needed in the information used to estimate the cost of reliability events. Specific areas for improvement include: coordinated, nationwide collection of updated information on the cost of reliability events; consistent definition and recording of the duration and frequency of reliability events, including power-quality events; and improved information on the costs of and efforts by consumers to reduce their vulnerability to reliability events.

  13. Decreasing Beam Auto Tuning Interruption Events with In-Situ Chemical Cleaning on Axcelis GSD

    SciTech Connect (OSTI)

    Fuchs, Dieter; Spreitzer, Stefan; Vogl, Josef [Infineon Technologies AG., Wernerwerkstr.2, 93049 Regensburg (Germany); Bishop, Steve; Eldridge, David; Kaim, Robert [ATMI Inc., 7 Commerce Drive, Danbury, CT 06810 (United States)

    2008-11-03

    Ion beam auto tuning time and success rate are often major factors in the utilization and productivity of ion implanters. Tuning software frequently fails to meet specified setup times or recipe parameters, causing production stoppages and requiring manual intervention. Build-up of conductive deposits in the arc chamber and extraction gap can be one of the main causes of auto tuning problems. The deposits cause glitching and ion beam instabilities, which lead to errors in the software optimization routines. Infineon Regensburg has been testing use of XeF{sub 2}, an in-situ chemical cleaning reagent, with positive results in reducing auto tuning interruption events.

  14. TECHNOLOGICAL FLUENCY THROUGH CIRCUIT BENDING

    E-Print Network [OSTI]

    ;Textbook Handmade Electronic Music Nicolas Collins #12;Circuit Bending Creatively hacking and re-purposing (upcycling?) electronics in the service of making sound ! Hardware Hacking vs. Circuit Bending #12 Toy hacking Oscillators Final project #12;Readings / Context Experimental and electronic music

  15. Transmission Line Circuit Alexander Glasser

    E-Print Network [OSTI]

    Anlage, Steven

    Chaos in a Transmission Line Circuit Alexander Glasser Marshal Miller With... Prof. Edward Ott Prof times become shorter, circuit connections behave more and more like transmission lines. Theoretical(t) - Transmission Line (Zo, T) #12;5 Cf/Cr 1000 Vf Capacitance Voltage Cf Cr Model for Nonlinear Capacitor

  16. Wavelet based analysis of circuit breaker operation 

    E-Print Network [OSTI]

    Ren, Zhifang Jennifer

    2004-09-30

    . To automate the diagnostic practice for circuit breaker operation and reduce the utility company's workload, Wavelet based analysis software of circuit breaker operation is developed here. Combined with circuit breaker monitoring system, the analysis software...

  17. Demultiplexer circuit for neural stimulation

    DOE Patents [OSTI]

    Wessendorf, Kurt O; Okandan, Murat; Pearson, Sean

    2012-10-09

    A demultiplexer circuit is disclosed which can be used with a conventional neural stimulator to extend the number of electrodes which can be activated. The demultiplexer circuit, which is formed on a semiconductor substrate containing a power supply that provides all the dc electrical power for operation of the circuit, includes digital latches that receive and store addressing information from the neural stimulator one bit at a time. This addressing information is used to program one or more 1:2.sup.N demultiplexers in the demultiplexer circuit which then route neural stimulation signals from the neural stimulator to an electrode array which is connected to the outputs of the 1:2.sup.N demultiplexer. The demultiplexer circuit allows the number of individual electrodes in the electrode array to be increased by a factor of 2.sup.N with N generally being in a range of 2-4.

  18. Photoconductive circuit element reflectometer

    DOE Patents [OSTI]

    Rauscher, Christen (Alexandria, VA)

    1990-01-01

    A photoconductive reflectometer for characterizing semiconductor devices at millimeter wavelength frequencies where a first photoconductive circuit element (PCE) is biased by a direct current voltage source and produces short electrical pulses when excited into conductance by short first laser light pulses. The electrical pulses are electronically conditioned to improve the frequency related amplitude characteristics of the pulses which thereafter propagate along a transmission line to a device under test. Second PCEs are connected along the transmission line to sample the signals on the transmission line when excited into conductance by short second laser light pulses, spaced apart in time a variable period from the first laser light pulses. Electronic filters connected to each of the second PCEs act as low-pass filters and remove parasitic interference from the sampled signals and output the sampled signals in the form of slowed-motion images of the signals on the transmission line.

  19. Integrated circuits, and design and manufacture thereof

    DOE Patents [OSTI]

    Auracher, Stefan; Pribbernow, Claus; Hils, Andreas

    2006-04-18

    A representation of a macro for an integrated circuit layout. The representation may define sub-circuit cells of a module. The module may have a predefined functionality. The sub-circuit cells may include at least one reusable circuit cell. The reusable circuit cell may be configured such that when the predefined functionality of the module is not used, the reusable circuit cell is available for re-use.

  20. Genetic Circuits in Salmonella typhimurium Arthur Prindle,

    E-Print Network [OSTI]

    Hasty, Jeff

    Genetic Circuits in Salmonella typhimurium Arthur Prindle, Jangir Selimkhanov, Tal Danino,# Phillip circuits that were originally constructed and tested in Escherichia coli translate to Salmonella

  1. Enhancing the quantum efficiency of InGaN yellow-green light-emitting diodes by growth interruption

    SciTech Connect (OSTI)

    Du, Chunhua; Ma, Ziguang; Zhou, Junming; Lu, Taiping; Jiang, Yang; Zuo, Peng; Jia, Haiqiang; Chen, Hong, E-mail: hchen@iphy.ac.cn [Key Laboratory for Renewable Energy, Chinese Academy of Sciences, Beijing Key Laboratory for New Energy Materials and Devices, Beijing National Laboratory for Condense Matter Physics, Institute of Physics, Chinese Academy of Sciences, Beijing 100190 (China)

    2014-08-18

    We studied the effect of multiple interruptions during the quantum well growth on emission-efficiency enhancement of InGaN-based yellow-green light emitting diodes on c-plane sapphire substrate. The output power and dominant wavelength at 20?mA are 0.24 mW and 556.3?nm. High resolution x-ray diffraction, photoluminescence, and electroluminescence measurements demonstrate that efficiency enhancement could be partially attributed to crystal quality improvement of the active region resulted from reduced In clusters and relevant defects on the surface of InGaN layer by introducing interruptions. The less tilted energy band in the quantum well is also caused by the decrease of In-content gradient along c-axis resulted from In segregation during the interruptions, which increases spatial overlap of electron-hole wavefunction and thus the internal quantum efficiency. The latter also leads to smaller blueshift of dominant wavelength with current increasing.

  2. Fault-tolerant dynamic task graph scheduling

    SciTech Connect (OSTI)

    Kurt, Mehmet C.; Krishnamoorthy, Sriram; Agrawal, Kunal; Agrawal, Gagan

    2014-11-16

    In this paper, we present an approach to fault tolerant execution of dynamic task graphs scheduled using work stealing. In particular, we focus on selective and localized recovery of tasks in the presence of soft faults. We elicit from the user the basic task graph structure in terms of successor and predecessor relationships. The work stealing-based algorithm to schedule such a task graph is augmented to enable recovery when the data and meta-data associated with a task get corrupted. We use this redundancy, and the knowledge of the task graph structure, to selectively recover from faults with low space and time overheads. We show that the fault tolerant design retains the essential properties of the underlying work stealing-based task scheduling algorithm, and that the fault tolerant execution is asymptotically optimal when task re-execution is taken into account. Experimental evaluation demonstrates the low cost of recovery under various fault scenarios.

  3. Collateral damage: Evolution with displacement of fracture distribution and secondary fault strands in fault damage zones

    E-Print Network [OSTI]

    Savage, Heather M.; Brodsky, Emily E.

    2011-01-01

    E. McCallum (1999), Reservoir damage around faults: OutcropSkar (2005), Controls on damage zone asymmetry of a normal2007), The evolution of the damage zone with fault growth in

  4. A fault location approach for fuzzy fault section estimation on radial distribution feeders 

    E-Print Network [OSTI]

    Andoh, Kwame Sarpong

    2000-01-01

    Locating the faulted section of a distribution system is a difficult task because of lack of accurate system models and the presence of uncertainty in the data used for estimating the fault section. Many of the methods used to account...

  5. Seismoelectric Imaging of a Shallow Fault System Employing Fault Guided Waves 

    E-Print Network [OSTI]

    Cohrs, Frelynn Joseph Reese

    2012-07-16

    . The seismic data revealed dispersive energy packets, indicative of guided waves, within the fault zone and absent in the surrounding lithologies. The seismoelectric data was able to produce comparable signals in the fault zone showing guided waves....

  6. ShrinkyCircuits: Sketching, Shrinking, and Formgiving for Electronic Circuits

    E-Print Network [OSTI]

    O'Brien, James F.

    technique that captures the flexibility of sketching and leverages properties of a common everyday plastic of sketching and leverages properties of a common everyday plastic polymer to enable prototyping circuits

  7. Overpulse railgun energy recovery circuit

    DOE Patents [OSTI]

    Honig, E.M.

    1984-09-28

    The invention presented relates to a high-power pulsing circuit and more particularly to a repetitive pulse inductive energy storage and transfer circuit for an electromagnetic launcher. In an electromagnetic launcher such as a railgun for propelling a projectile at high velocity, an overpulse energy recovery circuit is employed to transfer stored inductive energy from a source inductor to the railgun inductance to propel the projectile down the railgun. Switching circuitry and an energy transfer capacitor are used to switch the energy back to the source inductor in readiness for a repetitive projectile propelling cycle.

  8. Counterpulse railgun energy recovery circuit

    DOE Patents [OSTI]

    Honig, E.M.

    1984-09-28

    The invention presented relates to a high-power pulsing circuit and more particularly to a repetitive pulse inductive energy storage and transfer circuit for an electromagnetic launcher. In an electromagnetic launcher such as a railgun for propelling a projectile at high velocity, a counterpulse energy recovery circuit is employed to transfer stored inductive energy from a source inductor to the railgun inductance to propel the projectile down the railgun. Switching circuitry and an energy transfer capacitor are used to switch the energy back to the source inductor in readiness for a repetitive projectile propelling cycle.

  9. Earthquake Nucleation on Geometrically Complex Faults

    E-Print Network [OSTI]

    Fang, Zijun

    2009-01-01

    Preseismic fault slip and earthquake prediction, J. Geophys.Day, The 1999 Izmit, Turkey, earthquake: A 3D dynamic stresstransfer model of intra-earthquake triggering, Bull.

  10. Earthquake Nucleation on Geometrically Complex Faults

    E-Print Network [OSTI]

    Fang, Zijun

    2009-01-01

    fault slip and earthquake prediction, J. Geophys. Res. , [implications for an earthquake prediction field monitoringpredictions of hypocenter location and occurrence time of earthquakes,

  11. Electrolytic Hydrogen Evolution in DMFCs Induced by Oxygen Interruptions and Its Effect on Cell Performance

    E-Print Network [OSTI]

    Zhao, Tianshou

    - tem optimization and reliable operation of the fuel cell. Gas evolu- tion on the anode of a DMFC under flow field of a liquid-feed direct methanol fuel cell DMFC under open-circuit conditions after methanol fuel cells DMFCs are considered as one of the most competitive candidates for the future power

  12. Reverse engineering of integrated circuits

    DOE Patents [OSTI]

    Chisholm, Gregory H. (Shorewood, IL); Eckmann, Steven T. (Colorado Springs, CO); Lain, Christopher M. (Pittsburgh, PA); Veroff, Robert L. (Albuquerque, NM)

    2003-01-01

    Software and a method therein to analyze circuits. The software comprises several tools, each of which perform particular functions in the Reverse Engineering process. The analyst, through a standard interface, directs each tool to the portion of the task to which it is most well suited, rendering previously intractable problems solvable. The tools are generally used iteratively to produce a successively more abstract picture of a circuit, about which incomplete a priori knowledge exists.

  13. NPTEL Syllabus Basic Electrical Circuits -Video course

    E-Print Network [OSTI]

    Krishnapura, Nagendra

    with an introduction to basic linear elements used in electrical circuits. Mesh and node analysis for systematic analysis of large circuits will be studied. Fundamental circuit theorems and their use in analysis steady state analysis for simple analysis of such circuits will be studied. The concepts of power

  14. Tunable circuit for tunable capacitor devices

    DOE Patents [OSTI]

    Rivkina, Tatiana; Ginley, David S.

    2006-09-19

    A tunable circuit (10) for a capacitively tunable capacitor device (12) is provided. The tunable circuit (10) comprises a tunable circuit element (14) and a non-tunable dielectric element (16) coupled to the tunable circuit element (16). A tunable capacitor device (12) and a method for increasing the figure of merit in a tunable capacitor device (12) are also provided.

  15. Shielding circuits with groups Emanuele Viola

    E-Print Network [OSTI]

    Viola, Emanuele

    Shielding circuits with groups Eric Miles Emanuele Viola February 24, 2014 Abstract We show how/output behavior. A general goal in this area is to compile any circuit into a new "shielded" circuit such that any on obfuscation [BGI+ 01] implies that one cannot shield circuits against an attack that obtains just one extra

  16. Earthquake behavior and structure of oceanic transform faults

    E-Print Network [OSTI]

    Roland, Emily Carlson

    2012-01-01

    Oceanic transform faults that accommodate strain at mid-ocean ridge offsets represent a unique environment for studying fault mechanics. Here, I use seismic observations and models to explore how fault structure affects ...

  17. Fault Intersection | Open Energy Information

    Open Energy Info (EERE)

    AFDC Printable Version Share this resource Send a link to EERE: Alternative Fuels Data Center Home Page to someone by E-mail Share EERE: Alternative Fuels Data Center Home Page on Facebook Tweet about EERE: Alternative Fuels Data Center Home Page on Twitter Bookmark EERE: Alternative Fuels Data Center Home Page on Google Bookmark EERE: Alternative Fuels Data Center Home Page on QA:QA J-E-1 SECTIONRobertsdale, AlabamaETEC GmbHFarinello Geothermal Power Station JumpFaroeFaulk County,Fault

  18. Fault Mapping | Open Energy Information

    Open Energy Info (EERE)

    AFDC Printable Version Share this resource Send a link to EERE: Alternative Fuels Data Center Home Page to someone by E-mail Share EERE: Alternative Fuels Data Center Home Page on Facebook Tweet about EERE: Alternative Fuels Data Center Home Page on Twitter Bookmark EERE: Alternative Fuels Data Center Home Page on Google Bookmark EERE: Alternative Fuels Data Center Home Page on QA:QA J-E-1 SECTIONRobertsdale, AlabamaETEC GmbHFarinello Geothermal Power Station JumpFaroeFaulk County,FaultMapping

  19. The ESA/NASA SOHO Mission Interruption: Using the STAMP Accident Analysis Technique for a Software Related `Mishap'

    E-Print Network [OSTI]

    Johnson, Chris

    -1- The ESA/NASA SOHO Mission Interruption: Using the STAMP Accident Analysis Technique, University of Glasgow, Scotland. johnson@dcs.gla.ac.uk (b) NASA Langley Research Center, MS 130 / 100 NASA Road, Hampton, VA 23681-2199, USA c.m.holloway@larc.nasa.gov Abstract: Mishap investigations provide

  20. Complicating Consent: A Study of the Rhetorical Strategies Employed to Interrupt Rape Myths in the Prosecutor v. Kunarac

    E-Print Network [OSTI]

    Shook, Lindsey

    2010-08-31

    The justices in the trial of the Prosecutor v. Kunarac were able to interrupt the rape myths that generally exist in rape trials by complicating the notion of consent. In this paper I argue that the justices de-naturalize common myths about consent...

  1. Investigation of active faulting at the Emigrant Peak fault in Nevada using shallow seismic reflection and ground penetrating radar

    E-Print Network [OSTI]

    Christie, Michael Wayne

    2007-12-18

    The objective of this study was to assess fault displacement, off-fault deformation, and alluvial fan stratigraphy at the Emigrant Peak fault zone (EPFZ) in Fish Lake Valley, Nevada utilizing shallow seismic reflection (SSR) and ground penetrating...

  2. Evaluation of faulting characteristics and ground acceleration associated with recent movement along the Meers Fault, Southwestern Oklahoma 

    E-Print Network [OSTI]

    Burrell, Richard Dennis

    1997-01-01

    being cited as responsible for the Meers Fault scarp. Earthquakes of magnitude 7 to 8 occurring in conjunction with recent reactivation of the fault have been calculated. However, evidence found within the Wichita Mountains just south of the fault...

  3. Improving Distribution System Reliability Through Risk-base Doptimization of Fault Management and Improved Computer-based Fault Location 

    E-Print Network [OSTI]

    Dong, Yimai

    2013-11-07

    regulation on power quality. Optimization in fault management tasks has the potential of improving system reliability by reducing the duration and scale of outages caused by faults through fast fault isolation and service restoration. The research reported...

  4. PERSPECTIVES Deep Earthquakes: A Fault Too Big?

    E-Print Network [OSTI]

    Stein, Seth

    PERSPECTIVES Deep Earthquakes: A Fault Too Big? Seth Stein Because deep Earth processes are inacces. Recent results for the mys- terious deep earthquakes that occur to depths greater than 600 km is that large deep earthquakes (1-3) seem to have occurred on faults larger than ex- pected from the competing

  5. INDUCTION MOTOR FAULT DIAGNOSTIC AND MONITORING METHODS

    E-Print Network [OSTI]

    Povinelli, Richard J.

    INDUCTION MOTOR FAULT DIAGNOSTIC AND MONITORING METHODS by Aderiano M. da Silva, B.S. A Thesis;i Abstract Induction motors are used worldwide as the "workhorse" in industrial applications material. However, induction motor faults can be detected in an initial stage in order to prevent

  6. Sensor Fault Diagnosis Using Principal Component Analysis 

    E-Print Network [OSTI]

    Sharifi, Mahmoudreza

    2010-07-14

    The purpose of this research is to address the problem of fault diagnosis of sensors which measure a set of direct redundant variables. This study proposes: 1. A method for linear senor fault diagnosis 2. An analysis of isolability and detectability...

  7. Physiochemical Evidence of Faulting Processes and Modeling of Fluid in Evolving Fault Systems in Southern California

    SciTech Connect (OSTI)

    Boles, James [Professor

    2013-05-24

    Our study targets recent (Plio-Pleistocene) faults and young (Tertiary) petroleum fields in southern California. Faults include the Refugio Fault in the Transverse Ranges, the Ellwood Fault in the Santa Barbara Channel, and most recently the Newport- Inglewood in the Los Angeles Basin. Subsurface core and tubing scale samples, outcrop samples, well logs, reservoir properties, pore pressures, fluid compositions, and published structural-seismic sections have been used to characterize the tectonic/diagenetic history of the faults. As part of the effort to understand the diagenetic processes within these fault zones, we have studied analogous processes of rapid carbonate precipitation (scaling) in petroleum reservoir tubing and manmade tunnels. From this, we have identified geochemical signatures in carbonate that characterize rapid CO2 degassing. These data provide constraints for finite element models that predict fluid pressures, multiphase flow patterns, rates and patterns of deformation, subsurface temperatures and heat flow, and geochemistry associated with large fault systems.

  8. Self-triggering superconducting fault current limiter

    DOE Patents [OSTI]

    Yuan, Xing (Albany, NY); Tekletsadik, Kasegn (Rexford, NY)

    2008-10-21

    A modular and scaleable Matrix Fault Current Limiter (MFCL) that functions as a "variable impedance" device in an electric power network, using components made of superconducting and non-superconducting electrically conductive materials. The matrix fault current limiter comprises a fault current limiter module that includes a superconductor which is electrically coupled in parallel with a trigger coil, wherein the trigger coil is magnetically coupled to the superconductor. The current surge doing a fault within the electrical power network will cause the superconductor to transition to its resistive state and also generate a uniform magnetic field in the trigger coil and simultaneously limit the voltage developed across the superconductor. This results in fast and uniform quenching of the superconductors, significantly reduces the burnout risk associated with non-uniformity often existing within the volume of superconductor materials. The fault current limiter modules may be electrically coupled together to form various "n" (rows).times."m" (columns) matrix configurations.

  9. Automatic System for the D.C. High Voltage Qualification of the Superconducting Electrical Circuits of the LHC Machine

    E-Print Network [OSTI]

    Bozzini, D; Russenschuck, Stephan; Bednarek, M; Jurkiewicz, P; Kotarba, A; Ludwin, J; Olek, S

    2008-01-01

    A d.c. high voltage test system has been developed to verify automatically the insulation resistance of the powering circuits of the LHC. In the most complex case, up to 72 circuits share the same volume inside cryogenic lines. Each circuit can have an insulation fault versus any other circuit or versus ground. The system is able to connect up to 80 circuits and apply a voltage up to 2 kV D.C. The leakage current flowing through each circuit is measured within a range of 1 nA to 1.6 mA. The matrix of measurements allows characterizing the paths taken by the currents and locating weak points of the insulation between circuits. The system is composed of a D.C. voltage source and a data acquisition card. The card is able to measure with precision currents and voltages and to drive up to 5 high voltage switching modules offering 16 channels each. A LabVIEW application controls the system for an automatic and safe operation. This paper describes the hardware and software design, the testing methodology and the res...

  10. Nuclear sensor signal processing circuit

    DOE Patents [OSTI]

    Kallenbach, Gene A. (Bosque Farms, NM); Noda, Frank T. (Albuquerque, NM); Mitchell, Dean J. (Tijeras, NM); Etzkin, Joshua L. (Albuquerque, NM)

    2007-02-20

    An apparatus and method are disclosed for a compact and temperature-insensitive nuclear sensor that can be calibrated with a non-hazardous radioactive sample. The nuclear sensor includes a gamma ray sensor that generates tail pulses from radioactive samples. An analog conditioning circuit conditions the tail-pulse signals from the gamma ray sensor, and a tail-pulse simulator circuit generates a plurality of simulated tail-pulse signals. A computer system processes the tail pulses from the gamma ray sensor and the simulated tail pulses from the tail-pulse simulator circuit. The nuclear sensor is calibrated under the control of the computer. The offset is adjusted using the simulated tail pulses. Since the offset is set to zero or near zero, the sensor gain can be adjusted with a non-hazardous radioactive source such as, for example, naturally occurring radiation and potassium chloride.

  11. Fermionic Models with Superconducting Circuits

    E-Print Network [OSTI]

    U. Las Heras; L. García-Álvarez; A. Mezzacapo; E. Solano; L. Lamata

    2015-03-31

    We propose a method for the efficient quantum simulation of fermionic systems with superconducting circuits. It consists in the suitable use of Jordan-Wigner mapping, Trotter decomposition, and multiqubit gates, be with the use of a quantum bus or direct capacitive couplings. We apply our method to the paradigmatic cases of 1D and 2D Fermi-Hubbard models, involving couplings with nearest and next-nearest neighbours. Furthermore, we propose an optimal architecture for this model and discuss the benchmarking of the simulations in realistic circuit quantum electrodynamics setups.

  12. Mechanical Models of Fault-Related Folding

    SciTech Connect (OSTI)

    Johnson, A. M.

    2003-01-09

    The subject of the proposed research is fault-related folding and ground deformation. The results are relevant to oil-producing structures throughout the world, to understanding of damage that has been observed along and near earthquake ruptures, and to earthquake-producing structures in California and other tectonically-active areas. The objectives of the proposed research were to provide both a unified, mechanical infrastructure for studies of fault-related foldings and to present the results in computer programs that have graphical users interfaces (GUIs) so that structural geologists and geophysicists can model a wide variety of fault-related folds (FaRFs).

  13. Fault-Tolerant Exact State Transmission

    E-Print Network [OSTI]

    Zhao-Ming Wang; Lian-Ao Wu; Michele Modugno; Wang Yao; Bin Shao

    2012-05-02

    We show that a category of one-dimensional XY-type models may enable high-fidelity quantum state transmissions, regardless of details of coupling configurations. This observation leads to a fault- tolerant design of a state transmission setup. The setup is fault-tolerant, with specified thresholds, against engineering failures of coupling configurations, fabrication imperfections or defects, and even time-dependent noises. We propose the implementation of the fault-tolerant scheme using hard-core bosons in one-dimensional optical lattices.

  14. Cooperative application/OS DRAM fault recovery.

    SciTech Connect (OSTI)

    Ferreira, Kurt Brian; Bridges, Patrick G. (University of New Mexico, Albuquerque, NM); Heroux, Michael Allen; Hoemmen, Mark; Brightwell, Ronald Brian

    2012-05-01

    Exascale systems will present considerable fault-tolerance challenges to applications and system software. These systems are expected to suffer several hard and soft errors per day. Unfortunately, many fault-tolerance methods in use, such as rollback recovery, are unsuitable for many expected errors, for example DRAM failures. As a result, applications will need to address these resilience challenges to more effectively utilize future systems. In this paper, we describe work on a cross-layer application/OS framework to handle uncorrected memory errors. We illustrate the use of this framework through its integration with a new fault-tolerant iterative solver within the Trilinos library, and present initial convergence results.

  15. Fault Detection and Diagnosis in Building HVAC Systems

    E-Print Network [OSTI]

    Najafi, Massieh

    2010-01-01

    of outside air condition, occupant behavior, and buildingair condition and occupant behavior) and fault condition (

  16. Noise analysis for comparator-based circuits

    E-Print Network [OSTI]

    Sepke, Todd

    Noise analysis for comparator-based circuits is presented. The goal is to gain insight into the different sources of noise in these circuits for design purposes. After the general analysis techniques are established, they ...

  17. Circuit breaker monitoring application using wireless communication 

    E-Print Network [OSTI]

    Ved, Nitin

    2007-04-25

    . A low-cost automated circuit breaker monitoring system is developed to monitor circuit breaker control signals. An interface is designed on top of which different local and system-wide applications can be developed which utilize the data recorded...

  18. Conditioning circuit for temperature and strain measurement 

    E-Print Network [OSTI]

    Patel, Aashit Mahendra

    1997-01-01

    conventional techniques. The technique was originally developed at NASA, but has been slightly modified here to obtain the best possible results from the conditioning circuit. The core of the conditioning circuit is formed by a precision switched capacitor...

  19. Post regulation circuit with energy storage

    DOE Patents [OSTI]

    Ball, Don G. (Livermore, CA); Birx, Daniel L. (Oakley, CA); Cook, Edward G. (Livermore, CA)

    1992-01-01

    A charge regulation circuit provides regulation of an unregulated voltage supply and provides energy storage. The charge regulation circuit according to the present invention provides energy storage without unnecessary dissipation of energy through a resistor as in prior art approaches.

  20. Automatic test pattern generation for asynchronous circuits 

    E-Print Network [OSTI]

    Vasudevan, Dilip Prasad

    2012-11-29

    The testability of integrated circuits becomes worse with transistor dimensions reaching nanometer scales. Testing, the process of ensuring that circuits are fabricated without defects, becomes inevitably part of the ...

  1. Charge to the External Review Committee for the NSTX-U Arc Fault During the commissioning of NSTX-U for its first test plasma, an arc took place in its

    E-Print Network [OSTI]

    Princeton Plasma Physics Laboratory

    -U for its first test plasma, an arc took place in its Ohmic heating circuit inflicting significant damageCharge to the External Review Committee for the NSTX-U Arc Fault During the commissioning of NSTX questions below. 1. Technical cause: Are the causes for the arc correctly identified and understood

  2. Initiation of the San Jacinto Fault and its Interaction with the San Andreas Fault: Insights from Geodynamic Modeling

    E-Print Network [OSTI]

    Liu, Mian

    Initiation of the San Jacinto Fault and its Interaction with the San Andreas Fault: Insights from Geodynamic Modeling QINGSONG LI 1,2 and MIAN LIU 1 Abstract--The San Andreas Fault (SAF) is the Pacific is accommodated by the San Jacinto Fault (SJF). Here we investigate the initiation of the SJF and its interaction

  3. The propagation and linkage of normal faults: Insights from the Strathspey-Brent-Statfjord fault array, northern North Sea

    E-Print Network [OSTI]

    McLeod, Aileen E.

    2001-01-01

    Through examination of the scaling relations of faults and the use of seismic stratigraphic techniques,

  4. ECE 2100 Circuit Analysis NAME: ________________________________________________

    E-Print Network [OSTI]

    Miller, Damon A.

    ECE 2100 Circuit Analysis Fall 2011 Exam #1 NAME Schematics drawn using LTspice IV (linear.com). Some problems might be adapted from the course text Schematics drawn using LTspice IV (linear.com). Some problems might be adapted from the course text

  5. PERFORMANCE ENHANCEMENT TECHNIQUES FOR PHASED LOGIC CIRCUITS

    E-Print Network [OSTI]

    Thornton, Mitchell

    , these mechanims have been added to Phased Logic circuits by ad-hoc and manual means that require a designers

  6. Superconducting quantum circuits theory and application

    E-Print Network [OSTI]

    Deng, Xiuhao

    2015-01-01

    viii General theory of Superconducting cavity coupled to2.4 Decoherence in superconductingProposed circuit for superconducting qubits . . . . .

  7. Superconducting quantum circuits theory and application

    E-Print Network [OSTI]

    Deng, Xiuhao

    2015-01-01

    3.10 Energy diagram ofused to bias the system energy. (b) Schematic circuit modelqubit. (c) Charge energy diagram. . . . . . . . . . . . . .

  8. Structure of the eastern Red Rocks and Wind Ridge thrust faults, Wyoming: how a thrust fault gains displacement along strike 

    E-Print Network [OSTI]

    Huntsman, Brent Stanley

    1983-01-01

    OF FIELD MAPPING Methods . Thrust Faults . The Wind Ridge Thrust Fault System The Red Rocks Thrust Fault System CLAY MODEL STUDIES Purpose and Description Model Results DISCUSSION OF RESULTS Kinematics of the Red Rocks Thrust Fault Termination... . Kinematics of the Southern Wind Ridge Thrust Fault . . . A Conceptual Model of the Red Rocks Thrust Fault Termination Implications of the Red Rocks Fault Termination . . . . . . Page V1 V11 1X X1 X11 7 9 17 18 18 21 24 27 35 35 38 49 49...

  9. A connecting network with fault tolerance capabilities

    SciTech Connect (OSTI)

    Ciminiera, L.; Serra, A.

    1986-06-01

    A new multistage interconnection network is presented in this paper. It is able to handle the communications between the connected devices correctly, even in the presence of fault(s) in the network. This goal is achieved by using redundant paths with a fast procedure able to dynamically reroute the message. It is also shown that the rerouting properties are still valid when broadcasting transmission is used.

  10. Wind Power Plant Short Circuit Current Contribution for Different Fault and Wind Turbine Topologies: Preprint

    SciTech Connect (OSTI)

    Gevorgian, V.; Muljadi, E.

    2010-10-01

    This paper presents simulation results for SC current contribution for different types of WTGs obtained through transient and steady-state computer simulation software.

  11. Communication delay analysis of fault-tolerant pipelined circuit switching in torus

    E-Print Network [OSTI]

    Safaei, F.; Khonsari, A.; Ould-Khaoua, M.

    Safaei,F. Khonsari,A. Ould-Khaoua,M. Journal of Computer and System Sciences, to appear, 2008, ISSN: 0022-0000. Elsevier Science

  12. Compact discrete-time chaos generator circuit

    E-Print Network [OSTI]

    Dudek, Piotr

    Compact discrete-time chaos generator circuit P. Dudek and V.D. Juncu A three-transistor CMOS circuit is presented, with adjustable nonlinear characteristics, which can be used as a map that generates discrete-time chaotic signals. A method of constructing a chaos generator using two map circuits is also

  13. Voltage, energy and power in electric circuits

    E-Print Network [OSTI]

    Haase, Markus

    Voltage, energy and power in electric circuits Science teaching unit #12;Disclaimer The Department-2008DVD-EN Voltage, energy and power in electric circuits #12;#12;© Crown copyright 2008 1The National Strategies | Secondary Voltage, energy and power in electric circuits 00094-2008DVD-EN Contents Voltage

  14. Method of determining the open circuit voltage of a battery in a closed circuit

    DOE Patents [OSTI]

    Brown, William E. (Walnut Creek, CA)

    1980-01-01

    The open circuit voltage of a battery which is connected in a closed circuit is determined without breaking the circuit or causing voltage upsets therein. The closed circuit voltage across the battery and the current flowing through it are determined under normal load and then a fractional change is made in the load and the new current and voltage values determined. The open circuit voltage is then calculated, according to known principles, from the two sets of values.

  15. Fault-tolerant Sensor Network based on Fault Evaluation Matrix and Compensation for Intermittent Observation

    E-Print Network [OSTI]

    Fault-tolerant Sensor Network based on Fault Evaluation Matrix and Compensation for Intermittent-tolerant sensor network configuration problem for a target navigation. A sensor network system consists of many sensor nodes and its network connections. Each sensor node can exchange information by wireless

  16. Collateral damage: Evolution with displacement of fracture distribution and secondary fault strands in fault

    E-Print Network [OSTI]

    Savage, Heather M.

    Collateral damage: Evolution with displacement of fracture distribution and secondary fault strands in fault damage zones Heather M. Savage1,2 and Emily E. Brodsky1 Received 22 April 2010; revised 10 of fracture distributions as a function of displacement to determine whether damage around small and large

  17. Measuring and Modeling Fault Density for Plume-Fault Encounter Probability Estimation

    SciTech Connect (OSTI)

    Jordan, P.D.; Oldenburg, C.M.; Nicot, J.-P.

    2011-05-15

    Emission of carbon dioxide from fossil-fueled power generation stations contributes to global climate change. Storage of this carbon dioxide within the pores of geologic strata (geologic carbon storage) is one approach to mitigating the climate change that would otherwise occur. The large storage volume needed for this mitigation requires injection into brine-filled pore space in reservoir strata overlain by cap rocks. One of the main concerns of storage in such rocks is leakage via faults. In the early stages of site selection, site-specific fault coverages are often not available. This necessitates a method for using available fault data to develop an estimate of the likelihood of injected carbon dioxide encountering and migrating up a fault, primarily due to buoyancy. Fault population statistics provide one of the main inputs to calculate the encounter probability. Previous fault population statistics work is shown to be applicable to areal fault density statistics. This result is applied to a case study in the southern portion of the San Joaquin Basin with the result that the probability of a carbon dioxide plume from a previously planned injection had a 3% chance of encountering a fully seal offsetting fault.

  18. Fault Detection and Load Distribution for the Wind Farm Challenge

    SciTech Connect (OSTI)

    Borchehrsen, Anders B.; Larsen, Jesper A.; Stoustrup, Jakob

    2014-08-24

    In this paper a fault detection system and a fault tolerant controller for a wind farm model. The wind farm model used is the one proposed as a public challenge. In the model three types of faults are introduced to a wind farm consisting of nine turbines. A fault detection system designed, by taking advantage of the fact that within a wind farm several wind turbines will be operating under all most identical conditions. The turbines are then grouped, and then turbines within each group are used to generate residuals for turbines in the group. The generated residuals are then evaluated using dynamical cumulative sum. The designed fault detection system is cable of detecting all three fault types occurring in the model. But there is room for improving the fault detection in some areas. To take advantage of the fault detection system a fault tolerant controller for the wind farm has been designed. The fault tolerant controller is a dispatch controller which is estimating the possible power at each individual turbine and then setting the reference accordingly. The fault tolerant controller has been compared to a reference controller. And the comparison shows that the fault tolerant controller performance better in all measures. The fault detection and a fault tolerant controller has been designed, and based on the simulated results the overall performance of the wind farm is improved on all measures. Thereby this is a step towards improving the overall performance of current and future wind farms.

  19. Making Classical Ground State Spin Computing Fault-Tolerant

    E-Print Network [OSTI]

    Elizabeth Crosson; Dave Bacon; Kenneth R. Brown

    2014-11-18

    We examine a model of classical deterministic computing in which the ground state of the classical system is a spatial history of the computation. This model is relevant to quantum dot cellular automata as well as to recent universal adiabatic quantum computing constructions. In its most primitive form, systems constructed in this model cannot compute in an error free manner when working at non-zero temperature. However, by exploiting a mapping between the partition function for this model and probabilistic classical circuits we are able to show that it is possible to make this model effectively error free. We achieve this by using techniques in fault-tolerant classical computing and the result is that the system can compute effectively error free if the temperature is below a critical temperature. We further link this model to computational complexity and show that a certain problem concerning finite temperature classical spin systems is complete for the complexity class Merlin-Arthur. This provides an interesting connection between the physical behavior of certain many-body spin systems and computational complexity.

  20. Cluster-based architecture for fault-tolerant quantum computation

    E-Print Network [OSTI]

    Keisuke Fujii; Katsuji Yamamoto

    2009-12-28

    We present a detailed description of an architecture for fault-tolerant quantum computation, which is based on the cluster model of encoded qubits. In this cluster-based architecture, concatenated computation is implemented in a quite different way from the usual circuit-based architecture where physical gates are recursively replaced by logical gates with error-correction gadgets. Instead, some relevant cluster states, say fundamental clusters, are recursively constructed through verification and postselection in advance for the higher-level one-way computation, which namely provides error-precorrection of gate operations. A suitable code such as the Steane seven-qubit code is adopted for transversal operations. This concatenated construction of verified fundamental clusters has a simple transversal structure of logical errors, and achieves a high noise threshold ~ 3 % for computation by using appropriate verification procedures. Since the postselection is localized within each fundamental cluster with the help of deterministic bare controlled-Z gates without verification, divergence of resources is restrained, which reconciles postselection with scalability.

  1. Ionization tube simmer current circuit

    DOE Patents [OSTI]

    Steinkraus, R.F. Jr.

    1994-12-13

    A highly efficient flash lamp simmer current circuit utilizes a fifty percent duty cycle square wave pulse generator to pass a current over a current limiting inductor to a full wave rectifier. The DC output of the rectifier is then passed over a voltage smoothing capacitor through a reverse current blocking diode to a flash lamp tube to sustain ionization in the tube between discharges via a small simmer current. An alternate embodiment of the circuit combines the pulse generator and inductor in the form of an FET off line square wave generator with an impedance limited step up output transformer which is then applied to the full wave rectifier as before to yield a similar simmer current. 6 figures.

  2. Ionization tube simmer current circuit

    DOE Patents [OSTI]

    Steinkraus, Jr., Robert F. (Livermore, CA)

    1994-01-01

    A highly efficient flash lamp simmer current circuit utilizes a fifty percent duty cycle square wave pulse generator to pass a current over a current limiting inductor to a full wave rectifier. The DC output of the rectifier is then passed over a voltage smoothing capacitor through a reverse current blocking diode to a flash lamp tube to sustain ionization in the tube between discharges via a small simmer current. An alternate embodiment of the circuit combines the pulse generator and inductor in the form of an FET off line square wave generator with an impedance limited step up output transformer which is then applied to the full wave rectifier as before to yield a similar simmer current.

  3. Delta connected resonant snubber circuit

    DOE Patents [OSTI]

    Lai, J.S.; Peng, F.Z.; Young, R.W. Sr.; Ott, G.W. Jr.

    1998-01-20

    A delta connected, resonant snubber-based, soft switching, inverter circuit achieves lossless switching during dc-to-ac power conversion and power conditioning with minimum component count and size. Current is supplied to the resonant snubber branches solely by the dc supply voltage through the main inverter switches and the auxiliary switches. Component count and size are reduced by use of a single semiconductor switch in the resonant snubber branches. Component count is also reduced by maximizing the use of stray capacitances of the main switches as parallel resonant capacitors. Resonance charging and discharging of the parallel capacitances allows lossless, zero voltage switching. In one embodiment, circuit component size and count are minimized while achieving lossless, zero voltage switching within a three-phase inverter. 36 figs.

  4. Delta connected resonant snubber circuit

    DOE Patents [OSTI]

    Lai, Jih-Sheng (Knoxville, TN); Peng, Fang Zheng (Oak Ridge, TN); Young, Sr., Robert W. (Oak Ridge, TN); Ott, Jr., George W. (Knoxville, TN)

    1998-01-01

    A delta connected, resonant snubber-based, soft switching, inverter circuit achieves lossless switching during dc-to-ac power conversion and power conditioning with minimum component count and size. Current is supplied to the resonant snubber branches solely by the dc supply voltage through the main inverter switches and the auxiliary switches. Component count and size are reduced by use of a single semiconductor switch in the resonant snubber branches. Component count is also reduced by maximizing the use of stray capacitances of the main switches as parallel resonant capacitors. Resonance charging and discharging of the parallel capacitances allows lossless, zero voltage switching. In one embodiment, circuit component size and count are minimized while achieving lossless, zero voltage switching within a three-phase inverter.

  5. Circuit analog of quadratic optomechanics

    E-Print Network [OSTI]

    Eun-jong Kim; J. R. Johansson; Franco Nori

    2014-12-22

    We propose a superconducting electrical circuit that simulates a quadratic optomechanical system. A capacitor placed between two transmission-line (TL) resonators acts like a semi-transparent membrane, and a superconducting quantum interference device (SQUID) that terminates a TL resonator behaves like a movable mirror. Combining these circuit elements, it is possible to simulate a quadratic optomechanical coupling whose coupling strength is determined by the coupling capacitance and the tunable bias flux through the SQUIDs. Estimates using realistic parameters suggest that an improvement in the coupling strength could be realized, to five orders of magnitude from what has been observed in membrane-in-the-middle cavity optomechanical systems. This leads to the possibility of achieving the strong-coupling regime of quadratic optomechanics.

  6. 1166 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 5, MAY 2005 Design Analysis and Circuit Enhancements for

    E-Print Network [OSTI]

    Long, Stephen I.

    1166 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 5, MAY 2005 Design Analysis and Circuit from the layout in an analysis, see [6]. A. Open Circuit Time Constants The method of open circuit time finds exactly the value of for a linear circuit (corre- sponding to the dominant pole in the circuit

  7. Photoconductive circuit element pulse generator

    DOE Patents [OSTI]

    Rauscher, Christen (Alexandria, VA)

    1989-01-01

    A pulse generator for characterizing semiconductor devices at millimeter wavelength frequencies where a photoconductive circuit element (PCE) is biased by a direct current voltage source and produces short electrical pulses when excited into conductance by short laser light pulses. The electrical pulses are electronically conditioned to improve the frequency related amplitude characteristics of the pulses which thereafter propagate along a transmission line to a device under test.

  8. Counterpulse railgun energy recovery circuit

    DOE Patents [OSTI]

    Honig, Emanuel M. (Los Alamos, NM)

    1986-01-01

    In an electromagnetic launcher such as a railgun for propelling a projectile at high velocity, a counterpulse energy recovery circuit is employed to transfer stored inductive energy from a source inductor to the railgun inductance to propel the projectile down the railgun. Switching circuitry and an energy transfer capacitor are used to switch the energy back to the source inductor in readiness for a repetitive projectile propelling cycle.

  9. Overpulse railgun energy recovery circuit

    DOE Patents [OSTI]

    Honig, Emanuel M. (Los Alamos, NM)

    1989-01-01

    In an electromagnetic launcher such as a railgun for propelling a projectile at high velocity, an overpulse energy recovery circuit is employed to transfer stored inductive energy from a source inductor to the railgun inductance to propel the projectile down the railgun. Switching circuitry and an energy transfer capacitor are used to switch the energy back to the source inductor in readiness for a repetitive projectile propelling cycle.

  10. Faulted joints: kinematics, displacementlength scaling relations and criteria for their identication

    E-Print Network [OSTI]

    Engelder, Terry

    and kinematics based on two sets of joints, pinnate joints and fault striations, reveal that some mesoscale faults (i.e., faults without linked fault segments) at the mesoscale: ªneoformed faultsº which form

  11. A Hybrid Model Based and Statistical Fault Diagnosis System for Industrial Process 

    E-Print Network [OSTI]

    Lin, Chen-Han

    2014-11-21

    This thesis presents a hybrid model based and statistical fault diagnosis system, which applied on the nonlinear three-tank model. The purpose of fault diagnosis is generating and analyzing the residual to find out the fault occurrence. This fault...

  12. Stuck-at-fault test set compaction 

    E-Print Network [OSTI]

    Vanfickell, Jason Michael

    2013-02-22

    Proper testing of manufactured digital circuits is critical to ensuring the number of defective parts is minimized. Automated test pattern generation tools are created in order to produce test patterns that can be applied with the intention...

  13. VCSEL fault location apparatus and method

    DOE Patents [OSTI]

    Keeler, Gordon A. (Albuquerque, NM); Serkland, Darwin K. (Albuquerque, NM)

    2007-05-15

    An apparatus for locating a fault within an optical fiber is disclosed. The apparatus, which can be formed as a part of a fiber-optic transmitter or as a stand-alone instrument, utilizes a vertical-cavity surface-emitting laser (VCSEL) to generate a test pulse of light which is coupled into an optical fiber under test. The VCSEL is subsequently reconfigured by changing a bias voltage thereto and is used as a resonant-cavity photodetector (RCPD) to detect a portion of the test light pulse which is reflected or scattered from any fault within the optical fiber. A time interval .DELTA.t between an instant in time when the test light pulse is generated and the time the reflected or scattered portion is detected can then be used to determine the location of the fault within the optical fiber.

  14. Fault-tolerant three-level inverter

    DOE Patents [OSTI]

    Edwards, John; Xu, Longya; Bhargava, Brij B.

    2006-12-05

    A method for driving a neutral point clamped three-level inverter is provided. In one exemplary embodiment, DC current is received at a neutral point-clamped three-level inverter. The inverter has a plurality of nodes including first, second and third output nodes. The inverter also has a plurality of switches. Faults are checked for in the inverter and predetermined switches are automatically activated responsive to a detected fault such that three-phase electrical power is provided at the output nodes.

  15. Development of a bridge fault extractor tool 

    E-Print Network [OSTI]

    Bhat, Nandan D.

    2005-02-17

    are tools that analyze chip layouts and produce a realistic list of bridging faults within that chip. FedEx, previously developed at Texas A&M University, extracts all two-node intralayer bridges of any given chip layout and optionally extracts all two...) for this tool which aids in more effectively visualizing the bridge faults across the chip. The final aim of this thesis was to perform FedEx output analysis to understand the nature of the defects, such as variation of critical area (the area where...

  16. Motivation Methodology Conclusions A Fault Tolerance Bisimulation Proof for

    E-Print Network [OSTI]

    Francalanza, Adrian

    Motivation Methodology Conclusions A Fault Tolerance Bisimulation Proof for Consensus Adrian of Somewhere and Elsewhere A Fault Tolerance Bisimulation Proof for Consensus #12;Motivation Methodology Conclusions Outline 1 Motivation 2 Methodology 3 Conclusions Adrian Francalanza, Matthew Hennessy Universities

  17. Upper crustal faulting in an obliquely extending orogen, structural...

    Open Energy Info (EERE)

    field in the central Coso Range, eastern California, image brittle faults and other structures in a zone of localized crustal extension between two major strike-slip faults. The...

  18. Occupancy Based Fault Detection on Building Level - a Feasibility Study 

    E-Print Network [OSTI]

    Tuip, B.; Houten, M.; Trcka, M.; Hensen, M.

    2010-01-01

    -line, self learning fault detection tool on building level. Taking passive user behavior into account, the tool aims to distinguish real faults from unexpected user behavior. An artificial neural network model is used to predict building energy consumption...

  19. Two Similarity Measure Approaches to Whole Building Fault Diagnosis 

    E-Print Network [OSTI]

    Lin, G.; Claridge, D.

    2012-01-01

    similarity are defined and the methodology for implementing the proposed whole building fault diagnosis approaches is presented. Cosine similarity and Euclidean distance similarity are applied to two field observed fault test cases, and both the cosine...

  20. Dining philosophers with masking tolerance to crash faults 

    E-Print Network [OSTI]

    Idimadakala, Vijaya K.

    2009-05-15

    We examine the tolerance of dining philosopher algorithms subject to process crash faults in arbitrary conflict graphs. This classic problem is unsolvable in asynchronous message-passing systems subject to even a single crash fault. By contrast...

  1. Synthesis and evaluation of fault-tolerant quantum computer architectures

    E-Print Network [OSTI]

    Cross, Andrew W. (Andrew William), 1979-

    2005-01-01

    Fault-tolerance is the cornerstone of practical, large-scale quantum computing, pushed into its prominent position with heroic theoretical efforts. The fault-tolerance threshold, which is the component failure probability ...

  2. Realizing a supercapacitor in an electrical circuit

    SciTech Connect (OSTI)

    Fukuhara, Mikio Kuroda, Tomoyuki; Hasegawa, Fumihiko

    2014-11-17

    Capacitors are commonly used in electronic resonance circuits; however, capacitors have not been used for storing large amounts of electrical energy in electrical circuits. Here, we report a superior RC circuit which serves as an electrical storage system characterized by quick charging and long-term discharging of electricity. The improved energy storage characteristics in this mixed electric circuit (R{sub 1}?+?R{sub 2}C{sub 1}) with small resistor R{sub 1}, large resistor R{sub 2}, and large capacitor C{sub 1} are derived from the damming effect by large R{sub 2} in simple parallel R{sub 2}C{sub 1} circuit. However, no research work has been carried out previously on the use of capacitors as electrical energy storage devices in circuits. Combined with nanotechnology, we hope that our finding will play a remarkable role in a variety of applications such as hybrid electric vehicles and backup power supplies.

  3. Different Factors Affecting Short Circuit Behavior of a Wind Power Plant

    SciTech Connect (OSTI)

    Muljadi, E.; Samaan, Nader A.; Gevorgian, Vahan; Li, Jun; Pasupulati, Subbaiah

    2013-01-31

    A wind power plant consists of a large number of turbines interconnected by underground cable. A pad-mount transformer at each turbine steps up the voltage from generating voltage (690 V) to a medium voltage (34.5 kV). All turbines in the plant are connected to the substation transformer where the voltage is stepped up to the transmission level. An important aspect of wind power plant (WPP) impact studies is to evaluate the short-circuit (SC) current contribution of the plant into the transmission network under different fault conditions. This task can be challenging to protection engineers due to the topology differences between different types of wind turbine generators (WTGs) and the conventional generating units. This paper investigates the short circuit behavior of a wind power plant for different types of faults. The impact of wind turbine types, the transformer configuration, and the reactive compensation capacitor will be investigated. The voltage response at different buses will be observed. Finally, the SC line currents will be presented along with its symmetrical components.

  4. Different Factors Affecting Short Circuit Behavior of a Wind Power Plant

    SciTech Connect (OSTI)

    Muljadi, E.; Samaan, Nader A.; Gevorgian, Vahan; Li, Jun; Pasupulati, Subbaiah

    2010-12-21

    A wind power plant consists of a large number of turbines interconnected by underground cable. A pad-mount transformer at each turbine steps up the voltage from generating voltage (690 V) to a medium voltage (34.5 kV). All turbines in the plant are connected to the substation transformer where the voltage is stepped up to the transmission level. An important aspect of wind power plant (WPP) impact studies is to evaluate the short-circuit (SC) current contribution of the plant into the transmission network under different fault conditions. This task can be challenging to protection engineers due to the topology differences between different types of wind turbine generators (WTGs) and the conventional generating units. This paper investigates the short circuit behavior of a wind power plant for different types of faults. The impact of wind turbine types, the transformer configuration, and the reactive compensation capacitor will be investigated. The voltage response at different buses will be observed. Finally, the SC line currents will be presented along with its symmetrical components.

  5. Fault-Tolerant Non-interference Extended Version

    E-Print Network [OSTI]

    Russo, Alejandro

    a fault (induced by holding a light-bulb near the processor!) triggers a single bit flip in a malicious

  6. Deep drilling phase of the Pen Brand Fault Program

    SciTech Connect (OSTI)

    Stieve, A.

    1991-05-15

    This deep drilling activity is one element of the Pen Branch Fault Program at Savannah River Site (SRS). The effort will consist of three tasks: the extension of wells PBF-7 and PBF-8 into crystalline basement, geologic and drilling oversight during drilling operations, and the lithologic description and analysis of the recovered core. The drilling program addresses the association of the Pen Branch fault with order fault systems such as the fault that formed the Bunbarton basin in the Triassic.

  7. Detachment Faulting & Geothermal Resources- Pearl Hot Spring, NV

    Broader source: Energy.gov [DOE]

    Detachment Faulting & Geothermal Resources - Pearl Hot Spring, NV presentation at the April 2013 peer review meeting held in Denver, Colorado.

  8. Printed circuit dispersive transmission line

    DOE Patents [OSTI]

    Ikezi, H.; Lin-Liu, Y.R.; DeGrassie, J.S.

    1991-08-27

    A printed circuit dispersive transmission line structure is disclosed comprising an insulator, a ground plane formed on one surface of the insulator, a first transmission line formed on a second surface of the insulator, and a second transmission line also formed on the second surface of the insulator and of longer length than the first transmission line and periodically intersecting the first transmission line. In a preferred embodiment, the transmission line structure exhibits highly dispersive characteristics by designing the length of one of the transmission line between two adjacent periodic intersections to be longer than the other. 5 figures.

  9. Printed circuit dispersive transmission line

    DOE Patents [OSTI]

    Ikezi, Hiroyuki (Rancho Santa Fe, CA); Lin-Liu, Yuh-Ren (San Diego, CA); DeGrassie, John S. (Encinitas, CA)

    1991-01-01

    A printed circuit dispersive transmission line structure is disclosed comprising an insulator, a ground plane formed on one surface of the insulator, a first transmission line formed on a second surface of the insulator, and a second transmission line also formed on the second surface of the insulator and of longer length than the first transmission line and periodically intersecting the first transmission line. In a preferred embodiment, the transmission line structure exhibits highly dispersive characteristics by designing the length of one of the transmission line between two adjacent periodic intersections to be longer than the other.

  10. Polysilicon photoconductor for integrated circuits

    DOE Patents [OSTI]

    Hammond, R.B.; Bowman, D.R.

    1989-04-11

    A photoconductive element of polycrystalline silicon is provided with intrinsic response time which does not limit overall circuit response. An undoped polycrystalline silicon layer is deposited by LPCVD to a selected thickness on silicon dioxide. The deposited polycrystalline silicon is then annealed at a selected temperature and for a time effective to obtain crystal sizes effective to produce an enhanced current output. The annealed polycrystalline layer is subsequently exposed and damaged by ion implantation to a damage factor effective to obtain a fast photoconductive response. 6 figs.

  11. Modeling of transformers using circuit simulators

    SciTech Connect (OSTI)

    Archer, W.E.; Deveney, M.F.; Nagel, R.L.

    1994-07-01

    Transformers of two different designs; and unencapsulated pot core and an encapsulated toroidal core have been modeled for circuit analysis with circuit simulation tools. We selected MicroSim`s PSPICE and Anology`s SABER as the simulation tools and used experimental BH Loop and network analyzer measurements to generate the needed input data. The models are compared for accuracy and convergence using the circuit simulators. Results are presented which demonstrate the effects on circuit performance from magnetic core losses, eddy currents, and mechanical stress on the magnetic cores.

  12. Hybrid stretchable circuits on silicone substrate

    SciTech Connect (OSTI)

    Robinson, A., E-mail: adam.1.robinson@nokia.com; Aziz, A., E-mail: a.aziz1@lancaster.ac.uk [Nanoscience Centre, University of Cambridge, Cambridge CB01FF (United Kingdom); Liu, Q.; Suo, Z. [School of Engineering and Applied Sciences and Kavli Institute for Bionano Science and Technology, Harvard University, Cambridge, Massachusetts 02138 (United States); Lacour, S. P., E-mail: stephanie.lacour@epfl.ch [Centre for Neuroprosthetics and Laboratory for Soft Bioelectronics Interfaces, School of Engineering, Ecole Polytechnique Fédérale de Lausanne, Lausanne 1015 (Switzerland)

    2014-04-14

    When rigid and stretchable components are integrated onto a single elastic carrier substrate, large strain heterogeneities appear in the vicinity of the deformable-non-deformable interfaces. In this paper, we report on a generic approach to manufacture hybrid stretchable circuits where commercial electronic components can be mounted on a stretchable circuit board. Similar to printed circuit board development, the components are electrically bonded on the elastic substrate and interconnected with stretchable electrical traces. The substrate—a silicone matrix carrying concentric rigid disks—ensures both the circuit elasticity and the mechanical integrity of the most fragile materials.

  13. Fault-tolerant Architectures for Nanoelectronic and Quantum Devices

    E-Print Network [OSTI]

    van Vliet, Lucas J.

    ) . . . . . . . . . . . . . . . . . . . 6 2.1.4 Rapid single flux quantum (RSFQ) and superconducting circuits of Josephson junctions

  14. ELECTROMAGNETIC IMAGES OF THE TINTINA FAULT (NORTHERN CANADIAN CORDILLERA)

    E-Print Network [OSTI]

    Jones, Alan G.

    ELECTROMAGNETIC IMAGES OF THE TINTINA FAULT (NORTHERN CANADIAN CORDILLERA) Juanjo Ledo1 , Alan G to obtain a crustal scale electromagnetic image of the fault. A short, higher station density profile-dimensional (2- D) electromagnetic behavior of the fault. Distortion decomposition of the responses corroborated

  15. NASA Technical Memorandum 89098 The Fault-Tree Compiler

    E-Print Network [OSTI]

    Butler, Ricky W.

    L - NASA Technical Memorandum 89098 The Fault-Tree Compiler Anna L. Martensen Ricky W. Butler in preliminary design analysis. The goal of the Fault Tree Compiler (m)program is to provide the user with a tool also be performed, providing the user The motivation for the development of the Fault Tree Compiler

  16. Development of the Global Earthquake Model's neotectonic fault database

    E-Print Network [OSTI]

    New Hampshire, University of

    Development of the Global Earthquake Model's neotectonic fault database Annemarie Christophersen1 database and a unique graphical interface for the compilation of new fault data. A key design principle is that of an electronic field notebook for capturing observations a geologist would make about a fault. The database

  17. Synthesizing Round Based FaultTolerant Programs using Genetic Programming

    E-Print Network [OSTI]

    Fernandez, Thomas

    Synthesizing Round Based Fault­Tolerant Programs using Genetic Programming Ling Zhu and Sandeep based distributed fault­tolerant programs using stack based genetic pro­ gramming. Our approach evolves a fault­tolerant program based on a round based structure and the program specification. To permit

  18. Statistical estimation of multiple faults in aircraft gas turbine engines

    E-Print Network [OSTI]

    Ray, Asok

    415 Statistical estimation of multiple faults in aircraft gas turbine engines S Sarkar, C Rao of multiple faults in aircraft gas-turbine engines, based on a statistical pattern recognition tool called commercial aircraft engine. Keywords: aircraft propulsion, gas turbine engines, multiple fault estimation

  19. Online Fault Detection and Tolerance for Photovoltaic Energy Harvesting Systems

    E-Print Network [OSTI]

    Pedram, Massoud

    Online Fault Detection and Tolerance for Photovoltaic Energy Harvesting Systems Xue Lin 1 , Yanzhi, yanzhiwa, dizhu, pedram}@usc.edu, 2 naehyuck@elpl.snu.ac.kr ABSTRACT Photovoltaic energy harvesting systems, Performance, Reliability. Keywords Photovoltaic System, Fault Detection, Fault Tolerance, Photovoltaic Panel

  20. Symbolic Dynamic Analysis of Transient Time Series for Fault

    E-Print Network [OSTI]

    Ray, Asok

    Symbolic Dynamic Analysis of Transient Time Series for Fault Detection in Gas Turbine Engines paper presents a symbolic dynamics-based method for detection of incipient faults in gas turbine engines dynamics, fault detection, aircraft gas turbine engines 1 Introduction Performance monitoring of aircraft

  1. Protection from ground faults in the stator winding of generators at power plants in the Siberian networks

    SciTech Connect (OSTI)

    Vainshtein, R. A.; Lapin, V. I.; Naumov, A. M.; Doronin, A. V.; Yudin, S. M.

    2010-05-15

    The experience of many years of experience in developing and utilization of ground fault protection in the stator winding of generators in the Siberian networks is generalized. The main method of protection is to apply a direct current or an alternating current with a frequency of 25 Hz to the primary circuits of the stator. A direct current is applied to turbo generators operating in a unit with a transformer without a resistive coupling to the external grid or to other generators. Applying a 25 Hz control current is appropriate for power generation systems with compensation of a capacitive short circuit current to ground. This method forms the basis for protection of generators operating on busbars, hydroelectric generators with a neutral grounded through an arc-suppression reactor, including in consolidated units with generators operating in parallel on a single low-voltage transformer winding.

  2. The effects of lithology and initial fault angle in physical models of fault-propagation folds 

    E-Print Network [OSTI]

    McLain, Christopher Thomas

    2001-01-01

    with a weak brittle layer that deforms by faulting and fracturing (dried pottery clay simulates an interbedded siliciclastic unit). The models were deformed in a triaxial deformation rig at confining pressure of 50 Mpa at room temperature. Each model...

  3. An algorithm for faulted phase and feeder selection under high impedance fault conditions 

    E-Print Network [OSTI]

    Benner, Carl Lee

    1988-01-01

    . One method based on increases in third and fifth harmonic symmetrical current components under high impedance fault conditions has been proposed by Balser et. Journal model is IEEE Transactions on Power Delivery. al, of Power Technologies Inc [1...

  4. RC Circuits In this presentation, circuits with multiple batteries, resistors and

    E-Print Network [OSTI]

    Heller, Barbara

    RC Circuits ·In this presentation, circuits with multiple batteries, resistors and capacitors will be reduced to an equivalent system with a single battery, a single resistor, and a single capacitor. Kirchoff-constant of an RC circuit will be derived. #12;Ohm's Law When a battery is connected to a resistor, the battery

  5. Unifying sensor fault detection with energy conservation

    E-Print Network [OSTI]

    Dobson, Simon

    Unifying sensor fault detection with energy conservation Lei Fang and Simon Dobson School energy usage. Section 2 presents our framework, which is evaluated in section 3 by means of some reliability. Sensors are often energy-hungry and cannot operate over the long term, and the data they gather

  6. Symmetrical Fault Analysis 1.0 Definition

    E-Print Network [OSTI]

    McCalley, James D.

    , shunt admittances, and -Y phase shifts are neglected. Synchronous machines (generators and motors-286]. We begin with the simplest of examples. 3.0 Example Consider a single generator supplying an R that will be faulted). Eg: steady-state internal gen voltage Xd: synchronous (steady-state) reactance IL: load

  7. All row, planar fault detection system

    DOE Patents [OSTI]

    Archer, Charles Jens; Pinnow, Kurt Walter; Ratterman, Joseph D; Smith, Brian Edward

    2013-07-23

    An apparatus, program product and method for detecting nodal faults may simultaneously cause designated nodes of a cell to communicate with all nodes adjacent to each of the designated nodes. Furthermore, all nodes along the axes of the designated nodes are made to communicate with their adjacent nodes, and the communications are analyzed to determine if a node or connection is faulty.

  8. Safety Requirements and Fault Trees using Retrenchment

    E-Print Network [OSTI]

    Banach, Richard

    this initial model has been created, the elicitation of safety requirements yields a fresh set of criteria are applied, the information linking the design and the safety assessment phases is often carried outSafety Requirements and Fault Trees using Retrenchment R. Banach and R. Cross Computer Science

  9. ENGR 201 Electrical Fundamentals I Catalog Description: Analysis of linear circuits. Circuit laws and theorems. DC response of

    E-Print Network [OSTI]

    ENGR 201 ­ Electrical Fundamentals I Catalog Description: Analysis of linear circuits. Circuit laws and laws · Methods of analysis (e.g., nodal, mesh) · Circuit theorems · Operational amplifiers · Capacitors, and apply these for the analysis of dc circuits (ABET outcomes: A, e, m) 4. Analyze circuits made up

  10. Coordinated Fault Tolerance for High-Performance Computing

    SciTech Connect (OSTI)

    Dongarra, Jack; Bosilca, George; et al.

    2013-04-08

    Our work to meet our goal of end-to-end fault tolerance has focused on two areas: (1) improving fault tolerance in various software currently available and widely used throughout the HEC domain and (2) using fault information exchange and coordination to achieve holistic, systemwide fault tolerance and understanding how to design and implement interfaces for integrating fault tolerance features for multiple layers of the software stack—from the application, math libraries, and programming language runtime to other common system software such as jobs schedulers, resource managers, and monitoring tools.

  11. Timing Verification of Adaptive Integrated Circuits 

    E-Print Network [OSTI]

    Kumar, Rohit

    2014-08-01

    timing analysis (SSTA). The proposed method is validated on benchmark circuits including the recent ISPD'13 suite, which has circuit as large as 150K gates. The results show that our method can achieve orders of magnitude speed-up over Monte Carlo...

  12. Pipelined Asynchronous Circuits Andrew Matthew Lines

    E-Print Network [OSTI]

    Pipelined Asynchronous Circuits Andrew Matthew Lines June 1995, revised June 1998 This thesis building blocks for highly pipelined designs. The first chapter presents the implementation approach for individual cells. The second chapter in­ vestigates the time behavior of complex pipelined circuits

  13. Circuits in Power Electronics J. Waldvogel

    E-Print Network [OSTI]

    Grohs, Philipp

    control of locomotives and electric cars, control of power stations and power networks, etc. For everyCircuits in Power Electronics J. Waldvogel Research Report No. 94-13 October 1994 Seminar f¨ur Angewandte Mathematik Eidgen¨ossische Technische Hochschule CH-8092 Z¨urich Switzerland #12;Circuits in Power

  14. Entropy production by simple electrical circuits

    E-Print Network [OSTI]

    E. N. Miranda; S. Nikolskaia

    2012-08-13

    The entropy production by simple electrical circuits (R, RC, RL) is analyzed. It comes out that the entropy production is minimal, in agreement with a well known theorem due to Prigogine. In this way, it is wrong a recent result by Zupanovic, Juretic and Botric (Physica Review E 70, 056198) who claimed that the entropy production in simple electrical circuits is a maximum

  15. LABORATORY II ENERGY AND ELECTRIC CIRCUITS

    E-Print Network [OSTI]

    Minnesota, University of

    LABORATORY II ENERGY AND ELECTRIC CIRCUITS Lab II - 1 It is often useful to study physical. An electric circuit illustrates how energy can be transformed within a system, transferred to different parts it is the electric charge that transports the energy from one place in the system to another

  16. Low voltage amplifier architecture for high speed switched capacitor circuits 

    E-Print Network [OSTI]

    Shankar, Asit

    2001-01-01

    This work concentrates on circuit realization of high speed and low voltage switched capacitor circuits, with emphasis on the operational transconductance amplifier (OTA). An overview of switched capacitor circuits is given. Speed and voltage...

  17. Reusable vibration resistant integrated circuit mounting socket

    DOE Patents [OSTI]

    Evans, Craig N. (Irwin, PA)

    1995-01-01

    This invention discloses a novel form of socket for integrated circuits to be mounted on printed circuit boards. The socket uses a novel contact which is fabricated out of a bimetallic strip with a shape which makes the end of the strip move laterally as temperature changes. The end of the strip forms a barb which digs into an integrated circuit lead at normal temperatures and holds it firmly in the contact, preventing loosening and open circuits from vibration. By cooling the contact containing the bimetallic strip the barb end can be made to release so that the integrated circuit lead can be removed from the socket without damage either to the lead or to the socket components.

  18. Quantized hysteresis in a superfluid atomtronic circuit

    E-Print Network [OSTI]

    Eckel, Stephen; Jendrzejewski, Fred; Murray, Noel; Clark, Charles W; Lobb, Christopher J; Phillips, William D; Edwards, Mark; Campbell, Gretchen K

    2014-01-01

    Atomtronics is an emerging interdisciplinary field that seeks new functionality by creating devices and circuits where ultra-cold atoms play a role analogous to the electrons in electronics. Hysteresis in atomtronic circuits may prove to be a crucial feature for the development of practical devices, just as it has in electronic circuits like memory, digital noise filters (e.g., Schmitt triggers), and magnetometers (e.g., superconducting quantum interference devices [SQUIDs]). Here we demonstrate quantized hysteresis in an atomtronic circuit: a ring of superfluid, dilute-gas, Bose-Einstein condenstate (BEC) obstructed by a rotating weak link. Hysteresis is as fundamental to superfluidity (and superconductivity) as quantized persistent currents, critical velocity, and Josephson effects, but has not been previously observed in any atomic-gas, superfluid BEC despite multiple theoretical predictions. By contrast, hysteresis is routinely observed in superconducting circuits, and it is essential in rf-SQUIDs. Superf...

  19. Beta-gamma discriminator circuit

    SciTech Connect (OSTI)

    Erkkila, B.H.; Wolf, M.A.; Eisen, Y.; Unruh, W.P.; Brake, R.J.

    1984-01-01

    The major difficulty encountered in the determination of beta-ray dose in field conditions is generally the presence of a relatively high gamma-ray component. Conventional dosimetry instruments use a shield on the detector to estimate the gamma-ray component in comparison with the beta-ray component. More accurate dosimetry information can be obtained from the measured beta spectrum itself. At Los Alamos, a detector and discriminator circuit suitable for use in a portable spectrometer have been developed. This instrument will discriminate between gammas and betas in a mixed field. The portable package includes a 256-channel MCA which can be programmed to give a variety of outputs, including a spectral display, and may be programmed to read dose directly.

  20. Sequential power-up circuit

    DOE Patents [OSTI]

    Kronberg, J.W.

    1992-06-02

    A sequential power-up circuit for starting several electrical load elements in series to avoid excessive current surge, comprising a voltage ramp generator and a set of voltage comparators, each comparator having a different reference voltage and interfacing with a switch that is capable of turning on one of the load elements. As the voltage rises, it passes the reference voltages one at a time and causes the switch corresponding to that voltage to turn on its load element. The ramp is turned on and off by a single switch or by a logic-level electrical signal. The ramp rate for turning on the load element is relatively slow and the rate for turning the elements off is relatively fast. Optionally, the duration of each interval of time between the turning on of the load elements is programmable. 2 figs.

  1. Buford Major Rehabilitation Study (1996) and 11th Circuit Hydropower...

    Broader source: Energy.gov (indexed) [DOE]

    Buford Major Rehabilitation Study (1996) and 11th Circuit Hydropower Report (June 2012) Comparison The rehab study is compared to the 11th Circuit Hydropower Report for capacity...

  2. Simulating Quantum Circuits with Sparse Output Distributions

    E-Print Network [OSTI]

    Martin Schwarz; Maarten Van den Nest

    2013-10-24

    We show that several quantum circuit families can be simulated efficiently classically if it is promised that their output distribution is approximately sparse i.e. the distribution is close to one where only a polynomially small, a priori unknown subset of the measurement probabilities are nonzero. Classical simulations are thereby obtained for quantum circuits which---without the additional sparsity promise---are considered hard to simulate. Our results apply in particular to a family of Fourier sampling circuits (which have structural similarities to Shor's factoring algorithm) but also to several other circuit families, such as IQP circuits. Our results provide examples of quantum circuits that cannot achieve exponential speed-ups due to the presence of too much destructive interference i.e. too many cancelations of amplitudes. The crux of our classical simulation is an efficient algorithm for approximating the significant Fourier coefficients of a class of states called computationally tractable states. The latter result may have applications beyond the scope of this work. In the proof we employ and extend sparse approximation techniques, in particular the Kushilevitz-Mansour algorithm, in combination with probabilistic simulation methods for quantum circuits.

  3. Undulator Hall Air Temperature Fault Scenarios

    SciTech Connect (OSTI)

    Sevilla, J.; Welch, J.; ,

    2010-11-17

    Recent experience indicates that the LCLS undulator segments must not, at any time following tuning, be allowed to change temperature by more than about {+-}2.5 C or the magnetic center will irreversibly shift outside of acceptable tolerances. This vulnerability raises a concern that under fault conditions the ambient temperature in the Undulator Hall might go outside of the safe range and potentially could require removal and retuning of all the segments. In this note we estimate changes that can be expected in the Undulator Hall air temperature for three fault scenarios: (1) System-wide power failure; (2) Heating Ventilation and Air Conditioning (HVAC) system shutdown; and (3) HVAC system temperature regulation fault. We find that for either a system-wide power failure or an HVAC system shutdown (with the technical equipment left on), the short-term temperature changes of the air would be modest due to the ability of the walls and floor to act as a heat ballast. No action would be needed to protect the undulator system in the event of a system-wide power failure. Some action to adjust the heat balance, in the case of the HVAC power failure with the equipment left on, might be desirable but is not required. On the other hand, a temperature regulation failure of the HVAC system can quickly cause large excursions in air temperature and prompt action would be required to avoid damage to the undulator system.

  4. Development of Integrated Meso/Microscale Traffic Simulation Software for Testing Fault Detection and Handling in AHS

    E-Print Network [OSTI]

    Horowitz, Roberto

    2004-01-01

    Traffic Simulation Software for Testing Fault Detection andTraf?c Simulation Software for Testing Fault Detection andTraf?c Simulation Software for Testing Fault Detection and

  5. Features and Dimensions of the Hayward fault zone in the Strawberry and Blackberry Creek Area Berkeley, California

    E-Print Network [OSTI]

    Williams, P.L.

    2011-01-01

    Hayward Fault Zone in the Strawberry and Blackberry Creekward Fault Zone in the Strawberry and Blackberry Creek Area,Hayward fault zone in the Strawberry and Blackberry Creek

  6. Similarity Matching Techniques for Fault Diagnosis in Automotive Infotainment Electronics

    E-Print Network [OSTI]

    Kabir, Mashud

    2009-01-01

    Fault diagnosis has become a very important area of research during the last decade due to the advancement of mechanical and electrical systems in industries. The automobile is a crucial field where fault diagnosis is given a special attention. Due to the increasing complexity and newly added features in vehicles, a comprehensive study has to be performed in order to achieve an appropriate diagnosis model. A diagnosis system is capable of identifying the faults of a system by investigating the observable effects (or symptoms). The system categorizes the fault into a diagnosis class and identifies a probable cause based on the supplied fault symptoms. Fault categorization and identification are done using similarity matching techniques. The development of diagnosis classes is done by making use of previous experience, knowledge or information within an application area. The necessary information used may come from several sources of knowledge, such as from system analysis. In this paper similarity matching tec...

  7. On equivalent resistance of electrical circuits

    E-Print Network [OSTI]

    Kagan, Mikhail

    2015-01-01

    While the standard (introductory physics) way of computing the equvalent resistance of non-trivial electrical ciruits is based on Kirchhoff's rules, there is a mathematically and conceptually simpler approach, called the method of nodal potentials, whose basic variables are the values of electric potential at the circuit's nodes. In this paper, we review the method of nodal potentials and illustrate it using the Wheatstone bridge as an example. At the end, we derive - in a closed form - the equivalent resistance of a generic circuit, which we apply to a few sample circuits. The final result unveils a curious interplay between electrical circuits, matrix algebra, and graph theory and its applications to computer science. The paper is written at a level accessible by undergraduate students who are familiar with matrix arithmetic. For the more inquisitive reader, additional proofs and technical details are provided in the appendix.

  8. Design Robustness Analysis of Neuromorphic Circuits 

    E-Print Network [OSTI]

    Bashaireh, Ahmad

    2014-04-23

    of variability on the performance of the system. Monte Carlo analysis of a brain-inspired digital neuromorphic circuit in the presence of voltage, and temperature (PVT) variations is performed. A commercial 90nm technology process is utilized to synthesize...

  9. Analysis of S-Circuit Uncertainty 

    E-Print Network [OSTI]

    Ahmed, Taahir

    2011-08-08

    The theory of sensori-computational circuits provides a capable framework for the description and optimization of robotic systems, including on-line optimizations. This theory, however, is inadequate in that it does not account for uncertainty in a...

  10. Proof Nets and Boolean Circuits Kazushige Terui

    E-Print Network [OSTI]

    Terui, Kazushige

    -depth family of proof nets. We then have APNi = ACi(stCONN2). 1. Introduction Proof nets [4, 2, 6 [5, 7, 11]. Boolean circuits (see [17, 1, 16] for instance) are one of the standard models

  11. Carbon nanotube synthesis for integrated circuit interconnects

    E-Print Network [OSTI]

    Nessim, Gilbert Daniel

    2009-01-01

    Based on their properties, carbon nanotubes (CNTs) have been identified as ideal replacements for copper interconnects in integrated circuits given their higher current density, inertness, and higher resistance to ...

  12. Analog circuit for controlling acoustic transducer arrays

    DOE Patents [OSTI]

    Drumheller, Douglas S. (Cedar Crest, NM)

    1991-01-01

    A simplified ananlog circuit is presented for controlling electromechanical transducer pairs in an acoustic telemetry system. The analog circuit of this invention comprises a single electrical resistor which replaces all of the digital components in a known digital circuit. In accordance with this invention, a first transducer in a transducer pair of array is driven in series with the resistor. The voltage drop across this resistor is then amplified and used to drive the second transducer. The voltage drop across the resistor is proportional and in phase with the current to the transducer. This current is approximately 90 degrees out of phase with the driving voltage to the transducer. This phase shift replaces the digital delay required by the digital control circuit of the prior art.

  13. Parallel VLSI Circuit Analysis and Optimization 

    E-Print Network [OSTI]

    Ye, Xiaoji

    2012-02-14

    The prevalence of multi-core processors in recent years has introduced new opportunities and challenges to Electronic Design Automation (EDA) research and development. In this dissertation, a few parallel Very Large Scale Integration (VLSI) circuit...

  14. Analysis and Design of Resilient VLSI Circuits 

    E-Print Network [OSTI]

    Garg, Rajesh

    2010-07-14

    The reliable operation of Integrated Circuits (ICs) has become increasingly difficult to achieve in the deep sub-micron (DSM) era. With continuously decreasing device feature sizes, combined with lower supply voltages and higher operating...

  15. Microelectronic Devices and Circuits - 2006 Electronic Edition

    E-Print Network [OSTI]

    Fonstad, Clifton

    2006-10-01

    Combining semiconductor device physics and modeling with electronic circuit analysis and practice in a single sophomore/junior level microelectronics course, this textbook offers an integrated approach so students can truly ...

  16. Switch level optimization for CMOS circuits 

    E-Print Network [OSTI]

    Chugh, Pankaj Pravinkumar

    1997-01-01

    ' at nodes 1 and 4 in paths 1 and 3 respectively. Also, we can see that transistor with input 'e' is connected to transistor with input 'c' Pall-ap - Nerrrark Output Park I Palh 4 o o ge Fig. l. IJnoptimized example circuit. at nodes 3 and 2 in paths 2... for circuit one. Pulpup - network Output i C Fig. 4. Optimized circuit I Pull-up - Network Output 0 Fig. 5. Most optimized circuit 1 next/ adjacent to each other. We can group X(a, 1) ? X(a, 2), X(b, 3) ? X(b, 4), X(e, 2) ? X(e, 3), and X(d, 1) ? X...

  17. Quantum computation beyond the circuit model

    E-Print Network [OSTI]

    Jordan, Stephen Paul

    2008-01-01

    The quantum circuit model is the most widely used model of quantum computation. It provides both a framework for formulating quantum algorithms and an architecture for the physical construction of quantum computers. However, ...

  18. Dynamical Systems in Circuit Designer's Eyes

    SciTech Connect (OSTI)

    Odyniec, M.

    2011-05-09

    Examples of nonlinear circuit design are given. Focus of the design process is on theory and engineering methods (as opposed to numerical analysis). Modeling is related to measurements It is seen that the phase plane is still very useful with proper models Harmonic balance/describing function offers powerful insight (via the combination of simulation with circuit and ODE theory). Measurement and simulation capabilities increased, especially harmonics measurements (since sinusoids are easy to generate)

  19. Equivalent Circuit Modeling of Hysteresis Motors

    SciTech Connect (OSTI)

    Nitao, J J; Scharlemann, E T; Kirkendall, B A

    2009-08-31

    We performed a literature review and found that many equivalent circuit models of hysteresis motors in use today are incorrect. The model by Miyairi and Kataoka (1965) is the correct one. We extended the model by transforming it to quadrature coordinates, amenable to circuit or digital simulation. 'Hunting' is an oscillatory phenomenon often observed in hysteresis motors. While several works have attempted to model the phenomenon with some partial success, we present a new complete model that predicts hunting from first principles.

  20. Electrochemically controlled charging circuit for storage batteries

    DOE Patents [OSTI]

    Onstott, E.I.

    1980-06-24

    An electrochemically controlled charging circuit for charging storage batteries is disclosed. The embodiments disclosed utilize dc amplification of battery control current to minimize total energy expended for charging storage batteries to a preset voltage level. The circuits allow for selection of Zener diodes having a wide range of reference voltage levels. Also, the preset voltage level to which the storage batteries are charged can be varied over a wide range.

  1. Circuit level modeling of inductive elements

    SciTech Connect (OSTI)

    Muyshondt, G.P.; Portnoy, W.M.

    1989-01-01

    Design and analysis of spacecraft power systems have been difficult to perform because of the lack of circuit level models for nonlinear inductive elements. This paper reviews some of the models which have been proposed, their limitations, and applications. An improved saturation dependent model will be described. The model has been implemented in SPICE and with a commercial circuit program and demonstrated to be satisfactory in both implementations. 3 refs., 9 figs.

  2. Foundations for a Circuit Complexity Theory of Sensory Processing

    E-Print Network [OSTI]

    Maass, Wolfgang

    bounds, in particular with linear or almost linear total wire length. 1 Introduction Circuit complexity interest in neuromorphicengineering, especially analog VLSI, and the analysis of neural circuits mathematical analysis of such circuits. The standard mathematical approach is to model such circuits

  3. Challenges for Qualitative Electrical Reasoning in Automotive Circuit Simulation

    E-Print Network [OSTI]

    Snooke, Neal

    Challenges for Qualitative Electrical Reasoning in Automotive Circuit Simulation Neal Snooke it to be used for applications on realistic automotive circuits. The type of circuits for which it is most automotive circuits with more complex overall behaviour can be approximated using this type of modelling

  4. Differential transimpedance amplifier circuit for correlated differential amplification

    SciTech Connect (OSTI)

    Gresham, Christopher A.; Denton, M. Bonner; Sperline, Roger P.

    2008-07-22

    A differential transimpedance amplifier circuit for correlated differential amplification. The amplifier circuit increase electronic signal-to-noise ratios in charge detection circuits designed for the detection of very small quantities of electrical charge and/or very weak electromagnetic waves. A differential, integrating capacitive transimpedance amplifier integrated circuit comprising capacitor feedback loops performs time-correlated subtraction of noise.

  5. Fault-induced delayed voltage recovery in a long inhomogeneous...

    Office of Scientific and Technical Information (OSTI)

    Article: Fault-induced delayed voltage recovery in a long inhomogeneous power-distribution feeder Citation Details In-Document Search This content will become publicly...

  6. Fault Tolerant Evaluation of Continuous Selection Queries over Sensor Data

    E-Print Network [OSTI]

    Lazaridis, Iosif; Han, Qi; Mehrotra, Sharad; Venkatasubramanian, Nalini

    2009-01-01

    Evaluation of Continuous Selection Queries over Sensor Dataevaluation of continuous selection queries (CSQs) over sensor-sensor suffices and there is no Fault Tolerant Evaluation of

  7. STRESS AND FAULTING IN THE COSO GEOTHERMAL FIELD: UPDATE AND...

    Open Energy Info (EERE)

    108 24 in a transitional strike-slip to normal faulting stress regime. These structures bound regions of intense micro-seismicity and are complexly associated with surface...

  8. Dating of major normal fault systems using thermochronology-...

    Open Energy Info (EERE)

    faults, timing of ductile mylonite formation and passage of rocks through the crystal-plastic to brittle transition, and multiple events of extensional unroofing. Here we...

  9. Post-Cretaceous faulting at head of Mississippi embayment

    SciTech Connect (OSTI)

    Nelson, W.J. (Illinois State Geological Survey, Champaign, IL (United States)); Harrison, R.W. (Geological Survey, Reston, VA (United States))

    1993-03-01

    Recent mapping in southernmost Illinois and southeastern Missouri has revealed numerous faults that displace Cretaceous and Tertiary strata. Units as young as the Pliocene-Pleistocene( ) Mounds Gravel are deformed; some faults possibly displace Quaternary sediments. The faults strike northeast, dip nearly vertically, and exhibit characteristics of dextral strike-slip. Pull-apart grabens occur along right-stepping fault strands, they contain chaotically jumbled blocks of Paleozoic, Cretaceous and Tertiary rocks downdropped as much as 800 m relative to wall rocks. Faults at the head of the Mississippi embayment probably originated during Cambrian rifting (Reelfoot rift) and have a long, complex history of reactivation under different stress fields. Some faults are on strike with faults in the New Madrid seismic zone. Kinematics of post-Cretaceous displacements fit the contemporary stress regime of ENE-WSW compression. Similar fault orientations and kinematics, as well as close proximity, suggest a close link between faulting at the head of the embayment and ongoing tectonism in the New Madrid seismic zone.

  10. Recurrent faulting and petroleum accumulation, Cat Creek Anticline, central Montana

    SciTech Connect (OSTI)

    Nelson, W.J. (Illinois State Geological Survey, Champaign (United States))

    1991-06-01

    The Cat Creek anticline, scene of central Montana's first significant oil discovery, is underlain by a south-dipping high-angle fault (Cat Creek fault) that has undergone several episodes of movement with opposite sense of displacement. Borehole data suggest that the Cat Creek fault originated as a normal fault during Proterozoic rifting concurrent with deposition of the Belt Supergroup. Reverse faulting took place in Late Cambrian time, and again near the end of the Devonian Period. The Devonian episode, coeval with the Antler orogeny, raised the southern block several hundred feet. The southern block remained high through Meramecian time, then began to subside. Post-Atokan, pre-Middle Jurassic normal faulting lowered the southern block as much as 1,500 ft. During the Laramide orogeny (latest Cretaceous-Eocene) the Cat Creek fault underwent as much as 4,000 ft of reverse displacement and a comparable amount of left-lateral displacement. The Cat Creek anticline is a fault-propagation fold; en echelon domes and listric normal faults developed along its crest in response to wrenching. Oil was generated mainly in organic-rich shales of the Heath Formation (upper Chesterian Series) and migrated upward along tectonic fractures into Pennsylvanian, Jurassic, and Cretaceous reservoir rocks in structural traps in en echelon domes. Production has been achieved only from those domes where structural closure was retained from Jurassic through Holocene time.

  11. MODELING AND SIMULATION OF HVAC FAULTS IN ENERGYPLUS

    E-Print Network [OSTI]

    Basarkar, Mangesh

    2013-01-01

    and simulated building energy performance, Norford et al. (faults on whole building performance – energy consumption,and simulated energy performance of buildings is that most

  12. Recency of Faulting and Neotectonic Framework in the Dixie Valley...

    Open Energy Info (EERE)

    by active geothermal springs. More specifically, our investigation shows that induced stress concentrations at the endpoints of normal fault ruptures appear to promote favorable...

  13. Recency Of Faulting And Neotechtonic Framework In The Dixie Valley...

    Open Energy Info (EERE)

    by active geothermal springs. More specifically, our investigation shows that induced stress concentrations at the endpoints of normal fault ruptures appear to promote favorable...

  14. Active Fault Controls At High-Temperature Geothermal Sites- Prospectin...

    Open Energy Info (EERE)

    the level of unrecognized active faults present in these areas. Analysis of low-sun-angle aerial photography acquired over the Needle Rocks, Astor Pass, Empire, and Lee...

  15. Fault-tolerant distributed transactions for partitioned OLTP databases

    E-Print Network [OSTI]

    Jones, Evan P. C. (Evan Philip Charles), 1981-

    2012-01-01

    This thesis presents Dtxn, a fault-tolerant distributed transaction system designed specifically for building online transaction processing (OLTP) databases. Databases have traditionally been designed as general purpose ...

  16. Arc-Fault Detector Algorithm Evaluation Method Utilizing Prerecorded...

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Electrical Code Article 690.11 requires photovoltaic systems on or penetrating a building to include a DC arc-fault protection device. In order to satisfy this...

  17. Checksum-Based Fault Tolerance for LU Factorization

    E-Print Network [OSTI]

    Davies, Teresa

    2014-01-01

    study of failures in high-performance computing systems. InFault tolerant high performance computing by a codingfor large-scale high- performance computing. In 2012

  18. Effects of Volcanism, Crustal Thickness, and Large Scale Faulting...

    Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

    Effects of Volcanism, Crustal Thickness, and Large Scale Faulting on the Development and Evolution of Geothermal Systems: Collaborative Project in Chile Effects of Volcanism,...

  19. MICRO-SEISMICITY, FAULT STRUCTURE AND HYDRAULIC COMPARTMENTALIZATION...

    Open Energy Info (EERE)

    LibraryAdd to library Conference Proceedings: MICRO-SEISMICITY, FAULT STRUCTURE AND HYDRAULIC COMPARTMENTALIZATION WITHIN THE COSO GETHERMAL FIELD, CALIFORNIA Abstract High...

  20. PV Arc Fault Detector Challenges Due to Module Frequency Response...

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    This poster does not contain any proprietary or confidential information. Introduction PV system arc faults have led to a number of rooftop fires which have caused significant...

  1. Active shunt capacitance cancelling oscillator circuit

    DOE Patents [OSTI]

    Wessendorf, Kurt O.

    2003-09-23

    An oscillator circuit is disclosed which can be used to produce oscillation using a piezoelectric crystal, with a frequency of oscillation being largely independent of any shunt capacitance associated with the crystal (i.e. due to electrodes on the surfaces of the crystal and due to packaging and wiring for the crystal). The oscillator circuit is based on a tuned gain stage which operates the crystal at a frequency, f, near a series resonance frequency, f.sub.S. The oscillator circuit further includes a compensation circuit that supplies all the ac current flow through the shunt resistance associated with the crystal so that this ac current need not be supplied by the tuned gain stage. The compensation circuit uses a current mirror to provide the ac current flow based on the current flow through a reference capacitor that is equivalent to the shunt capacitance associated with the crystal. The oscillator circuit has applications for driving piezoelectric crystals for sensing of viscous, fluid or solid media by detecting a change in the frequency of oscillation of the crystal and a resonator loss which occur from contact of an exposed surface of the crystal by the viscous, fluid or solid media.

  2. A Comparison of Fault Detection Methods For a Transcritical Refrigeration System 

    E-Print Network [OSTI]

    Janecke, Alex Karl

    2012-10-19

    pairings of four faults: over/undercharge, evaporator fouling, gas cooler fouling, and compressor valve leakage. This technique allows for low cost measurement and independent detection of individual faults even when multiple faults are present. Results...

  3. Neural Network-Based Classification of Single-Phase Distribution Transformer Fault Data 

    E-Print Network [OSTI]

    Zhang, Xujia

    2006-08-16

    The ultimate goal of this research is to develop an online, non-destructive, incipient fault detection system that is able to detect incipient faults in transformers and other electric equipment before the faults become ...

  4. Fluids migration and dynamics of a blocks-and-faults system

    E-Print Network [OSTI]

    1910-70-11

    Keywords: earthquake catalog, block model, fault, tectonic structure, fluid, fil- ...... nal vertical fault near upper vertices of adjacent internal blocks, and formation of ... acts near the right external vertical fault: fractures filled in with water emerge ...

  5. Evaluation of a Decoupling-Based Fault Detection and Diagnostic Technique - Part I: Field Emulation Evaluation 

    E-Print Network [OSTI]

    Li, H.; Braun, J.

    2006-01-01

    Existing methods addressing automated fault detection and diagnosis (FDD) for vapor compression air conditioning system have good performance for faults that occur individually, but they have difficulty in handling multiple-simultaneous faults...

  6. ALLIANCE: An Architecture for Fault Tolerant, Cooperative Control of Heterogeneous Mobile Robots

    E-Print Network [OSTI]

    Parker, Lynne E.

    ALLIANCE: An Architecture for Fault Tolerant, Cooperative Control of Heterogeneous Mobile Robots ALLIANCE, that utilizes adaptive action selection to achieve fault toler- ant cooperative control in robot demonstration. These experiments illustrate the ability of ALLIANCE to achieve adaptive, fault

  7. Fault Tolerant Arithmetic with Applications in Nanotechnology based Systems

    E-Print Network [OSTI]

    Rao, Wenjing

    Fault Tolerant Arithmetic with Applications in Nanotechnology based Systems Wenjing Rao UC San nanotechnologies have been displaying the Neg- ative Differential Resistance (NDR) characteristic, which makes them fault-tolerant arithmetic in NDR nanotechnologies. Specifically, we show how linear block codes can

  8. Automatic Fault Characterization via Abnormality-Enhanced Classification

    SciTech Connect (OSTI)

    Bronevetsky, G; Laguna, I; de Supinski, B R

    2010-12-20

    Enterprise and high-performance computing systems are growing extremely large and complex, employing hundreds to hundreds of thousands of processors and software/hardware stacks built by many people across many organizations. As the growing scale of these machines increases the frequency of faults, system complexity makes these faults difficult to detect and to diagnose. Current system management techniques, which focus primarily on efficient data access and query mechanisms, require system administrators to examine the behavior of various system services manually. Growing system complexity is making this manual process unmanageable: administrators require more effective management tools that can detect faults and help to identify their root causes. System administrators need timely notification when a fault is manifested that includes the type of fault, the time period in which it occurred and the processor on which it originated. Statistical modeling approaches can accurately characterize system behavior. However, the complex effects of system faults make these tools difficult to apply effectively. This paper investigates the application of classification and clustering algorithms to fault detection and characterization. We show experimentally that naively applying these methods achieves poor accuracy. Further, we design novel techniques that combine classification algorithms with information on the abnormality of application behavior to improve detection and characterization accuracy. Our experiments demonstrate that these techniques can detect and characterize faults with 65% accuracy, compared to just 5% accuracy for naive approaches.

  9. Fault current limiter with shield and adjacent cores

    DOE Patents [OSTI]

    Darmann, Francis Anthony; Moriconi, Franco; Hodge, Eoin Patrick

    2013-10-22

    In a fault current limiter (FCL) of a saturated core type having at least one coil wound around a high permeability material, a method of suppressing the time derivative of the fault current at the zero current point includes the following step: utilizing an electromagnetic screen or shield around the AC coil to suppress the time derivative current levels during zero current conditions.

  10. An Information Flow Model of Fault Detection Margaret C. Thompson ?

    E-Print Network [OSTI]

    Massachusetts at Amherst, University of

    not be practical. Nonethe­ less, Relay provides insight into testing and fault de­ tection and suggests an approach and Computer Science Amherst, MA 01003 University of California Irvine, CA 92717 Abstract Relay is a model of how a fault causes a failure on execution of some test datum. This process begins with introduction

  11. Fault Tolerant Oxygen Control of a Diesel Engine Air System

    E-Print Network [OSTI]

    Paris-Sud XI, Université de

    Fault Tolerant Oxygen Control of a Diesel Engine Air System Rainer Nitsche Matthias Bitzer control problem of a Diesel engine air system having a jammed Exhaust Gas Recirculation (EGR) valve of the air system. Keywords: Fault tolerant control, Diesel engine, Air system, Model-based trajectory

  12. Symbolic identification for fault detection in aircraft gas turbine engines

    E-Print Network [OSTI]

    Ray, Asok

    Symbolic identification for fault detection in aircraft gas turbine engines S Chakraborty, S Sarkar and computationally inexpensive technique of component-level fault detection in aircraft gas-turbine engines identification, gas turbine engines, language-theoretic analysis 1 INTRODUCTION The propulsion system of modern

  13. On Distributed Fault-Tolerant Detection in Wireless Sensor Networks

    E-Print Network [OSTI]

    Dong, Ming

    --Distributed event detection, fault tolerance, sensor fusion, energy-efficiency, wireless sensor networks. æ 1 to choose a proper neighborhood size n for a sensor node in fault correction such that the energy could to achieve better detection and better balance between detection accuracy and energy usage. Our work makes

  14. Common Trends in Software Fault and Failure Data

    E-Print Network [OSTI]

    Goseva-Popstojanova, Katerina

    Common Trends in Software Fault and Failure Data Maggie Hamill, Member, IEEE, and Katerina Goseva with the findings from related studies. The consistency of several main trends across software systems in this paper-Popstojanova, Senior Member, IEEE Abstract--The benefits of the analysis of software faults and failures have been

  15. Fault Reporting Processes in Business-Critical Systems

    E-Print Network [OSTI]

    and reporting7 Quantitative and qualitativeHazard analysis vs. fault report analysis - DAIM 6 Qualitative projects4 Quantitative, explorativeFault report study of four projects3 Qualitative, descriptive and Information Science (IDI) University of Science and Technology (NTNU) Trondheim, Norway PhD thesis

  16. Fault Detection and Diagnosis Method for VAV Terminal Units 

    E-Print Network [OSTI]

    Miyata, M.; Yoshida, H.; Asada, M.; Wang, F.; Hashiguchi, S.

    2004-01-01

    This paper proposes two fault detection and diagnosis methods for VAV units without a sensor of supply air volume, and the results of applying these methods to a real building are presented. One method detects faults by applying a statistical method...

  17. SHIELD: A Fault-Tolerant MPI for an Infiniband Cluster

    E-Print Network [OSTI]

    Yeom, Heon Young

    SHIELD: A Fault-Tolerant MPI for an Infiniband Cluster Hyuck Han, Hyungsoo Jung, Jai Wug Kim, a successful solution has yet to be delivered to commercial vendors. This paper presents SHIELD, a prac- tical and easily-deployable fault-tolerant MPI and management system of MPI for an Infiniband cluster. SHIELD

  18. Outlier Detection Rules for Fault Detection in Solar Photovoltaic Arrays

    E-Print Network [OSTI]

    Lehman, Brad

    . The models must be modified due to different PV capacity, solar cell technology, or installation locationOutlier Detection Rules for Fault Detection in Solar Photovoltaic Arrays Ye Zhao, Brad Lehman Abstract-- Solar photovoltaic (PV) arrays are unique power sources that may have uncleared fault current

  19. Original Article Multi-sensor information fusion for fault

    E-Print Network [OSTI]

    Ray, Asok

    The article addresses data-driven fault detection in commercial aircraft gas turbine engines in the framework is validated on the NASA C-MAPSS simulation test bed of aircraft gas turbine engines; both single is also addressed. Keywords Gas turbine engines, fault detection, information fusion Date received: 15 May

  20. Fault Detection, Identification and Accommodation for an Electro-hydraulic

    E-Print Network [OSTI]

    Yao, Bin

    in electro-hydraulic systems. It is well known fact that any realistic model of a hydraulic system suffersFault Detection, Identification and Accommodation for an Electro-hydraulic System: An Adaptive, such a scheme becomes a natural choice for designing robust fault detection algorithms for electro-hydraulic

  1. Multi-sensor Wireless System for Fault Detection in Induction Motors

    E-Print Network [OSTI]

    Tarkesh Esfahani, Ehsan

    2012-01-01

    2 Faults in Motors 2.1 Bearing Faultcombined faults in induction motors,” IEEE Transactions onV. Climente-Alarcon, “Induction motor diagnosis based on a

  2. Development of Integrated Meso/Microscale Traffic Simulation Software for Testing Fault Detection and Handling Algorithms in AHS: Final Report

    E-Print Network [OSTI]

    Horowitz, Roberto

    2003-01-01

    Traffic Simulation Software for Testing Fault Detection andTra?c Simulation Software for Testing Fault Detection and

  3. Lockout device for high voltage circuit breaker

    DOE Patents [OSTI]

    Kozlowski, L.J.; Shirey, L.A.

    1993-01-26

    An improved lockout assembly is provided for a circuit breaker to lock the switch handle into a selected switch position. The lockout assembly includes two main elements, each having a respective foot for engaging a portion of the upper housing wall of the circuit breaker. The first foot is inserted into a groove in the upper housing wall, and the second foot is inserted into an adjacent aperture (e.g., a slot) in the upper housing wall. The first foot is slid under and into engagement with a first portion, and the second foot is slid under and into engagement with a second portion of the upper housing wall. At the same time the respective two feet are placed in engagement with the respective portions of the upper housing wall, two holes, one on each of the respective two main elements of the assembly, are placed in registration; and a locking device, such as a special scissors equipped with a padlock, is installed through the registered holes to secure the lockout assembly on the circuit breaker. When the lockout assembly of the invention is secured on the circuit breaker, the switch handle of the circuit breaker is locked into the selected switch position and prevented from being switched to another switch position.

  4. Lookout device for high voltage circuit breaker

    SciTech Connect (OSTI)

    Kozlowski, L.J.; Shirey, L.A.

    1991-12-31

    An improved lockout assembly is provided for a circuit breaker to lock the switch handle into a selected switch position. The lockout assembly includes two main elements, each having a respective foot for engaging a portion of the upper housing wall of the circuit breaker. The first foot is inserted into a groove in the upper housing wall, and the second foot is inserted into an adjacent aperture (e.g., a slot) in the upper housing wall. The first foot is slid under and into engagement with a first portion, and the second foot is slid under and into engagement with a second portion of the upper housing wall. At the same time the respective two feet are placed in engagement with the respective portions of the upper housing wall, two holes, one on each of the respective two main elements of the assembly, are placed in registration; and a locking device, such as a special scissors equipped with a padlock, is installed through the registered holes to secure the lockout assembly on the circuit breaker. When the lockout assembly of the invention is secured on the circuit breaker, the switch handle of the circuit breaker is locked into the selected switch position and prevented from being switched to another switch position.

  5. Lockout device for high voltage circuit breaker

    SciTech Connect (OSTI)

    Kozlowski, Lawrence J. (New Kensington, PA); Shirey, Lawrence A. (North Huntingdon, PA)

    1993-01-01

    An improved lockout assembly is provided for a circuit breaker to lock the switch handle into a selected switch position. The lockout assembly includes two main elements, each having a respective foot for engaging a portion of the upper housing wall of the circuit breaker. The first foot is inserted into a groove in the upper housing wall, and the second foot is inserted into an adjacent aperture (e.g., a slot) in the upper housing wall. The first foot is slid under and into engagement with a first portion, and the second foot is slid under and into engagement with a second portion of the upper housing wall. At the same time the repsective two feet are placed in engagement with the respective portions of the upper housing wall, two holes, one on each of the respective two main elements of the assembly, are placed in registration; and a locking device, such as a special scissors equipped with a padlock, is installed through the registered holes to secure the lockout assembly on the circuit breaker. When the lockout assembly of the invention is secured on the circuit breaker, the switch handle of the circuit breaker is locked into the selected switch position and prevented from being switched to another switch position.

  6. Dual circuit embossed sheet heat transfer panel

    DOE Patents [OSTI]

    Morgan, G.D.

    1984-02-21

    A heat transfer panel provides redundant cooling for fusion reactors or the like environment requiring low-mass construction. Redundant cooling is provided by two independent cooling circuits, each circuit consisting of a series of channels joined to inlet and outlet headers. The panel comprises a welded joinder of two full-size and two much smaller partial-size sheets. The first full-size sheet is embossed to form first portions of channels for the first and second circuits, as well as a header for the first circuit. The second full-sized sheet is then laid over and welded to the first full-size sheet. The first and second partial-size sheets are then overlaid on separate portions of the second full-sized sheet, and are welded thereto. The first and second partial-sized sheets are embossed to form inlet and outlet headers, which communicate with channels of the second circuit through apertures formed in the second full-sized sheet. 6 figs.

  7. Development of Hydrologic Characterization Technology of Fault Zones

    SciTech Connect (OSTI)

    Karasaki, Kenzi; Onishi, Tiemi; Wu, Yu-Shu

    2008-03-31

    Through an extensive literature survey we find that there is very limited amount of work on fault zone hydrology, particularly in the field using borehole testing. The common elements of a fault include a core, and damage zones. The core usually acts as a barrier to the flow across it, whereas the damage zone controls the flow either parallel to the strike or dip of a fault. In most of cases the damage zone isthe one that is controlling the flow in the fault zone and the surroundings. The permeability of damage zone is in the range of two to three orders of magnitude higher than the protolith. The fault core can have permeability up to seven orders of magnitude lower than the damage zone. The fault types (normal, reverse, and strike-slip) by themselves do not appear to be a clear classifier of the hydrology of fault zones. However, there still remains a possibility that other additional geologic attributes and scaling relationships can be used to predict or bracket the range of hydrologic behavior of fault zones. AMT (Audio frequency Magneto Telluric) and seismic reflection techniques are often used to locate faults. Geochemical signatures and temperature distributions are often used to identify flow domains and/or directions. ALSM (Airborne Laser Swath Mapping) or LIDAR (Light Detection and Ranging) method may prove to be a powerful tool for identifying lineaments in place of the traditional photogrammetry. Nonetheless not much work has been done to characterize the hydrologic properties of faults by directly testing them using pump tests. There are some uncertainties involved in analyzing pressure transients of pump tests: both low permeability and high permeability faults exhibit similar pressure responses. A physically based conceptual and numerical model is presented for simulating fluid and heat flow and solute transport through fractured fault zones using a multiple-continuum medium approach. Data from the Horonobe URL site are analyzed to demonstrate the proposed approach and to examine the flow direction and magnitude on both sides of a suspected fault. We describe a strategy for effective characterization of fault zone hydrology. We recommend conducting a long term pump test followed by a long term buildup test. We do not recommend isolating the borehole into too many intervals. We do recommend ensuring durability and redundancy for long term monitoring.

  8. Application-Specific Fault Tolerance via Data Access Characterization

    SciTech Connect (OSTI)

    Ali, Nawab; Krishnamoorthy, Sriram; Govind, Niranjan; Kowalski, Karol; Sadayappan, Ponnuswamy

    2011-08-30

    Recent trends in semiconductor technology and supercomputer design predict an increasing probability of faults during an application's execution. Designing an application that is resilient to system failures requires careful evaluation of the impact of various approaches on preserving key application state. In this paper, we present our experiences in an ongoing effort to make a large computational chemistry application fault tolerant. We construct the data access signatures of key application modules to evaluate alternative fault tolerance approaches. We present the instrumentation methodology, characterization of the application modules, and evaluation of fault tolerance techniques using the information collected. The application signatures developed capture application characteristics not traditionally revealed by performance tools. We believe these can be used in the design and evaluation of runtimes beyond fault tolerance.

  9. Feb. 11, 2008 Advanced Fault Tolerance Solutions for High Performance Computing 1/47 Advanced Fault Tolerance Solutions

    E-Print Network [OSTI]

    Engelmann, Christian

    Feb. 11, 2008 Advanced Fault Tolerance Solutions for High Performance Computing 1/47 RAS RAS Advanced Fault Tolerance Solutions for High Performance Computing Christian Engelmann Oak Ridge National Solutions for High Performance Computing 2/47 · Nation's largest energy laboratory · Nation's largest

  10. Rupture Dynamics of Strike-Slip Faults with Stepovers: From Conceptually Simplified to Realistically Complex Fault Systems 

    E-Print Network [OSTI]

    Liu, Zaifeng

    2014-05-05

    . The coupling effect of those two effects has also been studied. The possible correlation between the slip gradient nearby the first fault end and the ability of the rupture to jump over the structure stepover in the strike-slip fault system has been verified...

  11. Package for integrated optic circuit and method

    DOE Patents [OSTI]

    Kravitz, Stanley H. (26 Aspen Rd., Placitas, NM 87043); Hadley, G. Ronald (6012 Annapolis NE., Albuquerque, NM 87111); Warren, Mial E. (3825 Mary Ellen NE., Albuquerque, NM 87111); Carson, Richard F. (1036 Jewel Pl. NE., Albuquerque, NM 87123); Armendariz, Marcelino G. (1023 Oro Real NE., Albuquerque, NM 87123)

    1998-01-01

    A structure and method for packaging an integrated optic circuit. The package comprises a first wall having a plurality of microlenses formed therein to establish channels of optical communication with an integrated optic circuit within the package. A first registration pattern is provided on an inside surface of one of the walls of the package for alignment and attachment of the integrated optic circuit. The package in one embodiment may further comprise a fiber holder for aligning and attaching a plurality of optical fibers to the package and extending the channels of optical communication to the fibers outside the package. In another embodiment, a fiber holder may be used to hold the fibers and align the fibers to the package. The fiber holder may be detachably connected to the package.

  12. Package for integrated optic circuit and method

    DOE Patents [OSTI]

    Kravitz, S.H.; Hadley, G.R.; Warren, M.E.; Carson, R.F.; Armendariz, M.G.

    1998-08-04

    A structure and method are disclosed for packaging an integrated optic circuit. The package comprises a first wall having a plurality of microlenses formed therein to establish channels of optical communication with an integrated optic circuit within the package. A first registration pattern is provided on an inside surface of one of the walls of the package for alignment and attachment of the integrated optic circuit. The package in one embodiment may further comprise a fiber holder for aligning and attaching a plurality of optical fibers to the package and extending the channels of optical communication to the fibers outside the package. In another embodiment, a fiber holder may be used to hold the fibers and align the fibers to the package. The fiber holder may be detachably connected to the package. 6 figs.

  13. Radiation-hardened transistor and integrated circuit

    DOE Patents [OSTI]

    Ma, Kwok K. (Albuquerque, NM)

    2007-11-20

    A composite transistor is disclosed for use in radiation hardening a CMOS IC formed on an SOI or bulk semiconductor substrate. The composite transistor has a circuit transistor and a blocking transistor connected in series with a common gate connection. A body terminal of the blocking transistor is connected only to a source terminal thereof, and to no other connection point. The blocking transistor acts to prevent a single-event transient (SET) occurring in the circuit transistor from being coupled outside the composite transistor. Similarly, when a SET occurs in the blocking transistor, the circuit transistor prevents the SET from being coupled outside the composite transistor. N-type and P-type composite transistors can be used for each and every transistor in the CMOS IC to radiation harden the IC, and can be used to form inverters and transmission gates which are the building blocks of CMOS ICs.

  14. Circuit electromechanics with single photon strong coupling

    E-Print Network [OSTI]

    Zheng-Yuan Xue; Li-Na Yang; Jian Zhou

    2015-07-13

    In circuit electromechanics, the coupling strength is usually very small. Here, replacing the capacitor in circuit electromechanics by a superconducting flux qubit, we show that the coupling among the qubit and the two resonators can induce effective electromechanical coupling which can attain the strong coupling regime at the single photon level with feasible experimental parameters. We use dispersive couplings among two resonators and the qubit while the qubit is also driven by an external classical field. These couplings form a three-wave mixing configuration among the three elements where the qubit degree of freedom can be adiabatically eliminated, and thus results in the enhanced coupling between the two resonators. Therefore, our work constitutes the first step towards studying quantum nonlinear effect in circuit electromechanics.

  15. Electronic circuit for measuring series connected electrochemical cell voltages

    DOE Patents [OSTI]

    Ashtiani, Cyrus N. (West Bloomfield, MI); Stuart, Thomas A. (Toledo, OH)

    2000-01-01

    An electronic circuit for measuring voltage signals in an energy storage device is disclosed. The electronic circuit includes a plurality of energy storage cells forming the energy storage device. A voltage divider circuit is connected to at least one of the energy storage cells. A current regulating circuit is provided for regulating the current through the voltage divider circuit. A voltage measurement node is associated with the voltage divider circuit for producing a voltage signal which is proportional to the voltage across the energy storage cell.

  16. GENESIS ; a feasibility manager for electronic circuits 

    E-Print Network [OSTI]

    Fossati, Humberto Mario

    1989-01-01

    . This search algorithms, however, do not provide means for ranking of data. A recent review of current research in the area of automation of design for analog circuits shows the development of a new version of BLADES [14]. This software is an Expert Systems... based automated design approach for analog circuits being developed by ATILT Bell Laboratories. They claim to be the first ones to successfully design an expert systems in the analog design domain based on the original paper [10] dated 1986. BLADES...

  17. Locating hardware faults in a parallel computer

    DOE Patents [OSTI]

    Archer, Charles J.; Megerian, Mark G.; Ratterman, Joseph D.; Smith, Brian E.

    2010-04-13

    Locating hardware faults in a parallel computer, including defining within a tree network of the parallel computer two or more sets of non-overlapping test levels of compute nodes of the network that together include all the data communications links of the network, each non-overlapping test level comprising two or more adjacent tiers of the tree; defining test cells within each non-overlapping test level, each test cell comprising a subtree of the tree including a subtree root compute node and all descendant compute nodes of the subtree root compute node within a non-overlapping test level; performing, separately on each set of non-overlapping test levels, an uplink test on all test cells in a set of non-overlapping test levels; and performing, separately from the uplink tests and separately on each set of non-overlapping test levels, a downlink test on all test cells in a set of non-overlapping test levels.

  18. Self field triggered superconducting fault current limiter

    DOE Patents [OSTI]

    Tekletsadik, Kasegn D. (Rexford, NY)

    2008-02-19

    A superconducting fault current limiter array with a plurality of superconductor elements arranged in a meanding array having an even number of supconductors parallel to each other and arranged in a plane that is parallel to an odd number of the plurality of superconductors, where the odd number of supconductors are parallel to each other and arranged in a plane that is parallel to the even number of the plurality of superconductors, when viewed from a top view. The even number of superconductors are coupled at the upper end to the upper end of the odd number of superconductors. A plurality of lower shunt coils each coupled to the lower end of each of the even number of superconductors and a plurality of upper shunt coils each coupled to the upper end of each of the odd number of superconductors so as to generate a generally orthoganal uniform magnetic field during quenching using only the magenetic field generated by the superconductors.

  19. Online Monitoring System for Performance Fault Detection

    SciTech Connect (OSTI)

    Gioiosa, Roberto; Kestor, Gokcen; Kerbyson, Darren J.

    2014-05-19

    To achieve the exaFLOPS performance within a contain power budget, next supercomputers will feature hundreds of millions of components operating at low- and near-threshold voltage. As the probability that at least one of these components fails during the execution of an application approaches certainty, it seems unrealistic to expect that any run of a scientific application will not experience some performance faults. We believe that there is need of a new generation of light-weight performance and debugging tools that can be used online even during production runs of parallel applications and that can identify performance anomalies during the application execution. In this work we propose the design and implementation of a monitoring system that continuously inspects the evolution of run

  20. Development of Characterization Technology for Fault Zone Hydrology

    SciTech Connect (OSTI)

    Karasaki, Kenzi; Onishi, Tiemi; Gasperikova, Erika; Goto, Junichi; Tsuchi, Hiroyuki; Miwa, Tadashi; Ueta, Keiichi; Kiho, Kenzo; MIyakawa, Kimio

    2010-08-06

    Several deep trenches were cut, and a number of geophysical surveys were conducted across the Wildcat Fault in the hills east of Berkeley, California. The Wildcat Fault is believed to be a strike-slip fault and a member of the Hayward Fault System, with over 10 km of displacement. So far, three boreholes of ~;; 150m deep have been core-drilled and borehole geophysical logs were conducted. The rocks are extensively sheared and fractured; gouges were observed at several depths and a thick cataclasitic zone was also observed. While confirming some earlier, published conclusions from shallow observations about Wildcat, some unexpected findings were encountered. Preliminary analysis indicates that Wildcat near the field site consists of multiple faults. The hydraulic test data suggest the dual properties of the hydrologic structure of the fault zone. A fourth borehole is planned to penetrate the main fault believed to lie in-between the holes. The main philosophy behind our approach for the hydrologic characterization of such a complex fractured system is to let the system take its own average and monitor a long term behavior instead of collecting a multitude of data at small length and time scales, or at a discrete fracture scale and to ?up-scale,? which is extremely tenuous.

  1. A structural approach to delay optimization in combinational circuits 

    E-Print Network [OSTI]

    Munshi, Avinash

    1999-01-01

    A major problem in circuit design is achieving the maximum performance for a given technology. In the context of logic synthesis and optimization, maximizing performance means reducing the maximum propagation delay from circuit inputs to outputs...

  2. Supplementary Information for Simulating weak localization in superconducting quantum circuit

    E-Print Network [OSTI]

    Martinis, John M.

    Supplementary Information for Simulating weak localization in superconducting quantum circuit Yu-type entangled state in superconducting quantum circuits.[2, 3] We rst generated a photon in the readout qubit

  3. Parallel Algorithms for Time and Frequency Domain Circuit Simulation 

    E-Print Network [OSTI]

    Dong, Wei

    2010-10-12

    solution to circuit simulation besides the known application of distributed-memory clustered computing platforms, which provides abundant hardware computing resources. This research addresses the limitations of traditional serial circuit simulations...

  4. IMPACT OF DYNAMIC VOLTAGE SCALING (DVS) ON CIRCUIT OPTIMIZATION 

    E-Print Network [OSTI]

    Esquit Hernandez, Carlos A.

    2010-01-16

    Circuit designers perform optimization procedures targeting speed and power during the design of a circuit. Gate sizing can be applied to optimize for speed, while Dual-VT and Dynamic Voltage Scaling (DVS) can be applied to optimize for leakage...

  5. NEUTRAL-BEAM PLASMA SOURCE METAL-ARC PROTECTION CIRCUIT

    E-Print Network [OSTI]

    deVries, G.J.

    2010-01-01

    e r . METAL ARCS IN PLASMAS Metal-arcs in plasma sources are1981 NEUTRAL-BEAM PLASMA SOURCE METAL-ARC PROTECTION CIRCUIT48 NEUTRAL-BEAM PLASMA SOURCE METAL-ARC PROTECTION CIRCUIT*

  6. Protecting Circuits from Computationally Bounded and Noisy Leakage

    E-Print Network [OSTI]

    Faust, Sebastian

    Physical computational devices leak side-channel information that may, and often does, reveal secret internal states. We present a general transformation that compiles any circuit into a circuit with the same functionality ...

  7. A Taxonomy of Rerouting in Circuit-Switched Networks

    E-Print Network [OSTI]

    Wong, Eric Wing-Ming

    A Taxonomy of Rerouting in Circuit-Switched Networks Eric W. M. Wong and Andy K. M. Chan, City presents a taxonomy of rerouting in circuit- switched networks showing the various ways rerouting can

  8. Noise isolation system for high-speed circuits

    DOE Patents [OSTI]

    McNeilly, D.R.

    1983-12-29

    A noise isolation circuit is provided that consists of a dual function bypass which confines high-speed switching noise to the component or circuit which generates it and isolates the component or circuit from high-frequency noise transients which may be present on the ground and power supply busses. A local circuit ground is provided which is coupled to the system ground by sufficient impedance to force the dissipation of the noise signal in the local circuit or component generating the noise. The dual function bypass network couples high-frequency noise signals generated in the local component or circuit through a capacitor to the local ground while isolating the component or circuit from noise signals which may be present on the power supply busses or system ground. The network is an effective noise isolating system and is applicable to both high-speed analog and digital circuits.

  9. Noise isolation system for high-speed circuits

    DOE Patents [OSTI]

    McNeilly, David R. (Maryville, TN)

    1986-01-01

    A noise isolation circuit is provided that consists of a dual function bypass which confines high-speed switching noise to the component or circuit which generates it and isolates the component or circuit from high-frequency noise transients which may be present on the ground and power supply busses. A local circuit ground is provided which is coupled to the system ground by sufficient impedance to force the dissipation of the noise signal in the local circuit or component generating the noise. The dual function bypass network couples high-frequency noise signals generated in the local component or circuit through a capacitor to the local ground while isolating the component or circuit from noise signals which may be present on the power supply busses or system ground. The network is an effective noise isolating system and is applicable to both high-speed analog and digital circuits.

  10. Quantum computer of wire circuit architecture

    E-Print Network [OSTI]

    S. A. Moiseev; F. F. Gubaidullin; S. N. Andrianov

    2010-01-07

    First solid state quantum computer was built using transmons (cooper pair boxes). The operation of the computer is limited because of using a number of the rigit cooper boxes working with fixed frequency at temperatures of superconducting material. Here, we propose a novel architecture of quantum computer based on a flexible wire circuit of many coupled quantum nodes containing controlled atomic (molecular) ensembles. We demonstrate wide opportunities of the proposed computer. Firstly, we reveal a perfect storage of external photon qubits to multi-mode quantum memory node and demonstrate a reversible exchange of the qubits between any arbitrary nodes. We found optimal parameters of atoms in the circuit and self quantum modes for quantum processing. The predicted perfect storage has been observed experimentally for microwave radiation on the lithium phthalocyaninate molecule ensemble. Then also, for the first time we show a realization of the efficient basic two-qubit gate with direct coupling of two arbitrary nodes by using appropriate atomic frequency shifts in the circuit nodes. Proposed two-qubit gate runs with a speed drastically accelerated proportionally to the number of atoms in the node. The direct coupling and accelerated two-qubit gate can be realized for large number of the circuit nodes. Finally, we describe two and three-dimensional scalable architectures that pave the road to construction of universal multi-qubit quantum computer operating at room temperatures.

  11. Bioluminescent bioreporter integrated circuit detection methods

    DOE Patents [OSTI]

    Simpson, Michael L.; Paulus, Michael J.; Sayler, Gary S.; Applegate, Bruce M.; Ripp, Steven A.

    2005-06-14

    Disclosed are monolithic bioelectronic devices comprising a bioreporter and an OASIC. These bioluminescent bioreporter integrated circuit are useful in detecting substances such as pollutants, explosives, and heavy-metals residing in inhospitable areas such as groundwater, industrial process vessels, and battlefields. Also disclosed are methods and apparatus for detection of particular analytes, including ammonia and estrogen compounds.

  12. ECE 2100 Circuit Analysis Spring 2011

    E-Print Network [OSTI]

    Miller, Damon A.

    ECE 2100 Circuit Analysis Spring 2011 Exam #1 NAME analysis. #12;© 2011 Damon A. Miller Schematics drawn using LTspice IV (linear.com). Some problems might Schematics drawn using LTspice IV (linear.com). Some problems might be adapted from the course text

  13. Global and local properties of asynchronous circuits

    E-Print Network [OSTI]

    Global and local properties of asynchronous circuits optimized for energy efficiency Paul I. P optimized for E \\Theta t n , the relationship between energy consumption and com­ putation delay energy consumption a major concern in VLSI design. As a consequence, energy efficiency is becoming

  14. The Ideal Transformer Description and Circuit Symbol

    E-Print Network [OSTI]

    King, Roger

    . This discussion is limited to a basic design which has two windings placed on one core. The circuit symbol in Fig as "primary" and "secondary." This convention is often used when a generator is connected to a primary winding configurations and materials, including just air, and they may have more than two coils or windings

  15. CIRCUIT EQUATION FORMULATION OF RESISTIVE WALL MODE

    E-Print Network [OSTI]

    . POMPHREY, R.E. HATCHER Princeton Plasma Physics Laboratory, Princeton University, Princeton, New Jersey concepts from elec- trical circuit theory. Each of the coupled elements (the perturbed plasma current with a shaped cross-section has been crucial to the success of modern tokamak fusion research [1­8]. The key

  16. Count-doubling time safety circuit

    DOE Patents [OSTI]

    Rusch, Gordon K. (Downers Grove, IL); Keefe, Donald J. (Lemont, IL); McDowell, William P. (Downers Grove, IL)

    1981-01-01

    There is provided a nuclear reactor count-factor-increase time monitoring circuit which includes a pulse-type neutron detector, and means for counting the number of detected pulses during specific time periods. Counts are compared and the comparison is utilized to develop a reactor scram signal, if necessary.

  17. Visualization of stacking faults in fcc crystals in plastic deformations

    E-Print Network [OSTI]

    Takeshi Kawasaki; Akira Onuki

    2011-11-27

    Using molecular dynamics simulation, we investigate the dynamics of stacking faults in fcc crystals in uniaxial stretching in a Lennard-Jones binary mixture composed of 4096 particles in three dimensions. We visualize stacking faults using a disorder variable $D_j(t)$ for each particle $j$ constructed from local bond order parameters based on spherical harmonics (Steinhardt order parameters). Also introducing a method of bond breakage, we examine how stacking faults are formed and removed by collective particle motions. These processes are relevant in plasticity of fcc crystals.

  18. Static Fault Attack on Hardware DES Registers Philippe Loubet-Moundi, Francis Olivier, and David Vigilant

    E-Print Network [OSTI]

    International Association for Cryptologic Research (IACR)

    Static Fault Attack on Hardware DES Registers Philippe Loubet-Moundi, Francis Olivier, and David deals with static faults which lie in between. A static fault modifies a value loaded in a volatile], quickly became a privileged target for DFA. #12;2 Static Fault Attacks on Hardware DES Registers Indeed

  19. Can Fault Prediction Models and Metrics be Used for Vulnerability Prediction? Yonghee Shin and Laurie Williams

    E-Print Network [OSTI]

    Young, R. Michael

    are built with traditional metrics of complexity, code churn, and fault history. We have performed to the code [17]. Hence, complexity metrics and code churn metrics have been used for fault prediction [5, 17 fault prediction metrics ­ complexity, code churn, and fault history metrics for vulnerability

  20. Seismic behaviour of the Dead Sea fault along Araba valley, Y. Klinger,1,

    E-Print Network [OSTI]

    Avouac, Jean-Philippe

    rue Lafayette, F-75480 Paris cedex 10, France 4 Department of Geology, University of Jordan, Amman-lateral strike-slip fault. South of the Dead Sea basin, the Wadi Araba fault extends over 160 km to the Gulf the fault except around the Dead Sea and Gulf of Aqaba, where the fault splays into complex pull-apart basin

  1. Circuit design for embedded memory in low-power integrated circuits

    E-Print Network [OSTI]

    Qazi, Masood

    2012-01-01

    This thesis explores the challenges for integrating embedded static random access memory (SRAM) and non-volatile memory-based on ferroelectric capacitor technology-into lowpower integrated circuits. First considered is the ...

  2. Dual-circuit segmented rail phased induction motor

    DOE Patents [OSTI]

    Marder, Barry M. (Albuquerque, NM); Cowan, Jr., Maynard (Albuquerque, NM)

    2002-01-01

    An improved linear motor utilizes two circuits, rather that one circuit and an opposed plate, to gain efficiency. The powered circuit is a flat conductive coil. The opposed segmented rail circuit is either a plurality of similar conductive coils that are shorted, or a plurality of ladders formed of opposed conductive bars connected by a plurality of spaced conductors. In each embodiment, the conductors are preferably cables formed from a plurality of intertwined insulated wires to carry current evenly.

  3. A procedural language for automated analog circuit design 

    E-Print Network [OSTI]

    Macaluso, Edmond Roy

    1984-01-01

    new design system for the automated design of analog integrated circuits is presented. This system provides completely automated layout from a multilevel circuit description. The circuit description may include instances of fixed geomet- ric... Hierarchical Layout Description Languages for IC Design Summary Scope of Thesis Overview of Remainder of Thesis 1 2 4 5 6 g 11 14 15 16 II AUTOMATED ANALOG CIRCUIT DESIGN 18 2. 1 2. 2 2. 3 2. 4 Analog Design Requirements A Prototype System...

  4. TOWARDS A UNIFIED THEORY OF NEOCORTEX: Laminar Cortical Circuits for Vision and Cognition

    E-Print Network [OSTI]

    Grossberg, Stephen

    TOWARDS A UNIFIED THEORY OF NEOCORTEX: Laminar Cortical Circuits for Vision and Cognition Stephen laminar neocortical circuits give rise to biological intelligence. These circuits embody two new and revolutionary computational paradigms: Complementary Computing and Laminar Computing. Circuit properties include

  5. LOW VOLTAGE ANALOG CIRCUITS USING STANDARD CMOS TECHNOLOGY

    E-Print Network [OSTI]

    Rincon-Mora, Gabriel A.

    LOW VOLTAGE ANALOG CIRCUITS USING STANDARD CMOS TECHNOLOGY Phillip E. Allen, Benjamin J. Blalock implies battery operation which favors low voltage and low power circuits. These factors and others have of the magnitudes of the n-channel and p-channel thresholds [4]. This implies that low voltage analog circuits

  6. Galen Sasaki EE 260 University of Hawaii 1 Moore Circuit

    E-Print Network [OSTI]

    Sasaki, Galen H.

    Galen Sasaki EE 260 University of Hawaii 1 Moore Circuit CC SR Input CC Output Galen Sasaki EE 260 University of Hawaii 2 Why is this better than the Mealy Circuit Moore circuits prevent "loops University of Hawaii 3 Example: Loop of Inverters Inv Inv Inv Truth Table In Out 0 1 1 0 Inv Inv Inv 0 0 1

  7. Course Outline Engineer 2MM3 Electrical Circuits & Power

    E-Print Network [OSTI]

    Haykin, Simon

    .ece.mcmaster.ca/~mrhowlader/2mm3/notes.htm Text Book: S.J. Chapman, Electric Machinery Fundamentals, McGraw Hill, Fifth Edition Course Description: Fundamentals of electromechanical energy conversion. Motors and generators. Fundamentals of Magnetic Circuits; 2. Fundamentals of Electrical Circuits, Phasors; 3. Power in AC Circuits; 4

  8. Technique for extending the range of a signal measuring circuit

    DOE Patents [OSTI]

    Chaprnka, Anthony G. (Cockeysville, MD); Sun, Shan C. (Pittsburgh, PA); Vercellotti, Leonard C. (Verona, PA)

    1978-01-01

    An input signal supplied to a signal measuring circuit is either amplified or attenuated as necessary to establish the magnitude of the input signal within the defined dynamic range of the measuring circuit and the output signal developed by the measuring circuit is subsequently readjusted through amplification or attenuation to develop an output signal which corresponds to the magnitude of the initial input signal.

  9. EEE 334 Circuits II (4) [F, S] Course (Catalog) description

    E-Print Network [OSTI]

    Zhang, Junshan

    : EEE334 contributes to engineering science through linear and non-linear circuit analysis, problem Prerequisites by Topic: Circuits I Course Objectives: Application of electric network theory to analysis and design of the fundamental non- linear circuits of transistor electronics. Course Outcomes: 1. Apply

  10. Foundations for a Circuit Complexity Theory of Sensory Processing

    E-Print Network [OSTI]

    Maass, Wolfgang

    with linear or almost linear total wire length. 1 Introduction Circuit complexity theory is a classical area in neuromorphic engineering, especially analog VLSI, and the analysis of neural circuits in biological organisms modules'' (i.e., as gates) in our complexity analysis. #12; plexity measures in traditional circuit

  11. Timed Verification of the Generic Architecture of a Memory Circuit

    E-Print Network [OSTI]

    Encrenaz-Tiphène, Emmanuelle

    #cient linear constraints relating the delays of the internal gates of the circuit to the exter­ nal delays on the reachability analysis of a timed model of the circuit (with additional abstract interpretation techniques [10Timed Verification of the Generic Architecture of a Memory Circuit Using Parametric Timed Automata

  12. Verification of the Generic Architecture of a Memory Circuit

    E-Print Network [OSTI]

    Encrenaz-Tiphène, Emmanuelle

    -Cortadella's parametric method for verifying asynchronous circuits, we formally derive a set of linear constraints of sufficient linear constraints relating the delays of the internal gates of the circuit to the external delays on the reachability analysis of a timed model of the circuit (with additional abstract interpretation techniques [11

  13. Circuit Complexity and Multiplicative Complexity of Boolean Functions

    E-Print Network [OSTI]

    no example of an explicit function requiring super linear circuit size. Moreover, only a few proofs of linear (usually by a long case analysis) that for any circuit computing this function setting some variablesCircuit Complexity and Multiplicative Complexity of Boolean Functions Arist Kojevnikov1

  14. Tamper Resilient Circuits: The Adversary at the Gates Aggelos Kiayias

    E-Print Network [OSTI]

    International Association for Cryptologic Research (IACR)

    Tamper Resilient Circuits: The Adversary at the Gates Aggelos Kiayias Yiannis Tselekounis Abstract We initiate the investigation of gate-tampering attacks against cryptographic circuits. Our model is motivated by the plausibility of tampering directly with circuit gates and by the increasing use of tamper

  15. Improving Performance of an Energy Efficient Hydraulic Circuit

    E-Print Network [OSTI]

    Bahrami, Majid

    Improving Performance of an Energy Efficient Hydraulic Circuit A Thesis Submitted to the College 57 Campus Drive Saskatoon, Saskatchewan, S7N 5A9 Canada #12;ii Abstract Hydraulic circuits with fast costs combined with the demand on high performance has necessitated that hydraulic circuits become more

  16. Integrating Circuit Analyses for Assertion-based Verification

    E-Print Network [OSTI]

    Sen, Alper

    approach on a programmable low-pass filter circuit where cut-off frequency can be digitally controlled. I for their designs besides transient analysis. Therefore, assertions for other analog analyses and their integration, that is digitally-programmable analog circuits, where analog circuit characteristics can be controlled by switching

  17. Switching Cells and Their Implications for Power Electronic Circuits

    E-Print Network [OSTI]

    Tolbert, Leon M.

    Switching Cells and Their Implications for Power Electronic Circuits Leon M. Tolbert1 , Fang Zheng with their implications and applications in power electronic circuits. The concept of switching cells in power electronic cells function as the fundamental elements in power electronic circuits, which cannot be further broken

  18. Potential-induced degradation in solar cells: Electronic structure and diffusion mechanism of sodium in stacking faults of silicon

    SciTech Connect (OSTI)

    Ziebarth, Benedikt Gumbsch, Peter; Mrovec, Matous; Elsässer, Christian

    2014-09-07

    Sodium decorated stacking faults (SFs) were recently identified as the primary cause of potential-induced degradation in silicon (Si) solar-cells due to local electrical short-circuiting of the p-n junctions. In the present study, we investigate these defects by first principles calculations based on density functional theory in order to elucidate their structural, thermodynamic, and electronic properties. Our calculations show that the presence of sodium (Na) atoms leads to a substantial elongation of the Si-Si bonds across the SF, and the coverage and continuity of the Na layer strongly affect the diffusion behavior of Na within the SF. An analysis of the electronic structure reveals that the presence of Na in the SF gives rise to partially occupied defect levels within the Si band gap that participate in electrical conduction along the SF.

  19. Dynamic leakage of faults during differential depletion: Theory, models, and examples from the Niger delta

    SciTech Connect (OSTI)

    Watts, N.L.; Kaars Sijpestein, C.H.; Osai, L.N.; Okoli, O.C. (Shell Petroleum Development Co. of Nigeria, Lagos (Nigeria))

    1991-08-01

    Previous studies of fault sealing have addressed possible fault leakage during secondary migration due to the effects of increased hydrocarbon-water capillary pressure, fracturing, or small-scale incremental fault movements. Of equal importance to production geologists is the failure and leakage of faults during field development due to differential depletion of adjacent fault blocks. This paper examines the unique problems associated with this dynamic leakage of faults. It is theoretically shown that the fault sealing mechanism, and the extent of the seal, directly influences the failure process which in turn results in a variety of favorable and unfavorable effects on field development. The qualitative models give considerable insight into such aspects as oil-column expansion and resaturation losses, interfault block aquifer support (with important implications to material balance calculations), possible leakage or spillage of oil across faults, and potential fault failure during (re)injection projects. Examples of dynamic fault leakage are presented from selected fields of the Niger delta.

  20. Advanced Non-Krylov Subspace Model Order Reduction Techniques for Interconnect Circuits

    E-Print Network [OSTI]

    Yan, Boyuan

    2009-01-01

    Freund. Efficient linear circuit analysis by Pade approxima-for reduced order analysis of linear circuit with multiple

  1. Qualitative reasoning about fault effects in electrical cir-cuits has reached a level of achievement which allows it to

    E-Print Network [OSTI]

    Hamburg,.Universität

    - stance, the FLAME system (Pugh and Snooke 1996) per- forms failure mode and effects analysis (FMEA) is employed for automated FMEA and diagnosis guidelines generation for mechatronic car subsystems

  2. Bridging faults in CMOS circuits which are non-Iddq testable and their effect on delay testing 

    E-Print Network [OSTI]

    Tu, Gao

    1997-01-01

    Bridging defects which occur in CMOS complementary gates (rather than ratioed logic gates) are investigated. Realistic bridging defects are shown to exist which are non-Iddq testable, but which can be deterministically tested using at speed voltage...

  3. An information model for inter-organizational fault Patricia Marcu

    E-Print Network [OSTI]

    in the IT Infrastructure Library (ITIL) [2] and related frameworks in the area of IT service management (ITSM). But since ITIL and the related ITSM frameworks do not consider specific aspects of inter- organizational (fault

  4. Controls on Fault-Hosted Fluid Flow: Preliminary Results from...

    Open Energy Info (EERE)

    Controls on Fault-Hosted Fluid Flow: Preliminary Results from the Coso Geothermal Field, CA Jump to: navigation, search OpenEI Reference LibraryAdd to library Conference...

  5. Robust model-based fault diagnosis for chemical process systems 

    E-Print Network [OSTI]

    Rajaraman, Srinivasan

    2006-08-16

    Fault detection and diagnosis have gained central importance in the chemical process industries over the past decade. This is due to several reasons, one of them being that copious amount of data is available from a large ...

  6. Thermal Waters Along The Konocti Bay Fault Zone, Lake County...

    Open Energy Info (EERE)

    Thermal Waters Along The Konocti Bay Fault Zone, Lake County, California- A Re-Evaluation Jump to: navigation, search OpenEI Reference LibraryAdd to library Journal Article:...

  7. Microgrid Fault Protection Based on Symmetrical and Differential Current Components

    E-Print Network [OSTI]

    Microgrid Fault Protection Based on Symmetrical and Differential Current Components Prepared.........................................................................................8 2. AEP CERTS MICROGRID .........................................................................9 ........................................................................67 #12;3 Index of Figures Figure 1: Schematic representation of the AEP CERTS microgrid

  8. Compatible and Cost-Effective Fault Diagnostic Solutions for...

    Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

    Compatible and Cost-Effective Fault Diagnostic Solutions for Air Handling Unit-Variable Air Volume and Air Handling Unit-Constant Air Volume Systems - 2014 BTO Peer Review...

  9. COMPLETE FAULT ANALYSIS FOR LONG TRANSMISSION LINE USING

    E-Print Network [OSTI]

    sys- tem based approach is described in (Girgis and Johns, 1996) and a phasor measurement unit (PMU Measurement Unit (PMU) are further developed. Previous efforts were aimed at implementing accu- rate fault

  10. Fault Mechanics Earth Structure (2nd Edition), 2004

    E-Print Network [OSTI]

    , and normal faulting is ratio of pore-fluid pressure and lithostatic pressure ( ranges from 0.4 for hydrostatic fluid pressure to 1 for lithostatic fluid pressure) © EarthStructure (2nd ed) 610/25/2010 #12

  11. MODELING AND SIMULATION OF HVAC FAULTS IN ENERGYPLUS

    E-Print Network [OSTI]

    Basarkar, Mangesh

    2013-01-01

    http://www.eia.doe.gov/emeu/cbecs/ EnergyPlus. 2011, http://of HVAC Results in EnergyPlus Mangesh Basarkar, XiufengOF HVAC FAULTS IN ENERGYPLUS Mangesh Basarkar, Xiufeng Pang,

  12. A Low Overhead Fault Tolerant Coherence Protocol for CMP Architectures

    E-Print Network [OSTI]

    Acacio, Manuel

    A Low Overhead Fault Tolerant Coherence Protocol for CMP Architectures Ricardo Fern Murcia SPAIN {r.fernandez,jmgarcia,meacacio}@ditec.um.es Jos´e Duato Dpto. Inform´atica de Sistemas y

  13. Motion and evolution of the Chaochou Fault, Southern Taiwan 

    E-Print Network [OSTI]

    Hassler, Lauren E.

    2005-11-01

    The Chaochou Fault (CCF) is both an important lithologic boundary and a significant topographic feature in the Taiwan orogenic belt. It is the geologic boundary between the Slate Belt to the east, and the Western Foothills to the west. Although...

  14. Recent earthquake sequences at Coso: Evidence for conjugate faulting...

    Open Energy Info (EERE)

    Recent earthquake sequences at Coso: Evidence for conjugate faulting and stress loading near a geothermal field Jump to: navigation, search OpenEI Reference LibraryAdd to library...

  15. Understanding Fault Characteristics And Sediment Depth For Geothermal...

    Open Energy Info (EERE)

    of primarily E-W directed extension along N-NNW striking normal faults. Water well drilling on the eastern slopes of the Wassuk Range, west of the city of Hawthorne, Nevada...

  16. Fault Block Kinematics at a Releasing Stepover of the Eastern...

    Open Energy Info (EERE)

    Nascent Metamorphic Core Complex Citation Christopher J. Pluhar,Robert S. Coe,Jonathan C. Lewis,Francis C. Monastero,Jonathan M.G. Glen. 2006. Fault Block Kinematics at a Releasing...

  17. Non-intrusive fault detection in reciprocating compressors

    E-Print Network [OSTI]

    Schantz, Christopher James

    2011-01-01

    This thesis presents a set of techniques for non-intrusive sensing and fault detection in reciprocating compressors driven by induction motors. The procedures developed here are "non-intrusive" because they rely only on ...

  18. Fusing strategies for the dual-voltage fault

    E-Print Network [OSTI]

    Shrivastava, Rupam, 1981-

    2005-01-01

    This thesis focuses on the 42V - 14V fault in a dual voltage system and discusses the possibility of effective fusing. A simple model for the system had been created from technical documentation. Based on the model and the ...

  19. Fault-Tolerant Quantum Computation with Higher-Dimensional Systems

    E-Print Network [OSTI]

    Daniel Gottesman

    1998-02-02

    Instead of a quantum computer where the fundamental units are 2-dimensional qubits, we can consider a quantum computer made up of d-dimensional systems. There is a straightforward generalization of the class of stabilizer codes to d-dimensional systems, and I will discuss the theory of fault-tolerant computation using such codes. I prove that universal fault-tolerant computation is possible with any higher-dimensional stabilizer code for prime d.

  20. Microstructures and Rheology of a Limestone-Shale Thrust Fault 

    E-Print Network [OSTI]

    Wells, Rachel Kristen

    2011-02-22

    AND RHEOLOGY OF A LIMESTONE-SHALE THRUST FAULT A Thesis by RACHEL KRISTEN WELLS Submitted to the Office of Graduate Studies of Texas A&M University in partial fulfillment of the requirements for the degree of MASTER OF SCIENCE December... 2010 Major Subject: Geology MICROSTRUCTURES AND RHEOLOGY OF A LIMESTONE-SHALE THRUST FAULT A Thesis by RACHEL KRISTEN WELLS Submitted to the Office of Graduate Studies of Texas A&M University in partial fulfillment...

  1. Fault Detection, Diagnostics and Optimmization using BIG Data Analytics 

    E-Print Network [OSTI]

    Bonifay, X.

    2013-01-01

    buildings. Reduce footprint. ESL-IC-13-10-58a Proceedings of the 13th International Conference for Enhanced Building Operations, Montreal, Quebec, October 8-11, 2013 About IFCS ? Headquartered in Quebec, CANADA ? Founded in 1993 ? Y-Y Growth..., Equipment longevity, Occupant comfort ESL-IC-13-10-58a Proceedings of the 13th International Conference for Enhanced Building Operations, Montreal, Quebec, October 8-11, 2013 Fault Detection and Diagnostics - FDD Fault detection and diagnostics (FDD...

  2. Off-fault Damage Associated with a Localized Bend in the North Branch San Gabriel Fault, California 

    E-Print Network [OSTI]

    Becker, Andrew 1987-

    2012-08-15

    , such as bends and steps, are thought to affect earthquake rupture propagation and energy radiation, but the effects are not completely understood. We hypothesize that the rate of accumulation of new damage decreases as fault maturity increases, and damage...

  3. TRIAC/SCR proportional control circuit

    DOE Patents [OSTI]

    Hughes, W.J.

    1999-04-06

    A power controller device is disclosed which uses a voltage-to-frequency converter in conjunction with a zero crossing detector to linearly and proportionally control AC power being supplied to a load. The output of the voltage-to frequency converter controls the ``reset`` input of a R-S flip flop, while an ``0`` crossing detector controls the ``set`` input. The output of the flip flop triggers a monostable multivibrator controlling the SCR or TRIAC firing circuit connected to the load. Logic gates prevent the direct triggering of the multivibrator in the rare instance where the ``reset`` and ``set`` inputs of the flip flop are in coincidence. The control circuit can be supplemented with a control loop, providing compensation for line voltage variations. 9 figs.

  4. Vacuum die attach for integrated circuits

    DOE Patents [OSTI]

    Schmitt, E.H.; Tuckerman, D.B.

    1991-09-10

    A thin film eutectic bond for attaching an integrated circuit die to a circuit substrate is formed by coating at least one bonding surface on the die and substrate with an alloying metal, assembling the die and substrate under compression loading, and heating the assembly to an alloying temperature in a vacuum. A very thin bond, 10 microns or less, which is substantially void free, is produced. These bonds have high reliability, good heat and electrical conduction, and high temperature tolerance. The bonds are formed in a vacuum chamber, using a positioning and loading fixture to compression load the die, and an IR lamp or other heat source. For bonding a silicon die to a silicon substrate, a gold silicon alloy bond is used. Multiple dies can be bonded simultaneously. No scrubbing is required. 1 figure.

  5. A Docking Casette For Printed Circuit Boards

    DOE Patents [OSTI]

    Barringer, Dennis R. (Wallkill, NY); Seminaro, Edward J. (Milton, NY); Toffler, Harold M. (Newburgh, NY)

    2003-08-19

    A docking apparatus for printed circuit boards including a cassette housing, having a housing base, a housing cover and a housing wall, wherein the housing base and the housing wall are disposed relative to each other so as to define a housing cavity for containing a printed circuit board and wherein the housing wall includes a cable opening disposed so as to be communicated with the housing cavity, a linkage mechanism, wherein the linkage mechanism includes an engagement configuration and a disengagement configuration and wherein the linkage mechanism is disposed so as to be associated with the cassette housing and a housing bezel, wherein the housing bezel is disposed relative to the cassette housing so as to be associated with the cable opening.

  6. TRIAC/SCR proportional control circuit

    DOE Patents [OSTI]

    Hughes, Wallace J. (Boston Lake, NY)

    1999-01-01

    A power controller device which uses a voltage-to-frequency converter in conjunction with a zero crossing detector to linearly and proportionally control AC power being supplied to a load. The output of the voltage-to frequency converter controls the "reset" input of a R-S flip flop, while an "0" crossing detector controls the "set" input. The output of the flip flop triggers a monostable multivibrator controlling the SCR or TRIAC firing circuit connected to the load. Logic gates prevent the direct triggering of the multivibrator in the rare instance where the "reset" and "set" inputs of the flip flop are in coincidence. The control circuit can be supplemented with a control loop, providing compensation for line voltage variations.

  7. Quantum Heat Engines Using Superconducting Quantum Circuits

    E-Print Network [OSTI]

    H. T. Quan; Y. D. Wang; Yu-xi Liu; C. P. Sun; Franco Nori

    2006-09-14

    We propose a quantum analog of the internal combustion engine used in most cars. Specifically, we study how to implement the Otto-type quantum heat engine (QHE) with the assistance of a Maxwell's demon. Three steps are required: thermalization, quantum measurement, and quantum feedback controlled by the Maxwell demon. We derive the positive-work condition of this composite QHE. Our QHE can be constructed using superconducting quantum circuits. We explicitly demonstrate the essential role of the demon in this macroscopic QHE.

  8. Base drive and overlap protection circuit

    DOE Patents [OSTI]

    Gritter, David J. (Southfield, MI)

    1983-01-01

    An inverter (34) which provides power to an A. C. machine (28) is controlled by a circuit (36) employing PWM control strategy whereby A. C. power is supplied to the machine at a preselectable frequency and preselectable voltage. This is accomplished by the technique of waveform notching in which the shapes of the notches are varied to determine the average energy content of the overall waveform. Through this arrangement, the operational efficiency of the A. C. machine is optimized. The control circuit includes a microcomputer and memory element which receive various parametric inputs and calculate optimized machine control data signals therefrom. The control data is asynchronously loaded into the inverter through an intermediate buffer (38). A base drive and overlap protection circuit is included to insure that both transistors of a complimentary pair are not conducting at the same time. In its preferred embodiment, the present invention is incorporated within an electric vehicle (10) employing a 144 VDC battery pack (32) and a three-phase induction motor (18).

  9. Fault-tolerant corrector/detector chip for high-speed data processing

    DOE Patents [OSTI]

    Andaleon, D.D.; Napolitano, L.M. Jr.; Redinbo, G.R.; Shreeve, W.O.

    1994-03-01

    An internally fault-tolerant data error detection and correction integrated circuit device and a method of operating same is described. The device functions as a bidirectional data buffer between a 32-bit data processor and the remainder of a data processing system and provides a 32-bit datum with a relatively short eight bits of data-protecting parity. The 32-bits of data by eight bits of parity is partitioned into eight 4-bit nibbles and two 4-bit nibbles, respectively. For data flowing towards the processor the data and parity nibbles are checked in parallel and in a single operation employing a dual orthogonal basis technique. The dual orthogonal basis increase the efficiency of the implementation. Any one of ten (eight data, two parity) nibbles are correctable if erroneous, or two different erroneous nibbles are detectable. For data flowing away from the processor the appropriate parity nibble values are calculated and transmitted to the system along with the data. The device regenerates parity values for data flowing in either direction and compares regenerated to generated parity with a totally self-checking equality checker. As such, the device is self-validating and enabled to both detect and indicate an occurrence of an internal failure. A generalization of the device to protect 64-bit data with 16-bit parity to protect against byte-wide errors is also presented. 8 figures.

  10. Solid-State Fault Current Limiter Development : Design and Testing Update of a 15kV SSCL Power Stack

    SciTech Connect (OSTI)

    Dr. Ram Adapa; Mr. Dante Piccone

    2012-04-30

    ABSTRACT The Solid-State Fault Current Limiter (SSCL) is a promising technology that can be applied to utility power delivery systems to address the problem of increasing fault currents associated with load growth. As demand continues to grow, more power is added to utility system either by increasing generator capacity or by adding distributed generators, resulting in higher available fault currents, often beyond the capabilities of the present infrastructure. The SSCL is power-electronics based equipment designed to work with the present utility system to address this problem. The SSCL monitors the line current and dynamically inserts additional impedance into the line in the event of a fault being detected. The SSCL is based on a modular design and can be configured for 5kV through 69kV systems at nominal current ratings of 1000A to 4000A. Results and Findings This report provides the final test results on the development of 15kV class SSCL single phase power stack. The scope of work included the design of the modular standard building block sub-assemblies, the design and manufacture of the power stack and the testing of the power stack for the key functional tests of continuous current capability and fault current limiting action. Challenges and Objectives Solid-State Current Limiter technology impacts a wide spectrum of utility engineering and operating personnel. It addresses the problems associated with load growth both at Transmission and Distribution class networks. The design concept is pioneering in terms of developing the most efficient and compact power electronics equipment for utility use. The initial test results of the standard building blocks are promising. The independent laboratory tests of the power stack are promising. However the complete 3 phase system needs rigorous testing for performance and reliability. Applications, Values, and Use The SSCL is an intelligent power-electronics device which is modular in design and can provide current limiting or current interrupting capabilities. It can be applied to variety of applications from distribution class to transmission class power delivery grids and networks. It can also be applied to single major commercial and industrial loads and distributed generator supplies. The active switching of devices can be further utilized for protection of substation transformers. The stress on the system can be reduced substantially improving the life of the power system. It minimizes the voltage sag by speedy elimination of heavy fault currents and promises to be an important element of the utility power system. DOE Perspective This development effort is now focused on a 15kV system. This project will help mitigate the challenges of increasing available fault current. DOE has made a major contribution in providing a cost effective SSCL designed to integrate seamlessly into the Transmission and Distribution networks of today and the future. Approach SSCL development program for a 69kV SSCL was initiated which included the use of the Super GTO advanced semiconductor device which won the 2007 R&D100 Award. In the beginning, steps were identified to accomplish the economically viable design of a 69kV class Solid State Current Limiter that is extremely reliable, cost effective, and compact enough to be applied in urban transmission. The prime thrust in design and development was to encompass the 1000A and the 3000A ratings and provide a modular design to cover the wide range of applications. The focus of the project was then shifted to a 15kV class SSCL. The specifications for the 15kV power stack are reviewed. The design changes integrated into the 15kV power stack are discussed. In this Technical Update the complete project is summarized followed by a detailed test report. The power stack independent high voltage laboratory test requirements and results are presented. Keywords Solid State Current Limiter, SSCL, Fault Current Limiter, Fault Current Controller, Power electronics controller, Intelligent power-electronics Device, IED

  11. Fault Oblivious eXascale Whitepaper

    SciTech Connect (OSTI)

    Minnich, Ronald G.; Janssen, Curtis L.; Krishnamoorthy, Sriram; Marquez, Andres; Gokhale, Maya; Sadayappan, Ponnuswamy; Van Hensbergen, Eric; McKie, Jim; Appavoo, Jonathan

    2011-06-01

    In this paper we present a software system which supports dynamic, irregular, adaptive applications. Data objects are created and structured in a hierarchical manner, with replication as needed to provide a high degree of redundancy. The data objects can contain data, code, tasks (work descriptors with references to data, code, and other tasks) and higher level structures such as work queues. The higher level structures benefit from the properties of the data objects: redundant storage to support resiliency in the face of hardware failure; hierarchical structure to optimize use of the HPC system; and a presence of object names, available in the per-user file system name space, which allows any application, not just specially written HPC applications, to make use of the data even while it is on the HPC system. Our use of hierarchy will make the runtime scalable to very large systems. Our use of redundancy will allow programs to be written in a fault-oblivious manner, eliminating the need for system-level checkpointing. Putting data object names into the file system name space allows for interactive use of the system by users. With this approach, we will be able to finally leave the batch era behind, a half-century after the invention of time sharing. We will be able to stop bounding program through- put by the checkpoint interval. Application data will be accessible at any time, not hidden behind opaque 128-bit pointers or MPI ranks, but given a name that is visible everywhere. Programmers can stop laying out data, and thinking about where the data is, and the code is, and the nodes are, and stick with the problem of what the application is supposed to be doing. This work, if it succeeds, will enable scientific computing to scale to the next generation of machines.

  12. Capacitive charge generation apparatus and method for testing circuits

    DOE Patents [OSTI]

    Cole, Jr., Edward I. (Albuquerque, NM); Peterson, Kenneth A. (Albuquerque, NM); Barton, Daniel L. (Albuquerque, NM)

    1998-01-01

    An electron beam apparatus and method for testing a circuit. The electron beam apparatus comprises an electron beam incident on an outer surface of an insulating layer overlying one or more electrical conductors of the circuit for generating a time varying or alternating current electrical potential on the surface; and a measurement unit connected to the circuit for measuring an electrical signal capacitively coupled to the electrical conductors to identify and map a conduction state of each of the electrical conductors, with or without an electrical bias signal being applied to the circuit. The electron beam apparatus can further include a secondary electron detector for forming a secondary electron image for registration with a map of the conduction state of the electrical conductors. The apparatus and method are useful for failure analysis or qualification testing to determine the presence of any open-circuits or short-circuits, and to verify the continuity or integrity of electrical conductors buried below an insulating layer thickness of 1-100 .mu.m or more without damaging or breaking down the insulating layer. The types of electrical circuits that can be tested include integrated circuits, multi-chip modules, printed circuit boards and flexible printed circuits.

  13. Capacitive charge generation apparatus and method for testing circuits

    DOE Patents [OSTI]

    Cole, E.I. Jr.; Peterson, K.A.; Barton, D.L.

    1998-07-14

    An electron beam apparatus and method for testing a circuit are disclosed. The electron beam apparatus comprises an electron beam incident on an outer surface of an insulating layer overlying one or more electrical conductors of the circuit for generating a time varying or alternating current electrical potential on the surface; and a measurement unit connected to the circuit for measuring an electrical signal capacitively coupled to the electrical conductors to identify and map a conduction state of each of the electrical conductors, with or without an electrical bias signal being applied to the circuit. The electron beam apparatus can further include a secondary electron detector for forming a secondary electron image for registration with a map of the conduction state of the electrical conductors. The apparatus and method are useful for failure analysis or qualification testing to determine the presence of any open-circuits or short-circuits, and to verify the continuity or integrity of electrical conductors buried below an insulating layer thickness of 1-100 {micro}m or more without damaging or breaking down the insulating layer. The types of electrical circuits that can be tested include integrated circuits, multi-chip modules, printed circuit boards and flexible printed circuits. 7 figs.

  14. Constant-Optimized Quantum Circuits for Modular Multiplication and Exponentiation

    E-Print Network [OSTI]

    Igor L. Markov; Mehdi Saeedi

    2015-04-02

    Reversible circuits for modular multiplication $Cx$%$M$ with $xcircuit depth rather than actual values, producing fairly large circuits not optimized for specific $C$ and $M$ values. In this work, we develop such optimizations in a bottom-up fashion, starting with most convenient $C$ values. When zero-initialized ancilla registers are available, we reduce the search for compact circuits to a shortest-path problem. Some of our modular-multiplication circuits are asymptotically smaller than previous constructions, but worst-case bounds and average sizes remain $\\Theta(n^2)$. In the context of modular exponentiation, we offer several constant-factor improvements, as well as an improvement by a constant additive term that is significant for few-qubit circuits arising in ongoing laboratory experiments with Shor's algorithm.

  15. Circuit quantum electrodynamics with a nonlinear resonator

    E-Print Network [OSTI]

    P. Bertet; F. R. Ong; M. Boissonneault; A. Bolduc; F. Mallet; A. C. Doherty; A. Blais; D. Vion; D. Esteve

    2011-11-02

    One of the most studied model systems in quantum optics is a two-level atom strongly coupled to a single mode of the electromagnetic field stored in a cavity, a research field named cavity quantum electrodynamics or CQED. CQED has recently received renewed attention due to its implementation with superconducting artificial atoms and coplanar resonators in the so-called circuit quantum electrodynamics (cQED) architecture. In cQED, the couplings can be much stronger than in CQED due to the design flexibility of superconducting circuits and to the enhanced field confinement in one-dimensional cavities. This enabled the realization of fundamental quantum physics and quantum information processing experiments with a degree of control comparable to that obtained in CQED. The purpose of this chapter is to investigate the situation where the resonator to which the atom is coupled is made nonlinear with a Kerr-type nonlinearity, causing its energy levels to be nonequidistant. The system is then described by a nonlinear Jaynes-Cummings Hamiltonian. This considerably enriches the physics since a pumped nonlinear resonator displays bistability, parametric amplification, and squeezing. The interplay of strong coupling and these nonlinear effects constitutes a novel model system for quantum optics that can be implemented experimentally with superconducting circuits. This chapter is organized as follows. In a first section we present the system consisting of a superconducting Kerr nonlinear resonator strongly coupled to a transmon qubit. In the second section, we describe the response of the sole nonlinear resonator to an external drive. In the third section, we show how the resonator bistability can be used to perform a high-fidelity readout of the transmon qubit. In the last section, we investigate the quantum backaction exerted by the intracavity field on the qubit.

  16. COMBINATIONAL-CIRCUITCOMBINATIONAL CIRCUIT BUILDING BLOCKS

    E-Print Network [OSTI]

    Maeng, Seungryoul

    ) + w1 · f(1,w2, ... ,wn) The expansion can be done in terms of any of the n variables f t 11 11 wwMux)p ( ) multiplexer demultiplexer #12;2-to-1 Mux (Selector)2 to 1 Mux (Selector) 4 f s w0 w1 0 1 0 1 fs w0 w1 f=s'w0+sw1 (a) Graphical symbol 1 (b) Truth table 1 w1 w0 w0 fs w1 w1 f s (c) Sum-of-products circuit (d

  17. Numerical modeling of gas migration into and through faulted sand reservoirs in Pabst Field (Main Pass East Block 259), northern Gulf of Mexico 

    E-Print Network [OSTI]

    Li, Yuqian

    2006-08-16

    allow gas communication among the sands. Meanwhile, three fault families break up the three sands into numerous compartments. A primary fault and large synthetic and antithetic faults act as gas migration pathways: the synthetic and antithetic faults...

  18. Defect site prediction based upon statistical analysis of fault signatures 

    E-Print Network [OSTI]

    Trinka, Michael Robert

    2004-09-30

    Good failure analysis is the ability to determine the site of a circuit defect quickly and accurately. We propose a method for defect site prediction that is based on a site's probability of excitation, making no assumptions about the type...

  19. Health and Safety Guide for Home Performance Contractors

    E-Print Network [OSTI]

    Stratton, Chris

    2014-01-01

    Always plug heat tape into a GFCI (ground-fault circuit-Environmental tobacco smoke GFCI – Ground fault circuit

  20. An introduction to Fault-tolerant Quantum Computing

    E-Print Network [OSTI]

    Alexandru Paler; Simon J. Devitt

    2015-08-15

    In this paper we provide a basic introduction of the core ideas and theories surrounding fault-tolerant quantum computation. These concepts underly the theoretical framework of large-scale quantum computation and communications and are the driving force for many recent experimental efforts to construct small to medium sized arrays of controllable quantum bits. We examine the basic principals of redundant quantum encoding, required to protect quantum bits from errors generated from both imprecise control and environmental interactions and then examine the principals of fault-tolerance from largely a classical framework. As quantum fault-tolerance essentially is avoiding the uncontrollable cascade of errors caused by the interaction of quantum-bits, these concepts can be directly mapped to quantum information.

  1. Impact of Installation Faults on Heat Pump Performance

    SciTech Connect (OSTI)

    Hourahan, Mr. Glenn [Air Conditioning Contractors of America, Arlington, VA; Baxter, Van D [ORNL

    2015-01-01

    Numerous studies and surveys indicate that typically-installed HVAC equipment operate inefficiently and waste considerable energy due to varied installation errors (faults) such as improper refrigerant charge, incorrect airflow, oversized equipment, and leaky ducts. This article summarizes the results of a large United States (U.S.) experimental/analytical study (U.S. contribution to IEA HPP Annex 36) of the impact that different faults have on the performance of an air-source heat pump (ASHP) in a typical U.S. single-family house. It combines building effects, equipment effects, and climate effects in an evaluation of the faults impact on seasonal energy consumption through simulations of the house/ASHP pump system.

  2. Integrated Circuit Implementation for a GaN HFETs Driver Circuit

    E-Print Network [OSTI]

    Bakos, Jason D.

    @engr.sc.edu Abstract- The paper presents the design of an integrated circuit (IC) for a 10MHz low power-loss driver exploit the advantages of GaN devices, such as superior switching speed and operation in high-power the authors focus on the design of the IC and present preliminary results and considerations. The driver

  3. 6.002 Circuits and Electronics, Fall 2000

    E-Print Network [OSTI]

    Lang, Jeffrey (Jeffrey H.)

    Fundamentals of the lumped circuit abstraction. Resistive elements and networks; independent and dependent sources; switches and MOS devices; digital abstraction; amplifiers; and energy storage elements. Dynamics of first- ...

  4. Safety and performance enhancement circuit for primary explosive detonators

    DOE Patents [OSTI]

    Davis, Ronald W. (Tracy, CA)

    2006-04-04

    A safety and performance enhancement arrangement for primary explosive detonators. This arrangement involves a circuit containing an energy storage capacitor and preset self-trigger to protect the primary explosive detonator from electrostatic discharge (ESD). The circuit does not discharge into the detonator until a sufficient level of charge is acquired on the capacitor. The circuit parameters are designed so that normal ESD environments cannot charge the protection circuit to a level to achieve discharge. When functioned, the performance of the detonator is also improved because of the close coupling of the stored energy.

  5. 6.012 Microelectronic Devices and Circuits, Spring 2003

    E-Print Network [OSTI]

    Del Alamo, Jesus

    Modeling of microelectronic devices, and basic microelectronic circuit analysis and design. Physical electronics of semiconductor junction and MOS devices. Relation of electrical behavior to internal physical processes; ...

  6. Laser Micromachining of Active and Passive Photonic Integrated Circuits

    E-Print Network [OSTI]

    Cho, Seong-Ho

    2006-06-28

    This thesis describes the development of advanced laser resonators and applications of laserinduced micromachining for photonic circuit fabrication. Two major advantages of laserinduced micromachining are direct patterning ...

  7. Design for manufacturability with regular fabrics in digital integrated circuits

    E-Print Network [OSTI]

    Gazor, Mehdi (Seyed Mehdi)

    2005-01-01

    Integrated circuit design is limited by manufacturability. As devices scale down, sensitivity to process variation increases dramatically, making design for manufacturability a critical concern. Designers must identify the ...

  8. Designer gene circuits for basic science, engineering, and medicine /

    E-Print Network [OSTI]

    Prindle, Arthur

    2014-01-01

    Programmable Probiotics . . . . . . . . . . .Chapter 5 Programmable Probiotics: Gene circuit chaperonesFigure 5.1: PROP-Z probiotics for noninvasive cancer

  9. DSOPilot project Automatic receipt of short circuiting indicators...

    Open Energy Info (EERE)

    DSOPilot project Automatic receipt of short circuiting indicators (Smart Grid Project) Jump to: navigation, search Project Name DSOPilot project Automatic receipt of short...

  10. "Hardware Verification for Arithmetic Circuits" Michael Shliselberg, Jordan Kaplan

    E-Print Network [OSTI]

    Mountziaris, T. J.

    "Hardware Verification for Arithmetic Circuits" Michael Shliselberg, Jordan Kaplan Professor Maciej Ciesielski Our research pertains to finding either new or more efficient methods of hardware verification

  11. Multi-fault Tolerance for Cartesian Data Distributions

    SciTech Connect (OSTI)

    Ali, Nawab; Krishnamoorthy, Sriram; Halappanavar, Mahantesh; Daily, Jeffrey A.

    2013-06-01

    Faults are expected to play an increasingly important role in how algorithms and applications are designed to run on future extreme-scale sys- tems. Algorithm-based fault tolerance (ABFT) is a promising approach that involves modications to the algorithm to recover from faults with lower over- heads than replicated storage and a signicant reduction in lost work compared to checkpoint-restart techniques. Fault-tolerant linear algebra (FTLA) algo- rithms employ additional processors that store parities along the dimensions of a matrix to tolerate multiple, simultaneous faults. Existing approaches as- sume regular data distributions (blocked or block-cyclic) with the failures of each data block being independent. To match the characteristics of failures on parallel computers, we extend these approaches to mapping parity blocks in several important ways. First, we handle parity computation for generalized Cartesian data distributions with each processor holding arbitrary subsets of blocks in a Cartesian-distributed array. Second, techniques to handle corre- lated failures, i.e., multiple processors that can be expected to fail together, are presented. Third, we handle the colocation of parity blocks with the data blocks and do not require them to be on additional processors. Several al- ternative approaches, based on graph matching, are presented that attempt to balance the memory overhead on processors while guaranteeing the same fault tolerance properties as existing approaches that assume independent fail- ures on regular blocked data distributions. The evaluation of these algorithms demonstrates that the additional desirable properties are provided by the pro- posed approach with minimal overhead.

  12. Sedimentation Rates Test Models of Oceanic Detachment Faulting

    E-Print Network [OSTI]

    Parnell-Turner, Ross; Cann, Johnson R.; Smith, Deborah K.; Schouten, Hans; Yoerger, Dana; Palmiotto, Camilla; Zheleznov, Alexei; Bai, Hailong

    2014-10-23

    .R., Tolstoy, M., Dziak, R.P., Fox, C.G. & Smith, D.K., 2002. Aftershock 286 sequences in the mid-ocean ridge environment: an analysis using hydroacoustic data. 287 Tectonophysics, 354(1-2), 49–70. 288 Buck, W. R., 1988. Flexural Rotation of Normal Faults... Dick, H.J.B., Smith, D.K., Cann, J.R., Schouten, H., Marschall, H., Parnell-Turner, R.E. 313 & Yoerger, D., 2013. Crustal Heterogeneity and Stratigraphy on the Mid-Atlantic 314 PARNELL-TURNER ET AL.: SEDIMENTATION AND DETACHMENT FAULTS 16...

  13. Interseismic strain accumulation and the earthquake potential on the southern San Andreas fault system

    E-Print Network [OSTI]

    Fialko, Y

    2006-01-01

    lat- ter would imply subsidence to the east of the fault.indicate uplift, rather subsidence, to the east of the faultlikely involves ground subsidence to the west of the fault.

  14. A Survey of NASA and Military Standards on Fault Tolerance and Reliability Applied to Robotics

    E-Print Network [OSTI]

    Rice University - Center for Cooperative Autonomous Robots for Hazardous Environments

    A Survey of NASA and Military Standards on Fault Tolerance and Reliability Applied to Robotics of relevant Military and NASA standards for reliability and fault toler­ ance is included. 1 Introduction

  15. The dynamics of oceanic transform faults : constraints from geophysical, geochemical, and geodynamical modeling

    E-Print Network [OSTI]

    Gregg, Patricia Michelle Marie

    2008-01-01

    Segmentation and crustal accretion at oceanic transform fault systems are investigated through a combination of geophysical data analysis and geodynamical and geochemical modeling. Chapter 1 examines the effect of fault ...

  16. A methodology for experimentally verifying simulation models for distribution transformer internal faults 

    E-Print Network [OSTI]

    Palmer-Buckle, Peter

    1999-01-01

    Internal winding faults comprise 70-80% of modem transformer breakdown. In this era of deregulation, this phenomenon is likely to increase since loading transformers to their optimum capacity is becoming normal practice. These internal faults result...

  17. Simulation and Validation of Vapor Compression System Faults and Start-up/Shut-down Transients 

    E-Print Network [OSTI]

    Ayyagari, Balakrishna

    2012-10-19

    as vapor compression system faults. This thesis addresses these concerns and enhances the existing modeling library to capture the transients related to the above mentioned conditions. In this thesis, the various faults occurring in a vapor compressor...

  18. Observations on Faults and Associated Permeability Structures in Hydrogeologic Units at the Nevada Test Site

    SciTech Connect (OSTI)

    Prothro, Lance B.; Drellack, Sigmund L.; Haugstad, Dawn N.; Huckins-Gang, Heather E.; Townsend, Margaret J.

    2009-03-30

    Observational data on Nevada Test Site (NTS) faults were gathered from a variety of sources, including surface and tunnel exposures, core samples, geophysical logs, and down-hole cameras. These data show that NTS fault characteristics and fault zone permeability structures are similar to those of faults studied in other regions. Faults at the NTS form complex and heterogeneous fault zones with flow properties that vary in both space and time. Flow property variability within fault zones can be broken down into four major components that allow for the development of a simplified, first approximation model of NTS fault zones. This conceptual model can be used as a general guide during development and evaluation of groundwater flow and contaminate transport models at the NTS.

  19. Comparative analysis of electrical and mechanical fault signatures in induction motors 

    E-Print Network [OSTI]

    Venugopal, Arvind Madabushi

    2005-02-17

    This research deals with the comparison of fault signatures in induction motors. The primary objective is to study and analyze the similarities in the electrical and mechanical fault signatures, and to determine the ...

  20. Fault Current Issues for Market Driven Power Systems with Distributed Generation

    E-Print Network [OSTI]

    1 Fault Current Issues for Market Driven Power Systems with Distributed Generation Natthaphob of installing distributed generation (DG) to electric power systems. The proliferation of new generators creates Terms--Distributed / dispersed generation, power distri- bution, power system protection, fault

  1. ADECENTRALIZED APPROACH TOWARDS AUTONOMOUS FAULT DETECTION IN WIRELESS STRUCTURAL HEALTH MONITORING SYSTEMS

    E-Print Network [OSTI]

    Paris-Sud XI, Université de

    ADECENTRALIZED APPROACH TOWARDS AUTONOMOUS FAULT DETECTION IN WIRELESS STRUCTURAL HEALTH MONITORING structural health monitoring (SHM) systems may reduce the monitoring quality and, if remaining undetected : Autonomous fault detection, structural health monitoring, wireless sensor networks, smart sensors, analytical

  2. The structure and evolution of small-displacement strike-slip faults in porous sandstone 

    E-Print Network [OSTI]

    Schafer, Kirk Wyatt

    2002-01-01

    The early-evolution of fault structure is inferred from analysis of detailed maps of portions of strike-slip faults with uniform displacements ranging from mm to decimeter in porous quartzose sandstone. Emphasis is on ...

  3. Fault tree analysis of commonly occurring medication errors and methods to reduce them 

    E-Print Network [OSTI]

    Cherian, Sandhya Mary

    1994-01-01

    -depth analysis of over two hundred actual medication error incidents. These errors were then classified according to type, in an attempt at deriving a generalized fault tree for the medication delivery system that contributed to errors. This generalized fault...

  4. HEAT AND MASS TRANSFER IN A FAULT-CONTROLLED GEOTHERMAL RESERVOIR CHARGED AT CONSTANT PRESSURE

    E-Print Network [OSTI]

    Goyal, K.P.

    2013-01-01

    from the natural geothermal gradient ~T /L A quantitativegradients in a fault-controlled liquid dominated geothermalgradients in the fault-aquifer system. DEVELOPMENT OF CONCEPTUAL MODEL Studies of liquid-dominated geothermal

  5. Initiation propagation and termination of elastodynamic ruptures associated with segmentation of faults and shaking

    E-Print Network [OSTI]

    Shaw, Bruce E.

    Initiation propagation and termination of elastodynamic ruptures associated with segmentation the initiation, propagation, and termination of ruptures and their relationship to fault geometry and shaking of terminations near fault ends; and persistent propagation directivity effects. Taking advantage of long

  6. Dynamical System Analysis and Forecasting of Deformation Produced by an Earthquake Fault

    E-Print Network [OSTI]

    Ben-Zion, Yehuda

    is characterized by a set of parameters that describe the dynamics, rheology, property disorder, and fault geometry of an earthquake fault is not feasible at present because the governing physical laws, geometric and structural

  7. Finite element analysis of elastic interaction of two en echelon overlapping faults 

    E-Print Network [OSTI]

    Leem, Junghun

    1995-01-01

    on the faults. Attention is focuses on the role of variable fault spacing and overlap for constant far-field compressive principal stresses. The linear elastic, isotropic, plane strain, finite element analyses are obtained. The basic modeling approach...

  8. Microfracture fabric of the Punchbowl fault zone, San Andreas System, California 

    E-Print Network [OSTI]

    Wilson, Jennifer Elizabeth

    1999-01-01

    Andreas system. Open, healed, and sealed microfractures were analyzed with respect to density and orientation as a function of distance from the fault. Microfracture density decreases with distance from the fault core to background levels at approximately...

  9. Power system fault analysis based on intelligent techniques and intelligent electronic device data 

    E-Print Network [OSTI]

    Luo, Xu

    2007-09-17

    This dissertation has focused on automated power system fault analysis. New contributions to fault section estimation, protection system performance evaluation and power system/protection system interactive simulation have ...

  10. Formal Modelling and Analysis of Business Information Applications with Fault Tolerant Middleware

    E-Print Network [OSTI]

    Southampton, University of

    COMPUTING SCIENCE Formal Modelling and Analysis of Business Information Applications with Fault to prove properties of models of business protocols and expose weaknesses of certain middleware.. Formal Modelling and Analysis of Business Information Applications with Fault Tolerant Middleware [By] J

  11. On strong fault tolerance (or strong Menger-connectivity) of multicomputer networks 

    E-Print Network [OSTI]

    Oh, Eunseuk

    2004-11-15

    As the size of networks increases continuously, dealing with networks with faulty nodes becomes unavoidable. In this dissertation, we introduce a new measure for network fault tolerance, the strong fault tolerance (or ...

  12. Hydraulic actuator for an electric circuit breaker

    DOE Patents [OSTI]

    Imam, Imdad (Colonie, NY)

    1983-01-01

    This actuator comprises a fluid motor having a piston, a breaker-opening space at one side of the piston, and a breaker-closing space at its opposite side. An accumulator freely communicates with the breaker-opening space for supplying pressurized fluid thereto during a circuit breaker opening operation. The breaker-opening space and the breaker-closing space are connected by an impeded flow passage. A pilot valve opens to allow the pressurized liquid in the breaker-closing space to flow to a back chamber of a normally closed main valve to cause the main valve to be opened during a circuit breaker opening operation to release the pressurized liquid from the breaker-closing space. An impeded passage affords communication between the back chamber and a sump located on the opposite side of the main valve from the back chamber. The pilot valve and impeded passage allow rapid opening of the main valve with pressurized liquid from the breaker closing side of the piston.

  13. Hydraulic actuator for an electric circuit breaker

    DOE Patents [OSTI]

    Imam, I.

    1983-05-17

    This actuator comprises a fluid motor having a piston, a breaker-opening space at one side of the piston, and a breaker-closing space at its opposite side. An accumulator freely communicates with the breaker-opening space for supplying pressurized fluid thereto during a circuit breaker opening operation. The breaker-opening space and the breaker-closing space are connected by an impeded flow passage. A pilot valve opens to allow the pressurized liquid in the breaker-closing space to flow to a back chamber of a normally closed main valve to cause the main valve to be opened during a circuit breaker opening operation to release the pressurized liquid from the breaker-closing space. An impeded passage affords communication between the back chamber and a sump located on the opposite side of the main valve from the back chamber. The pilot valve and impeded passage allow rapid opening of the main valve with pressurized liquid from the breaker closing side of the piston. 3 figs.

  14. A Methodology and Tool Support for the Design and Evaluation of Fault Tolerant, Distributed Embedded Systems

    E-Print Network [OSTI]

    McKelvin, Jr., Mark Lee

    2011-01-01

    Complexity of Embedded Systems . . . . . . . . . . . . . . .Fault Tolerant Design of Distributed Embedded Systems DesignMethodologies for Embedded Systems . . . . . . . . . . . .

  15. Project EARTH-13-SHELLJC1: Polygonal faults and de-watering of mudrocks during early burial

    E-Print Network [OSTI]

    Henderson, Gideon

    Geology. 28, 1593-1610. Goulty, N.J. 2008. Geomechanics of polygonal fault systems: a review. Petroleum

  16. Numerical Simulation of Fault Zone Guided Waves: Accuracy and 3-D Effects

    E-Print Network [OSTI]

    Ben-Zion, Yehuda

    seismic velocity. When sources are located in or close to these low-velocity zones, guided seismic head for seismic fault zone head and trapped waves. Fault zone head waves propagate along material discontinuity Pure and Applied Geophysics #12;traveling inside low velocity fault zone layers with dispersive

  17. An Empirical Study on Testing and Fault Tolerance for Software Reliability Engineering

    E-Print Network [OSTI]

    Lyu, Michael R.

    An Empirical Study on Testing and Fault Tolerance for Software Reliability Engineering Michael R University of Hong Kong {lyu, zbhuang, samsze, xcai}@cse.cuhk.edu.hk Abstract Software testing and software the effectiveness of software testing and software fault tolerance, mutants were created by injecting real faults

  18. Oil and Gas CDT Bots in Rocks: Intelligent Rock Deformation for Fault Rock

    E-Print Network [OSTI]

    Henderson, Gideon

    Heriot-Watt University, Institute of Petroleum Engineering Supervisory Team · Dr Helen Lewis, Heriot://www.pet.hw.ac.uk/staff-directory/jimsomerville.htm Key Words Nano/Micro sensors; faults; fault zones; geomechanics; rock mechanics; rock deformation-deformed equivalent, a different lab-deformed example and a geomechanical simulation of a fault zone showing permanent

  19. Detection and extraction of fault surfaces in 3D seismic data Israel Cohen1

    E-Print Network [OSTI]

    Cohen, Israel

    for seismic interpretation. INTRODUCTION Fault surfaces are common subterranean structures that are asso that are unrelated to faults. Furthermore, creating a consistent geological interpretation from large 3D-seismicDetection and extraction of fault surfaces in 3D seismic data Israel Cohen1 , Nicholas Coult2

  20. Measuring radon flux across active faults: Relevance of excavating and possibility of satellite discharges

    E-Print Network [OSTI]

    Klinger, Yann

    Measuring radon flux across active faults: Relevance of excavating and possibility of satellite January 2010 Keywords: Exhalation flux Radon-222 Carbon dioxide Faults Earthquake Trench a b s t r a c on the Xidatan segment of the Kunlun Fault, Qinghai Province, China, using measurement of the radon- 222

  1. Resistive Bridge Fault Model Evolution From Conventional to Ultra Deep Submicron Technologies

    E-Print Network [OSTI]

    Polian, Ilia

    Resistive Bridge Fault Model Evolution From Conventional to Ultra Deep Submicron Technologies Ilia three resistive bridging fault models valid for dif- ferent CMOS technologies. The models. The second model is obtained by fitting SPICE data. The third resistive bridging fault model uses Berkeley

  2. Are stress distributions along faults the signature of asperity squeeze? J. Schmittbuhl,1

    E-Print Network [OSTI]

    Schmittbuhl, Jean

    Are stress distributions along faults the signature of asperity squeeze? J. Schmittbuhl,1 G of the stress field along faults and test our model in the case of the Nojima fault, Japan where unique estimates of the absolute stress field have been obtained. The model consists of two parts: an up

  3. Recommendations for CSM and Riso Ground Fault Detector Trip Jack Flicker and Jay Johnson

    E-Print Network [OSTI]

    " in the ground fault ground fault fuse.. As a result of this discovery, the Solar America Board for Codes and Standards identified a number of alternatives to ground fault fuses, but these technologies have limited on rooftop systems, the resulting fire can burn down the building and put occupants' lives at risk. Further

  4. Compiler-directed Program-fault Coverage for Highly Available Java Internet Services

    E-Print Network [OSTI]

    Martin, Richard P.

    Haverford, PA 19041 Abstract: We present a new approach that uses compiler- directed fault-injection appli- cation code in two ways: to direct fault injection to occur at appropriate points during analyses to direct fault injection and measure the resulting coverage of recovery code. Our technique

  5. A conceptual model for the origin of fault damage zone structures in high-porosity sandstone

    E-Print Network [OSTI]

    Cowie, Patience

    A conceptual model for the origin of fault damage zone structures in high-porosity sandstone Zoe K-porosity sandstones. Damage zone deformation has been particularly well constrained for two 4-km-long normal faults formed in the Navajo Sandstone of central Utah, USA. For these faults the width of the damage zone

  6. Yield Modeling and Analysis of a Clockless Asynchronous Wave Pipeline with Pulse Faults

    E-Print Network [OSTI]

    Ayers, Joseph

    Yield Modeling and Analysis of a Clockless Asynchronous Wave Pipeline with Pulse Faults T. Feng fault model and its modeling and analysis methods in a clockless asynchronous wave pipeline fault rate model for establishing a sound theoretical foundation for clockless wave pipeline design

  7. Modeling the heterogeneous hydraulic properties of faults using constraints from reservoir-induced

    E-Print Network [OSTI]

    Cowie, Patience

    Modeling the heterogeneous hydraulic properties of faults using constraints from reservoir the damage zone surrounding faults. The Ac¸u dam is a 34 m high earth-filled dam constructed in 1983 pattern of earthquake clustering and migration that suggests heterogeneous fault zone hydraulic properties

  8. Fault-Tolerant Queries over Sensor Data Iosif Lazaridis1

    E-Print Network [OSTI]

    Venkatasubramanian, Nalini

    -generated values in the presence of faults. Small sensors are fragile, have fi- nite energy and memory demon- strate the good performance of FATE-CSQ compared to competing protocols with realistic simulation, thus im- proving reaction times, (iii) preserving the crucial re- sources of wireless bandwidth

  9. RIS-M-2326 FAULT TREE AND CAUSE CONSEQUENCE ANALYSIS

    E-Print Network [OSTI]

    and control, nuclear reactor safety systems and aircraft landing systems. For systems of failure in operations. For example a nuclear reactor shutdown system should fail at a rate which Abstract. A theory underlying application of automatic fault tree analysis to computer programs

  10. IEEE TRANSACTION ON COMPUTERS 1 Adaptive Fault Management of Parallel

    E-Print Network [OSTI]

    Lan, Zhiling

    of high performance computing (HPC) continues to grow, application fault resilience becomes crucial- tions, High performance computing, Large-scale systems. I. INTRODUCTION IN the field of high performance Performance Computing Zhiling Lan, Member, IEEE, and Yawei Li, Student Member, IEEE Abstract--As the scale

  11. Experimental and computational studies on stacking faults in zinc titanate

    SciTech Connect (OSTI)

    Sun, W.; Ageh, V.; Mohseni, H.; Scharf, T. W. E-mail: Jincheng.Du@unt.edu; Du, J. E-mail: Jincheng.Du@unt.edu

    2014-06-16

    Zinc titanate (ZnTiO{sub 3}) thin films grown by atomic layer deposition with ilmenite structure have recently been identified as an excellent solid lubricant, where low interfacial shear and friction are achieved due to intrafilm shear velocity accommodation in sliding contacts. In this Letter, high resolution transmission electron microscopy with electron diffraction revealed that extensive stacking faults are present on ZnTiO{sub 3} textured (104) planes. These growth stacking faults serve as a pathway for dislocations to glide parallel to the sliding direction and hence achieve low interfacial shear/friction. Generalized stacking fault energy plots also known as ?-surfaces were computed for the (104) surface of ZnTiO{sub 3} using energy minimization method with classical effective partial charge potential and verified by using density functional theory first principles calculations for stacking fault energies along certain directions. These two are in qualitative agreement but classical simulations generally overestimate the energies. In addition, the lowest energy path was determined to be along the [451{sup ¯}] direction and the most favorable glide system is (104) ?451{sup ¯}? that is responsible for the experimentally observed sliding-induced ductility.

  12. Sensor Fault Detection in Power Plants Andrew Kusiak1

    E-Print Network [OSTI]

    Kusiak, Andrew

    Sensor Fault Detection in Power Plants Andrew Kusiak1 and Zhe Song2 Abstract: This paper presents models; Diagnosis; Combustion; Power plants; Probe instruments. Introduction Measurements in industrial and Soroush 2003 . Any false reading could lead to di- sastrous outcomes. In a coal-fired power plant, faulty

  13. Discriminative Pattern Mining in Software Fault Detection Giuseppe Di Fatta

    E-Print Network [OSTI]

    Leue, Stefan

    and Subject Descriptors D.2.5 [Software Engineering]: Testing and Debugging-- Debugging aids, Diagnostics. This money is largely spent during the software testing and debugging phases [12]. The applicable software of software testing data which can support and speedup the detection of software faults. The most commonly

  14. Fault properties from seismic Q M. H. Worthington1

    E-Print Network [OSTI]

    Cambridge, University of

    . Key words: attenuation, exploration seismology, fault models, Q, seismic wave propagation. I N T R O DFault properties from seismic Q M. H. Worthington1 and J. A. Hudson2 1 T. H. Huxley School of seismic Q from a North Sea vertical seismic pro®ling data set has revealed an abrupt increase

  15. Resource Aggregation for Fault Tolerance in Integrated Services Networks

    E-Print Network [OSTI]

    Dovrolis, Constantinos

    it is critical that the failure of a network component does not lead to unexpected termination or long dis of RAFT is to setup every fault tolerant flow along a secondary path that serves as a backup in case the primary path fails. The secondary path resource reservations are aggregated whenever possible to reduce

  16. Test Case Purification for Improving Fault Localization Jifeng Xuan

    E-Print Network [OSTI]

    Test Case Purification for Improving Fault Localization Jifeng Xuan INRIA Lille - Nord Europe Lille on the execution trace of test cases. Failing test cases and their assertions form test oracles for the failing behavior of the system under analysis. In this paper, we propose a novel concept of spectrum driven test

  17. Fault-Tolerant and Reliable Computation in Cloud Computing

    E-Print Network [OSTI]

    Deng, Jing

    Fault-Tolerant and Reliable Computation in Cloud Computing Jing Deng Scott C.-H. Huang Yunghsiang S, Taipei, 106 Taiwan. § Intelligent Automation, Inc., Rockville, MD, USA. Abstract-- Cloud computing of scientific computation in cloud computing. We investigate a cloud selection strategy to decompose the matrix

  18. Influence of plastic deformation on bimaterial fault rupture directivity

    E-Print Network [OSTI]

    Dmowska, Renata

    Influence of plastic deformation on bimaterial fault rupture directivity Nora DeDontney,1 Elizabeth of the role of the stress state on the distribution of plastic deformation and the direction of preferred in determining the location of plastic deformation. For different orientations, plastic deformation can

  19. Risk Assessment of Railway Transportation Systems using Timed Fault Trees

    E-Print Network [OSTI]

    Miller, Alice

    by the GRAIL (GNSS Introduction in the RAIL sector) project that is under development cooperated with ERTMS difference between the GRAIL and current railway systems is that it involves unmanned operation. Trains to eliminate the fault, to prevent the accident. There are still many unsolved problems related to GRAIL

  20. A Fault Tolerant Hierarchical Network on Chip Router Architecture

    E-Print Network [OSTI]

    Zilic, Zeljko

    Received: 15 March 2012 /Accepted: 19 July 2013 # Springer Science+Business Media New York 2013 Abstract and energy consumption. Keywords Network on chip . Hierarchical topology . Fault-tolerant 1 Introduction DueC architectures supply a practical alternative for traditional SoC interconnect ap- proaches [3]. While