National Library of Energy BETA

Sample records for fault circuit interrupt

  1. Apparatus for and method of testing an electrical ground fault circuit interrupt device

    DOE Patents [OSTI]

    Andrews, Lowell B.

    1998-01-01

    An apparatus for testing a ground fault circuit interrupt device includes a processor, an input device connected to the processor for receiving input from an operator, a storage media connected to the processor for storing test data, an output device connected to the processor for outputting information corresponding to the test data to the operator, and a calibrated variable load circuit connected between the processor and the ground fault circuit interrupt device. The ground fault circuit interrupt device is configured to trip a corresponding circuit breaker. The processor is configured to receive signals from the calibrated variable load circuit and to process the signals to determine a trip threshold current and/or a trip time. A method of testing the ground fault circuit interrupt device includes a first step of providing an identification for the ground fault circuit interrupt device. Test data is then recorded in accordance with the identification. By comparing test data from an initial test with test data from a subsequent test, a trend of performance for the ground fault circuit interrupt device is determined.

  2. Apparatus for and method of testing an electrical ground fault circuit interrupt device

    DOE Patents [OSTI]

    Andrews, L.B.

    1998-08-18

    An apparatus for testing a ground fault circuit interrupt device includes a processor, an input device connected to the processor for receiving input from an operator, a storage media connected to the processor for storing test data, an output device connected to the processor for outputting information corresponding to the test data to the operator, and a calibrated variable load circuit connected between the processor and the ground fault circuit interrupt device. The ground fault circuit interrupt device is configured to trip a corresponding circuit breaker. The processor is configured to receive signals from the calibrated variable load circuit and to process the signals to determine a trip threshold current and/or a trip time. A method of testing the ground fault circuit interrupt device includes a first step of providing an identification for the ground fault circuit interrupt device. Test data is then recorded in accordance with the identification. By comparing test data from an initial test with test data from a subsequent test, a trend of performance for the ground fault circuit interrupt device is determined. 17 figs.

  3. DIFFERENTIAL FAULT SENSING CIRCUIT

    DOE Patents [OSTI]

    Roberts, J.H.

    1961-09-01

    A differential fault sensing circuit is designed for detecting arcing in high-voltage vacuum tubes arranged in parallel. A circuit is provided which senses differences in voltages appearing between corresponding elements likely to fault. Sensitivity of the circuit is adjusted to some level above which arcing will cause detectable differences in voltage. For particular corresponding elements, a group of pulse transformers are connected in parallel with diodes connected across the secondaries thereof so that only voltage excursions are transmitted to a thyratron which is biased to the sensitivity level mentioned.

  4. Hybrid high direct current circuit interrupter

    DOE Patents [OSTI]

    Rockot, J.H.; Mikesell, H.E.; Jha, K.N.

    1998-08-11

    A device and a method are disclosed for interrupting very high direct currents (greater than 100,000 amperes) and simultaneously blocking high voltages (greater than 600 volts). The device utilizes a mechanical switch to carry very high currents continuously with low loss and a silicon controlled rectifier (SCR) to bypass the current around the mechanical switch while its contacts are separating. A commutation circuit, connected in parallel with the SCR, turns off the SCR by utilizing a resonant circuit to divert the SCR current after the switch opens. 7 figs.

  5. Hybrid high direct current circuit interrupter

    DOE Patents [OSTI]

    Rockot, Joseph H.; Mikesell, Harvey E.; Jha, Kamal N.

    1998-01-01

    A device and a method for interrupting very high direct currents (greater than 100,000 amperes) and simultaneously blocking high voltages (greater than 600 volts). The device utilizes a mechanical switch to carry very high currents continuously with low loss and a silicon controlled rectifier (SCR) to bypass the current around the mechanical switch while its contacts are separating. A commutation circuit, connected in parallel with the SCR, turns off the SCR by utilizing a resonant circuit to divert the SCR current after the switch opens.

  6. CONTROL AND FAULT DETECTOR CIRCUIT

    DOE Patents [OSTI]

    Winningstad, C.N.

    1958-04-01

    A power control and fault detectcr circuit for a radiofrequency system is described. The operation of the circuit controls the power output of a radio- frequency power supply to automatically start the flow of energizing power to the radio-frequency power supply and to gradually increase the power to a predetermined level which is below the point where destruction occurs upon the happening of a fault. If the radio-frequency power supply output fails to increase during such period, the control does not further increase the power. On the other hand, if the output of the radio-frequency power supply properly increases, then the control continues to increase the power to a maximum value. After the maximumn value of radio-frequency output has been achieved. the control is responsive to a ''fault,'' such as a short circuit in the radio-frequency system being driven, so that the flow of power is interrupted for an interval before the cycle is repeated.

  7. Adjustable direct current and pulsed circuit fault current limiter

    DOE Patents [OSTI]

    Boenig, Heinrich J.; Schillig, Josef B.

    2003-09-23

    A fault current limiting system for direct current circuits and for pulsed power circuit. In the circuits, a current source biases a diode that is in series with the circuits' transmission line. If fault current in a circuit exceeds current from the current source biasing the diode open, the diode will cease conducting and route the fault current through the current source and an inductor. This limits the rate of rise and the peak value of the fault current.

  8. Electric circuit breaker comprising a plurality of vacuum interrupters simultaneously operated by a common operator

    DOE Patents [OSTI]

    Barkan, Philip; Imam, Imdad

    1980-01-01

    This circuit breaker comprises a plurality of a vacuum-type circuit interrupters, each having a movable contact rod. A common operating device for the interrupters comprises a linearly-movable operating member. The interrupters are mounted at one side of the operating member with their movable contact rods extending in a direction generally toward the operating member. Means is provided for mechanically coupling the operating member to the contact rods, and this means comprises a plurality of insulating operating rods, each connected at one end to the operating member and at its opposite end to one of the movable contact rods. The operating rods are of substantially equal length and have longitudinal axes that converge and intersect at substantially a common point.

  9. Switch contact device for interrupting high current, high voltage, AC and DC circuits

    DOE Patents [OSTI]

    Via, Lester C.; Witherspoon, F. Douglas; Ryan, John M.

    2005-01-04

    A high voltage switch contact structure capable of interrupting high voltage, high current AC and DC circuits. The contact structure confines the arc created when contacts open to the thin area between two insulating surfaces in intimate contact. This forces the arc into the shape of a thin sheet which loses heat energy far more rapidly than an arc column having a circular cross-section. These high heat losses require a dramatic increase in the voltage required to maintain the arc, thus extinguishing it when the required voltage exceeds the available voltage. The arc extinguishing process with this invention is not dependent on the occurrence of a current zero crossing and, consequently, is capable of rapidly interrupting both AC and DC circuits. The contact structure achieves its high performance without the use of sulfur hexafluoride.

  10. Fault current limiter and alternating current circuit breaker

    DOE Patents [OSTI]

    Boenig, Heinrich J.

    1998-01-01

    A solid-state circuit breaker and current limiter for a load served by an alternating current source having a source impedance, the solid-state circuit breaker and current limiter comprising a thyristor bridge interposed between the alternating current source and the load, the thyristor bridge having four thyristor legs and four nodes, with a first node connected to the alternating current source, and a second node connected to the load. A coil is connected from a third node to a fourth node, the coil having an impedance of a value calculated to limit the current flowing therethrough to a predetermined value. Control means are connected to the thyristor legs for limiting the alternating current flow to the load under fault conditions to a predetermined level, and for gating the thyristor bridge under fault conditions to quickly reduce alternating current flowing therethrough to zero and thereafter to maintain the thyristor bridge in an electrically open condition preventing the alternating current from flowing therethrough for a predetermined period of time.

  11. Fault current limiter and alternating current circuit breaker

    DOE Patents [OSTI]

    Boenig, H.J.

    1998-03-10

    A solid-state circuit breaker and current limiter are disclosed for a load served by an alternating current source having a source impedance, the solid-state circuit breaker and current limiter comprising a thyristor bridge interposed between the alternating current source and the load, the thyristor bridge having four thyristor legs and four nodes, with a first node connected to the alternating current source, and a second node connected to the load. A coil is connected from a third node to a fourth node, the coil having an impedance of a value calculated to limit the current flowing therethrough to a predetermined value. Control means are connected to the thyristor legs for limiting the alternating current flow to the load under fault conditions to a predetermined level, and for gating the thyristor bridge under fault conditions to quickly reduce alternating current flowing therethrough to zero and thereafter to maintain the thyristor bridge in an electrically open condition preventing the alternating current from flowing therethrough for a predetermined period of time. 9 figs.

  12. Use of inverse time, adjustable instantaneous pickup circuit breakers for short circuit and ground fault protection of energy efficient motors

    SciTech Connect (OSTI)

    Heath, D.W.; Bradfield, H.L.

    1995-12-31

    Many energy efficient low voltage motors exhibit first half cycle instantaneous inrush current values greater than the National Electrical Code`s 13 times motor full load amperes maximum permissible setting for instantaneous trip circuit breakers. The alternate use of an inverse time circuit breaker could lead to inadequate protection if the breaker does not have adjustable instantaneous settings. Recent innovations in digital solid state trip unit technology have made available an inverse time, adjustable instantaneous trip circuit breaker in 15A to 150A ratings. This allows the instantaneous pickup to be adjusted to a value slightly above motor inrush so that low level faults will be cleared instantaneously while avoiding nuisance tripping at startup. Applications, settings and comparisons are discussed.

  13. Creating dynamic equivalent PV circuit models with impedance spectroscopy for arc-fault modeling.

    SciTech Connect (OSTI)

    Johnson, Jay Dean; Kuszmaul, Scott S.; Strauch, Jason E.; Schoenwald, David Alan

    2011-06-01

    Article 690.11 in the 2011 National Electrical Code{reg_sign} (NEC{reg_sign}) requires new photovoltaic (PV) systems on or penetrating a building to include a listed arc fault protection device. Currently there is little experimental or empirical research into the behavior of the arcing frequencies through PV components despite the potential for modules and other PV components to filter or attenuate arcing signatures that could render the arc detector ineffective. To model AC arcing signal propagation along PV strings, the well-studied DC diode models were found to inadequately capture the behavior of high frequency arcing signals. Instead dynamic equivalent circuit models of PV modules were required to describe the impedance for alternating currents in modules. The nonlinearities present in PV cells resulting from irradiance, temperature, frequency, and bias voltage variations make modeling these systems challenging. Linearized dynamic equivalent circuits were created for multiple PV module manufacturers and module technologies. The equivalent resistances and capacitances for the modules were determined using impedance spectroscopy with no bias voltage and no irradiance. The equivalent circuit model was employed to evaluate modules having irradiance conditions that could not be measured directly with the instrumentation. Although there was a wide range of circuit component values, the complex impedance model does not predict filtering of arc fault frequencies in PV strings for any irradiance level. Experimental results with no irradiance agree with the model and show nearly no attenuation for 1 Hz to 100 kHz input frequencies.

  14. Low Insertion HVDC Circuit Breaker: Magnetically Pulsed Hybrid Breaker for HVDC Power Distribution Protection

    SciTech Connect (OSTI)

    2012-01-09

    GENI Project: General Atomics is developing a direct current (DC) circuit breaker that could protect the grid from faults 100 times faster than its alternating current (AC) counterparts. Circuit breakers are critical elements in any electrical system. At the grid level, their main function is to isolate parts of the grid where a fault has occurred—such as a downed power line or a transformer explosion—from the rest of the system. DC circuit breakers must interrupt the system during a fault much faster than AC circuit breakers to prevent possible damage to cables, converters and other grid-level components. General Atomics’ high-voltage DC circuit breaker would react in less than 1/1,000th of a second to interrupt current during a fault, preventing potential hazards to people and equipment.

  15. Superior model for fault tolerance computation in designing nano-sized circuit systems

    SciTech Connect (OSTI)

    Singh, N. S. S. Muthuvalu, M. S.; Asirvadam, V. S.

    2014-10-24

    As CMOS technology scales nano-metrically, reliability turns out to be a decisive subject in the design methodology of nano-sized circuit systems. As a result, several computational approaches have been developed to compute and evaluate reliability of desired nano-electronic circuits. The process of computing reliability becomes very troublesome and time consuming as the computational complexity build ups with the desired circuit size. Therefore, being able to measure reliability instantly and superiorly is fast becoming necessary in designing modern logic integrated circuits. For this purpose, the paper firstly looks into the development of an automated reliability evaluation tool based on the generalization of Probabilistic Gate Model (PGM) and Boolean Difference-based Error Calculator (BDEC) models. The Matlab-based tool allows users to significantly speed-up the task of reliability analysis for very large number of nano-electronic circuits. Secondly, by using the developed automated tool, the paper explores into a comparative study involving reliability computation and evaluation by PGM and, BDEC models for different implementations of same functionality circuits. Based on the reliability analysis, BDEC gives exact and transparent reliability measures, but as the complexity of the same functionality circuits with respect to gate error increases, reliability measure by BDEC tends to be lower than the reliability measure by PGM. The lesser reliability measure by BDEC is well explained in this paper using distribution of different signal input patterns overtime for same functionality circuits. Simulation results conclude that the reliability measure by BDEC depends not only on faulty gates but it also depends on circuit topology, probability of input signals being one or zero and also probability of error on signal lines.

  16. Fault Locating, Prediction and Protection (FLPPS)

    SciTech Connect (OSTI)

    Yinger, Robert, J.; Venkata, S., S.; Centeno, Virgilio

    2010-09-30

    One of the main objectives of this DOE-sponsored project was to reduce customer outage time. Fault location, prediction, and protection are the most important aspects of fault management for the reduction of outage time. In the past most of the research and development on power system faults in these areas has focused on transmission systems, and it is not until recently with deregulation and competition that research on power system faults has begun to focus on the unique aspects of distribution systems. This project was planned with three Phases, approximately one year per phase. The first phase of the project involved an assessment of the state-of-the-art in fault location, prediction, and detection as well as the design, lab testing, and field installation of the advanced protection system on the SCE Circuit of the Future located north of San Bernardino, CA. The new feeder automation scheme, with vacuum fault interrupters, will limit the number of customers affected by the fault. Depending on the fault location, the substation breaker might not even trip. Through the use of fast communications (fiber) the fault locations can be determined and the proper fault interrupting switches opened automatically. With knowledge of circuit loadings at the time of the fault, ties to other circuits can be closed automatically to restore all customers except the faulted section. This new automation scheme limits outage time and increases reliability for customers. The second phase of the project involved the selection, modeling, testing and installation of a fault current limiter on the Circuit of the Future. While this project did not pay for the installation and testing of the fault current limiter, it did perform the evaluation of the fault current limiter and its impacts on the protection system of the Circuit of the Future. After investigation of several fault current limiters, the Zenergy superconducting, saturable core fault current limiter was selected for

  17. Fault finder

    DOE Patents [OSTI]

    Bunch, Richard H.

    1986-01-01

    A fault finder for locating faults along a high voltage electrical transmission line. Real time monitoring of background noise and improved filtering of input signals is used to identify the occurrence of a fault. A fault is detected at both a master and remote unit spaced along the line. A master clock synchronizes operation of a similar clock at the remote unit. Both units include modulator and demodulator circuits for transmission of clock signals and data. All data is received at the master unit for processing to determine an accurate fault distance calculation.

  18. Commutation circuit for an HVDC circuit breaker

    DOE Patents [OSTI]

    Premerlani, W.J.

    1981-11-10

    A commutation circuit for a high voltage DC circuit breaker incorporates a resistor capacitor combination and a charging circuit connected to the main breaker, such that a commutating capacitor is discharged in opposition to the load current to force the current in an arc after breaker opening to zero to facilitate arc interruption. In a particular embodiment, a normally open commutating circuit is connected across the contacts of a main DC circuit breaker to absorb the inductive system energy trapped by breaker opening and to limit recovery voltages to a level tolerable by the commutating circuit components. 13 figs.

  19. Commutation circuit for an HVDC circuit breaker

    DOE Patents [OSTI]

    Premerlani, William J.

    1981-01-01

    A commutation circuit for a high voltage DC circuit breaker incorporates a resistor capacitor combination and a charging circuit connected to the main breaker, such that a commutating capacitor is discharged in opposition to the load current to force the current in an arc after breaker opening to zero to facilitate arc interruption. In a particular embodiment, a normally open commutating circuit is connected across the contacts of a main DC circuit breaker to absorb the inductive system energy trapped by breaker opening and to limit recovery voltages to a level tolerable by the commutating circuit components.

  20. Adversary Sequence Interruption Model

    Energy Science and Technology Software Center (OSTI)

    1985-11-15

    PC EASI is an IBM personal computer or PC-compatible version of an analytical technique for measuring the effectiveness of physical protection systems. PC EASI utilizes a methodology called Estimate of Adversary Sequence Interruption (EASI) which evaluates the probability of interruption (PI) for a given sequence of adversary tasks. Probability of interruption is defined as the probability that the response force will arrive before the adversary force has completed its task. The EASI methodology is amore » probabilistic approach that analytically evaluates basic functions of the physical security system (detection, assessment, communications, and delay) with respect to response time along a single adversary path. It is important that the most critical scenarios for each target be identified to ensure that vulnerabilities have not been overlooked. If the facility is not overly complex, this can be accomplished by examining all paths. If the facility is complex, a global model such as Safeguards Automated Facility Evaluation (SAFE) may be used to identify the most vulnerable paths. PC EASI is menu-driven with screen forms for entering and editing the basic scenarios. In addition to evaluating PI for the basic scenario, the sensitivities of many of the parameters chosen in the scenario can be analyzed. These sensitivities provide information to aid the analyst in determining the tradeoffs for reducing the probability of interruption. PC EASI runs under the Micro Data Base Systems'' proprietary database management system Knowledgeman. KMAN provides the user environment and file management for the specified basic scenarios, and KGRAPH the graphical output of the sensitivity calculations. This software is not included. Due to errors in release 2 of KMAN, PC EASI will not execute properly; release 1.07 of KMAN is required.« less

  1. Interrupted polysilanes useful as photoresists

    DOE Patents [OSTI]

    Zeigler, John M.

    1988-01-01

    Polysilane polymers in which the Si backbone is interrupted by atoms such as O, Ge, Sn, P, etc., are useful photoresists especially in the solvent development mode.

  2. Interrupted polysilanes useful as photoresists

    DOE Patents [OSTI]

    Zeigler, J.M.

    1988-08-02

    Polysilane polymers in which the Si backbone is interrupted by atoms such as O, Ge, Sn, P, etc., are useful photoresists especially in the solvent development mode.

  3. Global interrupt and barrier networks

    DOE Patents [OSTI]

    Blumrich, Matthias A.; Chen, Dong; Coteus, Paul W.; Gara, Alan G.; Giampapa, Mark E; Heidelberger, Philip; Kopcsay, Gerard V.; Steinmacher-Burow, Burkhard D.; Takken, Todd E.

    2008-10-28

    A system and method for generating global asynchronous signals in a computing structure. Particularly, a global interrupt and barrier network is implemented that implements logic for generating global interrupt and barrier signals for controlling global asynchronous operations performed by processing elements at selected processing nodes of a computing structure in accordance with a processing algorithm; and includes the physical interconnecting of the processing nodes for communicating the global interrupt and barrier signals to the elements via low-latency paths. The global asynchronous signals respectively initiate interrupt and barrier operations at the processing nodes at times selected for optimizing performance of the processing algorithms. In one embodiment, the global interrupt and barrier network is implemented in a scalable, massively parallel supercomputing device structure comprising a plurality of processing nodes interconnected by multiple independent networks, with each node including one or more processing elements for performing computation or communication activity as required when performing parallel algorithm operations. One multiple independent network includes a global tree network for enabling high-speed global tree communications among global tree network nodes or sub-trees thereof. The global interrupt and barrier network may operate in parallel with the global tree network for providing global asynchronous sideband signals.

  4. Pulsed interrupter and method of operation

    DOE Patents [OSTI]

    Drake, Joel Lawton; Kratz, Robert

    2015-06-09

    Some embodiments provide interrupter systems comprising: a first electrode; a second electrode; a piston movably located at a first position and electrically coupled with the first and second electrodes establishing a closed state, the piston comprises an electrical conductor that couples with the first and second electrodes providing a conductive path; an electromagnetic launcher configured to, when activated, induce a magnetic field pulse causing the piston to move away from the electrical coupling with the first and second electrodes establishing an open circuit between the first and second electrodes; and a piston control system comprising a piston arresting system configured to control a deceleration of the piston following the movement of the piston induced by the electromagnetic launcher such that the piston is not in electrical contact with at least one of the first electrode and the second electrode when in the open state.

  5. High temperature superconducting fault current limiter

    DOE Patents [OSTI]

    Hull, John R.

    1997-01-01

    A fault current limiter (10) for an electrical circuit (14). The fault current limiter (10) includes a high temperature superconductor (12) in the electrical circuit (14). The high temperature superconductor (12) is cooled below its critical temperature to maintain the superconducting electrical properties during operation as the fault current limiter (10).

  6. High temperature superconducting fault current limiter

    DOE Patents [OSTI]

    Hull, J.R.

    1997-02-04

    A fault current limiter for an electrical circuit is disclosed. The fault current limiter includes a high temperature superconductor in the electrical circuit. The high temperature superconductor is cooled below its critical temperature to maintain the superconducting electrical properties during operation as the fault current limiter. 15 figs.

  7. PV Systems Reliability Final Technical Report: Ground Fault Detection

    SciTech Connect (OSTI)

    Lavrova, Olga; Flicker, Jack David; Johnson, Jay

    2016-01-01

    We have examined ground faults in PhotoVoltaic (PV) arrays and the efficacy of fuse, current detection (RCD), current sense monitoring/relays (CSM), isolation/insulation (Riso) monitoring, and Ground Fault Detection and Isolation (GFID) using simulations based on a Simulation Program with Integrated Circuit Emphasis SPICE ground fault circuit model, experimental ground faults installed on real arrays, and theoretical equations.

  8. Squishy Circuits

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Squishy Circuits Squishy Circuits Inspire your inner Ben Franklin Children of all ages create circuits and explore electronics-even making electricity flow with their own doughy...

  9. Executing application function calls in response to an interrupt

    DOE Patents [OSTI]

    Almasi, Gheorghe; Archer, Charles J.; Giampapa, Mark E.; Gooding, Thomas M.; Heidelberger, Philip; Parker, Jeffrey J.

    2010-05-11

    Executing application function calls in response to an interrupt including creating a thread; receiving an interrupt having an interrupt type; determining whether a value of a semaphore represents that interrupts are disabled; if the value of the semaphore represents that interrupts are not disabled: calling, by the thread, one or more preconfigured functions in dependence upon the interrupt type of the interrupt; yielding the thread; and if the value of the semaphore represents that interrupts are disabled: setting the value of the semaphore to represent to a kernel that interrupts are hard-disabled; and hard-disabling interrupts at the kernel.

  10. Hawaii Faults

    DOE Data Explorer [Office of Scientific and Technical Information (OSTI)]

    Nicole Lautze

    2015-01-01

    Faults combined from USGS 2007 Geologic Map of the State of Hawaii and the USGS Quaternary Fault and Fold database. This data is in shapefile format.

  11. Superconducting fault current controller/current controller

    DOE Patents [OSTI]

    Cha, Yung S.

    2004-06-15

    A superconducting fault current controller/current controller employs a superconducting-shielded core reactor (SSCR) with a variable impedance in a secondary circuit to control current in a primary circuit such as an electrical distribution system. In a second embodiment, a variable current source is employed in a secondary circuit of an SSCR to control current in the primary circuit. In a third embodiment, both a variable impedance in one secondary circuit and a variable current source in a second circuit of an SSCR are employed for separate and independent control of current in the primary circuit.

  12. Arc-Fault Detector Algorithm Evaluation Method Utilizing Prerecorded...

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    ... This pulse was fed into the AFD circuit to better tune the arc-fault detector. Figure 4 shows the string current (Hall Effect), the arc-fault voltage (Arc V (TEK)), and the arcing ...

  13. Measuring circuit

    DOE Patents [OSTI]

    Sun, Shan C.; Chaprnka, Anthony G.

    1977-01-11

    An automatic gain control circuit functions to adjust the magnitude of an input signal supplied to a measuring circuit to a level within the dynamic range of the measuring circuit while a log-ratio circuit adjusts the magnitude of the output signal from the measuring circuit to the level of the input signal and optimizes the signal-to-noise ratio performance of the measuring circuit.

  14. Short-Circuit Modeling of a Wind Power Plant: Preprint

    SciTech Connect (OSTI)

    Muljadi, E.; Gevorgian, V.

    2011-03-01

    This paper investigates the short-circuit behavior of a WPP for different types of wind turbines. The short-circuit behavior will be presented. Both the simplified models and detailed models are used in the simulations and both symmetrical faults and unsymmetrical faults are discussed.

  15. ADDER CIRCUIT

    DOE Patents [OSTI]

    Jacobsohn, D.H.; Merrill, L.C.

    1959-01-20

    An improved parallel addition unit is described which is especially adapted for use in electronic digital computers and characterized by propagation of the carry signal through each of a plurality of denominationally ordered stages within a minimum time interval. In its broadest aspects, the invention incorporates a fast multistage parallel digital adder including a plurality of adder circuits, carry-propagation circuit means in all but the most significant digit stage, means for conditioning each carry-propagation circuit during the time period in which information is placed into the adder circuits, and means coupling carry-generation portions of thc adder circuit to the carry propagating means.

  16. Passive fault current limiting device

    DOE Patents [OSTI]

    Evans, D.J.; Cha, Y.S.

    1999-04-06

    A passive current limiting device and isolator is particularly adapted for use at high power levels for limiting excessive currents in a circuit in a fault condition such as an electrical short. The current limiting device comprises a magnetic core wound with two magnetically opposed, parallel connected coils of copper, a high temperature superconductor or other electrically conducting material, and a fault element connected in series with one of the coils. Under normal operating conditions, the magnetic flux density produced by the two coils cancel each other. Under a fault condition, the fault element is triggered to cause an imbalance in the magnetic flux density between the two coils which results in an increase in the impedance in the coils. While the fault element may be a separate current limiter, switch, fuse, bimetal strip or the like, it preferably is a superconductor current limiter conducting one-half of the current load compared to the same limiter wired to carry the total current of the circuit. The major voltage during a fault condition is in the coils wound on the common core in a preferred embodiment. 6 figs.

  17. Passive fault current limiting device

    DOE Patents [OSTI]

    Evans, Daniel J.; Cha, Yung S.

    1999-01-01

    A passive current limiting device and isolator is particularly adapted for use at high power levels for limiting excessive currents in a circuit in a fault condition such as an electrical short. The current limiting device comprises a magnetic core wound with two magnetically opposed, parallel connected coils of copper, a high temperature superconductor or other electrically conducting material, and a fault element connected in series with one of the coils. Under normal operating conditions, the magnetic flux density produced by the two coils cancel each other. Under a fault condition, the fault element is triggered to cause an imbalance in the magnetic flux density between the two coils which results in an increase in the impedance in the coils. While the fault element may be a separate current limiter, switch, fuse, bimetal strip or the like, it preferably is a superconductor current limiter conducting one-half of the current load compared to the same limiter wired to carry the total current of the circuit. The major voltage during a fault condition is in the coils wound on the common core in a preferred embodiment.

  18. Arc fault detection system

    DOE Patents [OSTI]

    Jha, K.N.

    1999-05-18

    An arc fault detection system for use on ungrounded or high-resistance-grounded power distribution systems is provided which can be retrofitted outside electrical switchboard circuits having limited space constraints. The system includes a differential current relay that senses a current differential between current flowing from secondary windings located in a current transformer coupled to a power supply side of a switchboard, and a total current induced in secondary windings coupled to a load side of the switchboard. When such a current differential is experienced, a current travels through a operating coil of the differential current relay, which in turn opens an upstream circuit breaker located between the switchboard and a power supply to remove the supply of power to the switchboard. 1 fig.

  19. Arc fault detection system

    DOE Patents [OSTI]

    Jha, Kamal N.

    1999-01-01

    An arc fault detection system for use on ungrounded or high-resistance-grounded power distribution systems is provided which can be retrofitted outside electrical switchboard circuits having limited space constraints. The system includes a differential current relay that senses a current differential between current flowing from secondary windings located in a current transformer coupled to a power supply side of a switchboard, and a total current induced in secondary windings coupled to a load side of the switchboard. When such a current differential is experienced, a current travels through a operating coil of the differential current relay, which in turn opens an upstream circuit breaker located between the switchboard and a power supply to remove the supply of power to the switchboard.

  20. GATING CIRCUITS

    DOE Patents [OSTI]

    Merrill, L.C.

    1958-10-14

    Control circuits for vacuum tubes are described, and a binary counter having an improved trigger circuit is reported. The salient feature of the binary counter is the application of the input signal to the cathode of each of two vacuum tubes through separate capacitors and the connection of each cathode to ground through separate diodes. The control of the binary counter is achieved in this manner without special pulse shaping of the input signal. A further advantage of the circuit is the simplicity and minimum nuruber of components required, making its use particularly desirable in computer machines.

  1. MULTIPLIER CIRCUIT

    DOE Patents [OSTI]

    Thomas, R.E.

    1959-01-20

    An electronic circuit is presented for automatically computing the product of two selected variables by multiplying the voltage pulses proportional to the variables. The multiplier circuit has a plurality of parallel resistors of predetermined values connected through separate gate circults between a first input and the output terminal. One voltage pulse is applied to thc flrst input while the second voltage pulse is applied to control circuitry for the respective gate circuits. Thc magnitude of the second voltage pulse selects the resistors upon which the first voltage pulse is imprcssed, whereby the resultant output voltage is proportional to the product of the input voltage pulses

  2. Wind Power Plant Enhancement with a Fault-Current Limiter: Preprint

    SciTech Connect (OSTI)

    Muljadi, E.; Gevorgian, V.; DeLaRosa, F.

    2011-03-01

    This paper investigates the capability of a saturable core fault-current limiter to limit the short circuit current of different types of wind turbine generators.

  3. Development of Fault Models for Hybrid Fault Detection and Diagnostics Algorithm: October 1, 2014 -- May 5, 2015

    SciTech Connect (OSTI)

    Cheung, Howard; Braun, James E.

    2015-12-31

    This report describes models of building faults created for OpenStudio to support the ongoing development of fault detection and diagnostic (FDD) algorithms at the National Renewable Energy Laboratory. Building faults are operating abnormalities that degrade building performance, such as using more energy than normal operation, failing to maintain building temperatures according to the thermostat set points, etc. Models of building faults in OpenStudio can be used to estimate fault impacts on building performance and to develop and evaluate FDD algorithms. The aim of the project is to develop fault models of typical heating, ventilating and air conditioning (HVAC) equipment in the United States, and the fault models in this report are grouped as control faults, sensor faults, packaged and split air conditioner faults, water-cooled chiller faults, and other uncategorized faults. The control fault models simulate impacts of inappropriate thermostat control schemes such as an incorrect thermostat set point in unoccupied hours and manual changes of thermostat set point due to extreme outside temperature. Sensor fault models focus on the modeling of sensor biases including economizer relative humidity sensor bias, supply air temperature sensor bias, and water circuit temperature sensor bias. Packaged and split air conditioner fault models simulate refrigerant undercharging, condenser fouling, condenser fan motor efficiency degradation, non-condensable entrainment in refrigerant, and liquid line restriction. Other fault models that are uncategorized include duct fouling, excessive infiltration into the building, and blower and pump motor degradation.

  4. High performance protection circuit for power electronics applications

    SciTech Connect (OSTI)

    Tudoran, Cristian D. Dădârlat, Dorin N.; Toşa, Nicoleta; Mişan, Ioan

    2015-12-23

    In this paper we present a high performance protection circuit designed for the power electronics applications where the load currents can increase rapidly and exceed the maximum allowed values, like in the case of high frequency induction heating inverters or high frequency plasma generators. The protection circuit is based on a microcontroller and can be adapted for use on single-phase or three-phase power systems. Its versatility comes from the fact that the circuit can communicate with the protected system, having the role of a “sensor” or it can interrupt the power supply for protection, in this case functioning as an external, independent protection circuit.

  5. NREL: Awards and Honors - Current Interrupt Charging Algorithm...

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Current Interrupt Charging Algorithm for Lead-Acid Batteries Developers: Matthew A. Keyser, Ahmad A. Pesaran, and Mark M. Mihalic, National Renewable Energy Laboratory; Robert F....

  6. MULTIPLIER CIRCUIT

    DOE Patents [OSTI]

    Chase, R.L.

    1963-05-01

    An electronic fast multiplier circuit utilizing a transistor controlled voltage divider network is presented. The multiplier includes a stepped potentiometer in which solid state or transistor switches are substituted for mechanical wipers in order to obtain electronic switching that is extremely fast as compared to the usual servo-driven mechanical wipers. While this multiplier circuit operates as an approximation and in steps to obtain a voltage that is the product of two input voltages, any desired degree of accuracy can be obtained with the proper number of increments and adjustment of parameters. (AEC)

  7. Federated Testbed Circuits

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Testbed Circuits Network R&D Overview Experimental Network Testbeds 100G SDN Testbed Dark Fiber Testbed Federated Testbed Circuits Test Circuit Service Performance (perfSONAR)...

  8. Servicing a globally broadcast interrupt signal in a multi-threaded computer

    DOE Patents [OSTI]

    Attinella, John E.; Davis, Kristan D.; Musselman, Roy G.; Satterfield, David L.

    2015-12-29

    Methods, apparatuses, and computer program products for servicing a globally broadcast interrupt signal in a multi-threaded computer comprising a plurality of processor threads. Embodiments include an interrupt controller indicating in a plurality of local interrupt status locations that a globally broadcast interrupt signal has been received by the interrupt controller. Embodiments also include a thread determining that a local interrupt status location corresponding to the thread indicates that the globally broadcast interrupt signal has been received by the interrupt controller. Embodiments also include the thread processing one or more entries in a global interrupt status bit queue based on whether global interrupt status bits associated with the globally broadcast interrupt signal are locked. Each entry in the global interrupt status bit queue corresponds to a queued global interrupt.

  9. Galvanostatic interruption of lithium insertion into magnetite: Evidence of surface layer formation

    DOE Public Access Gateway for Energy & Science Beta (PAGES Beta)

    Nicholas W. Brady; Takeuchi, Esther S.; Knehr, K. W.; Cama, Christina A.; Lininger, Christianna N.; Lin, Zhou; Marschilok, Amy C.; Takeuchi, Kenneth J.; West, Alan C.

    2016-05-05

    Magnetite is a known lithium intercalation material, and the loss of active, nanocrystalline magnetite can be inferred from the open-circuit potential relaxation. Specifically, for current interruption after relatively small amounts of lithium insertion, the potential first increases and then decreases, and the decrease is hypothesized to be due to a formation of a surface layer, which increases the solid-state lithium concentration in the remaining active material. Comparisons of simulation to experiment suggest that the reactions with the electrolyte result in the formation of a thin layer of electrochemically inactive material, which is best described by a nucleation and growth mechanism.more » Simulations are consistent with experimental results observed for 6, 8 and 32-nm crystals. As a result, simulations capture the experimental differences in lithiation behavior between the first and second cycles.« less

  10. High speed, long distance, data transmission multiplexing circuit

    DOE Patents [OSTI]

    Mariotti, Razvan

    1991-01-01

    A high speed serial data transmission multiplexing circuit, which is operable to accurately transmit data over long distances (up to 3 Km), and to multiplex, select and continuously display real time analog signals in a bandwidth from DC to 100 Khz. The circuit is made fault tolerant by use of a programmable flywheel algorithm, which enables the circuit to tolerate one transmission error before losing synchronization of the transmitted frames of data. A method of encoding and framing captured and transmitted data is used which has a low overhead and prevents some particular transmitted data patterns from locking an included detector/decoder circuit.

  11. Multi-megampere current interruption from explosive deformation of conductors

    SciTech Connect (OSTI)

    Goforth, J.H.; Williams, A.H.; Marsh, S.P.

    1985-01-01

    Two approaches for using explosives to interrupt current flowing in solid conductors are described. One concept uses explosives to extrude the switch conductor into thin regions that fuse due to current in the switch. A preliminary scaling law is presented. The second approach employs dielectric jets to sever current carrying conductors. A feasibility experiment and an improved design are described.

  12. Charge regulation circuit

    DOE Patents [OSTI]

    Ball, Don G.

    1992-01-01

    A charge regulation circuit provides regulation of an unregulated voltage supply in the range of 0.01%. The charge regulation circuit is utilized in a preferred embodiment in providing regulated voltage for controlling the operation of a laser.

  13. Impact of Interruptible Natural Gas Service on Northeast Heating Oil Demand

    Reports and Publications (EIA)

    2001-01-01

    Assesses the extent of interruptible natural gas contracts and their effect on heating oil demand in the Northeast.

  14. Electrical Circuit Simulation Code

    Energy Science and Technology Software Center (OSTI)

    2001-08-09

    Massively-Parallel Electrical Circuit Simulation Code. CHILESPICE is a massively-arallel distributed-memory electrical circuit simulation tool that contains many enhanced radiation, time-based, and thermal features and models. Large scale electronic circuit simulation. Shared memory, parallel processing, enhance convergence. Sandia specific device models.

  15. Piezoelectric drive circuit

    DOE Patents [OSTI]

    Treu, C.A. Jr.

    1999-08-31

    A piezoelectric motor drive circuit is provided which utilizes the piezoelectric elements as oscillators and a Meacham half-bridge approach to develop feedback from the motor ground circuit to produce a signal to drive amplifiers to power the motor. The circuit automatically compensates for shifts in harmonic frequency of the piezoelectric elements due to pressure and temperature changes. 7 figs.

  16. Piezoelectric drive circuit

    DOE Patents [OSTI]

    Treu, Jr., Charles A.

    1999-08-31

    A piezoelectric motor drive circuit is provided which utilizes the piezoelectric elements as oscillators and a Meacham half-bridge approach to develop feedback from the motor ground circuit to produce a signal to drive amplifiers to power the motor. The circuit automatically compensates for shifts in harmonic frequency of the piezoelectric elements due to pressure and temperature changes.

  17. High voltage fault current limiter having immersed phase coils

    DOE Patents [OSTI]

    Darmann, Francis Anthony

    2014-04-22

    A fault current limiter including: a ferromagnetic circuit formed from a ferromagnetic material and including at least a first limb, and a second limb; a saturation mechanism surrounding a limb for magnetically saturating the ferromagnetic material; a phase coil wound around a second limb; a dielectric fluid surrounding the phase coil; a gaseous atmosphere surrounding the saturation mechanism.

  18. Rule based decision support system for single-line fault detection in a delta-delta connected distribution system

    SciTech Connect (OSTI)

    Momoh, J.A.; Dias, L.G.; Thor, T. . Dept. of Electrical Engineering); Laird, D. )

    1994-05-01

    Single-line fault detection, faulted feeder identification, fault type classification, fault location and fault impedance estimation, continue to pose a problem to delta-delta connected distribution systems such as the Los Angeles Department of Water and Power (LADWP) which has over 1,500 feeder circuits at the 4.8kV voltage level. This paper describes a rule based decision support (RBDS) system application to single-line fault detection in a delta-delta connected distribution system. The RBDS system is built from knowledge acquired through exhaustive simulation based on non-arcing type fault situations. It is primarily designed to detect the presence of a fault, identify the faulted feeder, the faulted phase and classify the fault type. It is also designed to gauge the proximity of the fault to the substation and to assess the fault impedance. A fault in the distribution system, upon identification, triggers an alarm with explanatory facility leading to the fault. The RBDS system was tested with different sets of simulated data and proved successful in most cases. Additional tests will be done using field data made available by LADWP. The RBDS system module is a prototype integrated fault detection scheme to be installed in a LADWP distribution substation.

  19. CIRCUITS FOR CURRENT MEASUREMENTS

    DOE Patents [OSTI]

    Cox, R.J.

    1958-11-01

    Circuits are presented for measurement of a logarithmic scale of current flowing in a high impedance. In one form of the invention the disclosed circuit is in combination with an ionization chamber to measure lonization current. The particular circuit arrangement lncludes a vacuum tube having at least one grid, an ionization chamber connected in series with a high voltage source and the grid of the vacuum tube, and a d-c amplifier feedback circuit. As the ionization chamber current passes between the grid and cathode of the tube, the feedback circuit acts to stabilize the anode current, and the feedback voltage is a measure of the logaritbm of the ionization current.

  20. Photovoltaic System Fault Detection

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Photovoltaic System Fault Detection and Diagnostics using Laterally Primed Adaptive Resonance Theory Neural Network C. Birk Jones, Joshua S. Stein, Sigifredo Gonzalez, and Bruce H. King Sandia National Laboratories, Albuquerque, NM, 87185, U.S.A Abstract-Cost effective integration of solar photovoltaic (PV) systems requires increased reliability. This can be achieved with a robust fault detection and diagnostic (FDD) tool that auto- matically discovers faults. This paper introduces the Laterally

  1. Fault Current Limiters

    Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

    Other benefits include: &17; Enhanced system safety, stability, and efficiency of the power ... large fault current desaturates the iron core of the series AC coils and the increased ...

  2. Workplace Charging: Safety and Management Policy For Level 1...

    Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

    Ground-fault circuit interrupter (GFCI) outlets, which protect against electrical shock, are required for outdoor use. Additionally, it is a good practice to ask an electrician to ...

  3. High-capacity single-pressure SF/sub 6/ interrupters. Final report

    SciTech Connect (OSTI)

    Rostron, J R; Berkebile, L E; Spindle, H E

    1983-05-01

    The object of this project was to design and develop a high-voltage, single-pressure, SF/sub 6/ interrupter with an interrupting capability of 120 kA at 145 kV with a continuous current rating of 5000 A and an interrupting time of 1.5 cycles or less. A second objective of 100 kA at 242 kV was added during the project. Mathematical models were used to extrapolate design requirements from existing data for 63 and 80 kA. Two model puffers, one liquid and the other gas, were designed and tested to obtain data at 100 kA. An interrupter, optimized on the basis of total prospective breaker cost, was designed using the mathematical models. A study was made of the construction materials to operate under the high-stress conditions in this interrupter. Existing high-speed movies of high-current arcs under double-flow conditions were analyzed to obtain more information for modeling the interrupter. The optimized interrupter design was built and tested. The interrupting capability confirmed calculations of predicted performance near current zero; however, the dielectric strength after interrupting these high-current arcs was not adequate for the 145-kV or the 242-kV ratings. The dielectric strength was reduced by hot gases flowing out of the interrupter. Valuable data have been obtained for modeling the SF/sub 6/ puffer interrupter for high currents.

  4. Solar system fault detection

    DOE Patents [OSTI]

    Farrington, Robert B.; Pruett, Jr., James C.

    1986-01-01

    A fault detecting apparatus and method are provided for use with an active solar system. The apparatus provides an indication as to whether one or more predetermined faults have occurred in the solar system. The apparatus includes a plurality of sensors, each sensor being used in determining whether a predetermined condition is present. The outputs of the sensors are combined in a pre-established manner in accordance with the kind of predetermined faults to be detected. Indicators communicate with the outputs generated by combining the sensor outputs to give the user of the solar system and the apparatus an indication as to whether a predetermined fault has occurred. Upon detection and indication of any predetermined fault, the user can take appropriate corrective action so that the overall reliability and efficiency of the active solar system are increased.

  5. Solar system fault detection

    DOE Patents [OSTI]

    Farrington, R.B.; Pruett, J.C. Jr.

    1984-05-14

    A fault detecting apparatus and method are provided for use with an active solar system. The apparatus provides an indication as to whether one or more predetermined faults have occurred in the solar system. The apparatus includes a plurality of sensors, each sensor being used in determining whether a predetermined condition is present. The outputs of the sensors are combined in a pre-established manner in accordance with the kind of predetermined faults to be detected. Indicators communicate with the outputs generated by combining the sensor outputs to give the user of the solar system and the apparatus an indication as to whether a predetermined fault has occurred. Upon detection and indication of any predetermined fault, the user can take appropriate corrective action so that the overall reliability and efficiency of the active solar system are increased.

  6. A Framework For Evaluating Comprehensive Fault Resilience Mechanisms In Numerical Programs

    SciTech Connect (OSTI)

    Chen, S.; Peng, L.; Bronevetsky, G.

    2015-01-09

    As HPC systems approach Exascale, their circuit feature will shrink, while their overall size will grow, all at a fixed power limit. These trends imply that soft faults in electronic circuits will become an increasingly significant problem for applications that run on these systems, causing them to occasionally crash or worse, silently return incorrect results. This is motivating extensive work on application resilience to such faults, ranging from generic techniques such as replication or checkpoint/restart to algorithm-specific error detection and resilience techniques. Effective use of such techniques requires a detailed understanding of (1) which vulnerable parts of the application are most worth protecting (2) the performance and resilience impact of fault resilience mechanisms on the application. This paper presents FaultTelescope, a tool that combines these two and generates actionable insights by presenting in an intuitive way application vulnerabilities and impact of fault resilience mechanisms on applications.

  7. Remote reset circuit

    DOE Patents [OSTI]

    Gritzo, Russell E.

    1987-01-01

    A remote reset circuit acts as a stand-alone monitor and controller by clocking in each character sent by a terminal to a computer and comparing it to a given reference character. When a match occurs, the remote reset circuit activates the system's hardware reset line. The remote reset circuit is hardware based centered around monostable multivibrators and is unaffected by system crashes, partial serial transmissions, or power supply transients.

  8. Regenerative feedback resonant circuit

    DOE Patents [OSTI]

    Jones, A. Mark; Kelly, James F.; McCloy, John S.; McMakin, Douglas L.

    2014-09-02

    A regenerative feedback resonant circuit for measuring a transient response in a loop is disclosed. The circuit includes an amplifier for generating a signal in the loop. The circuit further includes a resonator having a resonant cavity and a material located within the cavity. The signal sent into the resonator produces a resonant frequency. A variation of the resonant frequency due to perturbations in electromagnetic properties of the material is measured.

  9. Remote reset circuit

    DOE Patents [OSTI]

    Gritzo, R.E.

    1985-09-12

    A remote reset circuit acts as a stand-along monitor and controller by clocking in each character sent by a terminal to a computer and comparing it to a given reference character. When a match occurs, the remote reset circuit activates the system's hardware reset line. The remote reset circuit is hardware based centered around monostable multivibrators and is unaffected by system crashes, partial serial transmissions, or power supply transients. 4 figs.

  10. Laser energy control circuit

    SciTech Connect (OSTI)

    Howie, J.B.; Mcleod, J.

    1982-08-17

    A laser energy control circuit for a gas-discharge excited laser includes an energy source psu to supply energy to the gas discharge. First circuit means tr1, tr2 operate to limit the energy supplied to a first value for a first time interval, after which second circuit means a1, a2 allow the energy to rise to a maximum value and then decrease gradually to a second value over a second time interval. Subsequently, third circuit means including amplifiers a3 to a6 operate to maintain the light output of the laser at a desired value.

  11. Liquid detection circuit

    DOE Patents [OSTI]

    Regan, Thomas O.

    1987-01-01

    Herein is a circuit which is capable of detecting the presence of liquids, especially cryogenic liquids, and whose sensor will not overheat in a vacuum. The circuit parameters, however, can be adjusted to work with any liquid over a wide range of temperatures.

  12. Method for deposition of a conductor in integrated circuits

    DOE Patents [OSTI]

    Creighton, J.R.; Dominguez, F.; Johnson, A.W.; Omstead, T.R.

    1997-09-02

    A method is described for fabricating integrated semiconductor circuits and, more particularly, for the selective deposition of a conductor onto a substrate employing a chemical vapor deposition process. By way of example, tungsten can be selectively deposited onto a silicon substrate. At the onset of loss of selectivity of deposition of tungsten onto the silicon substrate, the deposition process is interrupted and unwanted tungsten which has deposited on a mask layer with the silicon substrate can be removed employing a halogen etchant. Thereafter, a plurality of deposition/etch back cycles can be carried out to achieve a predetermined thickness of tungsten. 2 figs.

  13. Method for deposition of a conductor in integrated circuits

    DOE Patents [OSTI]

    Creighton, J. Randall; Dominguez, Frank; Johnson, A. Wayne; Omstead, Thomas R.

    1997-01-01

    A method is described for fabricating integrated semiconductor circuits and, more particularly, for the selective deposition of a conductor onto a substrate employing a chemical vapor deposition process. By way of example, tungsten can be selectively deposited onto a silicon substrate. At the onset of loss of selectivity of deposition of tungsten onto the silicon substrate, the deposition process is interrupted and unwanted tungsten which has deposited on a mask layer with the silicon substrate can be removed employing a halogen etchant. Thereafter, a plurality of deposition/etch back cycles can be carried out to achieve a predetermined thickness of tungsten.

  14. OpenStudio - Fault Modeling

    Energy Science and Technology Software Center (OSTI)

    2014-09-19

    This software record documents the OpenStudio fault model development portion of the Fault Detection and Diagnostics LDRD project.The software provides a suite of OpenStudio measures (scripts) for modeling typical HVAC system faults in commercial buildings and also included supporting materials: example projects and OpenStudio measures for reporting fault costs and energy impacts.

  15. Compensated gain control circuit for buck regulator command charge circuit

    DOE Patents [OSTI]

    Barrett, David M.

    1996-01-01

    A buck regulator command charge circuit includes a compensated-gain control signal for compensating for changes in the component values in order to achieve optimal voltage regulation. The compensated-gain control circuit includes an automatic-gain control circuit for generating a variable-gain control signal. The automatic-gain control circuit is formed of a precision rectifier circuit, a filter network, an error amplifier, and an integrator circuit.

  16. Compensated gain control circuit for buck regulator command charge circuit

    DOE Patents [OSTI]

    Barrett, D.M.

    1996-11-05

    A buck regulator command charge circuit includes a compensated-gain control signal for compensating for changes in the component values in order to achieve optimal voltage regulation. The compensated-gain control circuit includes an automatic-gain control circuit for generating a variable-gain control signal. The automatic-gain control circuit is formed of a precision rectifier circuit, a filter network, an error amplifier, and an integrator circuit. 5 figs.

  17. Symmetrical and Unsymmetrical Fault Currents of a Wind Power Plant: Preprint

    SciTech Connect (OSTI)

    Gevorgian, V.; Singh, M.; Muljadi, E.

    2011-12-01

    This paper investigates the short-circuit behavior of a wind power plant for different types of wind turbines. Both symmetrical faults and unsymmetrical faults are investigated. The size of wind power plants (WPPs) keeps getting bigger and bigger. The number of wind plants in the U.S. has increased very rapidly in the past 10 years. It is projected that in the U.S., the total wind power generation will reach 330 GW by 2030. As the importance of WPPs increases, planning engi-neers must perform impact studies used to evaluate short-circuit current (SCC) contribution of the plant into the transmission network under different fault conditions. This information is needed to size the circuit breakers, to establish the proper sys-tem protection, and to choose the transient suppressor in the circuits within the WPP. This task can be challenging to protec-tion engineers due to the topology differences between different types of wind turbine generators (WTGs) and the conventional generating units. This paper investigates the short-circuit behavior of a WPP for different types of wind turbines. Both symmetrical faults and unsymmetrical faults are investigated. Three different soft-ware packages are utilized to develop this paper. Time domain simulations and steady-state calculations are used to perform the analysis.

  18. Sensor readout detector circuit

    DOE Patents [OSTI]

    Chu, Dahlon D.; Thelen, Jr., Donald C.

    1998-01-01

    A sensor readout detector circuit is disclosed that is capable of detecting sensor signals down to a few nanoamperes or less in a high (microampere) background noise level. The circuit operates at a very low standby power level and is triggerable by a sensor event signal that is above a predetermined threshold level. A plurality of sensor readout detector circuits can be formed on a substrate as an integrated circuit (IC). These circuits can operate to process data from an array of sensors in parallel, with only data from active sensors being processed for digitization and analysis. This allows the IC to operate at a low power level with a high data throughput for the active sensors. The circuit may be used with many different types of sensors, including photodetectors, capacitance sensors, chemically-sensitive sensors or combinations thereof to provide a capability for recording transient events or for recording data for a predetermined period of time following an event trigger. The sensor readout detector circuit has applications for portable or satellite-based sensor systems.

  19. Sensor readout detector circuit

    DOE Patents [OSTI]

    Chu, D.D.; Thelen, D.C. Jr.

    1998-08-11

    A sensor readout detector circuit is disclosed that is capable of detecting sensor signals down to a few nanoamperes or less in a high (microampere) background noise level. The circuit operates at a very low standby power level and is triggerable by a sensor event signal that is above a predetermined threshold level. A plurality of sensor readout detector circuits can be formed on a substrate as an integrated circuit (IC). These circuits can operate to process data from an array of sensors in parallel, with only data from active sensors being processed for digitization and analysis. This allows the IC to operate at a low power level with a high data throughput for the active sensors. The circuit may be used with many different types of sensors, including photodetectors, capacitance sensors, chemically-sensitive sensors or combinations thereof to provide a capability for recording transient events or for recording data for a predetermined period of time following an event trigger. The sensor readout detector circuit has applications for portable or satellite-based sensor systems. 6 figs.

  20. Approximate circuits for increased reliability

    DOE Patents [OSTI]

    Hamlet, Jason R.; Mayo, Jackson R.

    2015-08-18

    Embodiments of the invention describe a Boolean circuit having a voter circuit and a plurality of approximate circuits each based, at least in part, on a reference circuit. The approximate circuits are each to generate one or more output signals based on values of received input signals. The voter circuit is to receive the one or more output signals generated by each of the approximate circuits, and is to output one or more signals corresponding to a majority value of the received signals. At least some of the approximate circuits are to generate an output value different than the reference circuit for one or more input signal values; however, for each possible input signal value, the majority values of the one or more output signals generated by the approximate circuits and received by the voter circuit correspond to output signal result values of the reference circuit.

  1. Approximate circuits for increased reliability

    DOE Patents [OSTI]

    Hamlet, Jason R.; Mayo, Jackson R.

    2015-12-22

    Embodiments of the invention describe a Boolean circuit having a voter circuit and a plurality of approximate circuits each based, at least in part, on a reference circuit. The approximate circuits are each to generate one or more output signals based on values of received input signals. The voter circuit is to receive the one or more output signals generated by each of the approximate circuits, and is to output one or more signals corresponding to a majority value of the received signals. At least some of the approximate circuits are to generate an output value different than the reference circuit for one or more input signal values; however, for each possible input signal value, the majority values of the one or more output signals generated by the approximate circuits and received by the voter circuit correspond to output signal result values of the reference circuit.

  2. CALUTRON PROTECTIVE CIRCUIT

    DOE Patents [OSTI]

    Schmidt, F.H.

    1959-05-26

    A switch and relay circuit is described for protection of calutrons. By means of this arrangement no arc can be established in the arc chamber unless cooling water flow is established. (T.R.H.)

  3. CALUTRON CATHODE INTERLOCK CIRCUIT

    DOE Patents [OSTI]

    Baldwin, L.W.

    1959-05-26

    A circuit arrangement is described which prevents application of the arc voltage to an ion source of a calutron before the cathode has been heated to operating temperature. (T.R.H.)

  4. Test Circuit Service

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Test Circuit Service Network R&D Software-Defined Networking (SDN) Experimental Network Testbeds 100G SDN Testbed Dark Fiber Testbed Test Circuit Service Testbed Results Current Testbed Research Previous Testbed Research Performance (perfSONAR) Software & Tools Development Data for Researchers Partnerships Publications Workshops Contact Us Technical Assistance: 1 800-33-ESnet (Inside US) 1 800-333-7638 (Inside US) 1 510-486-7600 (Globally) 1 510-486-7607 (Globally) Report Network

  5. Superconducting flux flow digital circuits

    DOE Patents [OSTI]

    Hietala, Vincent M.; Martens, Jon S.; Zipperian, Thomas E.

    1995-01-01

    A NOR/inverter logic gate circuit and a flip flop circuit implemented with superconducting flux flow transistors (SFFTs). Both circuits comprise two SFFTs with feedback lines. They have extremely low power dissipation, very high switching speeds, and the ability to interface between Josephson junction superconductor circuits and conventional microelectronics.

  6. Superconducting flux flow digital circuits

    DOE Patents [OSTI]

    Hietala, V.M.; Martens, J.S.; Zipperian, T.E.

    1995-02-14

    A NOR/inverter logic gate circuit and a flip flop circuit implemented with superconducting flux flow transistors (SFFTs) are disclosed. Both circuits comprise two SFFTs with feedback lines. They have extremely low power dissipation, very high switching speeds, and the ability to interface between Josephson junction superconductor circuits and conventional microelectronics. 8 figs.

  7. Fault tolerant linear actuator

    DOE Patents [OSTI]

    Tesar, Delbert

    2004-09-14

    In varying embodiments, the fault tolerant linear actuator of the present invention is a new and improved linear actuator with fault tolerance and positional control that may incorporate velocity summing, force summing, or a combination of the two. In one embodiment, the invention offers a velocity summing arrangement with a differential gear between two prime movers driving a cage, which then drives a linear spindle screw transmission. Other embodiments feature two prime movers driving separate linear spindle screw transmissions, one internal and one external, in a totally concentric and compact integrated module.

  8. Computer hardware fault administration

    DOE Patents [OSTI]

    Archer, Charles J.; Megerian, Mark G.; Ratterman, Joseph D.; Smith, Brian E.

    2010-09-14

    Computer hardware fault administration carried out in a parallel computer, where the parallel computer includes a plurality of compute nodes. The compute nodes are coupled for data communications by at least two independent data communications networks, where each data communications network includes data communications links connected to the compute nodes. Typical embodiments carry out hardware fault administration by identifying a location of a defective link in the first data communications network of the parallel computer and routing communications data around the defective link through the second data communications network of the parallel computer.

  9. ELECTRONIC PHASE CONTROL CIRCUIT

    DOE Patents [OSTI]

    Salisbury, J.D.; Klein, W.W.; Hansen, C.F.

    1959-04-21

    An electronic circuit is described for controlling the phase of radio frequency energy applied to a multicavity linear accelerator. In one application of the circuit two cavities are excited from a single radio frequency source, with one cavity directly coupled to the source and the other cavity coupled through a delay line of special construction. A phase detector provides a bipolar d-c output signal proportional to the difference in phase between the voltage in the two cavities. This d-c signal controls a bias supply which provides a d-c output for varying the capacitnce of voltage sensitive capacitors in the delay line. The over-all operation of the circuit is completely electronic, overcoming the time response limitations of the electromechanical control systems, and the relative phase relationship of the radio frequency voltages in the two caviiies is continuously controlled to effect particle acceleration.

  10. ELECTRONIC TRIGGER CIRCUIT

    DOE Patents [OSTI]

    Russell, J.A.G.

    1958-01-01

    An electronic trigger circuit is described of the type where an output pulse is obtained only after an input voltage has cqualed or exceeded a selected reference voltage. In general, the invention comprises a source of direct current reference voltage in series with an impedance and a diode rectifying element. An input pulse of preselected amplitude causes the diode to conduct and develop a signal across the impedance. The signal is delivered to an amplifier where an output pulse is produced and part of the output is fed back in a positive manner to the diode so that the amplifier produces a steep wave front trigger pulsc at the output. The trigger point of the described circuit is not subject to variation due to the aging, etc., of multi-electrode tabes, since the diode circuit essentially determines the trigger point.

  11. ELECTRONIC MULTIPLIER CIRCUIT

    DOE Patents [OSTI]

    Thomas, R.E.

    1959-08-25

    An electronic multiplier circuit is described in which an output voltage having an amplitude proportional to the product or quotient of the input signals is accomplished in a novel manner which facilitates simplicity of circuit construction and a high degree of accuracy in accomplishing the multiplying and dividing function. The circuit broadly comprises a multiplier tube in which the plate current is proportional to the voltage applied to a first control grid multiplied by the difference between voltage applied to a second control grid and the voltage applied to the first control grid. Means are provided to apply a first signal to be multiplied to the first control grid together with means for applying the sum of the first signal to be multiplied and a second signal to be multiplied to the second control grid whereby the plate current of the multiplier tube is proportional to the product of the first and second signals to be multiplied.

  12. Row fault detection system

    DOE Patents [OSTI]

    Archer, Charles Jens; Pinnow, Kurt Walter; Ratterman, Joseph D.; Smith, Brian Edward

    2008-10-14

    An apparatus, program product and method checks for nodal faults in a row of nodes by causing each node in the row to concurrently communicate with its adjacent neighbor nodes in the row. The communications are analyzed to determine a presence of a faulty node or connection.

  13. Row fault detection system

    DOE Patents [OSTI]

    Archer, Charles Jens; Pinnow, Kurt Walter; Ratterman, Joseph D.; Smith, Brian Edward

    2012-02-07

    An apparatus, program product and method check for nodal faults in a row of nodes by causing each node in the row to concurrently communicate with its adjacent neighbor nodes in the row. The communications are analyzed to determine a presence of a faulty node or connection.

  14. Row fault detection system

    DOE Patents [OSTI]

    Archer, Charles Jens; Pinnow, Kurt Walter; Ratterman, Joseph D.; Smith, Brian Edward

    2010-02-23

    An apparatus and program product check for nodal faults in a row of nodes by causing each node in the row to concurrently communicate with its adjacent neighbor nodes in the row. The communications are analyzed to determine a presence of a faulty node or connection.

  15. Dynamic Fault Detection Chassis

    SciTech Connect (OSTI)

    Mize, Jeffery J

    2007-01-01

    Abstract The high frequency switching megawatt-class High Voltage Converter Modulator (HVCM) developed by Los Alamos National Laboratory for the Oak Ridge National Laboratory's Spallation Neutron Source (SNS) is now in operation. One of the major problems with the modulator systems is shoot-thru conditions that can occur in a IGBTs H-bridge topology resulting in large fault currents and device failure in a few microseconds. The Dynamic Fault Detection Chassis (DFDC) is a fault monitoring system; it monitors transformer flux saturation using a window comparator and dV/dt events on the cathode voltage caused by any abnormality such as capacitor breakdown, transformer primary turns shorts, or dielectric breakdown between the transformer primary and secondary. If faults are detected, the DFDC will inhibit the IGBT gate drives and shut the system down, significantly reducing the possibility of a shoot-thru condition or other equipment damaging events. In this paper, we will present system integration considerations, performance characteristics of the DFDC, and discuss its ability to significantly reduce costly down time for the entire facility.

  16. Electrical Circuit Tester

    DOE Patents [OSTI]

    Love, Frank

    2006-04-18

    An electrical circuit testing device is provided, comprising a case, a digital voltage level testing circuit with a display means, a switch to initiate measurement using the device, a non-shorting switching means for selecting pre-determined electrical wiring configurations to be tested in an outlet, a terminal block, a five-pole electrical plug mounted on the case surface and a set of adapters that can be used for various multiple-pronged electrical outlet configurations for voltages from 100 600 VAC from 50 100 Hz.

  17. Small circuits for cryptography.

    SciTech Connect (OSTI)

    Torgerson, Mark Dolan; Draelos, Timothy John; Schroeppel, Richard Crabtree; Miller, Russell D.; Anderson, William Erik

    2005-10-01

    This report examines a number of hardware circuit design issues associated with implementing certain functions in FPGA and ASIC technologies. Here we show circuit designs for AES and SHA-1 that have an extremely small hardware footprint, yet show reasonably good performance characteristics as compared to the state of the art designs found in the literature. Our AES performance numbers are fueled by an optimized composite field S-box design for the Stratix chipset. Our SHA-1 designs use register packing and feedback functionalities of the Stratix LE, which reduce the logic element usage by as much as 72% as compared to other SHA-1 designs.

  18. Magnetic switches and circuits

    SciTech Connect (OSTI)

    Nunnally, W.C.

    1982-05-01

    This report outlines the use of saturable inductors as switches in lumped-element, magnetic-pulse compression circuits is discussed and the characteristic use of each is defined. In addition, the geometric constraints and magnetic pulse compression circuits used in short-pulse, low-inductance systems are considered. The scaling of presaturation leakage currents, magnetic energy losses, and switching times with geometrical and material parameters are developed to aid in evaluating magnetic pulse compression systems in a particular application. Finally, a scheme for increasing the couping coefficient in saturable stripline transformers is proposed to enable their use in the short-pulse, high-voltage regime.

  19. A method to determine fault vectors in 4H-SiC from stacking sequences observed on high resolution transmission electron microscopy images

    SciTech Connect (OSTI)

    Wu, Fangzhen; Wang, Huanhuan; Raghothamachar, Balaji; Dudley, Michael; Mueller, Stephan G.; Chung, Gil; Sanchez, Edward K.; Hansen, Darren; Loboda, Mark J.; Zhang, Lihua; Su, Dong; Kisslinger, Kim; Stach, Eric

    2014-09-14

    A new method has been developed to determine the fault vectors associated with stacking faults in 4H-SiC from their stacking sequences observed on high resolution TEM images. This method, analogous to the Burgers circuit technique for determination of dislocation Burgers vector, involves determination of the vectors required in the projection of the perfect lattice to correct the deviated path constructed in the faulted material. Results for several different stacking faults were compared with fault vectors determined from X-ray topographic contrast analysis and were found to be consistent. This technique is expected to applicable to all structures comprising corner shared tetrahedra.

  20. Bioluminescent bioreporter integrated circuit

    DOE Patents [OSTI]

    Simpson, Michael L.; Sayler, Gary S.; Paulus, Michael J.

    2000-01-01

    Disclosed are monolithic bioelectronic devices comprising a bioreporter and an OASIC. These bioluminescent bioreporter integrated circuit are useful in detecting substances such as pollutants, explosives, and heavy-metals residing in inhospitable areas such as groundwater, industrial process vessels, and battlefields. Also disclosed are methods and apparatus for environmental pollutant detection, oil exploration, drug discovery, industrial process control, and hazardous chemical monitoring.

  1. Automatic sweep circuit

    DOE Patents [OSTI]

    Keefe, Donald J.

    1980-01-01

    An automatically sweeping circuit for searching for an evoked response in an output signal in time with respect to a trigger input. Digital counters are used to activate a detector at precise intervals, and monitoring is repeated for statistical accuracy. If the response is not found then a different time window is examined until the signal is found.

  2. Circuit breaker lockout device

    DOE Patents [OSTI]

    Kozlowski, Lawrence J.; Shirey, Lawrence A.

    1992-01-01

    An improved lockout assembly for locking a circuit breaker in a selected off or on position is provided. The lockout assembly includes a lock block and a lock pin. The lock block has a hollow interior which fits over the free end of a switch handle of the circuit breaker. The lock block includes at least one hole that is placed in registration with a hole in the free end of the switch handle. A lock tab on the lock block serves to align and register the respective holes on the lock block and switch handle. A lock pin is inserted through the registered holes and serves to connect the lock block to the switch handle. Once the lock block and the switch handle are connected, the position of the switch handle is prevented from being changed by the lock tab bumping up against a stationary housing portion of the circuit breaker. When the lock pin installed, an apertured-end portion of the lock pin is in registration with another hole on the lock block. Then a special scissors conforming to O.S.H.A. regulations can be installed, with one or more padlocks, on the lockout assembly to prevent removal of the lock pin from the lockout assembly, thereby preventing removal of the lockout assembly from the circuit breaker.

  3. Circuit breaker lockout device

    DOE Patents [OSTI]

    Kozlowski, L.J.; Shirey, L.A.

    1992-11-24

    An improved lockout assembly for locking a circuit breaker in a selected off or on position is provided. The lockout assembly includes a lock block and a lock pin. The lock block has a hollow interior which fits over the free end of a switch handle of the circuit breaker. The lock block includes at least one hole that is placed in registration with a hole in the free end of the switch handle. A lock tab on the lock block serves to align and register the respective holes on the lock block and switch handle. A lock pin is inserted through the registered holes and serves to connect the lock block to the switch handle. Once the lock block and the switch handle are connected, the position of the switch handle is prevented from being changed by the lock tab bumping up against a stationary housing portion of the circuit breaker. When the lock pin installed, an apertured-end portion of the lock pin is in registration with another hole on the lock block. Then a special scissors conforming to O.S.H.A. regulations can be installed, with one or more padlocks, on the lockout assembly to prevent removal of the lock pin from the lockout assembly, thereby preventing removal of the lockout assembly from the circuit breaker. 2 figs.

  4. Automatic Fault Classification

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Automatic Fault Classification of Photovoltaic Strings Based on an In Situ IV Characterization System and a Gaussian Process Algorithm. C. Birk Jones ∗ , Manel Mart´ ınez-Ram´ on ‡ , § Ryan Smith † , Craig K. Carmignani ∗ , Olga Lavrova ∗ , Charles Robinson ∗ , and Joshua S. Stein ∗ ∗ Sandia National Laboratories Solar PV & Grid Integration, Albuquerque, NM, USA. ‡ Department of Electrical and Computer Engineering, University of New Mexico, Albuquerque, NM, USA, §

  5. Methods of fabricating applique circuits

    DOE Patents [OSTI]

    Dimos, Duane B.; Garino, Terry J.

    1999-09-14

    Applique circuits suitable for advanced packaging applications are introduced. These structures are particularly suited for the simple integration of large amounts (many nanoFarads) of capacitance into conventional integrated circuit and multichip packaging technology. In operation, applique circuits are bonded to the integrated circuit or other appropriate structure at the point where the capacitance is required, thereby minimizing the effects of parasitic coupling. An immediate application is to problems of noise reduction and control in modern high-frequency circuitry.

  6. High voltage MOSFET switching circuit

    DOE Patents [OSTI]

    McEwan, T.E.

    1994-07-26

    The problem of source lead inductance in a MOSFET switching circuit is compensated for by adding an inductor to the gate circuit. The gate circuit inductor produces an inductive spike which counters the source lead inductive drop to produce a rectangular drive voltage waveform at the internal gate-source terminals of the MOSFET. 2 figs.

  7. High voltage MOSFET switching circuit

    DOE Patents [OSTI]

    McEwan, Thomas E.

    1994-01-01

    The problem of source lead inductance in a MOSFET switching circuit is compensated for by adding an inductor to the gate circuit. The gate circuit inductor produces an inductive spike which counters the source lead inductive drop to produce a rectangular drive voltage waveform at the internal gate-source terminals of the MOSFET.

  8. GAS PHOTOTUBE CIRCUIT

    DOE Patents [OSTI]

    Richardson, J.H.

    1958-03-01

    This patent pertains to electronic circuits for measuring the intensity of light and is especially concerned with measurement between preset light thresholds. Such a circuit has application in connection with devices for reading-out information stored on punch cards or tapes where the cards and tapes are translucent. By the novel arrangement of this invention thc sensitivity of a gas phototube is maintained at a low value when the light intensity is below a first threshold level. If the light level rises above the first threshold level, the tube is rendered highly sensitive and an output signal will vary in proportion to the light intensity change. When the light level decreases below a second threshold level, the gas phototube is automatically rendered highly insensitive. Each of these threshold points is adjustable.

  9. PARTICLE BEAM TRACKING CIRCUIT

    DOE Patents [OSTI]

    Anderson, O.A.

    1959-05-01

    >A particle-beam tracking and correcting circuit is described. Beam induction electrodes are placed on either side of the beam, and potentials induced by the beam are compared in a voltage comparator or discriminator. This comparison produces an error signal which modifies the fm curve at the voltage applied to the drift tube, thereby returning the orbit to the preferred position. The arrangement serves also to synchronize accelerating frequency and magnetic field growth. (T.R.H.)

  10. Fault Detection Tool Project: Automatic Discovery of Faults using...

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Energy Systems LaboratoryBrayton Lab Photovoltaic Systems Evaluation Laboratory PV ... HomeEnergy, Photovoltaic, Renewable Energy, Research & Capabilities, SolarFault ...

  11. Power system with an integrated lubrication circuit

    DOE Patents [OSTI]

    Hoff, Brian D.; Akasam, Sivaprasad; Algrain, Marcelo C.; Johnson, Kris W.; Lane, William H.

    2009-11-10

    A power system includes an engine having a first lubrication circuit and at least one auxiliary power unit having a second lubrication circuit. The first lubrication circuit is in fluid communication with the second lubrication circuit.

  12. Integrated coherent matter wave circuits

    DOE Public Access Gateway for Energy & Science Beta (PAGES Beta)

    Ryu, C.; Boshier, M. G.

    2015-09-21

    An integrated coherent matter wave circuit is a single device, analogous to an integrated optical circuit, in which coherent de Broglie waves are created and then launched into waveguides where they can be switched, divided, recombined, and detected as they propagate. Applications of such circuits include guided atom interferometers, atomtronic circuits, and precisely controlled delivery of atoms. We report experiments demonstrating integrated circuits for guided coherent matter waves. The circuit elements are created with the painted potential technique, a form of time-averaged optical dipole potential in which a rapidly moving, tightly focused laser beam exerts forces on atoms through theirmoreelectric polarizability. Moreover, the source of coherent matter waves is a BoseEinstein condensate (BEC). Finally, we launch BECs into painted waveguides that guide them around bends and form switches, phase coherent beamsplitters, and closed circuits. These are the basic elements that are needed to engineer arbitrarily complex matter wave circuitry.less

  13. Fault Mapping | Open Energy Information

    Open Energy Info (EERE)

    to help locate and identify geothermal systems that rely on faults as high permeability pathways for fluid circulation. There are many techniques that can be done to...

  14. Reversing-counterpulse repetitive-pulse inductive storage circuit

    DOE Patents [OSTI]

    Honig, E.M.

    1987-02-10

    A high-power reversing-counterpulse repetitive-pulse inductive storage and transfer circuit includes an opening switch, a main energy storage coil, a counterpulse capacitor and a small inductor. After counterpulsing the opening switch off, the counterpulse capacitor is recharged by the main energy storage coil before the load pulse is initiated. This gives the counterpulse capacitor sufficient energy for the next counterpulse operation, although the polarity of the capacitor's voltage must be reversed before that can occur. By using a current-zero switch as the counterpulse start switch, the capacitor is disconnected from the circuit (with a full charge) when the load pulse is initiated, preventing the capacitor from depleting its energy store by discharging through the load. After the load pulse is terminated by reclosing the main opening switch, the polarity of the counterpulse capacitor voltage is reversed by discharging the capacitor through a small inductor and interrupting the discharge current oscillation at zero current and peak reversed voltage. The circuit enables high-power, high-repetition-rate operation with reusable switches and features total control (pulse-to-pulse) over output pulse initiation, duration, repetition rate, and, to some extent, risetime. 10 figs.

  15. Reversing-counterpulse repetitive-pulse inductive storage circuit

    DOE Patents [OSTI]

    Honig, Emanuel M.

    1987-01-01

    A high-power reversing-counterpulse repetitive-pulse inductive storage and transfer circuit includes an opening switch, a main energy storage coil, a counterpulse capacitor and a small inductor. After counterpulsing the opening switch off, the counterpulse capacitor is recharged by the main energy storage coil before the load pulse is initiated. This gives the counterpulse capacitor sufficient energy for the next counterpulse operation, although the polarity of the capacitor's voltage must be reversed before that can occur. By using a current-zero switch as the counterpulse start switch, the capacitor is disconnected from the circuit (with a full charge) when the load pulse is initiated, preventing the capacitor from depleting its energy store by discharging through the load. After the load pulse is terminated by reclosing the main opening switch, the polarity of the counterpulse capacitor voltage is reversed by discharging the capacitor through a small inductor and interrupting the discharge current oscillation at zero current and peak reversed voltage. The circuit enables high-power, high-repetition-rate operation with reusable switches and features total control (pulse-to-pulse) over output pulse initiation, duration, repetition rate, and, to some extent, risetime.

  16. Reversing-counterpulse repetitive-pulse inductive storage circuit

    DOE Patents [OSTI]

    Honig, E.M.

    1984-06-05

    A high power reversing-counterpulse repetitive-pulse inductive storage and transfer circuit includes an opening switch, a main energy storage coil, a counterpulse capacitor and a small inductor. After counterpulsing the opening switch off, the counterpulse capacitor is recharged by the main energy storage coil before the load pulse is initiated. This gives the counterpulse capacitor sufficient energy for the next counterpulse operation, although the polarity of the capacitor's voltage must be reversed before that can occur. By using a current-zero switch as the counterpulse start switch, the capacitor is disconnected from the circuit (with a full charge) when the load pulse is initiated, preventing the capacitor from depleting its energy store by discharging through the load. After the load pulse is terminated by reclosing the main opening switch, the polarity of the counterpulse capacitor voltage is reversed by discharging the capacitor through a small inductor and interrupting the discharge current oscillation at zero current and peak reversed voltage. The circuit enables high-power, high-repetition-rate operation with reusable switches and features total control (pulse-to-pulse) over output pulse initiation, duration, repetition rate, and, to some extent, risetime.

  17. Fault current limiter

    DOE Patents [OSTI]

    Darmann, Francis Anthony

    2013-10-08

    A fault current limiter (FCL) includes a series of high permeability posts for collectively define a core for the FCL. A DC coil, for the purposes of saturating a portion of the high permeability posts, surrounds the complete structure outside of an enclosure in the form of a vessel. The vessel contains a dielectric insulation medium. AC coils, for transporting AC current, are wound on insulating formers and electrically interconnected to each other in a manner such that the senses of the magnetic field produced by each AC coil in the corresponding high permeability core are opposing. There are insulation barriers between phases to improve dielectric withstand properties of the dielectric medium.

  18. Final Technical Report: PV Fault Detection Tool.

    SciTech Connect (OSTI)

    King, Bruce Hardison; Jones, Christian Birk

    2015-12-01

    The PV Fault Detection Tool project plans to demonstrate that the FDT can (a) detect catastrophic and degradation faults and (b) identify the type of fault. This will be accomplished by collecting fault signatures using different instruments and integrating this information to establish a logical controller for detecting, diagnosing and classifying each fault.

  19. Colorado Regional Faults

    DOE Data Explorer [Office of Scientific and Technical Information (OSTI)]

    Hussein, Khalid

    2012-02-01

    Citation Information: Originator: Earth Science &Observation Center (ESOC), CIRES, University of Colorado at Boulder Originator: Colorado Geological Survey (CGS) Publication Date: 2012 Title: Regional Faults Edition: First Publication Information: Publication Place: Earth Science & Observation Center, Cooperative Institute for Research in Environmental Science, University of Colorado, Boulder Publisher: Earth Science &Observation Center (ESOC), CIRES, University of Colorado at Boulder Description: This layer contains the regional faults of Colorado Spatial Domain: Extent: Top: 4543192.100000 m Left: 144385.020000 m Right: 754585.020000 m Bottom: 4094592.100000 m Contact Information: Contact Organization: Earth Science &Observation Center (ESOC), CIRES, University of Colorado at Boulder Contact Person: Khalid Hussein Address: CIRES, Ekeley Building Earth Science & Observation Center (ESOC) 216 UCB City: Boulder State: CO Postal Code: 80309-0216 Country: USA Contact Telephone: 303-492-6782 Spatial Reference Information: Coordinate System: Universal Transverse Mercator (UTM) WGS’1984 Zone 13N False Easting: 500000.00000000 False Northing: 0.00000000 Central Meridian: -105.00000000 Scale Factor: 0.99960000 Latitude of Origin: 0.00000000 Linear Unit: Meter Datum: World Geodetic System 1984 (WGS ’984) Prime Meridian: Greenwich Angular Unit: Degree Digital Form: Format Name: Shape file

  20. Dynamic pulse difference circuit

    DOE Patents [OSTI]

    Erickson, Gerald L.

    1978-01-01

    A digital electronic circuit of especial use for subtracting background activity pulses in gamma spectrometry comprises an up-down counter connected to count up with signal-channel pulses and to count down with background-channel pulses. A detector responsive to the count position of the up-down counter provides a signal when the up-down counter has completed one scaling sequence cycle of counts in the up direction. In an alternate embodiment, a detector responsive to the count position of the up-down counter provides a signal upon overflow of the counter.

  1. Base drive circuit

    DOE Patents [OSTI]

    Lange, A.C.

    1995-04-04

    An improved base drive circuit having a level shifter for providing bistable input signals to a pair of non-linear delays. The non-linear delays provide gate control to a corresponding pair of field effect transistors through a corresponding pair of buffer components. The non-linear delays provide delayed turn-on for each of the field effect transistors while an associated pair of transistors shunt the non-linear delays during turn-off of the associated field effect transistor. 2 figures.

  2. Base drive circuit

    DOE Patents [OSTI]

    Lange, Arnold C.

    1995-01-01

    An improved base drive circuit (10) having a level shifter (24) for providing bistable input signals to a pair of non-linear delays (30, 32). The non-linear delays (30, 32) provide gate control to a corresponding pair of field effect transistors (100, 106) through a corresponding pair of buffer components (88, 94). The non-linear delays (30, 32) provide delayed turn-on for each of the field effect transistors (100, 106) while an associated pair of transistors (72, 80) shunt the non-linear delays (30, 32) during turn-off of the associated field effect transistor (100, 106).

  3. Sequential circuit design for radiation hardened multiple voltage integrated circuits

    DOE Patents [OSTI]

    Clark, Lawrence T.; McIver, III, John K.

    2009-11-24

    The present invention includes a radiation hardened sequential circuit, such as a bistable circuit, flip-flop or other suitable design that presents substantial immunity to ionizing radiation while simultaneously maintaining a low operating voltage. In one embodiment, the circuit includes a plurality of logic elements that operate on relatively low voltage, and a master and slave latches each having storage elements that operate on a relatively high voltage.

  4. Jitter compensation circuit

    DOE Patents [OSTI]

    Sullivan, J.S.; Ball, D.G.

    1997-09-09

    The instantaneous V{sub co} signal on a charging capacitor is sampled and the charge voltage on capacitor C{sub o} is captured just prior to its discharge into the first stage of magnetic modulator. The captured signal is applied to an averaging circuit with a long time constant and to the positive input terminal of a differential amplifier. The averaged V{sub co} signal is split between a gain stage (G = 0.975) and a feedback stage that determines the slope of the voltage ramp applied to the high speed comparator. The 97.5% portion of the averaged V{sub co} signal is applied to the negative input of a differential amplifier gain stage (G = 10). The differential amplifier produces an error signal by subtracting 97.5% of the averaged V{sub co} signal from the instantaneous value of sampled V{sub co} signal and multiplying the difference by ten. The resulting error signal is applied to the positive input of a high speed comparator. The error signal is then compared to a voltage ramp that is proportional to the averaged V{sub co} values squared divided by the total volt-second product of the magnetic compression circuit. 11 figs.

  5. Jitter compensation circuit

    DOE Patents [OSTI]

    Sullivan, James S.; Ball, Don G.

    1997-01-01

    The instantaneous V.sub.co signal on a charging capacitor is sampled and the charge voltage on capacitor C.sub.o is captured just prior to its discharge into the first stage of magnetic modulator. The captured signal is applied to an averaging circuit with a long time constant and to the positive input terminal of a differential amplifier. The averaged V.sub. co signal is split between a gain stage (G=0.975) and a feedback stage that determines the slope of the voltage ramp applied to the high speed comparator. The 97.5% portion of the averaged V.sub.co signal is applied to the negative input of a differential amplifier gain stage (G=10). The differential amplifier produces an error signal by subtracting 97.5% of the averaged V.sub.co signal from the instantaneous value of sampled V.sub.co signal and multiplying the difference by ten. The resulting error signal is applied to the positive input of a high speed comparator. The error signal is then compared to a voltage ramp that is proportional to the averaged V.sub.co values squared divided by the total volt-second product of the magnetic compression circuit.

  6. Magnetic compression laser driving circuit

    DOE Patents [OSTI]

    Ball, Don G.; Birx, Dan; Cook, Edward G.

    1993-01-01

    A magnetic compression laser driving circuit is disclosed. The magnetic compression laser driving circuit compresses voltage pulses in the range of 1.5 microseconds at 20 Kilovolts of amplitude to pulses in the range of 40 nanoseconds and 60 Kilovolts of amplitude. The magnetic compression laser driving circuit includes a multi-stage magnetic switch where the last stage includes a switch having at least two turns which has larger saturated inductance with less core material so that the efficiency of the circuit and hence the laser is increased.

  7. Magnetic compression laser driving circuit

    DOE Patents [OSTI]

    Ball, D.G.; Birx, D.; Cook, E.G.

    1993-01-05

    A magnetic compression laser driving circuit is disclosed. The magnetic compression laser driving circuit compresses voltage pulses in the range of 1.5 microseconds at 20 kilovolts of amplitude to pulses in the range of 40 nanoseconds and 60 kilovolts of amplitude. The magnetic compression laser driving circuit includes a multi-stage magnetic switch where the last stage includes a switch having at least two turns which has larger saturated inductance with less core material so that the efficiency of the circuit and hence the laser is increased.

  8. PRECISION TIME-DELAY CIRCUIT

    DOE Patents [OSTI]

    Creveling, R.

    1959-03-17

    A tine-delay circuit which produces a delay time in d. The circuit a capacitor, an te back resistance, connected serially with the anode of the diode going to ground. At the start of the time delay a negative stepfunction is applied to the series circuit and initiates a half-cycle transient oscillatory voltage terminated by a transient oscillatory voltage of substantially higher frequency. The output of the delay circuit is taken at the junction of the inductor and diode where a sudden voltage rise appears after the initiation of the higher frequency transient oscillations.

  9. Pipeline coating impedance effects on powerline fault current coupling

    SciTech Connect (OSTI)

    Dabkowski, J.

    1989-12-01

    Prior research leading to the development of predictive electromagnetic coupling computer codes has shown that the coating conductance is the principal factor in determining the response of a pipeline to magnetic induction from an overhead power transmission line. Under power line fault conditions, a high voltage may stress the coating causing a significant change in its conductance, and hence, the coupling response. Based upon laboratory experimentation and analysis, a model has been developed which allows prediction of the modified coating characteristics when subjected to high voltage during fault situations. Another program objective was the investigation of a method to determine the high voltage behavior of an existing coating from low voltage in situ field measurements. Such a method appeared conceptually feasible for non-porous coatings whose conductance is primarily a result of current leakage through existing holidays. However, limited testing has shown that difficulties in determining the steel-electrolyte capacitance limit the application of the method Methods for field measurement of the pipeline coating conductance were also studied for both dc ad ac signal excitation. Ac techniques offer the advantage that cathodic protection current interruption is not required, thus eliminating depolarization effects. However, ac field measurement techniques need additional refinement before these methods can be generally applied. 53 figs.

  10. Photoconductive circuit element reflectometer

    DOE Patents [OSTI]

    Rauscher, C.

    1987-12-07

    A photoconductive reflectometer for characterizing semiconductor devices at millimeter wavelength frequencies where a first photoconductive circuit element (PCE) is biased by a direct current voltage source and produces short electrical pulses when excited into conductance by short first laser light pulses. The electrical pulses are electronically conditioned to improve the frequency related amplitude characteristics of the pulses which thereafter propagate along a transmission line to a device under test. Second PCEs are connected along the transmission line to sample the signals on the transmission line when excited into conductance by short second laser light pulses, spaced apart in time a determinable period from the first laser light pulses. Electronic filters connected to each of the second PCEs act as low-pass filters and remove parasitic interference from the sampled signals and output the sampled signals in the form of slowed-motion images of the signals on the transmission line. 4 figs.

  11. Photoconductive circuit element reflectometer

    DOE Patents [OSTI]

    Rauscher, Christen (Alexandria, VA)

    1990-01-01

    A photoconductive reflectometer for characterizing semiconductor devices at millimeter wavelength frequencies where a first photoconductive circuit element (PCE) is biased by a direct current voltage source and produces short electrical pulses when excited into conductance by short first laser light pulses. The electrical pulses are electronically conditioned to improve the frequency related amplitude characteristics of the pulses which thereafter propagate along a transmission line to a device under test. Second PCEs are connected along the transmission line to sample the signals on the transmission line when excited into conductance by short second laser light pulses, spaced apart in time a variable period from the first laser light pulses. Electronic filters connected to each of the second PCEs act as low-pass filters and remove parasitic interference from the sampled signals and output the sampled signals in the form of slowed-motion images of the signals on the transmission line.

  12. ELECTRONIC PULSE SCALING CIRCUITS

    DOE Patents [OSTI]

    Cooke-Yarborough, E.H.

    1958-11-18

    Electronic pulse scaling circults of the klnd comprlsing a serles of bi- stable elements connected ln sequence, usually in the form of a rlng so as to be cycllcally repetitive at the highest scallng factor, are described. The scaling circuit comprises a ring system of bi-stable elements each arranged on turn-off to cause, a succeeding element of the ring to be turned-on, and one being arranged on turn-off to cause a further element of the ring to be turned-on. In addition, separate means are provided for applying a turn-off pulse to all the elements simultaneously, and for resetting the elements to a starting condition at the end of each cycle.

  13. ELECTRONIC INTEGRATING CIRCUIT

    DOE Patents [OSTI]

    Englemann, R.H.

    1963-08-20

    An electronic integrating circuit using a transistor with a capacitor connected between the emitter and collector through which the capacitor discharges at a rate proportional to the input current at the base is described. Means are provided for biasing the base with an operating bias and for applying a voltage pulse to the capacitor for charging to an initial voltage. A current dividing diode is connected between the base and emitter of the transistor, and signal input terminal means are coupled to the juncture of the capacitor and emitter and to the base of the transistor. At the end of the integration period, the residual voltage on said capacitor is less by an amount proportional to the integral of the input signal. Either continuous or intermittent periods of integration are provided. (AEC)

  14. Modeling cortical circuits.

    SciTech Connect (OSTI)

    Rohrer, Brandon Robinson; Rothganger, Fredrick H.; Verzi, Stephen J.; Xavier, Patrick Gordon

    2010-09-01

    The neocortex is perhaps the highest region of the human brain, where audio and visual perception takes place along with many important cognitive functions. An important research goal is to describe the mechanisms implemented by the neocortex. There is an apparent regularity in the structure of the neocortex [Brodmann 1909, Mountcastle 1957] which may help simplify this task. The work reported here addresses the problem of how to describe the putative repeated units ('cortical circuits') in a manner that is easily understood and manipulated, with the long-term goal of developing a mathematical and algorithmic description of their function. The approach is to reduce each algorithm to an enhanced perceptron-like structure and describe its computation using difference equations. We organize this algorithmic processing into larger structures based on physiological observations, and implement key modeling concepts in software which runs on parallel computing hardware.

  15. Comparison of Cenozoic Faulting at the Savannah River Site to Fault Characteristics of the Atlantic Coast Fault Province: Implications for Fault Capability

    SciTech Connect (OSTI)

    Cumbest, R.J.

    2000-11-14

    This study compares the faulting observed on the Savannah River Site and vicinity with the faults of the Atlantic Coastal Fault Province and concludes that both sets of faults exhibit the same general characteristics and are closely associated. Based on the strength of this association it is concluded that the faults observed on the Savannah River Site and vicinity are in fact part of the Atlantic Coastal Fault Province. Inclusion in this group means that the historical precedent established by decades of previous studies on the seismic hazard potential for the Atlantic Coastal Fault Province is relevant to faulting at the Savannah River Site. That is, since these faults are genetically related the conclusion of ''not capable'' reached in past evaluations applies.In addition, this study establishes a set of criteria by which individual faults may be evaluated in order to assess their inclusion in the Atlantic Coast Fault Province and the related association of the ''not capable'' conclusion.

  16. The Owens Valley Fault Zone Eastern California and Surface Faulting...

    Open Energy Info (EERE)

    it steps 3 km to the left and continues northwest across Crater Mountain and through Big Pine. The fault has an overall strike of 340 and dip of 8015 ENE. Surface...

  17. Fault Detection Tool Project: Automatic Discovery of Faults using Machine

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Learning Fault Detection Tool Project: Automatic Discovery of Faults using Machine Learning - Sandia Energy Energy Search Icon Sandia Home Locations Contact Us Employee Locator Energy & Climate Secure & Sustainable Energy Future Stationary Power Energy Conversion Efficiency Solar Energy Wind Energy Water Power Supercritical CO2 Geothermal Natural Gas Safety, Security & Resilience of the Energy Infrastructure Energy Storage Nuclear Power & Engineering Grid Modernization

  18. Demultiplexer circuit for neural stimulation

    DOE Patents [OSTI]

    Wessendorf, Kurt O; Okandan, Murat; Pearson, Sean

    2012-10-09

    A demultiplexer circuit is disclosed which can be used with a conventional neural stimulator to extend the number of electrodes which can be activated. The demultiplexer circuit, which is formed on a semiconductor substrate containing a power supply that provides all the dc electrical power for operation of the circuit, includes digital latches that receive and store addressing information from the neural stimulator one bit at a time. This addressing information is used to program one or more 1:2.sup.N demultiplexers in the demultiplexer circuit which then route neural stimulation signals from the neural stimulator to an electrode array which is connected to the outputs of the 1:2.sup.N demultiplexer. The demultiplexer circuit allows the number of individual electrodes in the electrode array to be increased by a factor of 2.sup.N with N generally being in a range of 2-4.

  19. Hot Pot Detail - Evidence of Quaternary Faulting

    DOE Data Explorer [Office of Scientific and Technical Information (OSTI)]

    Lane, Michael

    Compilation of published data, field observations and photo interpretation relevant to Quaternary faulting at Hot Pot.

  20. Hot Pot Detail - Evidence of Quaternary Faulting

    DOE Data Explorer [Office of Scientific and Technical Information (OSTI)]

    Lane, Michael

    2013-06-27

    Compilation of published data, field observations and photo interpretation relevant to Quaternary faulting at Hot Pot.

  1. Cell boundary fault detection system

    DOE Patents [OSTI]

    Archer, Charles Jens; Pinnow, Kurt Walter; Ratterman, Joseph D.; Smith, Brian Edward

    2009-05-05

    A method determines a nodal fault along the boundary, or face, of a computing cell. Nodes on adjacent cell boundaries communicate with each other, and the communications are analyzed to determine if a node or connection is faulty.

  2. Fault Controlled | Open Energy Information

    Open Energy Info (EERE)

    has been provided for this term. Add a Definition This classification is used if the literature describes the geothermal fluids as being controlled by faults, but not in detail....

  3. PHOTOSENSITIVE RELAY CONTROL CIRCUIT

    DOE Patents [OSTI]

    Martin, C.F.

    1958-01-14

    adapted for the measurement of the time required for an oscillating member to pass through a preselected number of oscillations, after being damped to a certain maximum amplitude of oscillation. A mirror is attached to the moving member and directs light successively to a photocell which is part of a trigger unit and to first and second photocells which are part of a starter unit, as the member swings to its maximum amplitude. The starter and trigger units comprise thyratrons and relays so interconnected that the trigger circuit, although generating a counter pulse, does not register a count in the counter when the light traverses both photocells of the starter unit. When the amplitude of oscillation of the member decreases to where the second photocell is not transversed, the triggei pulse is received by the counter. The counter taen operates to register the desired number of oscillations and initiates and terminates a timer for measuring the time irterval for the preselected number of oscillations.

  4. Integrated circuits, and design and manufacture thereof

    DOE Patents [OSTI]

    Auracher, Stefan; Pribbernow, Claus; Hils, Andreas

    2006-04-18

    A representation of a macro for an integrated circuit layout. The representation may define sub-circuit cells of a module. The module may have a predefined functionality. The sub-circuit cells may include at least one reusable circuit cell. The reusable circuit cell may be configured such that when the predefined functionality of the module is not used, the reusable circuit cell is available for re-use.

  5. Picture of the Week: Circuits of light

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    5 Circuits of light This artistic conceptualization of circuits made of light represents a new capability that could lead to advanced sensor systems, quantum information processing technology, and more. March 25, 2016 circuits of light artist's conception Circuits of light: artist's conception View a super-large 300 dpi version of this image on our Lab Flickr site. Circuits of light This artistic conceptualization of circuits made of light represents a new capability that could lead to advanced

  6. Counterpulse railgun energy recovery circuit

    DOE Patents [OSTI]

    Honig, E.M.

    1984-09-28

    The invention presented relates to a high-power pulsing circuit and more particularly to a repetitive pulse inductive energy storage and transfer circuit for an electromagnetic launcher. In an electromagnetic launcher such as a railgun for propelling a projectile at high velocity, a counterpulse energy recovery circuit is employed to transfer stored inductive energy from a source inductor to the railgun inductance to propel the projectile down the railgun. Switching circuitry and an energy transfer capacitor are used to switch the energy back to the source inductor in readiness for a repetitive projectile propelling cycle.

  7. Overpulse railgun energy recovery circuit

    DOE Patents [OSTI]

    Honig, E.M.

    1984-09-28

    The invention presented relates to a high-power pulsing circuit and more particularly to a repetitive pulse inductive energy storage and transfer circuit for an electromagnetic launcher. In an electromagnetic launcher such as a railgun for propelling a projectile at high velocity, an overpulse energy recovery circuit is employed to transfer stored inductive energy from a source inductor to the railgun inductance to propel the projectile down the railgun. Switching circuitry and an energy transfer capacitor are used to switch the energy back to the source inductor in readiness for a repetitive projectile propelling cycle.

  8. Solid-state circuit breaker with current-limiting characteristic using a superconducting coil

    DOE Patents [OSTI]

    Boenig, H.J.

    1982-08-16

    A thyristor bridge interposes an ac source and a load. A series connected DC source and superconducting coil within the bridge biases the thyristors thereof so as to permit bidirectional ac current flow therethrough under normal operating conditions. Upon a fault condition a control circuit triggers the thyristors so as to reduce ac current flow therethrough to zero in less than two eyeles and to open the bridge thereafter. Upon a temporary overload condition the control circuit triggers the thyristors so as to limit ac current flow therethrough to an acceptable level.

  9. Solid-state circuit breaker with current limiting characteristic using a superconducting coil

    DOE Patents [OSTI]

    Boenig, Heinrich J.

    1984-01-01

    A thyristor bridge interposes an ac source and a load. A series connected DC source and superconducting coil within the bridge biases the thyristors thereof so as to permit bidirectional ac current flow therethrough under normal operating conditions. Upon a fault condition a control circuit triggers the thyristors so as to reduce ac current flow therethrough to zero in less than two cycles and to open the bridge thereafter. Upon a temporary overload condition the control circuit triggers the thyristors so as to limit ac current flow therethrough to an acceptable level.

  10. printed-circuit heat exchanger PCHE

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    printed-circuit heat exchanger PCHE - Sandia Energy Energy Search Icon Sandia Home ... SunShot Grand Challenge: Regional Test Centers printed-circuit heat exchanger PCHE Home...

  11. Reverse engineering of integrated circuits

    DOE Patents [OSTI]

    Chisholm, Gregory H.; Eckmann, Steven T.; Lain, Christopher M.; Veroff, Robert L.

    2003-01-01

    Software and a method therein to analyze circuits. The software comprises several tools, each of which perform particular functions in the Reverse Engineering process. The analyst, through a standard interface, directs each tool to the portion of the task to which it is most well suited, rendering previously intractable problems solvable. The tools are generally used iteratively to produce a successively more abstract picture of a circuit, about which incomplete a priori knowledge exists.

  12. Cost of Power Interruptions to Electricity Consumers in the UnitedStates (U.S.)

    SciTech Connect (OSTI)

    Hamachi LaCommare, Kristina; Eto, Joseph H.

    2006-02-16

    The massive electric power blackout in the northeastern U.S.and Canada on August 14-15, 2003 catalyzed discussions about modernizingthe U.S. electricity grid. Industry sources suggested that investments of$50 to $100 billion would be needed. This work seeks to better understandan important piece of information that has been missing from thesediscussions: What do power interruptions and fluctuations in powerquality (power-quality events) cost electricity consumers? We developed abottom-up approach for assessing the cost to U.S. electricity consumersof power interruptions and power-quality events (referred to collectivelyas "reliability events"). The approach can be used to help assess thepotential benefits of investments in improving the reliability of thegrid. We developed a new estimate based on publicly availableinformation, and assessed how uncertainties in these data affect thisestimate using sensitivity analysis.

  13. Thermal fatigue due to beam interruptions in a Lead-Bismuth cooled ATW blanket

    SciTech Connect (OSTI)

    Dunn, F.

    2000-11-15

    Thermal fatigue consequences of frequent accelerator beam interruptions are quantified for both sodium and lead-bismuth cooled blankets in current designs for accelerator transmutation of waste devices. Temperature response was calculated using the SASSYS-1 systems analysis code for an immediate drop in beam current from full power to zero. Coolant temperatures from SASSYS-1 were fed into a multi-node structure temperature calculation to obtain thermal strains for various structural components. Fatigue curves from the American Society of Mechanical Engineers Boiler and Pressure Vessel Code were used to determine the number of cycles that these components could endure, based on these thermal strains. Beam interruption frequency data from a current accelerator were used to estimate design lifetimes for components. Mitigation options for reducing thermal fatigue are discussed.

  14. Tunable circuit for tunable capacitor devices

    DOE Patents [OSTI]

    Rivkina, Tatiana; Ginley, David S.

    2006-09-19

    A tunable circuit (10) for a capacitively tunable capacitor device (12) is provided. The tunable circuit (10) comprises a tunable circuit element (14) and a non-tunable dielectric element (16) coupled to the tunable circuit element (16). A tunable capacitor device (12) and a method for increasing the figure of merit in a tunable capacitor device (12) are also provided.

  15. Cell boundary fault detection system

    DOE Patents [OSTI]

    Archer, Charles Jens; Pinnow, Kurt Walter; Ratterman, Joseph D.; Smith, Brian Edward

    2011-04-19

    An apparatus and program product determine a nodal fault along the boundary, or face, of a computing cell. Nodes on adjacent cell boundaries communicate with each other, and the communications are analyzed to determine if a node or connection is faulty.

  16. HPCGridSANDReport

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    5916 Unlimited Release Printed July 2013 Series and Parallel Arc-Fault Circuit Interrupter Tests Jay Johnson, boB Gudgel, Andrew Meares, and Armando Fresquez Prepared by Sandia...

  17. Nuclear sensor signal processing circuit

    DOE Patents [OSTI]

    Kallenbach, Gene A.; Noda, Frank T.; Mitchell, Dean J.; Etzkin, Joshua L.

    2007-02-20

    An apparatus and method are disclosed for a compact and temperature-insensitive nuclear sensor that can be calibrated with a non-hazardous radioactive sample. The nuclear sensor includes a gamma ray sensor that generates tail pulses from radioactive samples. An analog conditioning circuit conditions the tail-pulse signals from the gamma ray sensor, and a tail-pulse simulator circuit generates a plurality of simulated tail-pulse signals. A computer system processes the tail pulses from the gamma ray sensor and the simulated tail pulses from the tail-pulse simulator circuit. The nuclear sensor is calibrated under the control of the computer. The offset is adjusted using the simulated tail pulses. Since the offset is set to zero or near zero, the sensor gain can be adjusted with a non-hazardous radioactive source such as, for example, naturally occurring radiation and potassium chloride.

  18. Vertically Integrated Circuits at Fermilab

    SciTech Connect (OSTI)

    Deptuch, Grzegorz; Demarteau, Marcel; Hoff, James; Lipton, Ronald; Shenai, Alpana; Trimpl, Marcel; Yarema, Raymond; Zimmerman, Tom; /Fermilab

    2009-01-01

    The exploration of the vertically integrated circuits, also commonly known as 3D-IC technology, for applications in radiation detection started at Fermilab in 2006. This paper examines the opportunities that vertical integration offers by looking at various 3D designs that have been completed by Fermilab. The emphasis is on opportunities that are presented by through silicon vias (TSV), wafer and circuit thinning and finally fusion bonding techniques to replace conventional bump bonding. Early work by Fermilab has led to an international consortium for the development of 3D-IC circuits for High Energy Physics. The consortium has submitted over 25 different designs for the Fermilab organized MPW run organized for the first time.

  19. Sensor/source electrometer circuit

    SciTech Connect (OSTI)

    Hughes, W.J.

    1991-12-31

    A multiple decade electrometer circuit is claimed which can measure low input currents or act as a current source and is comprised of a microprocessor controlled digital to analog converters to derive individual decades. A plurality of decades are created by multiple D-A voltage sources which generate electrometer currents through scaled resistors. After a first series of decades of current are successively produced, the converters are 10 cycled to generate current through new resistors scaled to produce another series decades of current. In this manner, the electrometer circuit generates or senses a plurality of decades of current without significant scale change.

  20. Circuit breaker lock out assembly

    DOE Patents [OSTI]

    Gordy, Wade T.

    1984-01-01

    A lock out assembly for a circuit breaker which consists of a generally step-shaped unitary base with an aperture in the small portion of the step-shaped base and a roughly "S" shaped retaining pin which loops through the large portion of the step-shaped base. The lock out assembly is adapted to fit over a circuit breaker with the handle switch projecting through the aperture, and the retaining pin projecting into an opening of the handle switch, preventing removal.

  1. Circuit breaker lock out assembly

    DOE Patents [OSTI]

    Gordy, W.T.

    1983-05-18

    A lock out assembly for a circuit breaker which consists of a generally step-shaped unitary base with an aperture in the small portion of the step-shaped base and a roughly S shaped retaining pin which loops through the large portion of the step-shaped base. The lock out assembly is adapted to fit over a circuit breaker with the handle switch projecting through the aperture, and the retaining pin projecting into an opening of the handle switch, preventing removal.

  2. Electric Power Interruption Cost Estimates for Individual Industries, Sectors, and U.S. Economy

    SciTech Connect (OSTI)

    Balducci, Patrick J.; Roop, Joseph M.; Schienbein, Lawrence A.; DeSteese, John G.; Weimar, Mark R.

    2002-02-27

    During the last 20 years, utilities and researchers have begun to understand the value in the collection and analysis of interruption cost data. The continued investigation of the monetary impact of power outages will facilitate the advancement of the analytical methods used to measure the costs and benefits from the perspective of the energy consumer. More in-depth analysis may be warranted because of the privatization and deregulation of power utilities, price instability in certain regions of the U.S. and the continued evolution of alternative auxiliary power systems.

  3. Understanding the cost of power interruptions to U.S. electricity consumers

    SciTech Connect (OSTI)

    LaCommare, Kristina Hamachi; Eto, Joseph H.

    2004-09-01

    The massive electric power blackout in the northeastern United States and Canada on August 14-15, 2003 resulted in the U.S. electricity system being called ''antiquated'' and catalyzed discussions about modernizing the grid. Industry sources suggested that investments of $50 to $100 billion would be needed. This report seeks to quantify an important piece of information that has been missing from these discussions: how much do power interruptions and fluctuations in power quality (power-quality events) cost U.S. electricity consumers? Accurately estimating this cost will help assess the potential benefits of investments in improving the reliability of the grid. We develop a comprehensive end-use framework for assessing the cost to U.S. electricity consumers of power interruptions and power-quality events (referred to collectively as ''reliability events''). The framework expresses these costs as a function of: (1) Number of customers by type in a region; (2) Frequency and type of reliability events experienced annually (including both power interruptions and power-quality events) by these customers; (3) Cost of reliability events; and (4) Vulnerability of customers to these events. The framework is designed so that its cost estimate can be improved as additional data become available. Using our framework, we estimate that the national cost of power interruptions is about $80 billion annually, based on the best information available in the public domain. However, there are large gaps in and significant uncertainties about the information currently available. Notably, we were not able to develop an estimate of power-quality events. Sensitivity analysis of some of these uncertainties suggests that the total annual cost could range from less than $30 billion to more than $130 billion. Because of this large range and the enormous cost of the decisions that may be based on this estimate, we encourage policy makers, regulators, and industry to jointly under take the

  4. Decreasing Beam Auto Tuning Interruption Events with In-Situ Chemical Cleaning on Axcelis GSD

    SciTech Connect (OSTI)

    Fuchs, Dieter; Spreitzer, Stefan; Vogl, Josef [Infineon Technologies AG., Wernerwerkstr.2, 93049 Regensburg (Germany); Bishop, Steve; Eldridge, David; Kaim, Robert [ATMI Inc., 7 Commerce Drive, Danbury, CT 06810 (United States)

    2008-11-03

    Ion beam auto tuning time and success rate are often major factors in the utilization and productivity of ion implanters. Tuning software frequently fails to meet specified setup times or recipe parameters, causing production stoppages and requiring manual intervention. Build-up of conductive deposits in the arc chamber and extraction gap can be one of the main causes of auto tuning problems. The deposits cause glitching and ion beam instabilities, which lead to errors in the software optimization routines. Infineon Regensburg has been testing use of XeF{sub 2}, an in-situ chemical cleaning reagent, with positive results in reducing auto tuning interruption events.

  5. Inverter Ground Fault Overvoltage Testing

    SciTech Connect (OSTI)

    Hoke, Andy; Nelson, Austin; Chakraborty, Sudipta; Chebahtah, Justin; Wang, Trudie; McCarty, Michael

    2015-08-12

    This report describes testing conducted at NREL to determine the duration and magnitude of transient overvoltages created by several commercial PV inverters during ground fault conditions. For this work, a test plan developed by the Forum on Inverter Grid Integration Issues (FIGII) has been implemented in a custom test setup at NREL. Load rejection overvoltage test results were reported previously in a separate technical report.

  6. Driver circuit for solid state light sources

    DOE Patents [OSTI]

    Palmer, Fred; Denvir, Kerry; Allen, Steven

    2016-02-16

    A driver circuit for a light source including one or more solid state light sources, a luminaire including the same, and a method of so driving the solid state light sources are provided. The driver circuit includes a rectifier circuit that receives an alternating current (AC) input voltage and provides a rectified AC voltage. The driver circuit also includes a switching converter circuit coupled to the light source. The switching converter circuit provides a direct current (DC) output to the light source in response to the rectified AC voltage. The driver circuit also includes a mixing circuit, coupled to the light source, to switch current through at least one solid state light source of the light source in response to each of a plurality of consecutive half-waves of the rectified AC voltage.

  7. Post regulation circuit with energy storage

    DOE Patents [OSTI]

    Ball, Don G.; Birx, Daniel L.; Cook, Edward G.

    1992-01-01

    A charge regulation circuit provides regulation of an unregulated voltage supply and provides energy storage. The charge regulation circuit according to the present invention provides energy storage without unnecessary dissipation of energy through a resistor as in prior art approaches.

  8. Fault Current Limiters (FCL) Fact Sheet | Department of Energy

    Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

    Fault Current Limiters (FCL) Fact Sheet Fault Current Limiters (FCL) Fact Sheet Plugging America Into the Future of Power: Superconducting & Solid-state Power Equipment What are Fault Current Limiters Why do we need Fault Current Limiters What are the benefits to utilities Fault Current Limiter projects Fault Current Limiters (926.42 KB) More Documents & Publications An Assessment of Fault Current Limiter Testing Requirements Superconductivity Program Overview Superconductivity for

  9. Delta connected resonant snubber circuit

    DOE Patents [OSTI]

    Lai, Jih-Sheng; Peng, Fang Zheng; Young, Sr., Robert W.; Ott, Jr., George W.

    1998-01-01

    A delta connected, resonant snubber-based, soft switching, inverter circuit achieves lossless switching during dc-to-ac power conversion and power conditioning with minimum component count and size. Current is supplied to the resonant snubber branches solely by the dc supply voltage through the main inverter switches and the auxiliary switches. Component count and size are reduced by use of a single semiconductor switch in the resonant snubber branches. Component count is also reduced by maximizing the use of stray capacitances of the main switches as parallel resonant capacitors. Resonance charging and discharging of the parallel capacitances allows lossless, zero voltage switching. In one embodiment, circuit component size and count are minimized while achieving lossless, zero voltage switching within a three-phase inverter.

  10. Delta connected resonant snubber circuit

    DOE Patents [OSTI]

    Lai, J.S.; Peng, F.Z.; Young, R.W. Sr.; Ott, G.W. Jr.

    1998-01-20

    A delta connected, resonant snubber-based, soft switching, inverter circuit achieves lossless switching during dc-to-ac power conversion and power conditioning with minimum component count and size. Current is supplied to the resonant snubber branches solely by the dc supply voltage through the main inverter switches and the auxiliary switches. Component count and size are reduced by use of a single semiconductor switch in the resonant snubber branches. Component count is also reduced by maximizing the use of stray capacitances of the main switches as parallel resonant capacitors. Resonance charging and discharging of the parallel capacitances allows lossless, zero voltage switching. In one embodiment, circuit component size and count are minimized while achieving lossless, zero voltage switching within a three-phase inverter. 36 figs.

  11. Ionization tube simmer current circuit

    DOE Patents [OSTI]

    Steinkraus, R.F. Jr.

    1994-12-13

    A highly efficient flash lamp simmer current circuit utilizes a fifty percent duty cycle square wave pulse generator to pass a current over a current limiting inductor to a full wave rectifier. The DC output of the rectifier is then passed over a voltage smoothing capacitor through a reverse current blocking diode to a flash lamp tube to sustain ionization in the tube between discharges via a small simmer current. An alternate embodiment of the circuit combines the pulse generator and inductor in the form of an FET off line square wave generator with an impedance limited step up output transformer which is then applied to the full wave rectifier as before to yield a similar simmer current. 6 figures.

  12. Ionization tube simmer current circuit

    DOE Patents [OSTI]

    Steinkraus, Jr., Robert F.

    1994-01-01

    A highly efficient flash lamp simmer current circuit utilizes a fifty percent duty cycle square wave pulse generator to pass a current over a current limiting inductor to a full wave rectifier. The DC output of the rectifier is then passed over a voltage smoothing capacitor through a reverse current blocking diode to a flash lamp tube to sustain ionization in the tube between discharges via a small simmer current. An alternate embodiment of the circuit combines the pulse generator and inductor in the form of an FET off line square wave generator with an impedance limited step up output transformer which is then applied to the full wave rectifier as before to yield a similar simmer current.

  13. Restoration and testing of an HTS fault current controller

    SciTech Connect (OSTI)

    Waynert, J. A.; Boenig, H.; Mielke, C. H.; Willis, J. O.; Burley, B. L.

    2002-01-01

    A three-phase, 1200 A, 12.5 kV fault current controller using three HTS 4 mH coils, was built by industry and tested in 1999 at the Center Substation of Southern California Edison in Norwalk, CA. During the testing, it appeared that each of the three single-phase units had experienced a voltage breakdown, one externally and two internally. Los Alamos National Laboratory (LANL) was asked by DOE to restore the operation of the fault current controller provided the HTS coils had not been damaged during the initial substation tests. When the internally-failed coil vacuum vessels were opened it became evident that in these two vessels, a flashover had occurred at the high voltage bus section leading to the terminals of the superconducting coil. An investigation into the failure mechanism resulted in six possible causes for the flashover. Based on these causes, the high voltage bus was completely redesigned. Single-phase tests were successfully performed on the modified unit at a 13.7 kV LANL substation. This paper presents the postulated voltage flashover failure mechanisms, the new high voltage bus design which mitigates the failure mechanisms, the sequence of tests used to validate the new design, and finally, the results of variable load and short-circuit tests with the single-phase unit operating on the LANL 13.7 kV substation.

  14. Photoconductive circuit element pulse generator

    DOE Patents [OSTI]

    Rauscher, Christen

    1989-01-01

    A pulse generator for characterizing semiconductor devices at millimeter wavelength frequencies where a photoconductive circuit element (PCE) is biased by a direct current voltage source and produces short electrical pulses when excited into conductance by short laser light pulses. The electrical pulses are electronically conditioned to improve the frequency related amplitude characteristics of the pulses which thereafter propagate along a transmission line to a device under test.

  15. Overpulse railgun energy recovery circuit

    DOE Patents [OSTI]

    Honig, Emanuel M.

    1989-01-01

    In an electromagnetic launcher such as a railgun for propelling a projectile at high velocity, an overpulse energy recovery circuit is employed to transfer stored inductive energy from a source inductor to the railgun inductance to propel the projectile down the railgun. Switching circuitry and an energy transfer capacitor are used to switch the energy back to the source inductor in readiness for a repetitive projectile propelling cycle.

  16. Counterpulse railgun energy recovery circuit

    DOE Patents [OSTI]

    Honig, Emanuel M.

    1986-01-01

    In an electromagnetic launcher such as a railgun for propelling a projectile at high velocity, a counterpulse energy recovery circuit is employed to transfer stored inductive energy from a source inductor to the railgun inductance to propel the projectile down the railgun. Switching circuitry and an energy transfer capacitor are used to switch the energy back to the source inductor in readiness for a repetitive projectile propelling cycle.

  17. Additive manufacturing of hybrid circuits

    DOE Public Access Gateway for Energy & Science Beta (PAGES Beta)

    Bell, Nelson S.; Sarobol, Pylin; Cook, Adam; Clem, Paul G.; Keicher, David M.; Hirschfeld, Deidre; Hall, Aaron Christopher

    2016-03-26

    There is a rising interest in developing functional electronics using additively manufactured components. Considerations in materials selection and pathways to forming hybrid circuits and devices must demonstrate useful electronic function; must enable integration; and must complement the complex shape, low cost, high volume, and high functionality of structural but generally electronically passive additively manufactured components. This article reviews several emerging technologies being used in industry and research/development to provide integration advantages of fabricating multilayer hybrid circuits or devices. First, we review a maskless, noncontact, direct write (DW) technology that excels in the deposition of metallic colloid inks for electrical interconnects.more » Second, we review a complementary technology, aerosol deposition (AD), which excels in the deposition of metallic and ceramic powder as consolidated, thick conformal coatings and is additionally patternable through masking. As a result, we show examples of hybrid circuits/devices integrated beyond 2-D planes, using combinations of DW or AD processes and conventional, established processes.« less

  18. Fault-tolerant dynamic task graph scheduling

    SciTech Connect (OSTI)

    Kurt, Mehmet C.; Krishnamoorthy, Sriram; Agrawal, Kunal; Agrawal, Gagan

    2014-11-16

    In this paper, we present an approach to fault tolerant execution of dynamic task graphs scheduled using work stealing. In particular, we focus on selective and localized recovery of tasks in the presence of soft faults. We elicit from the user the basic task graph structure in terms of successor and predecessor relationships. The work stealing-based algorithm to schedule such a task graph is augmented to enable recovery when the data and meta-data associated with a task get corrupted. We use this redundancy, and the knowledge of the task graph structure, to selectively recover from faults with low space and time overheads. We show that the fault tolerant design retains the essential properties of the underlying work stealing-based task scheduling algorithm, and that the fault tolerant execution is asymptotically optimal when task re-execution is taken into account. Experimental evaluation demonstrates the low cost of recovery under various fault scenarios.

  19. Sandia Energy - PV Arc-Fault and Ground Fault Detection and Mitigation...

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    prescribe maintenance schedules, and warn of arc-fault events. Investigating the proscons of module-level, string-level, and array-level arc-fault detection schemes....

  20. Method of determining the open circuit voltage of a battery in a closed circuit

    DOE Patents [OSTI]

    Brown, William E.

    1980-01-01

    The open circuit voltage of a battery which is connected in a closed circuit is determined without breaking the circuit or causing voltage upsets therein. The closed circuit voltage across the battery and the current flowing through it are determined under normal load and then a fractional change is made in the load and the new current and voltage values determined. The open circuit voltage is then calculated, according to known principles, from the two sets of values.

  1. Wind Power Plant Short Circuit Current Contribution for Different Fault and Wind Turbine Topologies: Preprint

    SciTech Connect (OSTI)

    Gevorgian, V.; Muljadi, E.

    2010-10-01

    This paper presents simulation results for SC current contribution for different types of WTGs obtained through transient and steady-state computer simulation software.

  2. Detachment Faulting & Geothermal Resources - Pearl Hot Spring...

    Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

    Detachment Faulting & Geothermal Resources - Pearl Hot Spring, NV Finding Large Aperture Fractures in Geothermal Resource Areas Using a Three-Component Long-Offset Surface Seismic ...

  3. Efficient Synchronization Stability Metrics for Fault Clearing...

    Office of Scientific and Technical Information (OSTI)

    Title: Efficient Synchronization Stability Metrics for Fault Clearing Authors: Backhaus, Scott N. 1 ; Chertkov, Michael 1 ; Bent, Russell Whitford 1 ; Bienstock, Daniel 2...

  4. Reducing the Risk of Arc-Faults

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    arc-fault detection algorithms by: 1. Performing arcing tests at the Distributed Energy Technologies Laboratory (DETL) with AFCI prototypes to verify their functionality on...

  5. Printed circuit dispersive transmission line

    DOE Patents [OSTI]

    Ikezi, H.; Lin-Liu, Y.R.; DeGrassie, J.S.

    1991-08-27

    A printed circuit dispersive transmission line structure is disclosed comprising an insulator, a ground plane formed on one surface of the insulator, a first transmission line formed on a second surface of the insulator, and a second transmission line also formed on the second surface of the insulator and of longer length than the first transmission line and periodically intersecting the first transmission line. In a preferred embodiment, the transmission line structure exhibits highly dispersive characteristics by designing the length of one of the transmission line between two adjacent periodic intersections to be longer than the other. 5 figures.

  6. Inductive storage pulse circuit device

    DOE Patents [OSTI]

    Parsons, William M.; Honig, Emanuel M.

    1984-01-01

    Inductive storage pulse circuit device which is capable of delivering a series of electrical pulses to a load in a sequential manner. Silicon controlled rectifiers as well as spark gap switches can be utilized in accordance with the present invention. A commutation switching array is utilized to produce a reverse current to turn-off the main opening switch. A commutation capacitor produces the reverse current and is initially charged to a predetermined voltage and subsequently charged in alternating directions by the inductive storage current.

  7. Polysilicon photoconductor for integrated circuits

    DOE Patents [OSTI]

    Hammond, R.B.; Bowman, D.R.

    1989-04-11

    A photoconductive element of polycrystalline silicon is provided with intrinsic response time which does not limit overall circuit response. An undoped polycrystalline silicon layer is deposited by LPCVD to a selected thickness on silicon dioxide. The deposited polycrystalline silicon is then annealed at a selected temperature and for a time effective to obtain crystal sizes effective to produce an enhanced current output. The annealed polycrystalline layer is subsequently exposed and damaged by ion implantation to a damage factor effective to obtain a fast photoconductive response. 6 figs.

  8. Polysilicon photoconductor for integrated circuits

    DOE Patents [OSTI]

    Hammond, Robert B.; Bowman, Douglas R.

    1989-01-01

    A photoconductive element of polycrystalline silicon is provided with intrinsic response time which does not limit overall circuit response. An undoped polycrystalline silicon layer is deposited by LPCVD to a selected thickness on silicon dioxide. The deposited polycrystalline silicon is then annealed at a selected temperature and for a time effective to obtain crystal sizes effective to produce an enhanced current output. The annealed polycrystalline layer is subsequently exposed and damaged by ion implantation to a damage factor effective to obtain a fast photoconductive response.

  9. Polysilicon photoconductor for integrated circuits

    DOE Patents [OSTI]

    Hammond, Robert B.; Bowman, Douglas R.

    1990-01-01

    A photoconductive element of polycrystalline silicon is provided with intrinsic response time which does not limit overall circuit response. An undoped polycrystalline silicon layer is deposited by LPCVD to a selected thickness on silicon dioxide. The deposited polycrystalline silicon is then annealed at a selected temperature and for a time effective to obtain crystal sizes effective to produce an enhanced current output. The annealed polycrystalline layer is subsequently exposed and damaged by ion implantation to a damage factor effective to obtain a fast photoconductive response.

  10. Printed circuit dispersive transmission line

    DOE Patents [OSTI]

    Ikezi, Hiroyuki; Lin-Liu, Yuh-Ren; DeGrassie, John S.

    1991-01-01

    A printed circuit dispersive transmission line structure is disclosed comprising an insulator, a ground plane formed on one surface of the insulator, a first transmission line formed on a second surface of the insulator, and a second transmission line also formed on the second surface of the insulator and of longer length than the first transmission line and periodically intersecting the first transmission line. In a preferred embodiment, the transmission line structure exhibits highly dispersive characteristics by designing the length of one of the transmission line between two adjacent periodic intersections to be longer than the other.

  11. Physiochemical Evidence of Faulting Processes and Modeling of Fluid in Evolving Fault Systems in Southern California

    SciTech Connect (OSTI)

    Boles, James

    2013-05-24

    Our study targets recent (Plio-Pleistocene) faults and young (Tertiary) petroleum fields in southern California. Faults include the Refugio Fault in the Transverse Ranges, the Ellwood Fault in the Santa Barbara Channel, and most recently the Newport- Inglewood in the Los Angeles Basin. Subsurface core and tubing scale samples, outcrop samples, well logs, reservoir properties, pore pressures, fluid compositions, and published structural-seismic sections have been used to characterize the tectonic/diagenetic history of the faults. As part of the effort to understand the diagenetic processes within these fault zones, we have studied analogous processes of rapid carbonate precipitation (scaling) in petroleum reservoir tubing and manmade tunnels. From this, we have identified geochemical signatures in carbonate that characterize rapid CO2 degassing. These data provide constraints for finite element models that predict fluid pressures, multiphase flow patterns, rates and patterns of deformation, subsurface temperatures and heat flow, and geochemistry associated with large fault systems.

  12. Self-triggering superconducting fault current limiter

    DOE Patents [OSTI]

    Yuan, Xing; Tekletsadik, Kasegn

    2008-10-21

    A modular and scaleable Matrix Fault Current Limiter (MFCL) that functions as a "variable impedance" device in an electric power network, using components made of superconducting and non-superconducting electrically conductive materials. The matrix fault current limiter comprises a fault current limiter module that includes a superconductor which is electrically coupled in parallel with a trigger coil, wherein the trigger coil is magnetically coupled to the superconductor. The current surge doing a fault within the electrical power network will cause the superconductor to transition to its resistive state and also generate a uniform magnetic field in the trigger coil and simultaneously limit the voltage developed across the superconductor. This results in fast and uniform quenching of the superconductors, significantly reduces the burnout risk associated with non-uniformity often existing within the volume of superconductor materials. The fault current limiter modules may be electrically coupled together to form various "n" (rows).times."m" (columns) matrix configurations.

  13. Interruptible service system: A demand-side management application for the City of Los Angeles Department of Water & Power

    SciTech Connect (OSTI)

    Leblanc, M.; Sweeney, D.

    1994-12-31

    The Los Angeles Department of Water & Power (LADWP) instituted an electric rate schedule, A3-B, for its largest industrial power consumers in 1985. The A3 rate provides these LADWP customers (2000 Kilowatts or more users) a significant savings on their electric service rate. LADWP benefits by having the capability to interrupt the industrial customer`s load after giving them a 10 minute warning notice of interruption. The Interruptible Service System (ISS) automates this formerly manual process and allows for continuous monitoring of the power used of the power system`s largest power consumers. An ISS remote terminal unit (RTU) is installed at each customer`s site. This RTU communicates with a master computer (desktop PC) at LADWP`s Energy Control Center (ECC). The ECC initiates control, monitoring, and interrupt operations involving all customers on the ISS rate. Communication between the master computer and the various ISS customer RTUs will be accomplished via Pacific Bell Telephone`s advanced digital network (ADN). Future Plans include expansion to monitoring and control of co-generation facilities and monitoring of other large industrial customer power consumption.

  14. MULTI-ELECTRODE TUBE PULSE MEMORY CIRCUIT

    DOE Patents [OSTI]

    Gundlach, J.C.; Reeves, J.B.

    1958-05-20

    Control circuits are described for pulse memory devices for scalers and the like, and more particularly to a driving or energizing circuit for a polycathode gaseous discharge tube having an elongated anode and a successive series of cathodes spaced opposite the anode along its length. The circuit is so arranged as to utilize an arc discharge between the anode and a cathode to count a series of pulses. Upon application of an input pulse the discharge is made to occur between the anode and the next successive cathode, and an output pulse is produced when a particular subsequent cathode is reached. The circuit means for transfering the discharge by altering the anode potential and potential of the cathodes and interconnecting the cathodes constitutes the novel aspects of the invention. A low response time and reduced number of circuit components are the practical advantages of the described circuit.

  15. Realizing a supercapacitor in an electrical circuit

    SciTech Connect (OSTI)

    Fukuhara, Mikio Kuroda, Tomoyuki; Hasegawa, Fumihiko

    2014-11-17

    Capacitors are commonly used in electronic resonance circuits; however, capacitors have not been used for storing large amounts of electrical energy in electrical circuits. Here, we report a superior RC circuit which serves as an electrical storage system characterized by quick charging and long-term discharging of electricity. The improved energy storage characteristics in this mixed electric circuit (R{sub 1}?+?R{sub 2}C{sub 1}) with small resistor R{sub 1}, large resistor R{sub 2}, and large capacitor C{sub 1} are derived from the damming effect by large R{sub 2} in simple parallel R{sub 2}C{sub 1} circuit. However, no research work has been carried out previously on the use of capacitors as electrical energy storage devices in circuits. Combined with nanotechnology, we hope that our finding will play a remarkable role in a variety of applications such as hybrid electric vehicles and backup power supplies.

  16. Multi-fault Tolerance for Cartesian Data Distributions (Journal...

    Office of Scientific and Technical Information (OSTI)

    Fault-tolerant linear algebra (FTLA) algo- rithms employ additional processors that store parities along the dimensions of a matrix to tolerate multiple, simultaneous faults. ...

  17. Modeling of fault reactivation and induced seismicity during...

    Office of Scientific and Technical Information (OSTI)

    Modeling of fault reactivation and induced seismicity during hydraulic fracturing of shale-gas reservoirs Citation Details In-Document Search Title: Modeling of fault reactivation ...

  18. Termination of a Major Normal Fault | Open Energy Information

    Open Energy Info (EERE)

    sometimes split into multiple closely-spaced faults that result in increased permeability. Fault sets at these terminations sometimes appear as "horsetailing" splays that...

  19. Multiplexer and time duration measuring circuit

    DOE Patents [OSTI]

    Gray, Jr., James

    1980-01-01

    A multiplexer device is provided for multiplexing data in the form of randomly developed, variable width pulses from a plurality of pulse sources to a master storage. The device includes a first multiplexer unit which includes a plurality of input circuits each coupled to one of the pulse sources, with all input circuits being disabled when one input circuit receives an input pulse so that only one input pulse is multiplexed by the multiplexer unit at any one time.

  20. Monitoring transients in low inductance circuits

    DOE Patents [OSTI]

    Guilford, R.P.; Rosborough, J.R.

    1985-10-21

    The instant invention relates to methods of and apparatus for monitoring transients in low inductance circuits and to a probe utilized to practice said method and apparatus. More particularly, the instant invention relates to methods of and apparatus for monitoring low inductance circuits, wherein the low inductance circuits include a pair of flat cable transmission lines. The instant invention is further directed to a probe for use in monitoring pairs of flat cable transmission lines.

  1. Predicting the reliability of electronic circuits.

    SciTech Connect (OSTI)

    Loescher, Douglas H.

    2004-06-01

    Procedures to predict the reliability of electrical circuits are discussed. Three cases are introduced and discussed. In Case 1, an analyst predicts the probability of any failure in the intended relations between circuit inputs and circuit outputs. In Case 2, an analyst predicts the probability that specified unintended outputs would occur. In Case 3, an analyst considers coupling between circuits. Logic models are given for the three cases, and sources of failure probabilities of components are mentioned. Methods of analysis are given, software tools are mentioned, and recommendations for presentation and review of results are discussed.

  2. Jabil Circuit Inc | Open Energy Information

    Open Energy Info (EERE)

    Florida Zip: 33716 Sector: Services Product: Florida-based company offering manufacturing and product management services for electronic goods. References: Jabil Circuit...

  3. Hybrid stretchable circuits on silicone substrate

    SciTech Connect (OSTI)

    Robinson, A., E-mail: adam.1.robinson@nokia.com; Aziz, A., E-mail: a.aziz1@lancaster.ac.uk [Nanoscience Centre, University of Cambridge, Cambridge CB01FF (United Kingdom); Liu, Q.; Suo, Z. [School of Engineering and Applied Sciences and Kavli Institute for Bionano Science and Technology, Harvard University, Cambridge, Massachusetts 02138 (United States); Lacour, S. P., E-mail: stephanie.lacour@epfl.ch [Centre for Neuroprosthetics and Laboratory for Soft Bioelectronics Interfaces, School of Engineering, Ecole Polytechnique Fdrale de Lausanne, Lausanne 1015 (Switzerland)

    2014-04-14

    When rigid and stretchable components are integrated onto a single elastic carrier substrate, large strain heterogeneities appear in the vicinity of the deformable-non-deformable interfaces. In this paper, we report on a generic approach to manufacture hybrid stretchable circuits where commercial electronic components can be mounted on a stretchable circuit board. Similar to printed circuit board development, the components are electrically bonded on the elastic substrate and interconnected with stretchable electrical traces. The substratea silicone matrix carrying concentric rigid disksensures both the circuit elasticity and the mechanical integrity of the most fragile materials.

  4. Demultiplexer circuit for neural stimulation (Patent) | DOEPatents

    Office of Scientific and Technical Information (OSTI)

    all the dc electrical power for operation of the circuit, includes digital latches that receive and store addressing information from the neural stimulator one bit at a time. ...

  5. Circuits of Atoms on Wires of Light

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Circuits of Atoms on Wires of Light 1663 Los Alamos science and technology magazine Latest Issue:July 2016 past issues All Issues » submit Circuits of Atoms on Wires of Light A new kind of circuitry-with electrons on conducting wires replaced by atoms on paths of laser light-is ushering in an era of "atomtronic" technology. March 8, 2016 Artist visualization of atomic circuits Los Alamos scientists have developed a reliable new way to create atomtronic circuits with waves of

  6. Modeling of transformers using circuit simulators

    SciTech Connect (OSTI)

    Archer, W.E.; Deveney, M.F.; Nagel, R.L.

    1994-07-01

    Transformers of two different designs; and unencapsulated pot core and an encapsulated toroidal core have been modeled for circuit analysis with circuit simulation tools. We selected MicroSim`s PSPICE and Anology`s SABER as the simulation tools and used experimental BH Loop and network analyzer measurements to generate the needed input data. The models are compared for accuracy and convergence using the circuit simulators. Results are presented which demonstrate the effects on circuit performance from magnetic core losses, eddy currents, and mechanical stress on the magnetic cores.

  7. Vertical Circuits Inc | Open Energy Information

    Open Energy Info (EERE)

    and intellectual property for the manufacture of low cost ultra high-speedhigh-density semiconductor components. References: Vertical Circuits, Inc.1 This article is a...

  8. Beta-gamma discriminator circuit

    SciTech Connect (OSTI)

    Erkkila, B.H.; Wolf, M.A.; Eisen, Y.; Unruh, W.P.; Brake, R.J.

    1984-01-01

    The major difficulty encountered in the determination of beta-ray dose in field conditions is generally the presence of a relatively high gamma-ray component. Conventional dosimetry instruments use a shield on the detector to estimate the gamma-ray component in comparison with the beta-ray component. More accurate dosimetry information can be obtained from the measured beta spectrum itself. At Los Alamos, a detector and discriminator circuit suitable for use in a portable spectrometer have been developed. This instrument will discriminate between gammas and betas in a mixed field. The portable package includes a 256-channel MCA which can be programmed to give a variety of outputs, including a spectral display, and may be programmed to read dose directly.

  9. Sequential power-up circuit

    DOE Patents [OSTI]

    Kronberg, James W.

    1992-01-01

    A sequential power-up circuit for starting several electrical load elements in series to avoid excessive current surge, comprising a voltage ramp generator and a set of voltage comparators, each comparator having a different reference voltage and interfacing with a switch that is capable of turning on one of the load elements. As the voltage rises, it passes the reference voltages one at a time and causes the switch corresponding to that voltage to turn on its load element. The ramp is turned on and off by a single switch or by a logic-level electrical signal. The ramp rate for turning on the load element is relatively slow and the rate for turning the elements off is relatively fast. Optionally, the duration of each interval of time between the turning on of the load elements is programmable.

  10. Sequential power-up circuit

    DOE Patents [OSTI]

    Kronberg, J.W.

    1992-06-02

    A sequential power-up circuit for starting several electrical load elements in series to avoid excessive current surge, comprising a voltage ramp generator and a set of voltage comparators, each comparator having a different reference voltage and interfacing with a switch that is capable of turning on one of the load elements. As the voltage rises, it passes the reference voltages one at a time and causes the switch corresponding to that voltage to turn on its load element. The ramp is turned on and off by a single switch or by a logic-level electrical signal. The ramp rate for turning on the load element is relatively slow and the rate for turning the elements off is relatively fast. Optionally, the duration of each interval of time between the turning on of the load elements is programmable. 2 figs.

  11. Shapeable short circuit resistant capacitor

    DOE Patents [OSTI]

    Taylor, Ralph S.; Myers, John D.; Baney, William J.

    2015-10-06

    A ceramic short circuit resistant capacitor that is bendable and/or shapeable to provide a multiple layer capacitor that is extremely compact and amenable to desirable geometries. The capacitor that exhibits a benign failure mode in which a multitude of discrete failure events result in a gradual loss of capacitance. Each event is a localized event in which localized heating causes an adjacent portion of one or both of the electrodes to vaporize, physically cleaning away electrode material from the failure site. A first metal electrode, a second metal electrode, and a ceramic dielectric layer between the electrodes are thin enough to be formed in a serpentine-arrangement with gaps between the first electrode and the second electrode that allow venting of vaporized electrode material in the event of a benign failure.

  12. TIME CALIBRATED OSCILLOSCOPE SWEEP CIRCUIT

    DOE Patents [OSTI]

    Smith, V.L.; Carstensen, H.K.

    1959-11-24

    An improved time calibrated sweep circuit is presented, which extends the range of usefulness of conventional oscilloscopes as utilized for time calibrated display applications in accordance with U. S. Patent No. 2,832,002. Principal novelty resides in the provision of a pair of separate signal paths, each of which is phase and amplitude adjustable, to connect a high-frequency calibration oscillator to the output of a sawtooth generator also connected to the respective horizontal deflection plates of an oscilloscope cathode ray tube. The amplitude and phase of the calibration oscillator signals in the two signal paths are adjusted to balance out feedthrough currents capacitively coupled at high frequencies of the calibration oscillator from each horizontal deflection plate to the vertical plates of the cathode ray tube.

  13. Maze solving automatons for self-healing of open interconnects: Modular add-on for circuit boards

    SciTech Connect (OSTI)

    Nair, Aswathi; Raghunandan, Karthik; Yaswant, Vaddi; Sambandan, Sanjiv E-mail: ssanjiv@isu.iisc.ernet.in; Pillai, Sreelal S.

    2015-03-23

    We present the circuit board integration of a self-healing mechanism to repair open faults. The electric field driven mechanism physically restores fractured interconnects in electronic circuits and has the ability to solve mazes. The repair is performed by conductive particles dispersed in an insulating fluid. We demonstrate the integration of the healing module onto printed circuit boards and the ability of maze solving. We model and perform experiments on the influence of the geometry of conductive particles as well as the terminal impedances of the route on the healing efficiency. The typical heal rate is 10 μm/s with healed route having mean resistance of 8 kΩ across a 200 micron gap and depending on the materials and concentrations used.

  14. Mechanical Models of Fault-Related Folding

    SciTech Connect (OSTI)

    Johnson, A. M.

    2003-01-09

    The subject of the proposed research is fault-related folding and ground deformation. The results are relevant to oil-producing structures throughout the world, to understanding of damage that has been observed along and near earthquake ruptures, and to earthquake-producing structures in California and other tectonically-active areas. The objectives of the proposed research were to provide both a unified, mechanical infrastructure for studies of fault-related foldings and to present the results in computer programs that have graphical users interfaces (GUIs) so that structural geologists and geophysicists can model a wide variety of fault-related folds (FaRFs).

  15. Reusable vibration resistant integrated circuit mounting socket

    DOE Patents [OSTI]

    Evans, Craig N.

    1995-01-01

    This invention discloses a novel form of socket for integrated circuits to be mounted on printed circuit boards. The socket uses a novel contact which is fabricated out of a bimetallic strip with a shape which makes the end of the strip move laterally as temperature changes. The end of the strip forms a barb which digs into an integrated circuit lead at normal temperatures and holds it firmly in the contact, preventing loosening and open circuits from vibration. By cooling the contact containing the bimetallic strip the barb end can be made to release so that the integrated circuit lead can be removed from the socket without damage either to the lead or to the socket components.

  16. HVAC Fault Detection and Diagnosis Toolkit

    Energy Science and Technology Software Center (OSTI)

    2004-12-31

    This toolkit supports component-level model-based fault detection methods in commercial building HVAC systems. The toolbox consists of five basic modules: a parameter estimator for model calibration, a preprocessor, an AHU model simulator, a steady-state detector, and a comparator. Each of these modules and the fuzzy logic rules for fault diagnosis are described in detail. The toolbox is written in C++ and also invokes the SPARK simulation program.

  17. A connecting network with fault tolerance capabilities

    SciTech Connect (OSTI)

    Ciminiera, L.; Serra, A.

    1986-06-01

    A new multistage interconnection network is presented in this paper. It is able to handle the communications between the connected devices correctly, even in the presence of fault(s) in the network. This goal is achieved by using redundant paths with a fast procedure able to dynamically reroute the message. It is also shown that the rerouting properties are still valid when broadcasting transmission is used.

  18. Different Factors Affecting Short Circuit Behavior of a Wind Power Plant

    SciTech Connect (OSTI)

    Muljadi, E.; Samaan, Nader A.; Gevorgian, Vahan; Li, Jun; Pasupulati, Subbaiah

    2010-12-21

    A wind power plant consists of a large number of turbines interconnected by underground cable. A pad-mount transformer at each turbine steps up the voltage from generating voltage (690 V) to a medium voltage (34.5 kV). All turbines in the plant are connected to the substation transformer where the voltage is stepped up to the transmission level. An important aspect of wind power plant (WPP) impact studies is to evaluate the short-circuit (SC) current contribution of the plant into the transmission network under different fault conditions. This task can be challenging to protection engineers due to the topology differences between different types of wind turbine generators (WTGs) and the conventional generating units. This paper investigates the short circuit behavior of a wind power plant for different types of faults. The impact of wind turbine types, the transformer configuration, and the reactive compensation capacitor will be investigated. The voltage response at different buses will be observed. Finally, the SC line currents will be presented along with its symmetrical components.

  19. Different Factors Affecting Short Circuit Behavior of a Wind Power Plant

    SciTech Connect (OSTI)

    Muljadi, E.; Samaan, Nader A.; Gevorgian, Vahan; Li, Jun; Pasupulati, Subbaiah

    2013-01-31

    A wind power plant consists of a large number of turbines interconnected by underground cable. A pad-mount transformer at each turbine steps up the voltage from generating voltage (690 V) to a medium voltage (34.5 kV). All turbines in the plant are connected to the substation transformer where the voltage is stepped up to the transmission level. An important aspect of wind power plant (WPP) impact studies is to evaluate the short-circuit (SC) current contribution of the plant into the transmission network under different fault conditions. This task can be challenging to protection engineers due to the topology differences between different types of wind turbine generators (WTGs) and the conventional generating units. This paper investigates the short circuit behavior of a wind power plant for different types of faults. The impact of wind turbine types, the transformer configuration, and the reactive compensation capacitor will be investigated. The voltage response at different buses will be observed. Finally, the SC line currents will be presented along with its symmetrical components.

  20. Overload protection circuit for output driver

    DOE Patents [OSTI]

    Stewart, Roger G.

    1982-05-11

    A protection circuit for preventing excessive power dissipation in an output transistor whose conduction path is connected between a power terminal and an output terminal. The protection circuit includes means for sensing the application of a turn on signal to the output transistor and the voltage at the output terminal. When the turn on signal is maintained for a period of time greater than a given period without the voltage at the output terminal reaching a predetermined value, the protection circuit decreases the turn on signal to, and the current conduction through, the output transistor.

  1. Industrial Circuit Breakers |GE Global Research

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Journey Inside the Complex and Powerful World of Industrial Circuit Breakers Click to email this to a friend (Opens in new window) Share on Facebook (Opens in new window) Click to share (Opens in new window) Click to share on LinkedIn (Opens in new window) Click to share on Tumblr (Opens in new window) A Journey Inside the Complex and Powerful World of Industrial Circuit Breakers Kathleen O'Brien 2015.04.21 Most of us only think about circuit breakers when one trips because we plugged in too

  2. BLOCKING OSCILLATOR DOUBLE PULSE GENERATOR CIRCUIT

    DOE Patents [OSTI]

    Haase, J.A.

    1961-01-24

    A double-pulse generator, particuiarly a double-pulse generator comprising a blocking oscillator utilizing a feedback circuit to provide means for producing a second pulse within the recovery time of the blocking oscillator, is described. The invention utilized a passive network which permits adjustment of the spacing between the original pulses derived from the blocking oscillator and further utilizes the original pulses to trigger a circuit from which other pulses are initiated. These other pulses are delayed and then applied to the input of the blocking oscillator, with the result that the output from the oscillator circuit contains twice the number of pulses originally initiated by the blocking oscillator itself.

  3. Serpentine and corduroy circuits to enhance the stretchability...

    Office of Scientific and Technical Information (OSTI)

    The apparatus comprises a stretchable polymer body, and at least one circuit line operatively connected to the stretchable polymer body, the at least one circuit line extending in ...

  4. Serpentine and corduroy circuits to enhance the stretchablity...

    Office of Scientific and Technical Information (OSTI)

    The apparatus comprises a stretchable polymer body, and at least one circuit line operatively connected to the stretchable polymer body, the at least one circuit line extending in ...

  5. Legos for the Fabrication of Atomically Precise Electronic Circuits...

    Office of Science (SC) Website

    circuits for faster, more energy efficient electronics and advanced solar cells. ... used to produce high performance circuits for use in future electronics and solar cells. ...

  6. Unitech Printed Circuit Board Corp UPCB | Open Energy Information

    Open Energy Info (EERE)

    Sector: Solar Product: Taiwan-based printed-circuit board maker with intent to enter into solar cell manufacturing industry. References: Unitech Printed Circuit Board Corp....

  7. Measuring and Modeling Fault Density for Plume-Fault Encounter Probability Estimation

    SciTech Connect (OSTI)

    Jordan, P.D.; Oldenburg, C.M.; Nicot, J.-P.

    2011-05-15

    Emission of carbon dioxide from fossil-fueled power generation stations contributes to global climate change. Storage of this carbon dioxide within the pores of geologic strata (geologic carbon storage) is one approach to mitigating the climate change that would otherwise occur. The large storage volume needed for this mitigation requires injection into brine-filled pore space in reservoir strata overlain by cap rocks. One of the main concerns of storage in such rocks is leakage via faults. In the early stages of site selection, site-specific fault coverages are often not available. This necessitates a method for using available fault data to develop an estimate of the likelihood of injected carbon dioxide encountering and migrating up a fault, primarily due to buoyancy. Fault population statistics provide one of the main inputs to calculate the encounter probability. Previous fault population statistics work is shown to be applicable to areal fault density statistics. This result is applied to a case study in the southern portion of the San Joaquin Basin with the result that the probability of a carbon dioxide plume from a previously planned injection had a 3% chance of encountering a fully seal offsetting fault.

  8. Internal configuration of prismatic lithium-ion cells at the onset of mechanically induced short circuit

    DOE Public Access Gateway for Energy & Science Beta (PAGES Beta)

    Wang, Hsin; Simunovic, Srdjan; Maleki, Hosein; Howard, Jason N.; Hallmark, Jerald A.

    2016-01-01

    The response of Li-ion cells to mechanically induced internal electrical shorts is an important safety performance metric design. We assume that the battery internal configuration at the onset of electrical short influences the subsequent response and can be used to gauge the safety risk. We subjected a series of prismatic Li-ion cells to lateral pinching using 0.25", 0.5", 1", 2" and 3" diameter steel balls until the onset of internal short. The external aluminum enclosure froze the internal cell configuration at the onset of short and enabled us to cross-section the cells, and take the cross-section images. The images indicatemore » that an internal electric short is preceded by extensive strain partitioning in the cells, fracturing and tearing of the current collectors, and cracking and slipping of the electrode layers with multiple fault lines across multiple layers. These observations are at odds with a common notion of homogeneous deformation across the layers and strain hardening of electrodes that eventually punch through the separator and short the cell. The faults are akin to tectonic movements of multiple layers that are characteristic of granular materials and bonded aggregates. As a result, the short circuits occur after extensive internal faulting, which implies significant stretching and tearing of separators.« less

  9. Internal configuration of prismatic lithium-ion cells at the onset of mechanically induced short circuit

    SciTech Connect (OSTI)

    Wang, Hsin; Simunovic, Srdjan; Maleki, Hosein; Howard, Jason N.; Hallmark, Jerald A.

    2016-01-01

    The response of Li-ion cells to mechanically induced internal electrical shorts is an important safety performance metric design. We assume that the battery internal configuration at the onset of electrical short influences the subsequent response and can be used to gauge the safety risk. We subjected a series of prismatic Li-ion cells to lateral pinching using 0.25", 0.5", 1", 2" and 3" diameter steel balls until the onset of internal short. The external aluminum enclosure froze the internal cell configuration at the onset of short and enabled us to cross-section the cells, and take the cross-section images. The images indicate that an internal electric short is preceded by extensive strain partitioning in the cells, fracturing and tearing of the current collectors, and cracking and slipping of the electrode layers with multiple fault lines across multiple layers. These observations are at odds with a common notion of homogeneous deformation across the layers and strain hardening of electrodes that eventually punch through the separator and short the cell. The faults are akin to tectonic movements of multiple layers that are characteristic of granular materials and bonded aggregates. As a result, the short circuits occur after extensive internal faulting, which implies significant stretching and tearing of separators.

  10. Demultiplexer circuit for neural stimulation (Patent) | DOEPatents

    Office of Scientific and Technical Information (OSTI)

    to an electrode array which is connected to the outputs of the 1:2.sup.N demultiplexer. The demultiplexer circuit allows the number of individual electrodes in the electrode array ...

  11. Analog circuit for controlling acoustic transducer arrays

    SciTech Connect (OSTI)

    Drumheller, Douglas S.

    1991-01-01

    A simplified ananlog circuit is presented for controlling electromechanical transducer pairs in an acoustic telemetry system. The analog circuit of this invention comprises a single electrical resistor which replaces all of the digital components in a known digital circuit. In accordance with this invention, a first transducer in a transducer pair of array is driven in series with the resistor. The voltage drop across this resistor is then amplified and used to drive the second transducer. The voltage drop across the resistor is proportional and in phase with the current to the transducer. This current is approximately 90 degrees out of phase with the driving voltage to the transducer. This phase shift replaces the digital delay required by the digital control circuit of the prior art.

  12. Circuit level modeling of inductive elements

    SciTech Connect (OSTI)

    Muyshondt, G.P.; Portnoy, W.M.

    1989-01-01

    Design and analysis of spacecraft power systems have been difficult to perform because of the lack of circuit level models for nonlinear inductive elements. This paper reviews some of the models which have been proposed, their limitations, and applications. An improved saturation dependent model will be described. The model has been implemented in SPICE and with a commercial circuit program and demonstrated to be satisfactory in both implementations. 3 refs., 9 figs.

  13. Electrochemically controlled charging circuit for storage batteries

    DOE Patents [OSTI]

    Onstott, E.I.

    1980-06-24

    An electrochemically controlled charging circuit for charging storage batteries is disclosed. The embodiments disclosed utilize dc amplification of battery control current to minimize total energy expended for charging storage batteries to a preset voltage level. The circuits allow for selection of Zener diodes having a wide range of reference voltage levels. Also, the preset voltage level to which the storage batteries are charged can be varied over a wide range.

  14. Communications circuit including a linear quadratic estimator

    DOE Patents [OSTI]

    Ferguson, Dennis D.

    2015-07-07

    A circuit includes a linear quadratic estimator (LQE) configured to receive a plurality of measurements a signal. The LQE is configured to weight the measurements based on their respective uncertainties to produce weighted averages. The circuit further includes a controller coupled to the LQE and configured to selectively adjust at least one data link parameter associated with a communication channel in response to receiving the weighted averages.

  15. Dynamical Systems in Circuit Designer's Eyes

    SciTech Connect (OSTI)

    Odyniec, M.

    2011-05-09

    Examples of nonlinear circuit design are given. Focus of the design process is on theory and engineering methods (as opposed to numerical analysis). Modeling is related to measurements It is seen that the phase plane is still very useful with proper models Harmonic balance/describing function offers powerful insight (via the combination of simulation with circuit and ODE theory). Measurement and simulation capabilities increased, especially harmonics measurements (since sinusoids are easy to generate)

  16. Equivalent Circuit Modeling of Hysteresis Motors

    SciTech Connect (OSTI)

    Nitao, J J; Scharlemann, E T; Kirkendall, B A

    2009-08-31

    We performed a literature review and found that many equivalent circuit models of hysteresis motors in use today are incorrect. The model by Miyairi and Kataoka (1965) is the correct one. We extended the model by transforming it to quadrature coordinates, amenable to circuit or digital simulation. 'Hunting' is an oscillatory phenomenon often observed in hysteresis motors. While several works have attempted to model the phenomenon with some partial success, we present a new complete model that predicts hunting from first principles.

  17. Fault Detection and Load Distribution for the Wind Farm Challenge

    SciTech Connect (OSTI)

    Borchehrsen, Anders B.; Larsen, Jesper A.; Stoustrup, Jakob

    2014-08-24

    In this paper a fault detection system and a fault tolerant controller for a wind farm model. The wind farm model used is the one proposed as a public challenge. In the model three types of faults are introduced to a wind farm consisting of nine turbines. A fault detection system designed, by taking advantage of the fact that within a wind farm several wind turbines will be operating under all most identical conditions. The turbines are then grouped, and then turbines within each group are used to generate residuals for turbines in the group. The generated residuals are then evaluated using dynamical cumulative sum. The designed fault detection system is cable of detecting all three fault types occurring in the model. But there is room for improving the fault detection in some areas. To take advantage of the fault detection system a fault tolerant controller for the wind farm has been designed. The fault tolerant controller is a dispatch controller which is estimating the possible power at each individual turbine and then setting the reference accordingly. The fault tolerant controller has been compared to a reference controller. And the comparison shows that the fault tolerant controller performance better in all measures. The fault detection and a fault tolerant controller has been designed, and based on the simulated results the overall performance of the wind farm is improved on all measures. Thereby this is a step towards improving the overall performance of current and future wind farms.

  18. Active shunt capacitance cancelling oscillator circuit

    DOE Patents [OSTI]

    Wessendorf, Kurt O.

    2003-09-23

    An oscillator circuit is disclosed which can be used to produce oscillation using a piezoelectric crystal, with a frequency of oscillation being largely independent of any shunt capacitance associated with the crystal (i.e. due to electrodes on the surfaces of the crystal and due to packaging and wiring for the crystal). The oscillator circuit is based on a tuned gain stage which operates the crystal at a frequency, f, near a series resonance frequency, f.sub.S. The oscillator circuit further includes a compensation circuit that supplies all the ac current flow through the shunt resistance associated with the crystal so that this ac current need not be supplied by the tuned gain stage. The compensation circuit uses a current mirror to provide the ac current flow based on the current flow through a reference capacitor that is equivalent to the shunt capacitance associated with the crystal. The oscillator circuit has applications for driving piezoelectric crystals for sensing of viscous, fluid or solid media by detecting a change in the frequency of oscillation of the crystal and a resonator loss which occur from contact of an exposed surface of the crystal by the viscous, fluid or solid media.

  19. Buried pipelines in large fault movements

    SciTech Connect (OSTI)

    Wang, L.J.; Wang, L.R.L.

    1995-12-31

    Responses of buried pipelines in large fault movements are examined based upon a non-linear cantilever beam analogy. This analogy assumes that the pipeline in a large deflection zone behaves like a cantilever beam under a transverse-concentrated shear at the inflection point with a uniformly distributed soil pressure along the entire span. The tangent modulus approach is adopted to analyze the coupled axial force-bending moment interaction on pipeline deformations in the inelastic range. The buckling load of compressive pipeline is computed by the modified Newmark`s numerical integration scheme. Parametric studies of both tensile and compressive pipeline responses to various fault movements, pipeline/fault crossing angles, soil/pipe friction angles, buried depths, pipe diameters and thickness are investigated. It is shown by the comparisons that previous findings were unconservative.

  20. VCSEL fault location apparatus and method

    DOE Patents [OSTI]

    Keeler, Gordon A.; Serkland, Darwin K.

    2007-05-15

    An apparatus for locating a fault within an optical fiber is disclosed. The apparatus, which can be formed as a part of a fiber-optic transmitter or as a stand-alone instrument, utilizes a vertical-cavity surface-emitting laser (VCSEL) to generate a test pulse of light which is coupled into an optical fiber under test. The VCSEL is subsequently reconfigured by changing a bias voltage thereto and is used as a resonant-cavity photodetector (RCPD) to detect a portion of the test light pulse which is reflected or scattered from any fault within the optical fiber. A time interval .DELTA.t between an instant in time when the test light pulse is generated and the time the reflected or scattered portion is detected can then be used to determine the location of the fault within the optical fiber.

  1. Fault-tolerant three-level inverter

    DOE Patents [OSTI]

    Edwards, John; Xu, Longya; Bhargava, Brij B.

    2006-12-05

    A method for driving a neutral point clamped three-level inverter is provided. In one exemplary embodiment, DC current is received at a neutral point-clamped three-level inverter. The inverter has a plurality of nodes including first, second and third output nodes. The inverter also has a plurality of switches. Faults are checked for in the inverter and predetermined switches are automatically activated responsive to a detected fault such that three-phase electrical power is provided at the output nodes.

  2. Triple effect absorption chiller utilizing two refrigeration circuits

    DOE Patents [OSTI]

    DeVault, Robert C.

    1988-01-01

    A triple effect absorption method and apparatus having a high coefficient of performance. Two single effect absorption circuits are combined with heat exchange occurring between a condenser and absorber of a high temperature circuit, and a generator of a low temperature circuit. The evaporators of both the high and low temperature circuits provide cooling to an external heat load.

  3. Differential transimpedance amplifier circuit for correlated differential amplification

    DOE Patents [OSTI]

    Gresham, Christopher A.; Denton, M. Bonner; Sperline, Roger P.

    2008-07-22

    A differential transimpedance amplifier circuit for correlated differential amplification. The amplifier circuit increase electronic signal-to-noise ratios in charge detection circuits designed for the detection of very small quantities of electrical charge and/or very weak electromagnetic waves. A differential, integrating capacitive transimpedance amplifier integrated circuit comprising capacitor feedback loops performs time-correlated subtraction of noise.

  4. Protective circuit for thyristor controlled systems and thyristor converter embodying such protective circuit

    DOE Patents [OSTI]

    Downhower, Jr., Francis H.; Finlayson, Paul T.

    1984-04-10

    A snubber circuit coupled across each thyristor to be gated in a chain of thyristors determines the critical output of a NOR LATCH whenever one snubber circuit could not be charged and discharged under normal gating conditions because of a short failure.

  5. Oregon Cascades Play Fairway Analysis: Faults and Heat Flow maps

    SciTech Connect (OSTI)

    Adam Brandt

    2015-11-15

    This submission includes a fault map of the Oregon Cascades and backarc, a probability map of heat flow, and a fault density probability layer. More extensive metadata can be found within each zip file.

  6. Lockout device for high voltage circuit breaker

    DOE Patents [OSTI]

    Kozlowski, Lawrence J.; Shirey, Lawrence A.

    1993-01-01

    An improved lockout assembly is provided for a circuit breaker to lock the switch handle into a selected switch position. The lockout assembly includes two main elements, each having a respective foot for engaging a portion of the upper housing wall of the circuit breaker. The first foot is inserted into a groove in the upper housing wall, and the second foot is inserted into an adjacent aperture (e.g., a slot) in the upper housing wall. The first foot is slid under and into engagement with a first portion, and the second foot is slid under and into engagement with a second portion of the upper housing wall. At the same time the repsective two feet are placed in engagement with the respective portions of the upper housing wall, two holes, one on each of the respective two main elements of the assembly, are placed in registration; and a locking device, such as a special scissors equipped with a padlock, is installed through the registered holes to secure the lockout assembly on the circuit breaker. When the lockout assembly of the invention is secured on the circuit breaker, the switch handle of the circuit breaker is locked into the selected switch position and prevented from being switched to another switch position.

  7. Dual circuit embossed sheet heat transfer panel

    DOE Patents [OSTI]

    Morgan, G.D.

    1984-02-21

    A heat transfer panel provides redundant cooling for fusion reactors or the like environment requiring low-mass construction. Redundant cooling is provided by two independent cooling circuits, each circuit consisting of a series of channels joined to inlet and outlet headers. The panel comprises a welded joinder of two full-size and two much smaller partial-size sheets. The first full-size sheet is embossed to form first portions of channels for the first and second circuits, as well as a header for the first circuit. The second full-sized sheet is then laid over and welded to the first full-size sheet. The first and second partial-size sheets are then overlaid on separate portions of the second full-sized sheet, and are welded thereto. The first and second partial-sized sheets are embossed to form inlet and outlet headers, which communicate with channels of the second circuit through apertures formed in the second full-sized sheet. 6 figs.

  8. Dual circuit embossed sheet heat transfer panel

    DOE Patents [OSTI]

    Morgan, Grover D.

    1984-01-01

    A heat transfer panel provides redundant cooling for fusion reactors or the like environment requiring low-mass construction. Redundant cooling is provided by two independent cooling circuits, each circuit consisting of a series of channels joined to inlet and outlet headers. The panel comprises a welded joinder of two full-size and two much smaller partial-size sheets. The first full-size sheet is embossed to form first portions of channels for the first and second circuits, as well as a header for the first circuit. The second full-sized sheet is then laid over and welded to the first full-size sheet. The first and second partial-size sheets are then overlaid on separate portions of the second full-sized sheet, and are welded thereto. The first and second partial-sized sheets are embossed to form inlet and outlet headers, which communicate with channels of the second circuit through apertures formed in the second full-sized sheet.

  9. Lockout device for high voltage circuit breaker

    DOE Patents [OSTI]

    Kozlowski, L.J.; Shirey, L.A.

    1993-01-26

    An improved lockout assembly is provided for a circuit breaker to lock the switch handle into a selected switch position. The lockout assembly includes two main elements, each having a respective foot for engaging a portion of the upper housing wall of the circuit breaker. The first foot is inserted into a groove in the upper housing wall, and the second foot is inserted into an adjacent aperture (e.g., a slot) in the upper housing wall. The first foot is slid under and into engagement with a first portion, and the second foot is slid under and into engagement with a second portion of the upper housing wall. At the same time the respective two feet are placed in engagement with the respective portions of the upper housing wall, two holes, one on each of the respective two main elements of the assembly, are placed in registration; and a locking device, such as a special scissors equipped with a padlock, is installed through the registered holes to secure the lockout assembly on the circuit breaker. When the lockout assembly of the invention is secured on the circuit breaker, the switch handle of the circuit breaker is locked into the selected switch position and prevented from being switched to another switch position.

  10. Deep drilling phase of the Pen Brand Fault Program

    SciTech Connect (OSTI)

    Stieve, A.

    1991-05-15

    This deep drilling activity is one element of the Pen Branch Fault Program at Savannah River Site (SRS). The effort will consist of three tasks: the extension of wells PBF-7 and PBF-8 into crystalline basement, geologic and drilling oversight during drilling operations, and the lithologic description and analysis of the recovered core. The drilling program addresses the association of the Pen Branch fault with order fault systems such as the fault that formed the Bunbarton basin in the Triassic.

  11. Understanding Fault Characteristics of Inverter-Based Distributed Energy Resources

    SciTech Connect (OSTI)

    Keller, J.; Kroposki, B.

    2010-01-01

    This report discusses issues and provides solutions for dealing with fault current contributions from inverter-based distributed energy resources.

  12. All row, planar fault detection system

    DOE Patents [OSTI]

    Archer, Charles Jens; Pinnow, Kurt Walter; Ratterman, Joseph D; Smith, Brian Edward

    2013-07-23

    An apparatus, program product and method for detecting nodal faults may simultaneously cause designated nodes of a cell to communicate with all nodes adjacent to each of the designated nodes. Furthermore, all nodes along the axes of the designated nodes are made to communicate with their adjacent nodes, and the communications are analyzed to determine if a node or connection is faulty.

  13. Multi-directional fault detection system

    DOE Patents [OSTI]

    Archer, Charles Jens; Pinnow, Kurt Walter; Ratterman, Joseph D.; Smith, Brian Edward

    2009-03-17

    An apparatus, program product and method checks for nodal faults in a group of nodes comprising a center node and all adjacent nodes. The center node concurrently communicates with the immediately adjacent nodes in three dimensions. The communications are analyzed to determine a presence of a faulty node or connection.

  14. Multi-directional fault detection system

    DOE Patents [OSTI]

    Archer, Charles Jens; Pinnow, Kurt Walter; Ratterman, Joseph D.; Smith, Brian Edward

    2010-11-23

    An apparatus, program product and method checks for nodal faults in a group of nodes comprising a center node and all adjacent nodes. The center node concurrently communicates with the immediately adjacent nodes in three dimensions. The communications are analyzed to determine a presence of a faulty node or connection.

  15. Multi-directional fault detection system

    DOE Patents [OSTI]

    Archer, Charles Jens; Pinnow, Kurt Walter; Ratterman, Joseph D.; Smith, Brian Edward

    2010-06-29

    An apparatus, program product and method checks for nodal faults in a group of nodes comprising a center node and all adjacent nodes. The center node concurrently communicates with the immediately adjacent nodes in three dimensions. The communications are analyzed to determine a presence of a faulty node or connection.

  16. Lithium Circuit Test Section Design and Fabrication

    SciTech Connect (OSTI)

    Godfroy, Thomas; Garber, Anne; Martin, James

    2006-01-20

    The Early Flight Fission -- Test Facilities (EFF-TF) team has designed and built an actively pumped lithium flow circuit. Modifications were made to a circuit originally designed for NaK to enable the use of lithium that included application specific instrumentation and hardware. Component scale freeze/thaw tests were conducted to both gain experience with handling and behavior of lithium in solid and liquid form and to supply anchor data for a Generalized Fluid System Simulation Program (GFSSP) model that was modified to include the physics for freeze/thaw transitions. Void formation was investigated. The basic circuit components include: reactor segment, lithium to gas heat exchanger, electromagnetic (EM) liquid metal pump, load/drain reservoir, expansion reservoir, instrumentation, and trace heaters. This paper discusses the overall system design and build and the component testing findings.

  17. Radiation-hardened transistor and integrated circuit

    DOE Patents [OSTI]

    Ma, Kwok K.

    2007-11-20

    A composite transistor is disclosed for use in radiation hardening a CMOS IC formed on an SOI or bulk semiconductor substrate. The composite transistor has a circuit transistor and a blocking transistor connected in series with a common gate connection. A body terminal of the blocking transistor is connected only to a source terminal thereof, and to no other connection point. The blocking transistor acts to prevent a single-event transient (SET) occurring in the circuit transistor from being coupled outside the composite transistor. Similarly, when a SET occurs in the blocking transistor, the circuit transistor prevents the SET from being coupled outside the composite transistor. N-type and P-type composite transistors can be used for each and every transistor in the CMOS IC to radiation harden the IC, and can be used to form inverters and transmission gates which are the building blocks of CMOS ICs.

  18. Circuit electromechanics with single photon strong coupling

    SciTech Connect (OSTI)

    Xue, Zheng-Yuan Yang, Li-Na; Zhou, Jian

    2015-07-13

    In circuit electromechanics, the coupling strength is usually very small. Here, replacing the capacitor in circuit electromechanics by a superconducting flux qubit, we show that the coupling among the qubit and the two resonators can induce effective electromechanical coupling which can attain the strong coupling regime at the single photon level with feasible experimental parameters. We use dispersive couplings among two resonators and the qubit while the qubit is also driven by an external classical field. These couplings form a three-wave mixing configuration among the three elements where the qubit degree of freedom can be adiabatically eliminated, and thus results in the enhanced coupling between the two resonators. Therefore, our work constitutes the first step towards studying quantum nonlinear effect in circuit electromechanics.

  19. Package for integrated optic circuit and method

    DOE Patents [OSTI]

    Kravitz, S.H.; Hadley, G.R.; Warren, M.E.; Carson, R.F.; Armendariz, M.G.

    1998-08-04

    A structure and method are disclosed for packaging an integrated optic circuit. The package comprises a first wall having a plurality of microlenses formed therein to establish channels of optical communication with an integrated optic circuit within the package. A first registration pattern is provided on an inside surface of one of the walls of the package for alignment and attachment of the integrated optic circuit. The package in one embodiment may further comprise a fiber holder for aligning and attaching a plurality of optical fibers to the package and extending the channels of optical communication to the fibers outside the package. In another embodiment, a fiber holder may be used to hold the fibers and align the fibers to the package. The fiber holder may be detachably connected to the package. 6 figs.

  20. Package for integrated optic circuit and method

    DOE Patents [OSTI]

    Kravitz, Stanley H.; Hadley, G. Ronald; Warren, Mial E.; Carson, Richard F.; Armendariz, Marcelino G.

    1998-01-01

    A structure and method for packaging an integrated optic circuit. The package comprises a first wall having a plurality of microlenses formed therein to establish channels of optical communication with an integrated optic circuit within the package. A first registration pattern is provided on an inside surface of one of the walls of the package for alignment and attachment of the integrated optic circuit. The package in one embodiment may further comprise a fiber holder for aligning and attaching a plurality of optical fibers to the package and extending the channels of optical communication to the fibers outside the package. In another embodiment, a fiber holder may be used to hold the fibers and align the fibers to the package. The fiber holder may be detachably connected to the package.

  1. Up-and-down chopper circuit

    DOE Patents [OSTI]

    Goffeau, Jacques R.

    1979-01-01

    An improved Up-and-Down Chopper Circuit is provided which is useful for voltage regulation in a bi-directional DC power system. In the down mode, power is switched from a DC power source to a lower voltage energy storing load while in the up mode stored energy in the load is transferred to the higher voltage source. The system uses Darlington transistor switches in a conventional connection. The improvement relates to circuit additions to eliminate the effects of inter-electrode capacitance inherent with this Darlington transistor switching arrangement.

  2. Circuit for measuring time differences among events

    DOE Patents [OSTI]

    Romrell, Delwin M.

    1977-01-01

    An electronic circuit has a plurality of input terminals. Application of a first input signal to any one of the terminals initiates a timing sequence. Later inputs to the same terminal are ignored but a later input to any other terminal of the plurality generates a signal which can be used to measure the time difference between the later input and the first input signal. Also, such time differences may be measured between the first input signal and an input signal to any other terminal of the plurality or the circuit may be reset at any time by an external reset signal.

  3. Internal cooling circuit for gas turbine bucket

    DOE Patents [OSTI]

    Hyde, Susan Marie; Davis, Richard Mallory

    2005-10-25

    In a gas turbine bucket having a shank portion and an airfoil portion having leading and trailing edges and pressure and suction sides, an internal cooling circuit, the internal cooling circuit having a serpentine configuration including plural radial outflow passages and plural radial inflow passages, and wherein a coolant inlet passage communicates with a first of the radial outflow passages along the trailing edge, the first radial outflow passage having a plurality of radially extending and radially spaced elongated rib segments extending between and connecting the pressure and suction sides in a middle region of the first passage to prevent ballooning of the pressure and suction sides at the first radial outflow passage.

  4. Superconducting-semiconducting circuits, devices and systems

    SciTech Connect (OSTI)

    Kroger, H.; Ghoshal, U.S.

    1991-06-18

    This paper describes a superconducting-semiconducting electrical circuit element. It comprises: a superconducting charge controlled three-terminal device, having a device control terminal, a second terminal and a third terminal, wherein the output current between the second and third terminals is controlled by the voltage applied to the control terminal, and wherein the output current exhibits superconducting characteristics as a function of temperature and input charge conditions; and a cryogenic semiconducting interconnect circuit, adapted to receive as an input an output signal from the superconducting device, and to provide a semiconductor switching voltage level output signal modulated by the input signal from the superconducting device.

  5. Protection from ground faults in the stator winding of generators at power plants in the Siberian networks

    SciTech Connect (OSTI)

    Vainshtein, R. A.; Lapin, V. I.; Naumov, A. M.; Doronin, A. V.; Yudin, S. M.

    2010-05-15

    The experience of many years of experience in developing and utilization of ground fault protection in the stator winding of generators in the Siberian networks is generalized. The main method of protection is to apply a direct current or an alternating current with a frequency of 25 Hz to the primary circuits of the stator. A direct current is applied to turbo generators operating in a unit with a transformer without a resistive coupling to the external grid or to other generators. Applying a 25 Hz control current is appropriate for power generation systems with compensation of a capacitive short circuit current to ground. This method forms the basis for protection of generators operating on busbars, hydroelectric generators with a neutral grounded through an arc-suppression reactor, including in consolidated units with generators operating in parallel on a single low-voltage transformer winding.

  6. Triple effect absorption chiller utilizing two refrigeration circuits

    SciTech Connect (OSTI)

    DeVault, R.C.

    1988-03-22

    This patent describes a heat absorption method for an absorption chiller. It comprises: providing a firs absorption system circuit for operation within a first temperature range, providing a second absorption system circuit for operation within a second temperature range; heat exchanging refrigerant and absorber solution; thermal communication with an external heat load. This patent describes a heat absorption apparatus for use as an absorption chiller. It includes: a first absorption system circuit for operation within a first temperature range; a second absorption system circuit for operation within a second temperature range which has a lower maximum temperature relative to the first temperature range; the first circuit having generator means, condenser means, evaporator means, and absorber means operatively connected together; the second circuit having generator means condenser means, evaporator means, and absorber means operative connected together; and the first circuit condenser means and the first circuit absorber means being in heat exchange communication with the second circuit generator means.

  7. Coordinated Fault Tolerance for High-Performance Computing

    SciTech Connect (OSTI)

    Dongarra, Jack; Bosilca, George; et al.

    2013-04-08

    Our work to meet our goal of end-to-end fault tolerance has focused on two areas: (1) improving fault tolerance in various software currently available and widely used throughout the HEC domain and (2) using fault information exchange and coordination to achieve holistic, systemwide fault tolerance and understanding how to design and implement interfaces for integrating fault tolerance features for multiple layers of the software stack—from the application, math libraries, and programming language runtime to other common system software such as jobs schedulers, resource managers, and monitoring tools.

  8. Pulse circuit apparatus for gas discharge laser

    DOE Patents [OSTI]

    Bradley, Laird P.

    1980-01-01

    Apparatus and method using a unique pulse circuit for a known gas discharge laser apparatus to provide an electric field for preconditioning the gas below gas breakdown and thereafter to place a maximum voltage across the gas which maximum voltage is higher than that previously available before the breakdown voltage of that gas laser medium thereby providing greatly increased pumping of the laser.

  9. Count-doubling time safety circuit

    DOE Patents [OSTI]

    Rusch, Gordon K.; Keefe, Donald J.; McDowell, William P.

    1981-01-01

    There is provided a nuclear reactor count-factor-increase time monitoring circuit which includes a pulse-type neutron detector, and means for counting the number of detected pulses during specific time periods. Counts are compared and the comparison is utilized to develop a reactor scram signal, if necessary.

  10. Bioluminescent bioreporter integrated circuit detection methods

    DOE Patents [OSTI]

    Simpson, Michael L.; Paulus, Michael J.; Sayler, Gary S.; Applegate, Bruce M.; Ripp, Steven A.

    2005-06-14

    Disclosed are monolithic bioelectronic devices comprising a bioreporter and an OASIC. These bioluminescent bioreporter integrated circuit are useful in detecting substances such as pollutants, explosives, and heavy-metals residing in inhospitable areas such as groundwater, industrial process vessels, and battlefields. Also disclosed are methods and apparatus for detection of particular analytes, including ammonia and estrogen compounds.

  11. Integrated Circuit Failure Analysis Hypertext Help System

    Energy Science and Technology Software Center (OSTI)

    1995-02-23

    This software assists a failure analyst performing failure analysis on integrated circuits. The software can also be used to train inexperienced failure analysts. The software also provides a method for storing information and making it easily available to experienced failure analysts.

  12. Integrated Circuit Failure Analysis Expert System

    Energy Science and Technology Software Center (OSTI)

    1995-10-03

    The software assists a failure analyst performing failure anaysis on intergrated circuits. The software can also be used to train inexperienced failure analysts. The software also provides a method for storing information and making it easily available to experienced failure analysts.

  13. Electronic circuit for measuring series connected electrochemical cell voltages

    DOE Patents [OSTI]

    Ashtiani, Cyrus N.; Stuart, Thomas A.

    2000-01-01

    An electronic circuit for measuring voltage signals in an energy storage device is disclosed. The electronic circuit includes a plurality of energy storage cells forming the energy storage device. A voltage divider circuit is connected to at least one of the energy storage cells. A current regulating circuit is provided for regulating the current through the voltage divider circuit. A voltage measurement node is associated with the voltage divider circuit for producing a voltage signal which is proportional to the voltage across the energy storage cell.

  14. Statistical Fault Detection & Diagnosis Expert System

    Energy Science and Technology Software Center (OSTI)

    1996-12-18

    STATMON is an expert system that performs real-time fault detection and diagnosis of redundant sensors in any industrial process requiring high reliability. After a training period performed during normal operation, the expert system monitors the statistical properties of the incoming signals using a pattern recognition test. If the test determines that statistical properties of the signals have changed, the expert system performs a sequence of logical steps to determine which sensor or machine component hasmoredegraded.less

  15. Undulator Hall Air Temperature Fault Scenarios

    SciTech Connect (OSTI)

    Sevilla, J.; Welch, J.; ,

    2010-11-17

    Recent experience indicates that the LCLS undulator segments must not, at any time following tuning, be allowed to change temperature by more than about {+-}2.5 C or the magnetic center will irreversibly shift outside of acceptable tolerances. This vulnerability raises a concern that under fault conditions the ambient temperature in the Undulator Hall might go outside of the safe range and potentially could require removal and retuning of all the segments. In this note we estimate changes that can be expected in the Undulator Hall air temperature for three fault scenarios: (1) System-wide power failure; (2) Heating Ventilation and Air Conditioning (HVAC) system shutdown; and (3) HVAC system temperature regulation fault. We find that for either a system-wide power failure or an HVAC system shutdown (with the technical equipment left on), the short-term temperature changes of the air would be modest due to the ability of the walls and floor to act as a heat ballast. No action would be needed to protect the undulator system in the event of a system-wide power failure. Some action to adjust the heat balance, in the case of the HVAC power failure with the equipment left on, might be desirable but is not required. On the other hand, a temperature regulation failure of the HVAC system can quickly cause large excursions in air temperature and prompt action would be required to avoid damage to the undulator system.

  16. Noise isolation system for high-speed circuits

    DOE Patents [OSTI]

    McNeilly, D.R.

    1983-12-29

    A noise isolation circuit is provided that consists of a dual function bypass which confines high-speed switching noise to the component or circuit which generates it and isolates the component or circuit from high-frequency noise transients which may be present on the ground and power supply busses. A local circuit ground is provided which is coupled to the system ground by sufficient impedance to force the dissipation of the noise signal in the local circuit or component generating the noise. The dual function bypass network couples high-frequency noise signals generated in the local component or circuit through a capacitor to the local ground while isolating the component or circuit from noise signals which may be present on the power supply busses or system ground. The network is an effective noise isolating system and is applicable to both high-speed analog and digital circuits.

  17. Noise isolation system for high-speed circuits

    DOE Patents [OSTI]

    McNeilly, David R.

    1986-01-01

    A noise isolation circuit is provided that consists of a dual function bypass which confines high-speed switching noise to the component or circuit which generates it and isolates the component or circuit from high-frequency noise transients which may be present on the ground and power supply busses. A local circuit ground is provided which is coupled to the system ground by sufficient impedance to force the dissipation of the noise signal in the local circuit or component generating the noise. The dual function bypass network couples high-frequency noise signals generated in the local component or circuit through a capacitor to the local ground while isolating the component or circuit from noise signals which may be present on the power supply busses or system ground. The network is an effective noise isolating system and is applicable to both high-speed analog and digital circuits.

  18. Author for correspondence: Publications@ieee-pvsc.org

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Accelerated Life Testing of PV Arc-Fault Detectors Jay Johnson, Michael Neilsen, Paul Vianco, N. Rob Sorensen, Michael Montoya, Armando Fresquez Sandia National Laboratories, Albuquerque, NM, 87185, USA Abstract - As of 2011, the National Electrical Code® (NEC) has required arc-fault circuit interrupters (AFCIs) to be incorporated into photovoltaic (PV) systems to prevent fires. Some manufacturers are designing AFCIs to consist of arc-fault detectors (AFD) incorporated into inverters or

  19. Calculating the probability of injected carbon dioxide plumes encountering faults

    SciTech Connect (OSTI)

    Jordan, P.D.

    2011-04-01

    One of the main concerns of storage in saline aquifers is leakage via faults. In the early stages of site selection, site-specific fault coverages are often not available for these aquifers. This necessitates a method using available fault data to estimate the probability of injected carbon dioxide encountering and migrating up a fault. The probability of encounter can be calculated from areal fault density statistics from available data, and carbon dioxide plume dimensions from numerical simulation. Given a number of assumptions, the dimension of the plume perpendicular to a fault times the areal density of faults with offsets greater than some threshold of interest provides probability of the plume encountering such a fault. Application of this result to a previously planned large-scale pilot injection in the southern portion of the San Joaquin Basin yielded a 3% and 7% chance of the plume encountering a fully and half seal offsetting fault, respectively. Subsequently available data indicated a half seal-offsetting fault at a distance from the injection well that implied a 20% probability of encounter for a plume sufficiently large to reach it.

  20. Detachment faults: Evidence for a low-angle origin

    SciTech Connect (OSTI)

    Scott, R.J.; Lister, G.S. )

    1992-09-01

    The origin of low-angle normal faults or detachment faults mantling metamorphic core complexes in the southwestern United States remains controversial. If [sigma][sub 1] is vertical during extension, the formation of, or even slip along, such low-angle normal faults is mechanically implausible. No records exist of earthquakes on low-angle normal faults in areas currently undergoing continental extension, except from an area of actively forming core complexes in the Solomon Sea, Papua New Guinea. In light of such geophysical and mechanical arguments, W.R. Buck and B. Wernicke and G.J. Axen proposed models in which detachment faults originate as high-angle normal faults, but rotate to low angles and become inactive as extension proceeds. These models are inconsistent with critical field relations in several core complexes. The Rawhide fault, an areally extensive detachment fault in western Arizona, propagated at close to its present subhorizontal orientation late in the Tertiary extension of the region. Neither the Wernicke and Axen nor Buck models predict such behavior; in fact, both models preclude the operation of low-angle normal faults. The authors recommend that alternative explanations or modifications of existing models are needed to explain the evidence that detachment faults form and operate with gentle dips.

  1. Dual-circuit segmented rail phased induction motor

    DOE Patents [OSTI]

    Marder, Barry M.; Cowan, Jr., Maynard

    2002-01-01

    An improved linear motor utilizes two circuits, rather that one circuit and an opposed plate, to gain efficiency. The powered circuit is a flat conductive coil. The opposed segmented rail circuit is either a plurality of similar conductive coils that are shorted, or a plurality of ladders formed of opposed conductive bars connected by a plurality of spaced conductors. In each embodiment, the conductors are preferably cables formed from a plurality of intertwined insulated wires to carry current evenly.

  2. Technique for extending the range of a signal measuring circuit

    DOE Patents [OSTI]

    Chaprnka, Anthony G.; Sun, Shan C.; Vercellotti, Leonard C.

    1978-01-01

    An input signal supplied to a signal measuring circuit is either amplified or attenuated as necessary to establish the magnitude of the input signal within the defined dynamic range of the measuring circuit and the output signal developed by the measuring circuit is subsequently readjusted through amplification or attenuation to develop an output signal which corresponds to the magnitude of the initial input signal.

  3. TRIAC/SCR proportional control circuit

    DOE Patents [OSTI]

    Hughes, W.J.

    1999-04-06

    A power controller device is disclosed which uses a voltage-to-frequency converter in conjunction with a zero crossing detector to linearly and proportionally control AC power being supplied to a load. The output of the voltage-to frequency converter controls the ``reset`` input of a R-S flip flop, while an ``0`` crossing detector controls the ``set`` input. The output of the flip flop triggers a monostable multivibrator controlling the SCR or TRIAC firing circuit connected to the load. Logic gates prevent the direct triggering of the multivibrator in the rare instance where the ``reset`` and ``set`` inputs of the flip flop are in coincidence. The control circuit can be supplemented with a control loop, providing compensation for line voltage variations. 9 figs.

  4. Nanoeletromechanical switch and logic circuits formed therefrom

    SciTech Connect (OSTI)

    Nordquist, Christopher D.; Czaplewski, David A.

    2010-05-18

    A nanoelectromechanical (NEM) switch is formed on a substrate with a source electrode containing a suspended electrically-conductive beam which is anchored to the substrate at each end. This beam, which can be formed of ruthenium, bows laterally in response to a voltage applied between a pair of gate electrodes and the source electrode to form an electrical connection between the source electrode and a drain electrode located near a midpoint of the beam. Another pair of gate electrodes and another drain electrode can be located on an opposite side of the beam to allow for switching in an opposite direction. The NEM switch can be used to form digital logic circuits including NAND gates, NOR gates, programmable logic gates, and SRAM and DRAM memory cells which can be used in place of conventional CMOS circuits, or in combination therewith.

  5. Custom VLSI circuits for high energy physics

    SciTech Connect (OSTI)

    Parker, S.

    1998-06-01

    This article provides a brief guide to integrated circuits, including their design, fabrication, testing, radiation hardness, and packaging. It was requested by the Panel on Instrumentation, Innovation, and Development of the International Committee for Future Accelerators, as one of a series of articles on instrumentation for future experiments. Their original request emphasized a description of available custom circuits and a set of recommendations for future developments. That has been done, but while traps that stop charge in solid-state devices are well known, those that stop physicists trying to develop the devices are not. Several years spent dodging the former and developing the latter made clear the need for a beginner`s guide through the maze, and that is the main purpose of this text.

  6. TRIAC/SCR proportional control circuit

    SciTech Connect (OSTI)

    Hughes, Wallace J.

    1997-12-01

    A power controller device which uses a voltage-to-frequency converter in conjunction with a zero crossing detector to linearly and proportionally control AC power being supplied to a load. The output of the voltage to frequency converter controls the reset input of a R-S flip flop, while an 0 crossing detector controls the set input. The output of the flip flop triggers a monostable multivibrator controlling the SCR or TRIAC firing circuit connected to the load. Logic gates prevent the direct triggering of the multivibrator in the rare instance where the reset and set inputs of the flip flop are in coincidence. The control circuit can be supplemented with a control loop, providing compensation for line voltage variations.

  7. TRIAC/SCR proportional control circuit

    DOE Patents [OSTI]

    Hughes, Wallace J.

    1999-01-01

    A power controller device which uses a voltage-to-frequency converter in conjunction with a zero crossing detector to linearly and proportionally control AC power being supplied to a load. The output of the voltage-to frequency converter controls the "reset" input of a R-S flip flop, while an "0" crossing detector controls the "set" input. The output of the flip flop triggers a monostable multivibrator controlling the SCR or TRIAC firing circuit connected to the load. Logic gates prevent the direct triggering of the multivibrator in the rare instance where the "reset" and "set" inputs of the flip flop are in coincidence. The control circuit can be supplemented with a control loop, providing compensation for line voltage variations.

  8. Vacuum die attach for integrated circuits

    DOE Patents [OSTI]

    Schmitt, Edward H.; Tuckerman, David B.

    1991-01-01

    A thin film eutectic bond for attaching an integrated circuit die to a circuit substrate is formed by coating at least one bonding surface on the die and substrate with an alloying metal, assembling the die and substrate under compression loading, and heating the assembly to an alloying temperature in a vacuum. A very thin bond, 10 microns or less, which is substantially void free, is produced. These bonds have high reliability, good heat and electrical conduction, and high temperature tolerance. The bonds are formed in a vacuum chamber, using a positioning and loading fixture to compression load the die, and an IR lamp or other heat source. For bonding a silicon die to a silicon substrate, a gold silicon alloy bond is used. Multiple dies can be bonded simultaneously. No scrubbing is required.

  9. Single event upset protection circuit and method

    DOE Patents [OSTI]

    Wallner, John; Gorder, Michael

    2016-03-22

    An SEU protection circuit comprises first and second storage means for receiving primary and redundant versions, respectively, of an n-bit wide data value that is to be corrected in case of an SEU occurrence; the correction circuit requires that the data value be a 1-hot encoded value. A parity engine performs a parity operation on the n bits of the primary data value. A multiplexer receives the primary and redundant data values and the parity engine output at respective inputs, and is arranged to pass the primary data value to an output when the parity engine output indicates `odd` parity, and to pass the redundant data value to the output when the parity engine output indicates `even` parity. The primary and redundant data values are suitably state variables, and the parity engine is preferably an n-bit wide XOR or XNOR gate.

  10. A Docking Casette For Printed Circuit Boards

    DOE Patents [OSTI]

    Barringer, Dennis R. (Wallkill, NY); Seminaro, Edward J. (Milton, NY); Toffler, Harold M. (Newburgh, NY)

    2003-08-19

    A docking apparatus for printed circuit boards including a cassette housing, having a housing base, a housing cover and a housing wall, wherein the housing base and the housing wall are disposed relative to each other so as to define a housing cavity for containing a printed circuit board and wherein the housing wall includes a cable opening disposed so as to be communicated with the housing cavity, a linkage mechanism, wherein the linkage mechanism includes an engagement configuration and a disengagement configuration and wherein the linkage mechanism is disposed so as to be associated with the cassette housing and a housing bezel, wherein the housing bezel is disposed relative to the cassette housing so as to be associated with the cable opening.

  11. Vacuum die attach for integrated circuits

    DOE Patents [OSTI]

    Schmitt, E.H.; Tuckerman, D.B.

    1991-09-10

    A thin film eutectic bond for attaching an integrated circuit die to a circuit substrate is formed by coating at least one bonding surface on the die and substrate with an alloying metal, assembling the die and substrate under compression loading, and heating the assembly to an alloying temperature in a vacuum. A very thin bond, 10 microns or less, which is substantially void free, is produced. These bonds have high reliability, good heat and electrical conduction, and high temperature tolerance. The bonds are formed in a vacuum chamber, using a positioning and loading fixture to compression load the die, and an IR lamp or other heat source. For bonding a silicon die to a silicon substrate, a gold silicon alloy bond is used. Multiple dies can be bonded simultaneously. No scrubbing is required. 1 figure.

  12. Base drive and overlap protection circuit

    DOE Patents [OSTI]

    Gritter, David J.

    1983-01-01

    An inverter (34) which provides power to an A. C. machine (28) is controlled by a circuit (36) employing PWM control strategy whereby A. C. power is supplied to the machine at a preselectable frequency and preselectable voltage. This is accomplished by the technique of waveform notching in which the shapes of the notches are varied to determine the average energy content of the overall waveform. Through this arrangement, the operational efficiency of the A. C. machine is optimized. The control circuit includes a microcomputer and memory element which receive various parametric inputs and calculate optimized machine control data signals therefrom. The control data is asynchronously loaded into the inverter through an intermediate buffer (38). A base drive and overlap protection circuit is included to insure that both transistors of a complimentary pair are not conducting at the same time. In its preferred embodiment, the present invention is incorporated within an electric vehicle (10) employing a 144 VDC battery pack (32) and a three-phase induction motor (18).

  13. Fault-Oblivious Exascale Computing Environment | Argonne Leadership

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Computing Facility Fault-Oblivious Exascale Computing Environment PI Name: Maya B. Gokhale PI Email: gokhale2@llnl.gov Allocation Program: INCITE Allocation Hours at ALCF: 10,000,000 Year: 2012 Research Domain: Computer Science Two areas of concern that have emerged from several DOE meetings on exascale systems (machines with 100 million cores) are runtime systems which can function at that scale, and fault management. The Fault Oblivious Exascale (FOX) project aims to build a software stack

  14. An Assessment of Fault Current Limiter Testing Requirements | Department of

    Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

    Energy Fault Current Limiter Testing Requirements An Assessment of Fault Current Limiter Testing Requirements The U.S. Department of Energy's (DOE) Office of Electricity Delivery and Energy Reliability (OE) is conducting research and development (R&D) on next-generation electricity delivery equipment including fault current limiters (FCLs). Prototype FCL devices are undergoing testing with the aim of market-ready devices making their debut in the transmission and distribution (T&D)

  15. Properties of the extra stage cube under multiple faults

    SciTech Connect (OSTI)

    Adams, G.B., III; Siegel, H.J.

    1982-01-01

    The extra stage cube (ESC) interconnection network, a fault tolerant structure, has been proposed for use in large-scale parallel and distributed systems. It has all of the interconnecting capabilities of the multistage cube-type networks that have been proposed for many systems, and the ESC provides fault tolerance for any single failure. The paper examines the ability of the ESC to operate with multiple faults. 9 references.

  16. High density printed electrical circuit board card connection system

    DOE Patents [OSTI]

    Baumbaugh, A.E.

    1997-05-06

    A zero insertion/extraction force printed circuit board card connection system comprises a cam-operated locking mechanism disposed along an edge portion of the printed circuit board. The extrusions along the circuit board mate with an extrusion fixed to the card cage having a plurality of electrical connectors. The card connection system allows the connectors to be held away from the circuit board during insertion/extraction and provides a constant mating force once the circuit board is positioned. The card connection system provides a simple solution to the need for a greater number of electrical signal connections. 12 figs.

  17. High density printed electrical circuit board card connection system

    DOE Patents [OSTI]

    Baumbaugh, Alan E.

    1997-01-01

    A zero insertion/extraction force printed circuit board card connection system comprises a cam-operated locking mechanism disposed along an edge portion of the printed circuit board. The extrusions along the circuit board mate with an extrusion fixed to the card cage having a plurality of electrical connectors. The card connection system allows the connectors to be held away from the circuit board during insertion/extraction and provides a constant mating force once the circuit board is positioned. The card connection system provides a simple solution to the need for a greater number of electrical signal connections.

  18. Recency of Faulting and Neotectonic Framework in the Dixie Valley...

    Open Energy Info (EERE)

    by active geothermal springs. More specifically, our investigation shows that induced stress concentrations at the endpoints of normal fault ruptures appear to promote favorable...

  19. Error Estimation for Fault Tolerance in Numerical Integration...

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Error Estimation for Fault Tolerance in Numerical Integration Solvers Event Sponsor: ... In numerical integration solvers, approximation error can be estimated at a low cost. We ...

  20. Understanding Fault Characteristics And Sediment Depth For Geothermal...

    Open Energy Info (EERE)

    Understanding Fault Characteristics And Sediment Depth For Geothermal Exploration Using 3D Gravity Inversion In Walker Valley, Nevada Jump to: navigation, search OpenEI Reference...

  1. Microsoft PowerPoint - HPC - Resilience-Fault Injection Research...

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    This document is approved for public release; further dissemination unlimited Resilience ... FIT 32Gbit High FIT 32Gbit Low FIT Resilience Fault Injection Research ...

  2. Upper crustal faulting in an obliquely extending orogen, structural...

    Open Energy Info (EERE)

    faulting in an obliquely extending orogen, structural control on permeability and production in the Coso Geothermal Field, eastern California Jump to: navigation, search OpenEI...

  3. Active Fault Controls At High-Temperature Geothermal Sites- Prospectin...

    Open Energy Info (EERE)

    model in which recently active (Holocene) faults are preferred conduits for migration of thermal water from deep crustal depths, and we infer that the detection of sites...

  4. Active Fault Segments As Potential Earthquake Sources- Inferences...

    Open Energy Info (EERE)

    Segments As Potential Earthquake Sources- Inferences From Integrated Geophysical Mapping Of The Magadi Fault System, Southern Kenya Rift Jump to: navigation, search OpenEI...

  5. Controls on Fault-Hosted Fluid Flow: Preliminary Results from...

    Open Energy Info (EERE)

    Flow: Preliminary Results from the Coso Geothermal Field, CA Abstract cap rock, permeability, fault, fracture, clay, Coso Authors Davatzes, N.C.; Hickman and S.H. Published...

  6. Dating of major normal fault systems using thermochronology-...

    Open Energy Info (EERE)

    Dating of major normal fault systems using thermochronology- An example from the Raft River detachment, Basin and Range, western United States Jump to: navigation, search OpenEI...

  7. Fault Mapping At Raft River Geothermal Area (1993) | Open Energy...

    Open Energy Info (EERE)

    Raft River Geothermal Area (1993) Jump to: navigation, search GEOTHERMAL ENERGYGeothermal Home Exploration Activity: Fault Mapping At Raft River Geothermal Area (1993) Exploration...

  8. Asking the right questions: benchmarking fault-tolerant extreme...

    Office of Scientific and Technical Information (OSTI)

    Title: Asking the right questions: benchmarking fault-tolerant extreme-scale systems. Abstract not provided. Authors: Widener, Patrick ; Ferreira, Kurt Brian ; Levy, Scott N. ; ...

  9. Statistical Fault Detection & Diagnosis Expert System

    Energy Science and Technology Software Center (OSTI)

    1996-12-18

    STATMON is an expert system that performs real-time fault detection and diagnosis of redundant sensors in any industrial process requiring high reliability. After a training period performed during normal operation, the expert system monitors the statistical properties of the incoming signals using a pattern recognition test. If the test determines that statistical properties of the signals have changed, the expert system performs a sequence of logical steps to determine which sensor or machine component hasmore » degraded.« less

  10. Accelerating functional verification of an integrated circuit

    SciTech Connect (OSTI)

    Deindl, Michael; Ruedinger, Jeffrey Joseph; Zoellin, Christian G.

    2015-10-27

    Illustrative embodiments include a method, system, and computer program product for accelerating functional verification in simulation testing of an integrated circuit (IC). Using a processor and a memory, a serial operation is replaced with a direct register access operation, wherein the serial operation is configured to perform bit shifting operation using a register in a simulation of the IC. The serial operation is blocked from manipulating the register in the simulation of the IC. Using the register in the simulation of the IC, the direct register access operation is performed in place of the serial operation.

  11. Accelerating functional verification of an integrated circuit

    DOE Patents [OSTI]

    Deindl, Michael; Ruedinger, Jeffrey Joseph; Zoellin, Christian G

    2015-11-05

    Illustrative embodiments include a method, system, and computer program product for accelerating functional verification in simulation testing of an integrated circuit (IC). Using a processor and a memory, a serial operation is replaced with a direct register access operation, wherein the serial operation is configured to perform bit shifting operation using a register in a simulation of the IC. The serial operation is blocked from manipulating the register in the simulation of the IC. Using the register in the simulation of the IC, the direct register access operation is performed in place of the serial operation.

  12. Simplified fabrication of magnetically coupled Josephson circuits

    SciTech Connect (OSTI)

    Smith, L.N.; Jillie, D.W.; Kroger, H.

    1985-03-01

    The authors describe a technique for fabricating magnetically coupled Josephson logic and memory circuits and SQUIDs which uses only two superconducting layers. These two layers perform multiple functions as the base and counterelectrodes of the tunnel junctions, the SQUID inductance and control lines, and the signal lines and groundplane between gates. This technique is illustrated by the specific example of a two junction, resistively damped SQUID designed to be fabricated using an all-refractory process which employs a total of five masking levels.

  13. Circuit for monitoring temperature of high-voltage equipment

    DOE Patents [OSTI]

    Jacobs, Martin E.

    1976-01-01

    This invention relates to an improved circuit for measuring temperature in a region at high electric potential and generating a read-out of the same in a region at lower potential. The circuit is specially designed to combine high sensitivity, stability, and accuracy. A major portion of the circuit situated in the high-potential region can take the form of an integrated circuit. The preferred form of the circuit includes an input section which is situated in the high-potential region and comprises a temperature-compensated thermocouple circuit for sensing temperature, an oscillator circuit for generating a train of ramp voltages whose rise time varies inversely with the thermocouple output, a comparator and switching circuit for converting the oscillator output to pulses whose frequency is proportional to the thermocouple output, and a light-emitting diode which is energized by these pulses. An optical coupling transmits the light pulses generated by the diode to an output section of the circuit, situated in a region at ground. The output section comprises means for converting the transmitted pulses to electrical pulses of corresponding frequency, means for amplifying the electrical pulses, and means for displaying the frequency of the same. The preferred embodiment of the overall circuit is designed so that the frequency of the output signal in hertz and tenths of hertz is equal to the sensed temperature in degrees and tenths of degrees.

  14. Capacitive charge generation apparatus and method for testing circuits

    DOE Patents [OSTI]

    Cole, E.I. Jr.; Peterson, K.A.; Barton, D.L.

    1998-07-14

    An electron beam apparatus and method for testing a circuit are disclosed. The electron beam apparatus comprises an electron beam incident on an outer surface of an insulating layer overlying one or more electrical conductors of the circuit for generating a time varying or alternating current electrical potential on the surface; and a measurement unit connected to the circuit for measuring an electrical signal capacitively coupled to the electrical conductors to identify and map a conduction state of each of the electrical conductors, with or without an electrical bias signal being applied to the circuit. The electron beam apparatus can further include a secondary electron detector for forming a secondary electron image for registration with a map of the conduction state of the electrical conductors. The apparatus and method are useful for failure analysis or qualification testing to determine the presence of any open-circuits or short-circuits, and to verify the continuity or integrity of electrical conductors buried below an insulating layer thickness of 1-100 {micro}m or more without damaging or breaking down the insulating layer. The types of electrical circuits that can be tested include integrated circuits, multi-chip modules, printed circuit boards and flexible printed circuits. 7 figs.

  15. Capacitive charge generation apparatus and method for testing circuits

    DOE Patents [OSTI]

    Cole, Jr., Edward I.; Peterson, Kenneth A.; Barton, Daniel L.

    1998-01-01

    An electron beam apparatus and method for testing a circuit. The electron beam apparatus comprises an electron beam incident on an outer surface of an insulating layer overlying one or more electrical conductors of the circuit for generating a time varying or alternating current electrical potential on the surface; and a measurement unit connected to the circuit for measuring an electrical signal capacitively coupled to the electrical conductors to identify and map a conduction state of each of the electrical conductors, with or without an electrical bias signal being applied to the circuit. The electron beam apparatus can further include a secondary electron detector for forming a secondary electron image for registration with a map of the conduction state of the electrical conductors. The apparatus and method are useful for failure analysis or qualification testing to determine the presence of any open-circuits or short-circuits, and to verify the continuity or integrity of electrical conductors buried below an insulating layer thickness of 1-100 .mu.m or more without damaging or breaking down the insulating layer. The types of electrical circuits that can be tested include integrated circuits, multi-chip modules, printed circuit boards and flexible printed circuits.

  16. All-to-all sequenced fault detection system

    DOE Patents [OSTI]

    Archer, Charles Jens; Pinnow, Kurt Walter; Ratterman, Joseph D.; Smith, Brian Edward

    2010-11-02

    An apparatus, program product and method enable nodal fault detection by sequencing communications between all system nodes. A master node may coordinate communications between two slave nodes before sequencing to and initiating communications between a new pair of slave nodes. The communications may be analyzed to determine the nodal fault.

  17. Folding associated with extensional faulting: Sheep Range detachment, southern Nevada

    SciTech Connect (OSTI)

    Guth, P.L.

    1985-01-01

    The Sheep Range detachment is a major Miocene extensional fault system of the Great Basin. Its major faults have a scoop shape, with straight, N-S traces extending 15-30 km and then abruptly turning to strike E-W. Tertiary deformation involved simultaneous normal faulting, sedimentation, landsliding, and strike-slip faulting. Folds occur in two settings: landslide blocks and drag along major faults. Folds occur in landslide blocks and beneath them. Most folds within landslide blocks are tight anticlines, with limbs dipping 40-60 degrees. Brecciation of the folds and landslide blocks suggests brittle deformation. Near Quijinump Canyon in the Sheep Range, at least three landslide blocks (up to 500 by 1500 m) slid into a small Tertiary basin. Tertiary limestone beneath the Paleozoic blocks was isoclinally folded. Westward dips reveal drag folds along major normal faults, as regional dips are consistently to the east. The Chowderhead anticline is the largest drag fold, along an extensional fault that offsets Ordovician units 8 km. East-dipping Ordovician and Silurian rocks in the Desert Range form the hanging wall. East-dipping Cambrian and Ordovician units in the East Desert Range form the foot wall and east limb of the anticline. Caught along the fault plane, the anticline's west-dipping west limb contains mostly Cambrian units.

  18. Fault current limiter with shield and adjacent cores

    DOE Patents [OSTI]

    Darmann, Francis Anthony; Moriconi, Franco; Hodge, Eoin Patrick

    2013-10-22

    In a fault current limiter (FCL) of a saturated core type having at least one coil wound around a high permeability material, a method of suppressing the time derivative of the fault current at the zero current point includes the following step: utilizing an electromagnetic screen or shield around the AC coil to suppress the time derivative current levels during zero current conditions.

  19. Automated Proactive Fault Isolation: A Key to Automated Commissioning

    SciTech Connect (OSTI)

    Katipamula, Srinivas; Brambley, Michael R.

    2007-07-31

    In this paper, we present a generic model for automated continuous commissioing and then delve in detail into one of the processes, proactive testing for fault isolation, which is key to automating commissioning. The automated commissioining process uses passive observation-based fault detction and diagnostic techniques, followed by automated proactive testing for fault isolation, automated fault evaluation, and automated reconfiguration of controls together to continuously keep equipment controlled and running as intended. Only when hard failures occur or a physical replacement is required does the process require human intervention, and then sufficient information is provided by the automated commissioning system to target manual maintenance where it is needed. We then focus on fault isolation by presenting detailed logic that can be used to automatically isolate faults in valves, a common component in HVAC systems, as an example of how automated proactive fault isolation can be accomplished. We conclude the paper with a discussion of how this approach to isolating faults can be applied to other common HVAC components and their automated commmissioning and a summary of key conclusions of the paper.

  20. Automatic Fault Characterization via Abnormality-Enhanced Classification

    SciTech Connect (OSTI)

    Bronevetsky, G; Laguna, I; de Supinski, B R

    2010-12-20

    Enterprise and high-performance computing systems are growing extremely large and complex, employing hundreds to hundreds of thousands of processors and software/hardware stacks built by many people across many organizations. As the growing scale of these machines increases the frequency of faults, system complexity makes these faults difficult to detect and to diagnose. Current system management techniques, which focus primarily on efficient data access and query mechanisms, require system administrators to examine the behavior of various system services manually. Growing system complexity is making this manual process unmanageable: administrators require more effective management tools that can detect faults and help to identify their root causes. System administrators need timely notification when a fault is manifested that includes the type of fault, the time period in which it occurred and the processor on which it originated. Statistical modeling approaches can accurately characterize system behavior. However, the complex effects of system faults make these tools difficult to apply effectively. This paper investigates the application of classification and clustering algorithms to fault detection and characterization. We show experimentally that naively applying these methods achieves poor accuracy. Further, we design novel techniques that combine classification algorithms with information on the abnormality of application behavior to improve detection and characterization accuracy. Our experiments demonstrate that these techniques can detect and characterize faults with 65% accuracy, compared to just 5% accuracy for naive approaches.

  1. Development of Hydrologic Characterization Technology of Fault Zones

    SciTech Connect (OSTI)

    Karasaki, Kenzi; Onishi, Tiemi; Wu, Yu-Shu

    2008-03-31

    Through an extensive literature survey we find that there is very limited amount of work on fault zone hydrology, particularly in the field using borehole testing. The common elements of a fault include a core, and damage zones. The core usually acts as a barrier to the flow across it, whereas the damage zone controls the flow either parallel to the strike or dip of a fault. In most of cases the damage zone isthe one that is controlling the flow in the fault zone and the surroundings. The permeability of damage zone is in the range of two to three orders of magnitude higher than the protolith. The fault core can have permeability up to seven orders of magnitude lower than the damage zone. The fault types (normal, reverse, and strike-slip) by themselves do not appear to be a clear classifier of the hydrology of fault zones. However, there still remains a possibility that other additional geologic attributes and scaling relationships can be used to predict or bracket the range of hydrologic behavior of fault zones. AMT (Audio frequency Magneto Telluric) and seismic reflection techniques are often used to locate faults. Geochemical signatures and temperature distributions are often used to identify flow domains and/or directions. ALSM (Airborne Laser Swath Mapping) or LIDAR (Light Detection and Ranging) method may prove to be a powerful tool for identifying lineaments in place of the traditional photogrammetry. Nonetheless not much work has been done to characterize the hydrologic properties of faults by directly testing them using pump tests. There are some uncertainties involved in analyzing pressure transients of pump tests: both low permeability and high permeability faults exhibit similar pressure responses. A physically based conceptual and numerical model is presented for simulating fluid and heat flow and solute transport through fractured fault zones using a multiple-continuum medium approach. Data from the Horonobe URL site are analyzed to demonstrate the

  2. Interrogator system for identifying electrical circuits

    DOE Patents [OSTI]

    Jatko, W.B.; McNeilly, D.R.

    1988-04-12

    A system for interrogating electrical leads to correctly ascertain the identity of equipment attached to remote ends of the leads is disclosed. The system includes a source of a carrier signal generated in a controller/receiver to be sent over the leads and an identifier unit at the equipment. The identifier is activated by command of the carrier and uses a portion of the carrier to produce a supply voltage. Each identifier is uniquely programmed for a specific piece of equipment, and causes the impedance of the circuit to be modified whereby the carrier signal is modulated according to that program. The modulation can be amplitude, frequency or phase modulation. A demodulator in the controller/receiver analyzes the modulated carrier signal, and if a verified signal is recognized displays and/or records the information. This information can be utilized in a computer system to prepare a wiring diagram of the electrical equipment attached to specific leads. Specific circuit values are given for amplitude modulation, and the system is particularly described for use with thermocouples. 6 figs.

  3. Interrogator system for identifying electrical circuits

    DOE Patents [OSTI]

    Jatko, William B.; McNeilly, David R.

    1988-01-01

    A system for interrogating electrical leads to correctly ascertain the identity of equipment attached to remote ends of the leads. The system includes a source of a carrier signal generated in a controller/receiver to be sent over the leads and an identifier unit at the equipment. The identifier is activated by command of the carrier and uses a portion of the carrier to produce a supply voltage. Each identifier is uniquely programmed for a specific piece of equipment, and causes the impedance of the circuit to be modified whereby the carrier signal is modulated according to that program. The modulation can be amplitude, frequency or phase modulation. A demodulator in the controller/receiver analyzes the modulated carrier signal, and if a verified signal is recognized displays and/or records the information. This information can be utilized in a computer system to prepare a wiring diagram of the electrical equipment attached to specific leads. Specific circuit values are given for amplitude modulation, and the system is particularly described for use with thermocouples.

  4. Hydraulic actuator for an electric circuit breaker

    DOE Patents [OSTI]

    Imam, Imdad

    1983-01-01

    This actuator comprises a fluid motor having a piston, a breaker-opening space at one side of the piston, and a breaker-closing space at its opposite side. An accumulator freely communicates with the breaker-opening space for supplying pressurized fluid thereto during a circuit breaker opening operation. The breaker-opening space and the breaker-closing space are connected by an impeded flow passage. A pilot valve opens to allow the pressurized liquid in the breaker-closing space to flow to a back chamber of a normally closed main valve to cause the main valve to be opened during a circuit breaker opening operation to release the pressurized liquid from the breaker-closing space. An impeded passage affords communication between the back chamber and a sump located on the opposite side of the main valve from the back chamber. The pilot valve and impeded passage allow rapid opening of the main valve with pressurized liquid from the breaker closing side of the piston.

  5. Hydraulic actuator for an electric circuit breaker

    DOE Patents [OSTI]

    Imam, I.

    1983-05-17

    This actuator comprises a fluid motor having a piston, a breaker-opening space at one side of the piston, and a breaker-closing space at its opposite side. An accumulator freely communicates with the breaker-opening space for supplying pressurized fluid thereto during a circuit breaker opening operation. The breaker-opening space and the breaker-closing space are connected by an impeded flow passage. A pilot valve opens to allow the pressurized liquid in the breaker-closing space to flow to a back chamber of a normally closed main valve to cause the main valve to be opened during a circuit breaker opening operation to release the pressurized liquid from the breaker-closing space. An impeded passage affords communication between the back chamber and a sump located on the opposite side of the main valve from the back chamber. The pilot valve and impeded passage allow rapid opening of the main valve with pressurized liquid from the breaker closing side of the piston. 3 figs.

  6. Locating an active fault zone in Coso geothermal field by analyzing...

    Open Energy Info (EERE)

    waves from microearthquake data Abstract Active fault systems usually provide high-permeability channels for hydrothermal outflow in geothermal fields. Locating such fault systems...

  7. Self field triggered superconducting fault current limiter

    DOE Patents [OSTI]

    Tekletsadik, Kasegn D.

    2008-02-19

    A superconducting fault current limiter array with a plurality of superconductor elements arranged in a meanding array having an even number of supconductors parallel to each other and arranged in a plane that is parallel to an odd number of the plurality of superconductors, where the odd number of supconductors are parallel to each other and arranged in a plane that is parallel to the even number of the plurality of superconductors, when viewed from a top view. The even number of superconductors are coupled at the upper end to the upper end of the odd number of superconductors. A plurality of lower shunt coils each coupled to the lower end of each of the even number of superconductors and a plurality of upper shunt coils each coupled to the upper end of each of the odd number of superconductors so as to generate a generally orthoganal uniform magnetic field during quenching using only the magenetic field generated by the superconductors.

  8. Locating hardware faults in a parallel computer

    DOE Patents [OSTI]

    Archer, Charles J.; Megerian, Mark G.; Ratterman, Joseph D.; Smith, Brian E.

    2010-04-13

    Locating hardware faults in a parallel computer, including defining within a tree network of the parallel computer two or more sets of non-overlapping test levels of compute nodes of the network that together include all the data communications links of the network, each non-overlapping test level comprising two or more adjacent tiers of the tree; defining test cells within each non-overlapping test level, each test cell comprising a subtree of the tree including a subtree root compute node and all descendant compute nodes of the subtree root compute node within a non-overlapping test level; performing, separately on each set of non-overlapping test levels, an uplink test on all test cells in a set of non-overlapping test levels; and performing, separately from the uplink tests and separately on each set of non-overlapping test levels, a downlink test on all test cells in a set of non-overlapping test levels.

  9. Online Monitoring System for Performance Fault Detection

    SciTech Connect (OSTI)

    Gioiosa, Roberto; Kestor, Gokcen; Kerbyson, Darren J.

    2014-05-19

    To achieve the exaFLOPS performance within a contain power budget, next supercomputers will feature hundreds of millions of components operating at low- and near-threshold voltage. As the probability that at least one of these components fails during the execution of an application approaches certainty, it seems unrealistic to expect that any run of a scientific application will not experience some performance faults. We believe that there is need of a new generation of light-weight performance and debugging tools that can be used online even during production runs of parallel applications and that can identify performance anomalies during the application execution. In this work we propose the design and implementation of a monitoring system that continuously inspects the evolution of run

  10. Anastomosing grabens, low-angle faults, and Tertiary thrust( ) faults, western Markagunt Plateau, southwestern Utah

    SciTech Connect (OSTI)

    Maldonado, F.; Sable, E.G. )

    1993-04-01

    A structurally complex terrane composed of grabens and horsts, low-angle faults, Tertiary thrust( ) faults, gravity-slide blocks, and debris deposits has been mapped along the western Markagunt Plateau, east of Parowan and Summit, southwestern Utah. This terrane, structurally situated within the transition between the Basin and Range and Colorado Plateau provinces, contains Tertiary volcanic and sedimentary and Cretaceous sedimentary rocks. The structures are mostly Miocene to Oligocene but some are Pleistocene. The oldest structure is the Red Hills low-angle shear zone, interpreted as a shallow structure that decoupled an upper plate composed of a Miocene-Oligocene volcanic ash-flow tuff and volcaniclastic succession from a lower plate of Tertiary sedimentary rocks. The period of deformation on the shear zone is bracketed from field relationships between 22.5 and 20 Ma. The graben-horst system trends northeast and formed after about 20 Ma (and probably much later) based on displacement of dated dikes and a laccolith. The central part of the system contains many grabens that merge toward its southerly end to become a single graben. Within these grabens, (1) older structures are preserved, (2) debris eroded from horst walls forms lobe-shaped deposits, (3) Pleistocene basaltic cinder cones have localized along graben-bounding faults, and (4) rock units are locally folded suggesting some component of lateral translation along graben-bounding faults. Megabreccia deposits and landslide debris are common. Megabreccia deposits are interpreted as gravity-slide blocks of Miocene-Oligocene( ) age resulting from formation of the Red Hills shear zone, although some may be related to volcanism, and still others to later deformation. The debris deposits are landslides of Pleistocene-Pliocene( ) age possibly caused by continued uplift of the Markagunt Plateau.

  11. DSOPilot project Automatic receipt of short circuiting indicators...

    Open Energy Info (EERE)

    project Automatic receipt of short circuiting indicators Country Denmark Coordinates 56.26392, 9.501785 Loading map... "minzoom":false,"mappingservice":"googlemaps3","type...

  12. High Temperature, High Voltage Fully Integrated Gate Driver Circuit...

    Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

    D.C. PDF icon ape003tolbert2010p.pdf More Documents & Publications High Temperature, High Voltage Fully Integrated Gate Driver Circuit Wide Bandgap Materials Smart ...

  13. High Temperature, High Voltage Fully Integrated Gate Driver Circuit...

    Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

    -- Washington D.C. PDF icon ape03marlino.pdf More Documents & Publications High Temperature, High Voltage Fully Integrated Gate Driver Circuit Smart Integrated Power Module ...

  14. Automatic ranging circuit for a digital panel meter

    DOE Patents [OSTI]

    Mueller, Theodore R.; Ross, Harley H.

    1976-01-01

    This invention relates to a range changing circuit that operates in conjunction with a digital panel meter of fixed sensitivity. The circuit decodes the output of the panel meter and uses that information to change the gain of an input amplifier to the panel meter in order to insure that the maximum number of significant figures is always displayed in the meter. The circuit monitors five conditions in the meter and responds to any of four combinations of these conditions by means of logic elements to carry out the function of the circuit.

  15. Numerical and Experimental Investigation of Internal Short Circuit...

    Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

    Battery Thermal Modeling and Testing Implantation, Activation, Characterization and PreventionMitigation of Internal Short Circuits in Lithium-Ion Cells Progress of DOE Materials, ...

  16. ELECTRICAL CIRCUITS USING COLD-CATHODE TRIODE VALVES

    DOE Patents [OSTI]

    Goulding, F.S.

    1957-11-26

    An electrical circuit which may be utilized as a pulse generator or voltage stabilizer is presented. The circuit employs a cold-cathode triode valve arranged to oscillate between its on and off stages by the use of selected resistance-capacitance time constant components in the plate and trigger grid circuits. The magnitude of the d-c voltage applied to the trigger grid circuit effectively controls the repetition rate of the output pulses. In the voltage stabilizer arrangement the d-c control voltage is a portion of the supply voltage and the rectified output voltage is substantially constant.

  17. Safety and performance enhancement circuit for primary explosive detonators

    DOE Patents [OSTI]

    Davis, Ronald W.

    2006-04-04

    A safety and performance enhancement arrangement for primary explosive detonators. This arrangement involves a circuit containing an energy storage capacitor and preset self-trigger to protect the primary explosive detonator from electrostatic discharge (ESD). The circuit does not discharge into the detonator until a sufficient level of charge is acquired on the capacitor. The circuit parameters are designed so that normal ESD environments cannot charge the protection circuit to a level to achieve discharge. When functioned, the performance of the detonator is also improved because of the close coupling of the stored energy.

  18. Cluster-based architecture for fault-tolerant quantum computation...

    Office of Scientific and Technical Information (OSTI)

    In this cluster-based architecture, concatenated computation is implemented in a quite different way from the usual circuit-based architecture where physical gates are recursively ...

  19. Timing control by redundant inhibitory neuronal circuits

    SciTech Connect (OSTI)

    Tristan, I. Rulkov, N. F.; Huerta, R.; Rabinovich, M.

    2014-03-15

    Rhythms and timing control of sequential activity in the brain is fundamental to cognition and behavior. Although experimental and theoretical studies support the understanding that neuronal circuits are intrinsically capable of generating different time intervals, the dynamical origin of the phenomenon of functionally dependent timing control is still unclear. Here, we consider a new mechanism that is related to the multi-neuronal cooperative dynamics in inhibitory brain motifs consisting of a few clusters. It is shown that redundancy and diversity of neurons within each cluster enhances the sensitivity of the timing control with the level of neuronal excitation of the whole network. The generality of the mechanism is shown to work on two different neuronal models: a conductance-based model and a map-based model.

  20. Development of Characterization Technology for Fault Zone Hydrology

    SciTech Connect (OSTI)

    Karasaki, Kenzi; Onishi, Tiemi; Gasperikova, Erika; Goto, Junichi; Tsuchi, Hiroyuki; Miwa, Tadashi; Ueta, Keiichi; Kiho, Kenzo; MIyakawa, Kimio

    2010-08-06

    Several deep trenches were cut, and a number of geophysical surveys were conducted across the Wildcat Fault in the hills east of Berkeley, California. The Wildcat Fault is believed to be a strike-slip fault and a member of the Hayward Fault System, with over 10 km of displacement. So far, three boreholes of ~;; 150m deep have been core-drilled and borehole geophysical logs were conducted. The rocks are extensively sheared and fractured; gouges were observed at several depths and a thick cataclasitic zone was also observed. While confirming some earlier, published conclusions from shallow observations about Wildcat, some unexpected findings were encountered. Preliminary analysis indicates that Wildcat near the field site consists of multiple faults. The hydraulic test data suggest the dual properties of the hydrologic structure of the fault zone. A fourth borehole is planned to penetrate the main fault believed to lie in-between the holes. The main philosophy behind our approach for the hydrologic characterization of such a complex fractured system is to let the system take its own average and monitor a long term behavior instead of collecting a multitude of data at small length and time scales, or at a discrete fracture scale and to ?up-scale,? which is extremely tenuous.

  1. High Resolution PV Power Modeling for Distribution Circuit Analysis

    SciTech Connect (OSTI)

    Norris, B. L.; Dise, J. H.

    2013-09-01

    NREL has contracted with Clean Power Research to provide 1-minute simulation datasets of PV systems located at three high penetration distribution feeders in the service territory of Southern California Edison (SCE): Porterville, Palmdale, and Fontana, California. The resulting PV simulations will be used to separately model the electrical circuits to determine the impacts of PV on circuit operations.

  2. Developing 300°C Ceramic Circuit Boards

    SciTech Connect (OSTI)

    Normann, Randy A

    2015-02-15

    This paper covers the development of a geothermal ceramic circuit board technology using 3D traces in a machinable ceramic. Test results showing the circuit board to be operational to at least 550°C. Discussion on producing this type of board is outlined along with areas needing improvement.

  3. Leaky insulating paint for preventing discharge anomalies on circuit boards

    SciTech Connect (OSTI)

    Frederickson, A.R.; Enloe, C.L.; Mullen, E.G. ); Nanevicz, J.E.; Thayer, J.S. )

    1989-12-01

    This paper reports on a semi-insulating paint formulated and tested for preventing pulse discharges from causing damage to circuits on heavily irradiated circuit boards. The paint is tin oxide filled phenoxy resin with a bulk resistivity of 10{sup 8} ohm-cm. A typical coating is then 10{sup 10} ohms per square. It is applied over the finished, conformally coated circuit board and connected to ground where possible on the board. It works by minimizing the stored electric field energy prior to the discharge. With such high resistivity it can not load down most circuits. Tests were performed on circuit boards with and without the paint using energetic electron beams to simulate very high space exposure levels. Many potentially damaging pulses were seen without the paint, but application of the paint removed all large pulses and only a few small pulses were seen.

  4. Multi-channel detector readout method and integrated circuit

    DOE Patents [OSTI]

    Moses, William W.; Beuville, Eric; Pedrali-Noy, Marzio

    2004-05-18

    An integrated circuit which provides multi-channel detector readout from a detector array. The circuit receives multiple signals from the elements of a detector array and compares the sampled amplitudes of these signals against a noise-floor threshold and against one another. A digital signal is generated which corresponds to the location of the highest of these signal amplitudes which exceeds the noise floor threshold. The digital signal is received by a multiplexing circuit which outputs an analog signal corresponding the highest of the input signal amplitudes. In addition a digital control section provides for programmatic control of the multiplexer circuit, amplifier gain, amplifier reset, masking selection, and test circuit functionality on each input thereof.

  5. Multi-channel detector readout method and integrated circuit

    DOE Patents [OSTI]

    Moses, William W.; Beuville, Eric; Pedrali-Noy, Marzio

    2006-12-12

    An integrated circuit which provides multi-channel detector readout from a detector array. The circuit receives multiple signals from the elements of a detector array and compares the sampled amplitudes of these signals against a noise-floor threshold and against one another. A digital signal is generated which corresponds to the location of the highest of these signal amplitudes which exceeds the noise floor threshold. The digital signal is received by a multiplexing circuit which outputs an analog signal corresponding the highest of the input signal amplitudes. In addition a digital control section provides for programmatic control of the multiplexer circuit, amplifier gain, amplifier reset, masking selection, and test circuit functionality on each input thereof.

  6. Analysis of the growth of strike-slip faults using effective medium theory

    SciTech Connect (OSTI)

    Aydin, A.; Berryman, J.G.

    2009-10-15

    Increases in the dimensions of strike-slip faults including fault length, thickness of fault rock and the surrounding damage zone collectively provide quantitative definition of fault growth and are commonly measured in terms of the maximum fault slip. The field observations indicate that a common mechanism for fault growth in the brittle upper crust is fault lengthening by linkage and coalescence of neighboring fault segments or strands, and fault rock-zone widening into highly fractured inner damage zone via cataclastic deformation. The most important underlying mechanical reason in both cases is prior weakening of the rocks surrounding a fault's core and between neighboring fault segments by faulting-related fractures. In this paper, using field observations together with effective medium models, we analyze the reduction in the effective elastic properties of rock in terms of density of the fault-related brittle fractures and fracture intersection angles controlled primarily by the splay angles. Fracture densities or equivalent fracture spacing values corresponding to the vanishing Young's, shear, and quasi-pure shear moduli were obtained by extrapolation from the calculated range of these parameters. The fracture densities or the equivalent spacing values obtained using this method compare well with the field data measured along scan lines across the faults in the study area. These findings should be helpful for a better understanding of the fracture density/spacing distribution around faults and the transition from discrete fracturing to cataclastic deformation associated with fault growth and the related instabilities.

  7. Coupled hydro-mechanical processes and fault reactivation induced...

    Office of Scientific and Technical Information (OSTI)

    Coupled hydro-mechanical processes and fault reactivation induced by Co2 Injection in a three-layer storage formation Citation Details In-Document Search This content will become ...

  8. Recent earthquake sequences at Coso: Evidence for conjugate faulting...

    Open Energy Info (EERE)

    earthquake sequences at Coso: Evidence for conjugate faulting and stress loading near a geothermal field Jump to: navigation, search OpenEI Reference LibraryAdd to library Journal...

  9. STRESS AND FAULTING IN THE COSO GEOTHERMAL FIELD: UPDATE AND...

    Open Energy Info (EERE)

    STRESS AND FAULTING IN THE COSO GEOTHERMAL FIELD: UPDATE AND RECENT RESULTS FROM THE EAST FLANK AND COSO WASH Jump to: navigation, search OpenEI Reference LibraryAdd to library...

  10. INVESTIGATION OF HOLOCENE FAULTING PROPOSED C-746-U LANDFILL EXPANSION

    SciTech Connect (OSTI)

    Lettis, William

    2006-07-01

    This report presents the findings of a fault hazard investigation for the C-746-U landfill's proposed expansion located at the Department of Energy's (DOE) Paducah Gaseous Diffusion Plant (PGDP), in Paducah, Kentucky. The planned expansion is located directly north of the present-day C-746-U landfill. Previous geophysical studies within the PGDP site vicinity interpret possible northeast-striking faults beneath the proposed landfill expansion, although prior to this investigation the existence, locations, and ages of these inferred faults have not been confirmed through independent subsurface exploration. The purpose of this investigation is to assess whether or not Holocene-active fault displacement is present beneath the footprint of the proposed landfill expansion.

  11. Fault Tree Reliability Analysis and Design-for-reliability

    Energy Science and Technology Software Center (OSTI)

    1998-05-05

    WinR provides a fault tree analysis capability for performing systems reliability and design-for-reliability analyses. The package includes capabilities for sensitivity and uncertainity analysis, field failure data analysis, and optimization.

  12. Fault and joint geometry at Raft River geothermal area, Idaho...

    Open Energy Info (EERE)

    may be useful for locating the surface traces of faults in the reservoir. Authors Guth, L. R.; Bruhn, R. L.; Beck and S. L. Published DOE Information Bridge, 711981 DOI...

  13. High-Resolution Aeromagnetic Survey to Image Shallow Faults,...

    Open Energy Info (EERE)

    to Image Shallow Faults, Dixie Valley Geothermal Field, Nevada Abstract NA Author V. J. S. Grauch Published U.S. Geological Survey, 2002 Report Number 02-384 DOI Not Provided...

  14. Potential-induced degradation in solar cells: Electronic structure and diffusion mechanism of sodium in stacking faults of silicon

    SciTech Connect (OSTI)

    Ziebarth, Benedikt Gumbsch, Peter; Mrovec, Matous; Elssser, Christian

    2014-09-07

    Sodium decorated stacking faults (SFs) were recently identified as the primary cause of potential-induced degradation in silicon (Si) solar-cells due to local electrical short-circuiting of the p-n junctions. In the present study, we investigate these defects by first principles calculations based on density functional theory in order to elucidate their structural, thermodynamic, and electronic properties. Our calculations show that the presence of sodium (Na) atoms leads to a substantial elongation of the Si-Si bonds across the SF, and the coverage and continuity of the Na layer strongly affect the diffusion behavior of Na within the SF. An analysis of the electronic structure reveals that the presence of Na in the SF gives rise to partially occupied defect levels within the Si band gap that participate in electrical conduction along the SF.

  15. Exploiting data representation for fault tolerance

    DOE Public Access Gateway for Energy & Science Beta (PAGES Beta)

    Hoemmen, Mark Frederick; Elliott, J.; Sandia National Lab.; Mueller, F.

    2015-01-06

    Incorrect computer hardware behavior may corrupt intermediate computations in numerical algorithms, possibly resulting in incorrect answers. Prior work models misbehaving hardware by randomly flipping bits in memory. We start by accepting this premise, and present an analytic model for the error introduced by a bit flip in an IEEE 754 floating-point number. We then relate this finding to the linear algebra concepts of normalization and matrix equilibration. In particular, we present a case study illustrating that normalizing both vector inputs of a dot product minimizes the probability of a single bit flip causing a large error in the dot product'smore » result. Moreover, the absolute error is either less than one or very large, which allows detection of large errors. Then, we apply this to the GMRES iterative solver. We count all possible errors that can be introduced through faults in arithmetic in the computationally intensive orthogonalization phase of GMRES, and show that when the matrix is equilibrated, the absolute error is bounded above by one.« less

  16. Exploiting data representation for fault tolerance

    SciTech Connect (OSTI)

    Hoemmen, Mark Frederick; Elliott, J.; Mueller, F.

    2015-01-06

    Incorrect computer hardware behavior may corrupt intermediate computations in numerical algorithms, possibly resulting in incorrect answers. Prior work models misbehaving hardware by randomly flipping bits in memory. We start by accepting this premise, and present an analytic model for the error introduced by a bit flip in an IEEE 754 floating-point number. We then relate this finding to the linear algebra concepts of normalization and matrix equilibration. In particular, we present a case study illustrating that normalizing both vector inputs of a dot product minimizes the probability of a single bit flip causing a large error in the dot product's result. Moreover, the absolute error is either less than one or very large, which allows detection of large errors. Then, we apply this to the GMRES iterative solver. We count all possible errors that can be introduced through faults in arithmetic in the computationally intensive orthogonalization phase of GMRES, and show that when the matrix is equilibrated, the absolute error is bounded above by one.

  17. Detachment Faulting & Geothermal Resources - Pearl Hot Spring, NV |

    Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

    Department of Energy Detachment Faulting & Geothermal Resources - Pearl Hot Spring, NV presentation at the April 2013 peer review meeting held in Denver, Colorado. pearl_hot_springs_peer2013.pdf (1.5 MB) More Documents & Publications Detachment Faulting & Geothermal Resources - Pearl Hot Spring, NV Conducting a 3D Converted Shear Wave Project to Reduce Exploration Risk at Wister, CA Crump Geyser: High Precision Geophysics & Detailed Structural Exploration & Slim Well

  18. Near-surface geophysical characterization of Holocene faults conducive to

    Office of Scientific and Technical Information (OSTI)

    geothermal flow near Pyramid Lake, Nevada (Conference) | SciTech Connect Conference: Near-surface geophysical characterization of Holocene faults conducive to geothermal flow near Pyramid Lake, Nevada Citation Details In-Document Search Title: Near-surface geophysical characterization of Holocene faults conducive to geothermal flow near Pyramid Lake, Nevada Colton Dudley, Alison Dorsey, Paul Opdyke, Dustin Naphan, Marlon Ramos, John Louie, Paul Schwering, and Satish Pullammanappallil, 2013,

  19. Preliminary observations on Quaternary reverse faulting along the southern front of the Northern Range of Trinidad

    SciTech Connect (OSTI)

    Beltran, C. , Caracus )

    1993-02-01

    Several geomorphological evidences of Quaternary reverse faulting are observed along the southern front of the Northern Range in Trinidad between Port-of-Spain and Matura Point. Such a mountain front is associated to a reverse fault system showing an imbricated pattern southward. In the north, the system is limited by a structural feature showing an important vertical component. Southward this system progressively changes to low angle faults. This geometry is corroborated by seismic profiling in the continent shelf. The active faulting evidences consist in lateral drainage offsets, fault trenches, sag-ponds, triangular facets, and saddles. Some quaternary terraces show fault scarps and tilting. We postulate that these reverse fault systems as Arima Fault instead of El Pilar fault as it is not actually connected to the San Sebestian-El Pilar right-lateral slip system, due to the southward prolongation of the southern limit of the Caribbean Plate through the fault system of Los Bajos-El Soldado.

  20. Adding Fault Tolerance to NPB Benchmarks Using ULFM

    SciTech Connect (OSTI)

    Parchman, Zachary W; Vallee, Geoffroy R; Naughton III, Thomas J; Engelmann, Christian; Bernholdt, David E; Scott, Stephen L

    2016-01-01

    In the world of high-performance computing, fault tolerance and application resilience are becoming some of the primary concerns because of increasing hardware failures and memory corruptions. While the research community has been investigating various options, from system-level solutions to application-level solutions, standards such as the Message Passing Interface (MPI) are also starting to include such capabilities. The current proposal for MPI fault tolerant is centered around the User-Level Failure Mitigation (ULFM) concept, which provides means for fault detection and recovery of the MPI layer. This approach does not address application-level recovery, which is currently left to application developers. In this work, we present a mod- ification of some of the benchmarks of the NAS parallel benchmark (NPB) to include support of the ULFM capabilities as well as application-level strategies and mechanisms for application-level failure recovery. As such, we present: (i) an application-level library to checkpoint and restore data, (ii) extensions of NPB benchmarks for fault tolerance based on different strategies, (iii) a fault injection tool, and (iv) some preliminary results that show the impact of such fault tolerant strategies on the application execution.

  1. Microcomputer applications of, and modifications to, the modular fault trees

    SciTech Connect (OSTI)

    Zimmerman, T.L.; Graves, N.L.; Payne, A.C. Jr.; Whitehead, D.W.

    1994-10-01

    The LaSalle Probabilistic Risk Assessment was the first major application of the modular logic fault trees after the IREP program. In the process of performing the analysis, many errors were discovered in the fault tree modules that led to difficulties in combining the modules to form the final system fault trees. These errors are corrected in the revised modules listed in this report. In addition, the application of the modules in terms of editing them and forming them into the system fault trees was inefficient. Originally, the editing had to be done line by line and no error checking was performed by the computer. This led to many typos and other logic errors in the construction of the modular fault tree files. Two programs were written to help alleviate this problem: (1) MODEDIT - This program allows an operator to retrieve a file for editing, edit the file for the plant specific application, perform some general error checking while the file is being modified, and store the file for later use, and (2) INDEX - This program checks that the modules that are supposed to form one fault tree all link up appropriately before the files are,loaded onto the mainframe computer. Lastly, the modules were not designed for relay type logic common in BWR designs but for solid state type logic. Some additional modules were defined for modeling relay logic, and an explanation and example of their use are included in this report.

  2. Engine lubrication circuit including two pumps

    DOE Patents [OSTI]

    Lane, William H.

    2006-10-03

    A lubrication pump coupled to the engine is sized such that the it can supply the engine with a predetermined flow volume as soon as the engine reaches a peak torque engine speed. In engines that operate predominately at speeds above the peak torque engine speed, the lubrication pump is often producing lubrication fluid in excess of the predetermined flow volume that is bypassed back to a lubrication fluid source. This arguably results in wasted power. In order to more efficiently lubricate an engine, a lubrication circuit includes a lubrication pump and a variable delivery pump. The lubrication pump is operably coupled to the engine, and the variable delivery pump is in communication with a pump output controller that is operable to vary a lubrication fluid output from the variable delivery pump as a function of at least one of engine speed and lubrication flow volume or system pressure. Thus, the lubrication pump can be sized to produce the predetermined flow volume at a speed range at which the engine predominately operates while the variable delivery pump can supplement lubrication fluid delivery from the lubrication pump at engine speeds below the predominant engine speed range.

  3. Conceptual studies for a mercury target circuit

    SciTech Connect (OSTI)

    Sigg, B.

    1996-06-01

    For the now favored target design of the European Spallation Source project, i.e. the version using mercury as target material, a basic concept of the primary system has been worked out. It does not include a detailed design of the various components of the target circuit, but tries to outline a feasible solution for the system. Besides the removal of the thermal power of about 3MW produced in the target by the proton beam, the primary system has to satisfy a number of other requirements related to processing, safety, and operation. The basic proposal uses an electromagnetic pump and a mercury-water intermediate heat excanger, but other alternatives are also being discussed. Basic safety requirements, i.e. protection against radiation and toxic mercury vapours, are satisfied by a design using an air-tight primary system containment, double-walled tubes in the intermediate heat exchanger, a fail-safe system for decay heat removal, and a remote handling facility for the active part of the system. Much engineering work has still to be done, because many details of the design of the mercury and gas processing systems remain to be clarified, the thermal-hydraulic components need further optimisation, the system for control and instrumentation is only known in outline and a through safety analysis will be required.

  4. Screening technology reduces ash in spiral circuits

    SciTech Connect (OSTI)

    Brodzik, P.

    2007-05-15

    In 2006, the James River Coal Co. selected the Stack Sizer to remove the minus 100 mesh high ash clay fraction from the clean coal spiral product circuits at the McCoy-Elkhorn Bevins Branch prep plant and at the Blue Diamond Leatherwood prep plant in Kentucky. The Stack Sizer is a multi-deck, high-frequency vibrating screen capable of separations as fine as 75 microns when fitted with Derrick Corp.'s patented high open area urethane screen panels. Full-scale lab tests and more than 10 months of continuous production have confirmed that the Stack Sizer fitted with Derrick 100 micron urethane screen panels consistently produces a clean coal fraction that ranges from 8 to 10% ash. Currently, each five-deck Stack Sizer operating at the Bevins Branch and Leatherwood prep plants is producing approximately 33 tons per hour of clean coal containing about 9% ash. This represents a clean coal yield of about 75% and an ash reduction of about 11% from the feed slurry. 3 figs. 2 tabs.

  5. Thermally-induced voltage alteration for integrated circuit analysis

    DOE Patents [OSTI]

    Cole, Jr., Edward I.

    2000-01-01

    A thermally-induced voltage alteration (TIVA) apparatus and method are disclosed for analyzing an integrated circuit (IC) either from a device side of the IC or through the IC substrate to locate any open-circuit or short-circuit defects therein. The TIVA apparatus uses constant-current biasing of the IC while scanning a focused laser beam over electrical conductors (i.e. a patterned metallization) in the IC to produce localized heating of the conductors. This localized heating produces a thermoelectric potential due to the Seebeck effect in any conductors with open-circuit defects and a resistance change in any conductors with short-circuit defects, both of which alter the power demand by the IC and thereby change the voltage of a source or power supply providing the constant-current biasing. By measuring the change in the supply voltage and the position of the focused and scanned laser beam over time, any open-circuit or short-circuit defects in the IC can be located and imaged. The TIVA apparatus can be formed in part from a scanning optical microscope, and has applications for qualification testing or failure analysis of ICs.

  6. Measurements of the Effects of Smoke on Active Circuits

    SciTech Connect (OSTI)

    Tanaka, T.J.

    1999-02-09

    Smoke has long been recognized as the most common source of fire damage to electrical equipment; however, most failures have been analyzed after the fire was out and the smoke vented. The effects caused while the smoke is still in the air have not been explored. Such effects have implications for new digital equipment being installed in nuclear reactors. The U.S. Nuclear Regulatory Commission is sponsoring work to determine the impact of smoke on digital instrumentation and control. As part of this program, Sandia National Laboratories has tested simple active circuits to determine how smoke affects them. These tests included the study of three possible failure modes on a functional board: (1) circuit bridging, (2) corrosion (metal loss), and (3) induction of stray capacitance. The performance of nine different circuits was measured continuously on bare and conformably coated boards during smoke exposures lasting 1 hour each and continued for 24 hours after the exposure started. The circuit that was most affected by smoke (100% change in measured values) was the one most sensitive to circuit bridging. Its high impedance (50 M{Omega}) was shorted during the exposure, but in some cases recovered after the smoke was vented. The other two failure modes, corrosion and induced stray capacitance, caused little change in the function of the circuits. The smoke permanently increased resistance of the circuit tested for corrosion, implying that the cent acts were corroded. However, the change was very small (< 2%). The stray-capacitance test circuit showed very little change after a smoke exposure in either the short or long term. The results of the tests suggest that conformal coatings and type of circuit are major considerations when designing digital circuitry to be used in critical control systems.

  7. High density electronic circuit and process for making

    DOE Patents [OSTI]

    Morgan, William P.

    1999-01-01

    High density circuits with posts that protrude beyond one surface of a substrate to provide easy mounting of devices such as integrated circuits. The posts also provide stress relief to accommodate differential thermal expansion. The process allows high interconnect density with fewer alignment restrictions and less wasted circuit area than previous processes. The resulting substrates can be test platforms for die testing and for multi-chip module substrate testing. The test platform can contain active components and emulate realistic operational conditions, replacing shorts/opens net testing.

  8. Biasing and fast degaussing circuit for magnetic materials

    DOE Patents [OSTI]

    Dress, W.B. Jr.; McNeilly, D.R.

    1983-10-04

    A dual-function circuit is provided which may be used to both magnetically bias and alternately, quickly degauss a magnetic device. The circuit may be magnetically coupled or directly connected electrically to a magnetic device, such as a magnetostrictive transducer, to magnetically bias the device by applying a dc current and alternately apply a selectively damped ac current to the device to degauss the device. The circuit is of particular value in many systems which use magnetostrictive transducers for ultrasonic transmission in different propagation modes over very short time periods.

  9. High density electronic circuit and process for making

    DOE Patents [OSTI]

    Morgan, W.P.

    1999-06-29

    High density circuits with posts that protrude beyond one surface of a substrate to provide easy mounting of devices such as integrated circuits are disclosed. The posts also provide stress relief to accommodate differential thermal expansion. The process allows high interconnect density with fewer alignment restrictions and less wasted circuit area than previous processes. The resulting substrates can be test platforms for die testing and for multi-chip module substrate testing. The test platform can contain active components and emulate realistic operational conditions, replacing shorts/opens net testing. 8 figs.

  10. Biasing and fast degaussing circuit for magnetic materials

    DOE Patents [OSTI]

    Dress, Jr., William B.; McNeilly, David R.

    1984-01-01

    A dual-function circuit is provided which may be used to both magnetically bias and alternately, quickly degauss a magnetic device. The circuit may be magnetically coupled or directly connected electrically to a magnetic device, such as a magnetostrictive transducer, to magnetically bias the device by applying a d.c. current and alternately apply a selectively damped a.c. current to the device to degauss the device. The circuit is of particular value in many systems which use magnetostrictive transducers for ultrasonic transmission in different propagation modes over very short time periods.

  11. Apparatus for mounting a diode in a microwave circuit

    DOE Patents [OSTI]

    Liu, Shing-gong

    1976-07-27

    Apparatus for mounting a diode in a microwave circuit for making electrical contact between the circuit and ground and for dissipation of heat between the diode and a heat sink. The diode, supported on a thermally and electrically conductive member, is resiliently pressed in electrical contact with the microwave circuit. A tapered collar on the member is elastically deformably wedged into a tapered aperture formed in a heat sink. The wedged collar tightens firmly around the member establishing good thermal and electrical conduction from the diode to the heat sink and ground. Disassembly is facilitated because of the elastically deformed collar.

  12. Compact fluid cooled power converter supporting multiple circuit boards

    DOE Patents [OSTI]

    Radosevich, Lawrence D.; Meyer, Andreas A.; Beihoff, Bruce C.; Kannenberg, Daniel G.

    2005-03-08

    A support may receive one or more power electronic circuits. The support may aid in removing heat from the circuits through fluid circulating through the support. The support, in conjunction with other packaging features may form a shield from both external EMI/RFI and from interference generated by operation of the power electronic circuits. Features may be provided to permit and enhance connection of the circuitry to external circuitry, such as improved terminal configurations. Modular units may be assembled that may be coupled to electronic circuitry via plug-in arrangements or through interface with a backplane or similar mounting and interconnecting structures.

  13. INSTRUCTIONS FOR PREPARATION OF PAPERS

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    PHOTOVOLTAIC FIRE DANGER REDUCTION WITH ARC-FAULT CIRCUIT INTERRUPTERS Kenneth M. Armijo*, Jay Johnson*, Richard K. Harrison*, Kara E. Thomas**, Michael Hibbs*, Armando Fresquez* * Sandia National Laboratories P.O. Box 5800 Albuquerque, NM 87185 kmarmij@sandia.gov jjohns2@sandia.gov rkharri@sandia.gov mhibbs@sandia.gov afresqu@sandia.gov ** The George Washington University Department of Chemistry 725 21st Street NW Washington, DC 20052 kethoma@sandia.gov ABSTRACT: Unmitigated arc-faults present

  14. High-Temperature Circuit Boards for Use in Geothermal Well Monitoring...

    Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

    High-Temperature Circuit Boards for Use in Geothermal Well Monitoring Applications Project objective: Develop and demonstrate high-temperature; multilayer electronic circuits ...

  15. Fault-tolerant corrector/detector chip for high-speed data processing

    DOE Patents [OSTI]

    Andaleon, David D.; Napolitano, Jr., Leonard M.; Redinbo, G. Robert; Shreeve, William O.

    1994-01-01

    An internally fault-tolerant data error detection and correction integrated circuit device (10) and a method of operating same. The device functions as a bidirectional data buffer between a 32-bit data processor and the remainder of a data processing system and provides a 32-bit datum is provided with a relatively short eight bits of data-protecting parity. The 32-bits of data by eight bits of parity is partitioned into eight 4-bit nibbles and two 4-bit nibbles, respectively. For data flowing towards the processor the data and parity nibbles are checked in parallel and in a single operation employing a dual orthogonal basis technique. The dual orthogonal basis increase the efficiency of the implementation. Any one of ten (eight data, two parity) nibbles are correctable if erroneous, or two different erroneous nibbles are detectable. For data flowing away from the processor the appropriate parity nibble values are calculated and transmitted to the system along with the data. The device regenerates parity values for data flowing in either direction and compares regenerated to generated parity with a totally self-checking equality checker. As such, the device is self-validating and enabled to both detect and indicate an occurrence of an internal failure. A generalization of the device to protect 64-bit data with 16-bit parity to protect against byte-wide errors is also presented.

  16. Fault-tolerant corrector/detector chip for high-speed data processing

    DOE Patents [OSTI]

    Andaleon, D.D.; Napolitano, L.M. Jr.; Redinbo, G.R.; Shreeve, W.O.

    1994-03-01

    An internally fault-tolerant data error detection and correction integrated circuit device and a method of operating same is described. The device functions as a bidirectional data buffer between a 32-bit data processor and the remainder of a data processing system and provides a 32-bit datum with a relatively short eight bits of data-protecting parity. The 32-bits of data by eight bits of parity is partitioned into eight 4-bit nibbles and two 4-bit nibbles, respectively. For data flowing towards the processor the data and parity nibbles are checked in parallel and in a single operation employing a dual orthogonal basis technique. The dual orthogonal basis increase the efficiency of the implementation. Any one of ten (eight data, two parity) nibbles are correctable if erroneous, or two different erroneous nibbles are detectable. For data flowing away from the processor the appropriate parity nibble values are calculated and transmitted to the system along with the data. The device regenerates parity values for data flowing in either direction and compares regenerated to generated parity with a totally self-checking equality checker. As such, the device is self-validating and enabled to both detect and indicate an occurrence of an internal failure. A generalization of the device to protect 64-bit data with 16-bit parity to protect against byte-wide errors is also presented. 8 figures.

  17. Triple inverter pierce oscillator circuit suitable for CMOS

    DOE Patents [OSTI]

    Wessendorf; Kurt O.

    2007-02-27

    An oscillator circuit is disclosed which can be formed using discrete field-effect transistors (FETs), or as a complementary metal-oxide-semiconductor (CMOS) integrated circuit. The oscillator circuit utilizes a Pierce oscillator design with three inverter stages connected in series. A feedback resistor provided in a feedback loop about a second inverter stage provides an almost ideal inverting transconductance thereby allowing high-Q operation at the resonator-controlled frequency while suppressing a parasitic oscillation frequency that is inherent in a Pierce configuration using a "standard" triple inverter for the sustaining amplifier. The oscillator circuit, which operates in a range of 10 50 MHz, has applications for use as a clock in a microprocessor and can also be used for sensor applications.

  18. Factors affecting the recognition of faults exposed in exploratory trenches. Bulletin

    SciTech Connect (OSTI)

    Bonilla, M.G.; Lienkaemper, J.J.

    1991-01-01

    During excavation of the reactor shaft at the proposed Bodega Head nuclear reactor in California, a fault was found in the sediments overlying bedrock. This apparent lack of a complete connection with the bedrock fault led to disagreement as to whether the fault in the sediments was of tectonic or landslide origin. The report provides information on some of the conditions under which fault strands in trench walls are either difficult to see or die out, and the frequency of occurrence of these phenomena. Information is also provided on the widths of fault zones, on the deformation of the hanging wall and footwall of dip-slip faults, and on the frequency of occurrence of pebble rotation, open fissures, gouge, slickensides, mixing, fault breccia, fault rubble, crushing, polishing, water barriers, and liquefaction effects. Short summaries of information relating to fault strands that are poorly expressed or that die out have already been published (Bonilla and Lienkaemper, 1988, 1990).

  19. DOE - Office of Legacy Management -- Electro Circuits Inc - CA 08

    Office of Legacy Management (LM)

    Electro Circuits Inc - CA 08 FUSRAP Considered Sites Site: Electro Circuits, Inc. (CA.08 ) Eliminated from consideration under FUSRAP Designated Name: Not Designated Alternate Name: None Location: 401 East Green Street , Pasadena , California CA.08-1 Evaluation Year: 1994 CA.08-2 Site Operations: Conducted ultrasonic tests on uranium ingots in the early 1950s. CA.08-3 CA.08-4 Site Disposition: Eliminated - Potential for contamination remote based on limited operations at the site CA.08-2

  20. Low Power Photomultiplier Tube Circuit And Method Thereor

    DOE Patents [OSTI]

    Bochenski, Edwin B.; Skinner, Jack L.; Dentinger, Paul M.; Lindblom, Scott C.

    2006-04-18

    An electrical circuit for a photomultiplier tube (PMT) is disclosed that reduces power consumption to a point where the PMT may be powered for extended periods with a battery. More specifically, the invention concerns a PMT circuit comprising a low leakage switch and a high voltage capacitor positioned between a resistive divider and each of the PMT dynodes, and a low power control scheme for recharging the capacitors.

  1. Cooling circuit for a gas turbine bucket and tip shroud

    DOE Patents [OSTI]

    Willett, Fred Thomas; Itzel, Gary Michael; Stathopoulos, Dimitrios; Plemmons, Larry Wayne; Plemmons, Helen M.; Lewis, Doyle C.

    2002-01-01

    An open cooling circuit for a gas turbine bucket wherein the bucket has an airfoil portion, and a tip shroud, the cooling circuit including a plurality of radial cooling holes extending through the airfoil portion and communicating with an enlarged internal area within the tip shroud before exiting the tip shroud such that a cooling medium used to cool the airfoil portion is subsequently used to cool the tip shroud.

  2. Design and Modeling of Pulsed Power Accelerators Via Circuit Analysis

    Energy Science and Technology Software Center (OSTI)

    1996-12-05

    SCREAMER simulates electrical circuits which may contain elements of variable resistance, capacitance and inductance. The user may add variable circuit elements in a simulation by choosing from a library of models or by writing a subroutine describing the element. Transmission lines, magnetically insulated transmission lines (MITLs) and arbitrary voltage and current sources may also be included. Transmission lines are modeled using pi-sections connected in series. Many models of switches and loads are included.

  3. Field Guide for Testing Existing Photovoltaic Systems for Ground Faults and Installing Equipment to Mitigate Fire Hazards

    SciTech Connect (OSTI)

    Brooks, William; Basso, Thomas; Coddington, Michael

    2015-10-01

    Ground faults and arc faults are the two most common reasons for fires in photovoltaic (PV) arrays and methods exist that can mitigate the hazards. This report provides field procedures for testing PV arrays for ground faults, and for implementing high resolution ground fault and arc fault detectors in existing and new PV system designs.

  4. Accident Fault Trees for Defense Waste Processing Facility

    SciTech Connect (OSTI)

    Sarrack, A.G.

    1999-06-22

    The purpose of this report is to document fault tree analyses which have been completed for the Defense Waste Processing Facility (DWPF) safety analysis. Logic models for equipment failures and human error combinations that could lead to flammable gas explosions in various process tanks, or failure of critical support systems were developed for internal initiating events and for earthquakes. These fault trees provide frequency estimates for support systems failures and accidents that could lead to radioactive and hazardous chemical releases both on-site and off-site. Top event frequency results from these fault trees will be used in further APET analyses to calculate accident risk associated with DWPF facility operations. This report lists and explains important underlying assumptions, provides references for failure data sources, and briefly describes the fault tree method used. Specific commitments from DWPF to provide new procedural/administrative controls or system design changes are listed in the ''Facility Commitments'' section. The purpose of the ''Assumptions'' section is to clarify the basis for fault tree modeling, and is not necessarily a list of items required to be protected by Technical Safety Requirements (TSRs).

  5. Ultra-low power microwave CHFET integrated circuit development

    SciTech Connect (OSTI)

    Baca, A.G.; Hietala, V.M.; Greenway, D.; Sloan, L.R.; Shul, R.J.; Muyshondt, G.P.; Dubbert, D.F.

    1998-04-01

    This report summarizes work on the development of ultra-low power microwave CHFET integrated circuit development. Power consumption of microwave circuits has been reduced by factors of 50--1,000 over commercially available circuits. Positive threshold field effect transistors (nJFETs and PHEMTs) have been used to design and fabricate microwave circuits with power levels of 1 milliwatt or less. 0.7 {micro}m gate nJFETs are suitable for both digital CHFET integrated circuits as well as low power microwave circuits. Both hybrid amplifiers and MMICs were demonstrated at the 1 mW level at 2.4 GHz. Advanced devices were also developed and characterized for even lower power levels. Amplifiers with 0.3 {micro}m JFETs were simulated with 8--10 dB gain down to power levels of 250 microwatts ({mu}W). However 0.25 {micro}m PHEMTs proved superior to the JFETs with amplifier gain of 8 dB at 217 MHz and 50 {mu}W power levels but they are not integrable with the digital CHFET technology.

  6. Solid-State Fault Current Limiter Development : Design and Testing Update of a 15kV SSCL Power Stack

    SciTech Connect (OSTI)

    Dr. Ram Adapa; Mr. Dante Piccone

    2012-04-30

    limiting or current interrupting capabilities. It can be applied to variety of applications from distribution class to transmission class power delivery grids and networks. It can also be applied to single major commercial and industrial loads and distributed generator supplies. The active switching of devices can be further utilized for protection of substation transformers. The stress on the system can be reduced substantially improving the life of the power system. It minimizes the voltage sag by speedy elimination of heavy fault currents and promises to be an important element of the utility power system. DOE Perspective This development effort is now focused on a 15kV system. This project will help mitigate the challenges of increasing available fault current. DOE has made a major contribution in providing a cost effective SSCL designed to integrate seamlessly into the Transmission and Distribution networks of today and the future. Approach SSCL development program for a 69kV SSCL was initiated which included the use of the Super GTO advanced semiconductor device which won the 2007 R&D100 Award. In the beginning, steps were identified to accomplish the economically viable design of a 69kV class Solid State Current Limiter that is extremely reliable, cost effective, and compact enough to be applied in urban transmission. The prime thrust in design and development was to encompass the 1000A and the 3000A ratings and provide a modular design to cover the wide range of applications. The focus of the project was then shifted to a 15kV class SSCL. The specifications for the 15kV power stack are reviewed. The design changes integrated into the 15kV power stack are discussed. In this Technical Update the complete project is summarized followed by a detailed test report. The power stack independent high voltage laboratory test requirements and results are presented. Keywords Solid State Current Limiter, SSCL, Fault Current Limiter, Fault Current Controller, Power electronics

  7. Impact of Installation Faults on Heat Pump Performance

    DOE Public Access Gateway for Energy & Science Beta (PAGES Beta)

    Hourahan, Glenn; Baxter, Van D.

    2015-01-01

    Numerous studies and surveys indicate that typically-installed HVAC equipment operate inefficiently and waste considerable energy due to varied installation errors (faults) such as improper refrigerant charge, incorrect airflow, oversized equipment, and leaky ducts. This article summarizes the results of a large United States (U.S.) experimental/analytical study (U.S. contribution to IEA HPP Annex 36) of the impact that different faults have on the performance of an air-source heat pump (ASHP) in a typical U.S. single-family house. It combines building effects, equipment effects, and climate effects in an evaluation of the faults impact on seasonal energy consumption through simulations of the house/ASHPmore » pump system.« less

  8. Network resilience; A measure of network fault tolerance

    SciTech Connect (OSTI)

    Najjar, W. . Dept. of Computer Science); Gaudoit, J.L. . Dept. of Electrical Engineering)

    1990-02-01

    The failure of a node in a multicomputer system will not only reduce the computational power but also alter the network's topology. Network fault tolerance is a measure of the number of failures the network can sustain before a disconnection occurs. It is expressed traditionally as the network's node degree. In this paper, the authors propose a probabilistic measure of network fault tolerance expressed as the probability f a disconnection. Qualitative evaluation of this measure is presented. As expected, the single-node disconnection probability is the dominant factor irrespective of the topology under consideration. They derive an analytical approximation of the disconnection probability and verify it with Monte Carlo simulation. Based on this model, the measures of network resilience and relative network resilience are proposed as probabilistic measures of network fault tolerance. These are then used to evaluate the effects of the disconnection probability on the reliability of the system.

  9. Impact of Installation Faults on Heat Pump Performance

    SciTech Connect (OSTI)

    Hourahan, Glenn; Baxter, Van D.

    2015-01-01

    Numerous studies and surveys indicate that typically-installed HVAC equipment operate inefficiently and waste considerable energy due to varied installation errors (faults) such as improper refrigerant charge, incorrect airflow, oversized equipment, and leaky ducts. This article summarizes the results of a large United States (U.S.) experimental/analytical study (U.S. contribution to IEA HPP Annex 36) of the impact that different faults have on the performance of an air-source heat pump (ASHP) in a typical U.S. single-family house. It combines building effects, equipment effects, and climate effects in an evaluation of the faults impact on seasonal energy consumption through simulations of the house/ASHP pump system.

  10. Garbage collection: an exercise in distributed, fault-tolerant programming

    SciTech Connect (OSTI)

    Vestal, S.C.

    1987-01-01

    Two garbage-collection algorithms are presented to reclaim unused storage in object-oriented systems implemented on local area networks. The algorithms are fault-tolerant and allowed parallel, incremental collection in an object address space distributed throughout the system. The two approaches allow multiple collectors, so some unused storage can be reclaimed in partitioned networks. The first method makes use of fault-tolerant reference counts together with an algorithm to collect cycles of objects that would otherwise remain unclaimed. The second method adapts a parallel collector so that it can be used to collect subspaces of the entire network address space. Throughout this work concern is with a methodology for developing distributed, parallel, fault-tolerant programs. Also, there is concern with the suitability of object-oriented systems for such applications.

  11. Multistage network with an additional stage for fault tolerance

    SciTech Connect (OSTI)

    Adams, G.B. III; Siegel, H.J.

    1982-01-01

    The extra stage cube (ESC) network, a fault tolerant structure, is proposed for use in large-scale parallel and distributed supercomputer systems. This network is derived from the generalised cube network by the addition of one stage of interchange boxes and a bypass capability for two stages. It is shown that the ESC provides fault tolerance for any single failure. Further, the network can be controlled even when it has a single failure, using a simple modification of a routing tag scheme proposed for the generalised cube. Both one-to-one and broadcast connections under routing tag control are performable by the faulted ESC. The effects of the extra stage on the partitioning and permuting abilities of the network are described. 19 references.

  12. Observations on Faults and Associated Permeability Structures in Hydrogeologic Units at the Nevada Test Site

    SciTech Connect (OSTI)

    Prothro, Lance B.; Drellack, Sigmund L.; Haugstad, Dawn N.; Huckins-Gang, Heather E.; Townsend, Margaret J.

    2009-03-30

    Observational data on Nevada Test Site (NTS) faults were gathered from a variety of sources, including surface and tunnel exposures, core samples, geophysical logs, and down-hole cameras. These data show that NTS fault characteristics and fault zone permeability structures are similar to those of faults studied in other regions. Faults at the NTS form complex and heterogeneous fault zones with flow properties that vary in both space and time. Flow property variability within fault zones can be broken down into four major components that allow for the development of a simplified, first approximation model of NTS fault zones. This conceptual model can be used as a general guide during development and evaluation of groundwater flow and contaminate transport models at the NTS.

  13. Attachment method for stacked integrated circuit (IC) chips

    DOE Patents [OSTI]

    Bernhardt, A.F.; Malba, V.

    1999-08-03

    An attachment method for stacked integrated circuit (IC) chips is disclosed. The method involves connecting stacked chips, such as DRAM memory chips, to each other and/or to a circuit board. Pads on the individual chips are rerouted to form pads on the side of the chip, after which the chips are stacked on top of each other whereby desired interconnections to other chips or a circuit board can be accomplished via the side-located pads. The pads on the side of a chip are connected to metal lines on a flexible plastic tape (flex) by anisotropically conductive adhesive (ACA). Metal lines on the flex are likewise connected to other pads on chips and/or to pads on a circuit board. In the case of a stack of DRAM chips, pads to corresponding address lines on the various chips may be connected to the same metal line on the flex to form an address bus. This method has the advantage of reducing the number of connections required to be made to the circuit board due to bussing; the flex can accommodate dimensional variation in the alignment of chips in the stack; bonding of the ACA is accomplished at low temperature and is otherwise simpler and less expensive than solder bonding; chips can be bonded to the ACA all at once if the sides of the chips are substantially coplanar, as in the case for stacks of identical chips, such as DRAM. 12 figs.

  14. Dual-circuit embossed-sheet heat-transfer panel

    DOE Patents [OSTI]

    Morgan, G.D.

    1982-08-23

    A heat transfer panel provides redundant cooling for fusion reactors or the like environment requiring low-mass construction. Redundant cooling is provided by two independent cooling circuits, each circuit consisting of a series of channels joined to inlet and outlet headers. The panel comprises a welded joinder of two full-size and two much smaller partial-size sheets. The first full-size sheet is embossed for form first portions of channels for the first and second circuits, as well as a header for the first circuit. The second full-sized sheet is then laid over and welded to the first full-size sheet. The first and second partial-size sheets are then overlaid on separate portions of the second full-sized sheet, and are welded thereto. The first and second partial-sized sheets are embossed to form inlet and outlet headers, which communicate with channels of the second circuit through apertures formed in the second full-sized sheet.

  15. Attachment method for stacked integrated circuit (IC) chips

    DOE Patents [OSTI]

    Bernhardt, Anthony F.; Malba, Vincent

    1999-01-01

    An attachment method for stacked integrated circuit (IC) chips. The method involves connecting stacked chips, such as DRAM memory chips, to each other and/or to a circuit board. Pads on the individual chips are rerouted to form pads on the side of the chip, after which the chips are stacked on top of each other whereby desired interconnections to other chips or a circuit board can be accomplished via the side-located pads. The pads on the side of a chip are connected to metal lines on a flexible plastic tape (flex) by anisotropically conductive adhesive (ACA). Metal lines on the flex are likewise connected to other pads on chips and/or to pads on a circuit board. In the case of a stack of DRAM chips, pads to corresponding address lines on the various chips may be connected to the same metal line on the flex to form an address bus. This method has the advantage of reducing the number of connections required to be made to the circuit board due to bussing; the flex can accommodate dimensional variation in the alignment of chips in the stack; bonding of the ACA is accomplished at low temperature and is otherwise simpler and less expensive than solder bonding; chips can be bonded to the ACA all at once if the sides of the chips are substantially coplanar, as in the case for stacks of identical chips, such as DRAM.

  16. Faulted reservoirs characterization by an image processing technique

    SciTech Connect (OSTI)

    Martinez-Angeles, R.

    1994-12-31

    This paper has developed an image processing method for obtaining the discontinuous areal distribution of oil parameters (formation top, porosity, water saturation,...) of faulted heterogeneous oil reservoirs. For its application it requires the previous knowledge of a set of discrete values z(k,l) from well-logs and seismic profiles. Faulted structures were discretized into continuous structures or blocks bounded by faults. The theoretical fundamental assumption of the proposed method establishes that the natural distributions can be considered as the superposition of several elementary brownian distributions, represented by discrete values z(k,l), whose physical model is the diffusion differential equation and its solution associated. This is a technique that allows the representation of a composed brownian distribution as a linear combination of all elementary brownian functions. For illustrating the operational aspect of brownian analysis, two examples are studied. The results are presented as a digital images by means of an image processing software. This method can be applied in mapping, three dimensions interpolation and reserves calculation of faulted reservoirs.

  17. Experimental and computational studies on stacking faults in zinc titanate

    SciTech Connect (OSTI)

    Sun, W.; Ageh, V.; Mohseni, H.; Scharf, T. W. E-mail: Jincheng.Du@unt.edu; Du, J. E-mail: Jincheng.Du@unt.edu

    2014-06-16

    Zinc titanate (ZnTiO{sub 3}) thin films grown by atomic layer deposition with ilmenite structure have recently been identified as an excellent solid lubricant, where low interfacial shear and friction are achieved due to intrafilm shear velocity accommodation in sliding contacts. In this Letter, high resolution transmission electron microscopy with electron diffraction revealed that extensive stacking faults are present on ZnTiO{sub 3} textured (104) planes. These growth stacking faults serve as a pathway for dislocations to glide parallel to the sliding direction and hence achieve low interfacial shear/friction. Generalized stacking fault energy plots also known as ?-surfaces were computed for the (104) surface of ZnTiO{sub 3} using energy minimization method with classical effective partial charge potential and verified by using density functional theory first principles calculations for stacking fault energies along certain directions. These two are in qualitative agreement but classical simulations generally overestimate the energies. In addition, the lowest energy path was determined to be along the [451{sup }] direction and the most favorable glide system is (104) ?451{sup }? that is responsible for the experimentally observed sliding-induced ductility.

  18. Reduced circuit implementation of encoder and syndrome generator

    DOE Patents [OSTI]

    Trager, Barry M; Winograd, Shmuel

    2014-05-27

    An error correction method and system includes an Encoder and Syndrome-generator that operate in parallel to reduce the amount of circuitry used to compute check symbols and syndromes for error correcting codes. The system and method computes the contributions to the syndromes and check symbols 1 bit at a time instead of 1 symbol at a time. As a result, the even syndromes can be computed as powers of the odd syndromes. Further, the system assigns symbol addresses so that there are, for an example GF(2.sup.8) which has 72 symbols, three (3) blocks of addresses which differ by a cube root of unity to allow the data symbols to be combined for reducing size and complexity of odd syndrome circuits. Further, the implementation circuit for generating check symbols is derived from syndrome circuit using the inverse of the part of the syndrome matrix for check locations.

  19. 3D circuit integration for Vertex and other detectors

    SciTech Connect (OSTI)

    Yarema, Ray; /Fermilab

    2007-09-01

    High Energy Physics continues to push the technical boundaries for electronics. There is no area where this is truer than for vertex detectors. Lower mass and power along with higher resolution and radiation tolerance are driving forces. New technologies such as SOI CMOS detectors and three dimensional (3D) integrated circuits offer new opportunities to meet these challenges. The fundamentals for SOI CMOS detectors and 3D integrated circuits are discussed. Examples of each approach for physics applications are presented. Cost issues and ways to reduce development costs are discussed.

  20. Berkeley Lab Scientists Grow Atomically Thin Transistors and Circuits |

    Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

    Department of Energy Berkeley Lab Scientists Grow Atomically Thin Transistors and Circuits Berkeley Lab Scientists Grow Atomically Thin Transistors and Circuits July 12, 2016 - 10:29am Addthis This schematic shows the chemical assembly of two-dimensional crystals. Graphene is first etched into channels and the TMDC molybdenum disulfide (MoS2) begins to nucleate around the edges and within the channel. On the edges, MoS2 slightly overlaps on top of the graphene. Finally, further growth

  1. Base drive circuit for a four-terminal power Darlington

    DOE Patents [OSTI]

    Lee, Fred C.; Carter, Roy A.

    1983-01-01

    A high power switching circuit which utilizes a four-terminal Darlington transistor block to improve switching speed, particularly in rapid turn-off. Two independent reverse drive currents are utilized during turn off in order to expel the minority carriers of the Darlington pair at their own charge sweep-out rate. The reverse drive current may be provided by a current transformer, the secondary of which is tapped to the base terminal of the power stage of the Darlington block. In one application, the switching circuit is used in each power switching element in a chopper-inverter drive of an electric vehicle propulsion system.

  2. Superconductor-semiconductor hybrid devices, circuits, and systems

    SciTech Connect (OSTI)

    Kroger, H.; Hilbert, C.; Gibson, D.A.; Ghoshal, U.; Smith, L.N.

    1989-08-01

    The discovery of superconductors whose critical temperatures are above liquid nitrogen temperature has prompted considerable interest in hybrid superconducting-semiconducting electronics applications. This paper reviews the efforts to hybridize these technologies. Some of these efforts have already been demonstrated on a laboratory scale; others are at present just theoretical proposals. Hybridization is possible on the system, circuit, and device levels. The authors review studies of the applications of superconductors for interconnecting semiconductor systems and combining semiconductor and superconductor devices to enhance the performance of both digital and analog systems. Novel circuit combinations of superconducting and semiconducting devices are mentioned, as are proposal to combine these materials on the device level.

  3. Thermometry and thermal management of carbon nanotube circuits

    SciTech Connect (OSTI)

    Mayle, Scott; Gupta, Tanuj; Davis, Sam; Chandrasekhar, Venkat; Shafraniuk, Serhii

    2015-05-21

    Monitoring of the intrinsic temperature and the thermal management is discussed for the carbon nanotube nano-circuits. The experimental results concerning fabricating and testing of a thermometer able to monitor the intrinsic temperature on nanoscale are reported. We also suggest a model which describes a bi-metal multilayer system able to filter the heat flow, based on separating the electron and phonon components one from another. The bi-metal multilayer structure minimizes the phonon component of the heat flow, while retaining the electronic part. The method allows one to improve the overall performance of the electronic nano-circuits due to minimizing the energy dissipation.

  4. Development of Asset Fault Signatures for Prognostic and Health Management in the Nuclear Industry

    SciTech Connect (OSTI)

    Vivek Agarwal; Nancy J. Lybeck; Randall Bickford; Richard Rusaw

    2014-06-01

    Proactive online monitoring in the nuclear industry is being explored using the Electric Power Research Institute’s Fleet-Wide Prognostic and Health Management (FW-PHM) Suite software. The FW-PHM Suite is a set of web-based diagnostic and prognostic tools and databases that serves as an integrated health monitoring architecture. The FW-PHM Suite has four main modules: Diagnostic Advisor, Asset Fault Signature (AFS) Database, Remaining Useful Life Advisor, and Remaining Useful Life Database. This paper focuses on development of asset fault signatures to assess the health status of generator step-up generators and emergency diesel generators in nuclear power plants. Asset fault signatures describe the distinctive features based on technical examinations that can be used to detect a specific fault type. At the most basic level, fault signatures are comprised of an asset type, a fault type, and a set of one or more fault features (symptoms) that are indicative of the specified fault. The AFS Database is populated with asset fault signatures via a content development exercise that is based on the results of intensive technical research and on the knowledge and experience of technical experts. The developed fault signatures capture this knowledge and implement it in a standardized approach, thereby streamlining the diagnostic and prognostic process. This will support the automation of proactive online monitoring techniques in nuclear power plants to diagnose incipient faults, perform proactive maintenance, and estimate the remaining useful life of assets.

  5. Characterization of Quaternary and suspected Quaternary faults, regional studies, Nevada and California

    SciTech Connect (OSTI)

    Anderson, R.E.; Bucknam, R.C.; Crone, A.J.; Haller, K.M.; Machette, M.N.; Personius, S.F.; Barnhard, T.P.; Cecil, M.J.; Dart, R.L.

    1995-12-31

    This report presents the results of geologic studies that help define the Quaternary history of selected faults in the region around Yucca Mountain, Nevada. These results are relevant to the seismic-design basis of a potential nuclear waste repository at Yucca Mountain. The relevancy is based, in part, on a need for additional geologic data that became apparent in ongoing studies that resulted in the identification of 51 relevant and potentially relevant individual and compound faults and fault zones in the 100-km-radius region around the Yucca Mountain site. Geologic data used to characterize the regional faults and fault zones as relevant or potentially relevant seismic sources includes age and displacement information, maximum fault lengths, and minimum distances between the fault and the Yucca Mountain site. For many of the regional faults, no paleoseismic field studies have previously been conducted, and age and displacement data are sparse to nonexistent. In November 1994, the Branch of Earthquake and Landslide Hazards entered into two Memoranda of Agreement with the Yucca Mountain Project Branch to conduct field reconnaissance, analysis, and interpretation of six relevant and six potentially relevant regional faults. This report describes the results of study of those faults exclusive of those in the Pahrump-Stewart Valley-Ash Meadows-Amargosa Valley areas. We also include results of a cursory study of faults on the west flank of the Specter Range and in the northern part of the Last Chance Range. A four-phase strategy was implemented for the field study.

  6. Demodulation circuit for AC motor current spectral analysis

    DOE Patents [OSTI]

    Hendrix, Donald E.; Smith, Stephen F.

    1990-12-18

    A motor current analysis method for the remote, noninvasive inspection of electric motor-operated systems. Synchronous amplitude demodulation and phase demodulation circuits are used singly and in combination along with a frequency analyzer to produce improved spectral analysis of load-induced frequencies present in the electric current flowing in a motor-driven system.

  7. Bioluminescent bioreporter integrated circuit devices and methods for detecting ammonia

    DOE Patents [OSTI]

    Simpson, Michael L [Knoxville, TN; Paulus, Michael J [Knoxville, TN; Sayler, Gary S [Blaine, TN; Applegate, Bruce M [West Lafayette, IN; Ripp, Steven A [Knoxville, TN

    2007-04-24

    Monolithic bioelectronic devices for the detection of ammonia includes a microorganism that metabolizes ammonia and which harbors a lux gene fused with a heterologous promoter gene stably incorporated into the chromosome of the microorganism and an Optical Application Specific Integrated Circuit (OASIC). The microorganism is generally a bacterium.

  8. Gas microstrip detectors based on flexible printed circuit technology

    SciTech Connect (OSTI)

    Salomon, M.; Crowe, K.; Faszer, W.; Lindsay, P.; Maier, J.M.C.

    1996-06-01

    The authors have studied the properties of a new type of Gas Microstrip Counter built using flexible printed circuit technology. They describe the manufacturing procedures, the assembly of the device, as well as its operation under a variety of conditions, gases and types of radiation. They also describe two new passivation materials, tantalum and niobium, which produce effective surfaces.

  9. Integrated circuit with dissipative layer for photogenerated carriers

    DOE Patents [OSTI]

    Myers, D.R.

    1988-04-20

    The sensitivity of an integrated circuit to single-event upsets is decreased by providing a dissipative layer of silicon nitride between a silicon substrate and the active device. Free carriers generated in the substrate are dissipated by the layer before they can build up charge on the active device. 1 fig.

  10. Compensated count-rate circuit for radiation survey meter

    DOE Patents [OSTI]

    Todd, R.A.

    1980-05-12

    A count-rate compensating circuit is provided which may be used in a portable Geiger-Mueller (G-M) survey meter to ideally compensate for couting loss errors in the G-M tube detector. In a G-M survey meter, wherein the pulse rate from the G-M tube is converted into a pulse rate current applied to a current meter calibrated to indicate dose rate, the compensation circuit generates and controls a reference voltage in response to the rate of pulses from the detector. This reference voltage is gated to the current-generating circuit at a rate identical to the rate of pulses coming from the detector so that the current flowing through the meter is varied in accordance with both the frequency and amplitude of the reference voltage pulses applied thereto so that the count rate is compensated ideally to indicate a true count rate within 1% up to a 50% duty cycle for the detector. A positive feedback circuit is used to control the reference voltage so that the meter output tracks true count rate indicative of the radiation dose rate.

  11. Compensated count-rate circuit for radiation survey meter

    DOE Patents [OSTI]

    Todd, Richard A.

    1981-01-01

    A count-rate compensating circuit is provided which may be used in a portable Geiger-Mueller (G-M) survey meter to ideally compensate for counting loss errors in the G-M tube detector. In a G-M survey meter, wherein the pulse rate from the G-M tube is converted into a pulse rate current applied to a current meter calibrated to indicate dose rate, the compensated circuit generates and controls a reference voltage in response to the rate of pulses from the detector. This reference voltage is gated to the current-generating circuit at a rate identical to the rate of pulses coming from the detector so that the current flowing through the meter is varied in accordance with both the frequency and amplitude of the reference voltage pulses applied thereto so that the count rate is compensated ideally to indicate a true count rate within 1% up to a 50% duty cycle for the detector. A positive feedback circuit is used to control the reference voltage so that the meter output tracks true count rate indicative of the radiation dose rate.

  12. Integrated circuit with dissipative layer for photogenerated carriers

    DOE Patents [OSTI]

    Myers, D.R.

    1989-09-12

    The sensitivity of an integrated circuit to single-event upsets is decreased by providing a dissi The U.S. Government has rights in this invention pursuant to Contract No. DE-ACO4-76DP00789 between the Department of Energy and AT&T Technologies, Inc.

  13. Integrated circuit with dissipative layer for photogenerated carriers

    DOE Patents [OSTI]

    Myers, David R.

    1989-01-01

    The sensitivity of an integrated circuit to single-event upsets is decreased by providing a dissi The U.S. Government has rights in this invention pursuant to Contract No. DE-ACO4-76DP00789 between the Department of Energy and AT&T Technologies, Inc.

  14. Two-dimensional lattice gauge theories with superconducting quantum circuits

    SciTech Connect (OSTI)

    Marcos, D.; Widmer, P.; Rico, E.; Hafezi, M.; Rabl, P.; Wiese, U.-J.; Zoller, P.

    2014-12-15

    A quantum simulator of U(1) lattice gauge theories can be implemented with superconducting circuits. This allows the investigation of confined and deconfined phases in quantum link models, and of valence bond solid and spin liquid phases in quantum dimer models. Fractionalized confining strings and the real-time dynamics of quantum phase transitions are accessible as well. Here we show how state-of-the-art superconducting technology allows us to simulate these phenomena in relatively small circuit lattices. By exploiting the strong non-linear couplings between quantized excitations emerging when superconducting qubits are coupled, we show how to engineer gauge invariant Hamiltonians, including ring-exchange and four-body Ising interactions. We demonstrate that, despite decoherence and disorder effects, minimal circuit instances allow us to investigate properties such as the dynamics of electric flux strings, signaling confinement in gauge invariant field theories. The experimental realization of these models in larger superconducting circuits could address open questions beyond current computational capability.

  15. High resolution, shallow seismic reflection survey of the Pen Branch fault

    SciTech Connect (OSTI)

    Stieve, A.

    1991-05-15

    The purpose of this project, at the Savannah River River Site (SRS) was to acquire, process, and interpret 28 km (17.4 miles) of high resolution seismic reflection data taken across the trace of the Pen Branch fault and other suspected, intersecting north-south trending faults. The survey was optimized for the upper 300 ft of geologic strata in order to demonstrate the existence of very shallow, flat lying horizons, and to determine the depth of the fault or to sediments deformed by the fault. Field acquisition and processing parameters were selected to define small scale spatial variability and structural features in the vicinity of the Pen Branch fault leading to the definition and the location of the Pen Branch fault, the shallowest extent of the fault, and the quantification of the sense and magnitude of motion. Associated geophysical, borehole, and geologic data were incorporated into the investigation to assist in the determination of optimal parameters and aid in the interpretation.

  16. When did movement begin on the Furnace Creek fault zone

    SciTech Connect (OSTI)

    Reheis, M. )

    1993-04-01

    About 50 km of post-Jurassic right-lateral slip has occurred on the northern part of the Furnace Creek fault zone (FCFZ). The sedimentology, stratigraphy, and structure of Tertiary rocks suggest that movement on the fault began no earlier than 12--8 Ma and possibly as late as 5--4 Ma. Large remnants of erosion surfaces occur on both sides of the FCFZ in the southern White Mountains and Fish Lake Valley and are buried by rhyolite and basalt, mostly 12--10 Ma; the ash flows and welded tuffs were likely erupted from sources at least 40 km to the east. Thus, the area probably had gentle topography, suggesting a lengthy period of pre-late Miocene tectonic stability. On the west side of the FCFZ, Cambrian sedimentary rocks are buried by a fanglomerate with an [sup [minus

  17. Testing of 3-meter Prototype Fault Current Limiting Cables

    SciTech Connect (OSTI)

    Gouge, Michael J; Duckworth, Robert C; Demko, Jonathan A; Rey, Christopher M; Thompson, James R; Lindsay, David T; Tolbert, Jerry Carlton; Willen, Dag; Lentge, Heidi; Thidemann, Carsten; Carter, Bill

    2009-01-01

    Two 3-m long, single-phase cables have been fabricated by Ultera from second generation (2G) superconductor supplied by American Superconductor. The first cable was made with two layers of 2G tape conductor and had a critical current of 5,750 A while the second cable had four layers and a critical current of 8,500 A. AC loss was measured for both cables at ac currents of up to 4 kArms. Ultera performed initial fault current studies of both cables in Denmark with limited currents in the range from 9.1 to 44 kA. Results from these tests will provide a basis for a 25-m long, three-phase, prototype cable to be tested at ORNL early next year and a 300-m long, fault current limiting, superconducting cable to be installed in a ConEd substation in New York City.

  18. NREL Research Proves Wind Can Provide Ancillary Grid Fault Response |

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Energy Systems Integration | NREL NREL Research Proves Wind Can Provide Ancillary Grid Fault Response April 1, 2016 Interior of the controllable grid interface test facility, showing a long hallway and shelves full of electronic equipment. The controllable grid interface test facility at the National Wind Technology Center makes it possible to research the effectiveness of wind energy in providing ancillary grid services such as frequency control. Photo by Dennis Schroeder/NREL 27442 Image

  19. Superconducting fault current-limiter with variable shunt impedance

    DOE Patents [OSTI]

    Llambes, Juan Carlos H; Xiong, Xuming

    2013-11-19

    A superconducting fault current-limiter is provided, including a superconducting element configured to resistively or inductively limit a fault current, and one or more variable-impedance shunts electrically coupled in parallel with the superconducting element. The variable-impedance shunt(s) is configured to present a first impedance during a superconducting state of the superconducting element and a second impedance during a normal resistive state of the superconducting element. The superconducting element transitions from the superconducting state to the normal resistive state responsive to the fault current, and responsive thereto, the variable-impedance shunt(s) transitions from the first to the second impedance. The second impedance of the variable-impedance shunt(s) is a lower impedance than the first impedance, which facilitates current flow through the variable-impedance shunt(s) during a recovery transition of the superconducting element from the normal resistive state to the superconducting state, and thus, facilitates recovery of the superconducting element under load.

  20. High-Temperature Circuit Boards for Use in Geothermal Well Monitoring Applications

    Broader source: Energy.gov [DOE]

    Project objective: Develop and demonstrate high-temperature; multilayer electronic circuits capable of sustained operation at 300˚ C.

  1. Particle sorter comprising a fluid displacer in a closed-loop fluid circuit

    DOE Patents [OSTI]

    Perroud, Thomas D.; Patel, Kamlesh D.; Renzi, Ronald F.

    2012-04-24

    Disclosed herein are methods and devices utilizing a fluid displacer in a closed-loop fluid circuit.

  2. User`s guide and physics manual for the SCATPlus circuit code

    SciTech Connect (OSTI)

    Yapuncich, M.L.; Deninger, W.J.; Gribble, R.F.

    1994-05-09

    ScatPlus is a user friendly circuit code and an expandable library of circuit models for electrical components and devices; it can be used to predict the transient behavior in electric circuits. The heart of ScatPlus is the transient circuit solver SCAT written in 1986 by R.F. Gribble. This manual includes system requirements, physics manual, ScatPlus component library, tutorial, ScatPlus screen, menus and toolbar, ScatPlus tool bar, procedures.

  3. Modeling of fault activation and seismicity by injection directly into a fault zone associated with hydraulic fracturing of shale-gas reservoirs

    DOE Public Access Gateway for Energy & Science Beta (PAGES Beta)

    Rutqvist, Jonny; Rinaldi, Antonio P.; Cappa, Frédéric; Moridis, George J.

    2015-03-01

    We conducted three-dimensional coupled fluid-flow and geomechanical modeling of fault activation and seismicity associated with hydraulic fracturing stimulation of a shale-gas reservoir. We simulated a case in which a horizontal injection well intersects a steeply dip- ping fault, with hydraulic fracturing channeled within the fault, during a 3-hour hydraulic fracturing stage. Consistent with field observations, the simulation results show that shale-gas hydraulic fracturing along faults does not likely induce seismic events that could be felt on the ground surface, but rather results in numerous small microseismic events, as well as aseismic deformations along with the fracture propagation. The calculated seismicmore » moment magnitudes ranged from about -2.0 to 0.5, except for one case assuming a very brittle fault with low residual shear strength, for which the magnitude was 2.3, an event that would likely go unnoticed or might be barely felt by humans at its epicenter. The calculated moment magnitudes showed a dependency on injection depth and fault dip. We attribute such dependency to variation in shear stress on the fault plane and associated variation in stress drop upon reactivation. Our simulations showed that at the end of the 3-hour injection, the rupture zone associated with tensile and shear failure extended to a maximum radius of about 200 m from the injection well. The results of this modeling study for steeply dipping faults at 1000 to 2500 m depth is in agreement with earlier studies and field observations showing that it is very unlikely that activation of a fault by shale-gas hydraulic fracturing at great depth (thousands of meters) could cause felt seismicity or create a new flow path (through fault rupture) that could reach shallow groundwater resources.« less

  4. Modeling of fault activation and seismicity by injection directly into a fault zone associated with hydraulic fracturing of shale-gas reservoirs

    SciTech Connect (OSTI)

    Rutqvist, Jonny; Rinaldi, Antonio P.; Cappa, Frédéric; Moridis, George J.

    2015-03-01

    We conducted three-dimensional coupled fluid-flow and geomechanical modeling of fault activation and seismicity associated with hydraulic fracturing stimulation of a shale-gas reservoir. We simulated a case in which a horizontal injection well intersects a steeply dip- ping fault, with hydraulic fracturing channeled within the fault, during a 3-hour hydraulic fracturing stage. Consistent with field observations, the simulation results show that shale-gas hydraulic fracturing along faults does not likely induce seismic events that could be felt on the ground surface, but rather results in numerous small microseismic events, as well as aseismic deformations along with the fracture propagation. The calculated seismic moment magnitudes ranged from about -2.0 to 0.5, except for one case assuming a very brittle fault with low residual shear strength, for which the magnitude was 2.3, an event that would likely go unnoticed or might be barely felt by humans at its epicenter. The calculated moment magnitudes showed a dependency on injection depth and fault dip. We attribute such dependency to variation in shear stress on the fault plane and associated variation in stress drop upon reactivation. Our simulations showed that at the end of the 3-hour injection, the rupture zone associated with tensile and shear failure extended to a maximum radius of about 200 m from the injection well. The results of this modeling study for steeply dipping faults at 1000 to 2500 m depth is in agreement with earlier studies and field observations showing that it is very unlikely that activation of a fault by shale-gas hydraulic fracturing at great depth (thousands of meters) could cause felt seismicity or create a new flow path (through fault rupture) that could reach shallow groundwater resources.

  5. Area-efficient physically unclonable function circuit architecture

    DOE Patents [OSTI]

    Gurrieri, Thomas; Hamlet, Jason; Bauer, Todd; Helinski, Ryan; Pierson, Lyndon G

    2015-04-28

    Generating a physically a physically unclonable function ("PUF") circuit value includes comparing each of first identification components in a first bank to each of second identification components in a second bank. A given first identification component in the first bank is not compared to another first identification component in the first bank and a given second identification component in the second bank is not compared to another second identification component in the second bank. A digital bit value is generated for each comparison made while comparing each of the first identification components to each of the second identification components. A PUF circuit value is generated from the digital bit values from each comparison made.

  6. Methods for improving solar cell open circuit voltage

    DOE Patents [OSTI]

    Jordan, John F.; Singh, Vijay P.

    1979-01-01

    A method for producing a solar cell having an increased open circuit voltage. A layer of cadmium sulfide (CdS) produced by a chemical spray technique and having residual chlorides is exposed to a flow of hydrogen sulfide (H.sub.2 S) heated to a temperature of 400.degree.-600.degree. C. The residual chlorides are reduced and any remaining CdCl.sub.2 is converted to CdS. A heterojunction is formed over the CdS and electrodes are formed. Application of chromium as the positive electrode results in a further increase in the open circuit voltage available from the H.sub.2 S-treated solar cell.

  7. Coaxial connector for use with printed circuit board edge connector

    DOE Patents [OSTI]

    Howard, Donald R.; MacGill, Robert A.

    1989-01-01

    A coaxial cable connector for interfacing with an edge connector for a printed circuit board whereby a coaxial cable can be interconnected with a printed circuit board through the edge connector. The coaxial connector includes a body having two leg portions extending from one side for receiving the edge connector therebetween, and a tubular portion extending from an opposing side for receiving a coaxial cable. A cavity within the body receives a lug of the edge connector and the center conductor of the coaxial cable. Adjacent lugs of the edge connector can be bend around the edge connector housing to function as spring-loaded contacts for receiving the coaxial connector. The lugs also function to facilitate shielding of the center conductor where fastened to the edge connector lug.

  8. Gas microstrip detectors based on flexible printed circuit

    SciTech Connect (OSTI)

    Salomon, M.; Crowe, K.; Faszer, W.; Lindsay, P.; Curran Maier, J.M.

    1995-09-01

    Microstrip Gas Detectors (MSGC`s) were introduced some years ago as position sensitive detectors capable of operating at very high rates. The authors have studied the properties of a new type of Gas Microstrip Counter built using flexible printed circuit technology. They describe the manufacturing procedures, the assembly of the device, as well as its operation under a variety of conditions, gases and types of radiation. They also describe two new passivation materials, tantalum and niobium, which produce effective surfaces.

  9. Double sided circuit board and a method for its manufacture

    DOE Patents [OSTI]

    Lindenmeyer, C.W.

    1988-04-14

    Conductance between the sides of a large double sided printed circuit board is provided using a method which eliminates the need for chemical immersion or photographic exposure of the entire large board. A plurality of through-holes are drilled or punched in a substratum according to the desired pattern, conductive laminae are made to adhere to both sides of the substratum covering the holes and the laminae are pressed together and permanently joined within the holes, providing conductive paths. 4 figs.

  10. Double sided circuit board and a method for its manufacture

    DOE Patents [OSTI]

    Lindenmeyer, Carl W.

    1989-01-01

    Conductance between the sides of a large double sided printed circuit board is provided using a method which eliminates the need for chemical immersion or photographic exposure of the entire large board. A plurality of through-holes are drilled or punched in a substratum according to the desired pattern, conductive laminae are made to adhere to both sides of the substratum covering the holes and the laminae are pressed together and permanently joined within the holes, providing conductive paths.

  11. Cryogenic CMOS circuits for single charge digital readout.

    SciTech Connect (OSTI)

    Gurrieri, Thomas M.; Longoria, Erin Michelle; Eng, Kevin; Carroll, Malcolm S.; Hamlet, Jason R.; Young, Ralph Watson

    2010-03-01

    The readout of a solid state qubit often relies on single charge sensitive electrometry. However the combination of fast and accurate measurements is non trivial due to large RC time constants due to the electrometers resistance and shunt capacitance from wires between the cold stage and room temperature. Currently fast sensitive measurements are accomplished through rf reflectrometry. I will present an alternative single charge readout technique based on cryogenic CMOS circuits in hopes to improve speed, signal-to-noise, power consumption and simplicity in implementation. The readout circuit is based on a current comparator where changes in current from an electrometer will trigger a digital output. These circuits were fabricated using Sandia's 0.35 {micro}m CMOS foundry process. Initial measurements of comparators with an addition a current amplifier have displayed current sensitivities of < 1nA at 4.2K, switching speeds up to {approx}120ns, while consuming {approx}10 {micro}W. I will also discuss an investigation of noise characterization of our CMOS process in hopes to obtain a better understanding of the ultimate limit in signal to noise performance.

  12. Ambient temperature cadmium zinc telluride radiation detector and amplifier circuit

    DOE Patents [OSTI]

    McQuaid, James H.; Lavietes, Anthony D.

    1998-05-29

    A low noise, low power consumption, compact, ambient temperature signal amplifier for a Cadmium Zinc Telluride (CZT) radiation detector. The amplifier can be used within a larger system (e.g., including a multi-channel analyzer) to allow isotopic analysis of radionuclides in the field. In one embodiment, the circuit stages of the low power, low noise amplifier are constructed using integrated circuit (IC) amplifiers , rather than discrete components, and include a very low noise, high gain, high bandwidth dual part preamplification stage, an amplification stage, and an filter stage. The low noise, low power consumption, compact, ambient temperature amplifier enables the CZT detector to achieve both the efficiency required to determine the presence of radio nuclides and the resolution necessary to perform isotopic analysis to perform nuclear material identification. The present low noise, low power, compact, ambient temperature amplifier enables a CZT detector to achieve resolution of less than 3% full width at half maximum at 122 keV for a Cobalt-57 isotope source. By using IC circuits and using only a single 12 volt supply and ground, the novel amplifier provides significant power savings and is well suited for prolonged portable in-field use and does not require heavy, bulky power supply components.

  13. Ambient temperature cadmium zinc telluride radiation detector and amplifier circuit

    DOE Patents [OSTI]

    McQuaid, J.H.; Lavietes, A.D.

    1998-05-26

    A low noise, low power consumption, compact, ambient temperature signal amplifier for a Cadmium Zinc Telluride (CZT) radiation detector is disclosed. The amplifier can be used within a larger system (e.g., including a multi-channel analyzer) to allow isotopic analysis of radionuclides in the field. In one embodiment, the circuit stages of the low power, low noise amplifier are constructed using integrated circuit (IC) amplifiers , rather than discrete components, and include a very low noise, high gain, high bandwidth dual part preamplification stage, an amplification stage, and an filter stage. The low noise, low power consumption, compact, ambient temperature amplifier enables the CZT detector to achieve both the efficiency required to determine the presence of radionuclides and the resolution necessary to perform isotopic analysis to perform nuclear material identification. The present low noise, low power, compact, ambient temperature amplifier enables a CZT detector to achieve resolution of less than 3% full width at half maximum at 122 keV for a Cobalt-57 isotope source. By using IC circuits and using only a single 12 volt supply and ground, the novel amplifier provides significant power savings and is well suited for prolonged portable in-field use and does not require heavy, bulky power supply components. 9 figs.

  14. Characterization of the human oncogene SCL/TAL1 interrupting locus (Stil) mediated Sonic hedgehog (Shh) signaling transduction in proliferating mammalian dopaminergic neurons

    SciTech Connect (OSTI)

    Sun, Lei; Carr, Aprell L.; Li, Ping; Lee, Jessica; McGregor, Mary; Li, Lei

    2014-07-11

    Highlights: Stil is a human oncogene that is conserved in vertebrate species. Stil functions in the Shh pathway in mammalian cells. The expression of Stil is required for mammalian dopaminergic cell proliferation. - Abstract: The human oncogene SCL/TAL1 interrupting locus (Stil) is highly conserved in all vertebrate species. In humans, the expression of Stil is involved in cancer cell survival, apoptosis and proliferation. In this research, we investigated the roles of Stil expression in cell proliferation of mammalian dopaminergic (DA) PC12 cells. Stil functions through the Sonic hedgehog (Shh) signal transduction pathway. Co-immunoprecipitation tests revealed that STIL interacts with Shh downstream components, which include SUFU and GLI1. By examining the expression of Stil, Gli1, CyclinD2 (cell-cycle marker) and PCNA (proliferating cell nuclear antigen), we found that up-regulation of Stil expression (transfection with overexpression plasmids) increased Shh signaling transduction and PC12 cell proliferation, whereas down-regulation of Stil expression (by shRNA) inhibited Shh signaling transduction, and thereby decreased PC12 cell proliferation. Transient transfection of PC12 cells with Stil knockdown or overexpression plasmids did not affect PC12 cell neural differentiation, further indicating the specific roles of Stil in cell proliferation. The results from this research suggest that Stil may serve as a bio-marker for neurological diseases involved in DA neurons, such as Parkinsons disease.

  15. Significance of recurrent fault movement at Grays Point quarry, southeast Missouri

    SciTech Connect (OSTI)

    Diehl, S.F.; Throckmorton, C.K. ); Clendenin, C.W. )

    1993-03-01

    Geologic relationships indicate recurrent movement on a fault exposed at Grays Point, MO. Faulting offsets Middle-Late Ordovician Plattin Group, Decorah Group, Kimmswick Limestone, and Maquoketa Group strata. In plan, the fault is characterized by a relatively narrow zone (30--70 m) of northeast-striking fault slices associated with a northwest-striking zone of right-stepping en echelon fractures. This systematic fracture-fault array identifies right-lateral strike-slip movement. A vertically offset basal Decorah Group contact shows 22 m of down-to-the-southeast dip slip, which indicates a component of oblique slip. Oldest recognizable movement on the fault is evidenced by Maquoketa Group strata that fill a northeast-striking, wedge-shaped synform. Post-Ordovician movement along an adjacent subvertical fault displaces part of this synform 300 m right laterally. In thin section, the northwest-striking fracture set shows a polyphase history of deformation indicated by cataclastic textures and intrusion of carbonate-rich fluids. Three periods of movement occurred: (1) initial fracturing sealed by authigenic mineral cements; (2) renewed fracturing associated with recrystallization of sub-rounded clasts; and (3) subsequent brecciation marked by angular clasts and filling of fractures and vugs. Each successive fluid intrusion is characterized by an increase in grain size of the authigenic cement. The fault is subparallel to the regional, northeast-striking English Hill fault system. Polyphase oblique-slip deformation suggests that the fault, like others in southeastern Missouri, is a reactivated Late Proterozoic-Cambrian zone of weakness. Initial fault reactivation occurred during Middle-Late Ordovician as opposed to Devonian, as commonly interpreted for southeast Missouri. Multiple authigenic mineral cements imply that fluids may have been an important factor influencing the fault's tendency to be reactivated.

  16. Arc-Fault Detector Algorithm Evaluation Method Utilizing Prerecorded Arcing Signatures

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Arc-Fault Detector Algorithm Evaluation Method Utilizing Prerecorded Arcing Signatures Jay Johnson 1 and Jack Kang 2 1 Sandia National Laboratories, Albuquerque, NM, USA 2 Sensata Technologies, Attleboro, MA, USA ABSTRACT Abstract - The 2011 National Electrical Code® Article 690.11 requires photovoltaic systems on or penetrating a building to include a DC arc-fault protection device. In order to satisfy this requirement, new Arc-Fault Detectors (AFDs) are being developed by multiple

  17. NEAR-SURFACE GEOPHYSICAL CHARACTERIZATION OF A HOLOCENE FAULT CONDUCIVE TO

    Office of Scientific and Technical Information (OSTI)

    GEOTHERMAL FLOW NEAR PYRAMID LAKE, NEVADA (Other) | SciTech Connect NEAR-SURFACE GEOPHYSICAL CHARACTERIZATION OF A HOLOCENE FAULT CONDUCIVE TO GEOTHERMAL FLOW NEAR PYRAMID LAKE, NEVADA Citation Details In-Document Search Title: NEAR-SURFACE GEOPHYSICAL CHARACTERIZATION OF A HOLOCENE FAULT CONDUCIVE TO GEOTHERMAL FLOW NEAR PYRAMID LAKE, NEVADA Linear deposits of calcium carbonate tufa columns mark recent faults that cut 11 ka Lake Lahontan sediments at Astor Pass, north of Pyramid Lake,

  18. Investigations of stacking fault density in perpendicular recording media

    SciTech Connect (OSTI)

    Piramanayagam, S. N. Varghese, Binni; Yang, Yi; Kiat Lee, Wee; Khume Tan, Hang

    2014-06-28

    In magnetic recording media, the grains or clusters reverse their magnetization over a range of reversal field, resulting in a switching field distribution. In order to achieve high areal densities, it is desirable to understand and minimize such a distribution. Clusters of grains which contain stacking faults (SF) or fcc phase have lower anisotropy, an order lower than those without them. It is believed that such low anisotropy regions reverse their magnetization at a much lower reversal field than the rest of the material with a larger anisotropy. Such clusters/grains cause recording performance deterioration, such as adjacent track erasure and dc noise. Therefore, the observation of clusters that reverse at very low reversal fields (nucleation sites, NS) could give information on the noise and the adjacent track erasure. Potentially, the observed clusters could also provide information on the SF. In this paper, we study the reversal of nucleation sites in granular perpendicular media based on a magnetic force microscope (MFM) methodology and validate the observations with high resolution cross-section transmission electron microscopy (HRTEM) measurements. Samples, wherein a high anisotropy CoPt layer was introduced to control the NS or SF in a systematic way, were evaluated by MFM, TEM, and magnetometry. The magnetic properties indicated that the thickness of the CoPt layer results in an increase of nucleation sites. TEM measurements indicated a correlation between the thickness of CoPt layer and the stacking fault density. A clear correlation was also observed between the MFM results, TEM observations, and the coercivity and nucleation field of the samples, validating the effectiveness of the proposed method in evaluating the nucleation sites which potentially arise from stacking faults.

  19. Non-abelian fractional quantum hall effect for fault-resistant...

    Office of Scientific and Technical Information (OSTI)

    Non-abelian fractional quantum hall effect for fault-resistant topological quantum computation. Citation Details In-Document Search Title: Non-abelian fractional quantum hall...

  20. Sandia Research on PV Arc-Fault Detection Submitted for US Patent

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Predictive Simulation of Engines Transportation Energy Consortiums Engine Combustion ... The 2011 National Electrical Code requires PV DC series arc-fault protection, but does ...

  1. Pull-Apart in Strike-Slip Fault Zone | Open Energy Information

    Open Energy Info (EERE)

    of sinistral fault systems, resulting in localized crustal extension and enhanced permeability. Other definitions:Wikipedia Reegle Controlling Structures List of controlling...

  2. VOLTTRON Compatible Whole-Building Root-Fault Detection and Diagnosis...

    Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

    tool that integrates both statistical process control and machine learning techniques and rule-based methods to achieve a whole-building energy system "root-fault" diagnosis. ...

  3. Stepover or Relay Ramp in Normal Fault Zones | Open Energy Information

    Open Energy Info (EERE)

    intersections between the overlapping fault strands results in increased fracture density that enhances hydrothermal fluid flow. Other definitions:Wikipedia Reegle Controlling...

  4. A Fault Oblivious Extreme-Scale Execution Environment

    SciTech Connect (OSTI)

    McKie, Jim

    2014-11-20

    The FOX project, funded under the ASCR X-stack I program, developed systems software and runtime libraries for a new approach to the data and work distribution for massively parallel, fault oblivious application execution. Our work was motivated by the premise that exascale computing systems will provide a thousand-fold increase in parallelism and a proportional increase in failure rate relative to today’s machines. To deliver the capability of exascale hardware, the systems software must provide the infrastructure to support existing applications while simultaneously enabling efficient execution of new programming models that naturally express dynamic, adaptive, irregular computation; coupled simulations; and massive data analysis in a highly unreliable hardware environment with billions of threads of execution. Our OS research has prototyped new methods to provide efficient resource sharing, synchronization, and protection in a many-core compute node. We have experimented with alternative task/dataflow programming models and shown scalability in some cases to hundreds of thousands of cores. Much of our software is in active development through open source projects. Concepts from FOX are being pursued in next generation exascale operating systems. Our OS work focused on adaptive, application tailored OS services optimized for multi → many core processors. We developed a new operating system NIX that supports role-based allocation of cores to processes which was released to open source. We contributed to the IBM FusedOS project, which promoted the concept of latency-optimized and throughput-optimized cores. We built a task queue library based on distributed, fault tolerant key-value store and identified scaling issues. A second fault tolerant task parallel library was developed, based on the Linda tuple space model, that used low level interconnect primitives for optimized communication. We designed fault tolerance mechanisms for task parallel computations

  5. Field Guide for Testing Existing Photovoltaic Systems for Ground Faults and Installing Equipment to Mitigate Fire Hazards: November 2012 - October 2013

    SciTech Connect (OSTI)

    Brooks, William

    2015-02-01

    Ground faults and arc faults are the two most common reasons for fires in photovoltaic (PV) arrays and methods exist that can mitigate the hazards. This report provides field procedures for testing PV arrays for ground faults, and for implementing high resolution ground fault and arc fault detectors in existing and new PV system designs.

  6. Development of Hydrologic Characterization Technology of Fault Zones -- Phase I, 2nd Report

    SciTech Connect (OSTI)

    Karasaki, Kenzi; Onishi, Tiemi; Black, Bill; Biraud, Sebastien

    2009-03-31

    This is the year-end report of the 2nd year of the NUMO-LBNL collaborative project: Development of Hydrologic Characterization Technology of Fault Zones under NUMO-DOE/LBNL collaboration agreement, the task description of which can be found in the Appendix 3. Literature survey of published information on the relationship between geologic and hydrologic characteristics of faults was conducted. The survey concluded that it may be possible to classify faults by indicators based on various geometric and geologic attributes that may indirectly relate to the hydrologic property of faults. Analysis of existing information on the Wildcat Fault and its surrounding geology was performed. The Wildcat Fault is thought to be a strike-slip fault with a thrust component that runs along the eastern boundary of the Lawrence Berkeley National Laboratory. It is believed to be part of the Hayward Fault system but is considered inactive. Three trenches were excavated at carefully selected locations mainly based on the information from the past investigative work inside the LBNL property. At least one fault was encountered in all three trenches. Detailed trench mapping was conducted by CRIEPI (Central Research Institute for Electric Power Industries) and LBNL scientists. Some intriguing and puzzling discoveries were made that may contradict with the published work in the past. Predictions are made regarding the hydrologic property of the Wildcat Fault based on the analysis of fault structure. Preliminary conceptual models of the Wildcat Fault were proposed. The Wildcat Fault appears to have multiple splays and some low angled faults may be part of the flower structure. In parallel, surface geophysical investigations were conducted using electrical resistivity survey and seismic reflection profiling along three lines on the north and south of the LBNL site. Because of the steep terrain, it was difficult to find optimum locations for survey lines as it is desirable for them to be as

  7. Coordinated Fault-Tolerance for High-Performance Computing Final Project Report

    SciTech Connect (OSTI)

    Panda, Dhabaleswar Kumar; Beckman, Pete

    2011-07-28

    With the Coordinated Infrastructure for Fault Tolerance Systems (CIFTS, as the original project came to be called) project, our aim has been to understand and tackle the following broad research questions, the answers to which will help the HEC community analyze and shape the direction of research in the field of fault tolerance and resiliency on future high-end leadership systems. Will availability of global fault information, obtained by fault information exchange between the different HEC software on a system, allow individual system software to better detect, diagnose, and adaptively respond to faults? If fault-awareness is raised throughout the system through fault information exchange, is it possible to get all system software working together to provide a more comprehensive end-to-end fault management on the system? #15; What are the missing fault-tolerance features that widely used HEC system software lacks today that would inhibit such software from taking advantage of systemwide global fault information? #15; What are the practical limitations of a systemwide approach for end-to-end fault management based on fault awareness and coordination? #15; What mechanisms, tools, and technologies are needed to bring about fault awareness and coordination of responses on a leadership-class system? #15; What standards, outreach, and community interaction are needed for adoption of the concept of fault awareness and coordination for fault management on future systems? Keeping our overall objectives in mind, the CIFTS team has taken a parallel fourfold approach. #15; Our central goal was to design and implement a light-weight, scalable infrastructure with a simple, standardized interface to allow communication of fault-related information through the system and facilitate coordinated responses. This work led to the development of the Fault Tolerance Backplane (FTB) publish-subscribe API specification, together with a reference implementation and several experimental

  8. Award ER25750: Coordinated Infrastructure for Fault Tolerance Systems Indiana University Final Report

    SciTech Connect (OSTI)

    Lumsdaine, Andrew

    2013-03-08

    The main purpose of the Coordinated Infrastructure for Fault Tolerance in Systems initiative has been to conduct research with a goal of providing end-to-end fault tolerance on a systemwide basis for applications and other system software. While fault tolerance has been an integral part of most high-performance computing (HPC) system software developed over the past decade, it has been treated mostly as a collection of isolated stovepipes. Visibility and response to faults has typically been limited to the particular hardware and software subsystems in which they are initially observed. Little fault information is shared across subsystems, allowing little flexibility or control on a system-wide basis, making it practically impossible to provide cohesive end-to-end fault tolerance in support of scientific applications. As an example, consider faults such as communication link failures that can be seen by a network library but are not directly visible to the job scheduler, or consider faults related to node failures that can be detected by system monitoring software but are not inherently visible to the resource manager. If information about such faults could be shared by the network libraries or monitoring software, then other system software, such as a resource manager or job scheduler, could ensure that failed nodes or failed network links were excluded from further job allocations and that further diagnosis could be performed. As a founding member and one of the lead developers of the Open MPI project, our efforts over the course of this project have been focused on making Open MPI more robust to failures by supporting various fault tolerance techniques, and using fault information exchange and coordination between MPI and the HPC system software stack from the application, numeric libraries, and programming language runtime to other common system components such as jobs schedulers, resource managers, and monitoring tools.

  9. Mobility and coalescence of stacking fault tetrahedra in Cu

    DOE Public Access Gateway for Energy & Science Beta (PAGES Beta)

    Martínez, Enrique; Uberuaga, Blas P.

    2015-03-13

    Stacking fault tetrahedra (SFTs) are ubiquitous defects in face-centered cubic metals. They are produced during cold work plastic deformation, quenching experiments or under irradiation. From a dislocation point of view, the SFTs are comprised of a set of stair-rod dislocations at the (110) edges of a tetrahedron bounding triangular stacking faults. These defects are extremely stable, increasing their energetic stability as they grow in size. At the sizes visible within transmission electron microscope they appear nearly immobile. Contrary to common belief, we show in this report, using a combination of molecular dynamics and temperature accelerated dynamics, how small SFTs canmore » diffuse by temporarily disrupting their structure through activated thermal events. More over, we demonstrate that the diffusivity of defective SFTs is several orders of magnitude higher than perfect SFTs, and can be even higher than isolated vacancies. Finally, we show how SFTs can coalesce, forming a larger defect in what is a new mechanism for the growth of these omnipresent defects.« less

  10. Editorial: Mathematical Methods and Modeling in Machine Fault Diagnosis

    DOE Public Access Gateway for Energy & Science Beta (PAGES Beta)

    Yan, Ruqiang; Chen, Xuefeng; Li, Weihua; Sheng, Shuangwen

    2014-12-18

    Modern mathematics has commonly been utilized as an effective tool to model mechanical equipment so that their dynamic characteristics can be studied analytically. This will help identify potential failures of mechanical equipment by observing change in the equipment’s dynamic parameters. On the other hand, dynamic signals are also important and provide reliable information about the equipment’s working status. Modern mathematics has also provided us with a systematic way to design and implement various signal processing methods, which are used to analyze these dynamic signals, and to enhance intrinsic signal components that are directly related to machine failures. This special issuemore » is aimed at stimulating not only new insights on mathematical methods for modeling but also recently developed signal processing methods, such as sparse decomposition with potential applications in machine fault diagnosis. Finally, the papers included in this special issue provide a glimpse into some of the research and applications in the field of machine fault diagnosis through applications of the modern mathematical methods.« less

  11. Editorial: Mathematical Methods and Modeling in Machine Fault Diagnosis

    SciTech Connect (OSTI)

    Yan, Ruqiang; Chen, Xuefeng; Li, Weihua; Sheng, Shuangwen

    2014-12-18

    Modern mathematics has commonly been utilized as an effective tool to model mechanical equipment so that their dynamic characteristics can be studied analytically. This will help identify potential failures of mechanical equipment by observing change in the equipment’s dynamic parameters. On the other hand, dynamic signals are also important and provide reliable information about the equipment’s working status. Modern mathematics has also provided us with a systematic way to design and implement various signal processing methods, which are used to analyze these dynamic signals, and to enhance intrinsic signal components that are directly related to machine failures. This special issue is aimed at stimulating not only new insights on mathematical methods for modeling but also recently developed signal processing methods, such as sparse decomposition with potential applications in machine fault diagnosis. Finally, the papers included in this special issue provide a glimpse into some of the research and applications in the field of machine fault diagnosis through applications of the modern mathematical methods.

  12. Unconventional modelling of faulted reservoirs: a case study

    SciTech Connect (OSTI)

    Goldthorpe, W.H.; Chow, Y.S.

    1985-02-01

    An example is presented of detailed unconventional gridding of the North Rankin Field, which is a large, structurally complex gas-condensate field offshore Western Australia. A non-Cartesian areal grid was used with corner point geometry to approximate a generalized curvilinear coordinate system for the surface and interior of each reservoir unit. Coordinate lines in the vertical plane at any node in the grid were tilted where necessary to define sloping edges and sides of grid blocks. Thus, any sloping twisted surface could be modelled. To investigate possible communication across faults between different geological units, transmissibilities at faults were automatically calculated for any over-lapping cells and sensitivities made of the effect of varying these transmissibilities on well production, recovery factors, pressure decline and water encroachment. The model was solved with a fully implicit simulator using a Newton-Raphson iteration method for the non-linear equations and a variant of the Conjugate Gradient procedure with a preconditioning matrix for the linear equations.

  13. Amplifier circuit operable over a wide temperature range

    DOE Patents [OSTI]

    Kelly, Ronald D.; Cannon, William L.

    1979-01-01

    An amplifier circuit having stable performance characteristics over a wide temperature range from approximately 0.degree. C up to as high as approximately 500.degree. C, such as might be encountered in a geothermal borehole. The amplifier utilizes ceramic vacuum tubes connected in directly coupled differential amplifier pairs having a common power supply and a cathode follower output stage. In an alternate embodiment, for operation up to 500.degree. C, positive and negative power supplies are utilized to provide improved gain characteristics, and all electrical connections are made by welding. Resistor elements in this version of the invention are specially heat treated to improve their stability with temperature.

  14. Dual-circuit, multiple-effect refrigeration system and method

    DOE Patents [OSTI]

    DeVault, Robert C.

    1995-01-01

    A dual circuit absorption refrigeration system comprising a high temperature single-effect refrigeration loop and a lower temperature double-effect refrigeration loop separate from one another and provided with a double-condenser coupling therebetween. The high temperature condenser of the single-effect refrigeration loop is double coupled to both of the generators in the double-effect refrigeration loop to improve internal heat recovery and a heat and mass transfer additive such as 2-ethyl-1-hexanol is used in the lower temperature double-effect refrigeration loop to improve the performance of the absorber in the double-effect refrigeration loop.

  15. Eddy current gauge for monitoring displacement using printed circuit coil

    DOE Patents [OSTI]

    Visioli, Jr., Armando J.

    1977-01-01

    A proximity detection system for non-contact displacement and proximity measurement of static or dynamic metallic or conductive surfaces is provided wherein the measurement is obtained by monitoring the change in impedance of a flat, generally spiral-wound, printed circuit coil which is excited by a constant current, constant frequency source. The change in impedance, which is detected as a corresponding change in voltage across the coil, is related to the eddy current losses in the distant conductive material target. The arrangement provides for considerable linear displacement range with increased accuracies, stability, and sensitivity over the entire range.

  16. Light-induced voltage alteration for integrated circuit analysis

    DOE Patents [OSTI]

    Cole, Jr., Edward I.; Soden, Jerry M.

    1995-01-01

    An apparatus and method are described for analyzing an integrated circuit (IC), The invention uses a focused light beam that is scanned over a surface of the IC to generate a light-induced voltage alteration (LIVA) signal for analysis of the IC, The LIVA signal may be used to generate an image of the IC showing the location of any defects in the IC; and it may be further used to image and control the logic states of the IC. The invention has uses for IC failure analysis, for the development of ICs, for production-line inspection of ICs, and for qualification of ICs.

  17. Light-induced voltage alteration for integrated circuit analysis

    DOE Patents [OSTI]

    Cole, E.I. Jr.; Soden, J.M.

    1995-07-04

    An apparatus and method are described for analyzing an integrated circuit (IC). The invention uses a focused light beam that is scanned over a surface of the IC to generate a light-induced voltage alteration (LIVA) signal for analysis of the IC. The LIVA signal may be used to generate an image of the IC showing the location of any defects in the IC; and it may be further used to image and control the logic states of the IC. The invention has uses for IC failure analysis, for the development of ICs, for production-line inspection of ICs, and for qualification of ICs. 18 figs.

  18. Trap seal for open circuit liquid cooled turbines

    DOE Patents [OSTI]

    Grondahl, Clayton M.; Germain, Malcolm R.

    1980-01-01

    An improved trap seal for open circuit liquid cooled turbines is disclosed. The trap seal of the present invention includes an annular recess formed in the supply conduit of cooling channels formed in the airfoil of the turbine buckets. A cylindrical insert is located in the annular recesses and has a plurality of axial grooves formed along the outer periphery thereof and a central recess formed in one end thereof. The axial grooves and central recess formed in the cylindrical insert cooperate with the annular recess to define a plurality of S-shaped trap seals which permit the passage of liquid coolant but prohibit passage of gaseous coolant.

  19. Influence of Transcontinental arch on Cretaceous listric-normal faulting, west flank, Denver basin

    SciTech Connect (OSTI)

    Davis, T.L.

    1983-08-01

    Seismic studies along the west flank of the Denver basin near Boulder and Greeley, Colorado illustrate the interrelationship between shallow listric-normal faulting in the Cretaceous and deeper basement-controlled faulting. Deeper fault systems, primarily associated with the Transcontinental arch, control the styles and causative mechanisms of listric-normal faulting that developed in the Cretaceous. Three major stratigraphic levels of listric-normal faulting occur in the Boulder-Greeley area. These tectonic sensitive intervals are present in the following Cretaceous formations: Laramie-Fox Hills-upper Pierre, middle Pierre Hygiene zone, and the Niobrara-Carlile-Greenhorn. Documentation of the listric-normal fault style reveals a Wattenberg high, a horst block or positive feature of the greater Transcontinental arch, was active in the east Boulder-Greeley area during Cretaceous time. Paleotectonic events associated with the Wattenberg high are traced through analysis of the listric-normal fault systems that occur in the area. These styles are important to recognize because of their stratigraphic and structural influence on Cretaceous petroleum reservoir systems in the Denver basin. Similar styles of listric-normal faulting occur in the Cretaceous in many Rocky Mountain foreland basins.

  20. Effect of faulting on ground-water movement in the Death Valley region, Nevada and California

    SciTech Connect (OSTI)

    Faunt, C.C.

    1997-12-31

    This study characterizes the hydrogeologic system of the Death Valley region, an area covering approximately 100,000 square kilometers. The study also characterizes the effects of faults on ground-water movement in the Death Valley region by synthesizing crustal stress, fracture mechanics,a nd structural geologic data. The geologic conditions are typical of the Basin and Range Province; a variety of sedimentary and igneous intrusive and extrusive rocks have been subjected to both compressional and extensional deformation. Faulting and associated fracturing is pervasive and greatly affects ground-water flow patterns. Faults may become preferred conduits or barriers to flow depending on whether they are in relative tension, compression, or shear and other factors such as the degree of dislocations of geologic units caused by faulting, the rock types involved, the fault zone materials, and the depth below the surface. The current crustal stress field was combined with fault orientations to predict potential effects of faults on the regional ground-water flow regime. Numerous examples of fault-controlled ground-water flow exist within the study area. Hydrologic data provided an independent method for checking some of the assumptions concerning preferential flow paths. 97 refs., 20 figs., 5 tabs.

  1. System for detecting and limiting electrical ground faults within electrical devices

    DOE Patents [OSTI]

    Gaubatz, Donald C.

    1990-01-01

    An electrical ground fault detection and limitation system for employment with a nuclear reactor utilizing a liquid metal coolant. Elongate electromagnetic pumps submerged within the liquid metal coolant and electrical support equipment experiencing an insulation breakdown occasion the development of electrical ground fault current. Without some form of detection and control, these currents may build to damaging power levels to expose the pump drive components to liquid metal coolant such as sodium with resultant undesirable secondary effects. Such electrical ground fault currents are detected and controlled through the employment of an isolated power input to the pumps and with the use of a ground fault control conductor providing a direct return path from the affected components to the power source. By incorporating a resistance arrangement with the ground fault control conductor, the amount of fault current permitted to flow may be regulated to the extent that the reactor may remain in operation until maintenance may be performed, notwithstanding the existence of the fault. Monitors such as synchronous demodulators may be employed to identify and evaluate fault currents for each phase of a polyphase power, and control input to the submerged pump and associated support equipment.

  2. The role of the digital fault recorder in the automated substation

    SciTech Connect (OSTI)

    Brandt, J.D.

    1996-10-01

    This paper addresses the role of the digital fault recorder in the automated substation. The topics of the paper include distributed architecture, the substation LAN and reduced installation costs, multiple functions, improved substation intelligence, record generation and record merging, fault summaries, master station software, and future considerations.

  3. System and method for filling a plurality of isolated vehicle fluid circuits through a common fluid fill port

    DOE Patents [OSTI]

    Sullivan, Scott C; Fansler, Douglas

    2014-10-14

    A vehicle having multiple isolated fluid circuits configured to be filled through a common fill port includes a first fluid circuit disposed within the vehicle, the first fluid circuit having a first fill port, a second fluid circuit disposed within the vehicle, and a conduit defining a fluid passageway between the first fluid circuit and second fluid circuit, the conduit including a valve. The valve is configured such that the first and second fluid circuits are fluidly coupled via the passageway when the valve is open, and are fluidly isolated when the valve is closed.

  4. System and method for motor fault detection using stator current noise cancellation

    DOE Patents [OSTI]

    Zhou, Wei; Lu, Bin; Nowak, Michael P.; Dimino, Steven A.

    2010-12-07

    A system and method for detecting incipient mechanical motor faults by way of current noise cancellation is disclosed. The system includes a controller configured to detect indicia of incipient mechanical motor faults. The controller further includes a processor programmed to receive a baseline set of current data from an operating motor and define a noise component in the baseline set of current data. The processor is also programmed to acquire at least on additional set of real-time operating current data from the motor during operation, redefine the noise component present in each additional set of real-time operating current data, and remove the noise component from the operating current data in real-time to isolate any fault components present in the operating current data. The processor is then programmed to generate a fault index for the operating current data based on any isolated fault components.

  5. System and method for bearing fault detection using stator current noise cancellation

    DOE Patents [OSTI]

    Zhou, Wei; Lu, Bin; Habetler, Thomas G.; Harley, Ronald G.; Theisen, Peter J.

    2010-08-17

    A system and method for detecting incipient mechanical motor faults by way of current noise cancellation is disclosed. The system includes a controller configured to detect indicia of incipient mechanical motor faults. The controller further includes a processor programmed to receive a baseline set of current data from an operating motor and define a noise component in the baseline set of current data. The processor is also programmed to repeatedly receive real-time operating current data from the operating motor and remove the noise component from the operating current data in real-time to isolate any fault components present in the operating current data. The processor is then programmed to generate a fault index for the operating current data based on any isolated fault components.

  6. Hydraulically-actuated operating system for an electric circuit breaker

    DOE Patents [OSTI]

    Barkan, Philip; Imam, Imdad

    1978-01-01

    This hydraulically-actuated operating system comprises a cylinder, a piston movable therein in an opening direction to open a circuit breaker, and an accumulator for supplying pressurized liquid to a piston-actuating space within the cylinder. A normally-closed valve between the accumulator and the actuating space is openable to allow pressurized liquid from the accumulator to flow through the valve into the actuating space to drive the piston in an opening direction. A vent is located hydraulically between the actuating space and the valve for affording communication between said actuating space and a low pressure region. Flow control means is provided for restricting leakage through said vent to a rate that prevents said leakage from substantially detracting from the development of pressure within said actuatng space during the period from initial opening of the valve to the time when said piston has moved through most of its opening stroke. Following such period and while the valve is still open, said flow control means allows effective leakage through said vent. The accumulator has a limited capacity that results in the pressure within said actuating space decaying promptly to a low value as a result of effective leakage through said vent after the piston has moved through a circuit-breaker opening stroke and while the valve is in its open state. Means is provided for resetting the valve to its closed state in response to said pressure decay in the actuating space.

  7. Hydraulically-activated operating system for an electric circuit breaker

    DOE Patents [OSTI]

    Imam, Imdad; Barkan, Philip

    1979-01-01

    This operating system comprises a fluid motor having a piston, a breaker-opening space at one side of the piston, and a breaker-closing space at its opposite side. An accumulator freely communicates with the breaker-opening space for supplying pressurized fluid thereto during a circuit-breaker opening operation. A normally-closed valve located on the breaker-closing-side of the piston is openable to release liquid from the breaker-closing space so that pressurized liquid in the breaker-opening space can drive the piston in an opening direction. Means is provided for restoring the valve to its closed position following the circuit-breaker opening operation. An impeded passage affords communication between the accumulator and the breaker-closing space to allow pressurized liquid to flow from the accumulator to the breaker-closing space and develop a pressure therein substantially equal to accumulator pressure when the valve is restored to closed position following breaker-opening. This passage is so impeded that the flow therethrough from the accumulator into the breaker-closing space is sufficiently low during initial opening motion of the piston through a substantial portion of its opening stroke as to avoid interference with said initial opening motion of the piston.

  8. Printed circuit board impedance matching step for microwave (millimeter wave) devices

    DOE Patents [OSTI]

    Pao, Hsueh-Yuan; Aguirre, Jerardo; Sargis, Paul

    2013-10-01

    An impedance matching ground plane step, in conjunction with a quarter wave transformer section, in a printed circuit board provides a broadband microwave matching transition from board connectors or other elements that require thin substrates to thick substrate (>quarter wavelength) broadband microwave (millimeter wave) devices. A method of constructing microwave and other high frequency electrical circuits on a substrate of uniform thickness, where the circuit is formed of a plurality of interconnected elements of different impedances that individually require substrates of different thicknesses, by providing a substrate of uniform thickness that is a composite or multilayered substrate; and forming a pattern of intermediate ground planes or impedance matching steps interconnected by vias located under various parts of the circuit where components of different impedances are located so that each part of the circuit has a ground plane substrate thickness that is optimum while the entire circuit is formed on a substrate of uniform thickness.

  9. Push-pull radio frequency circuit with integral transistion to waveguide output

    DOE Patents [OSTI]

    Bennett, Wilfred P.

    1987-01-01

    A radio frequency circuit for ICRF heating includes a resonant push-pull circuit, a double ridged rectangular waveguide, and a coupling transition which joins the waveguide to the resonant circuit. The resonant circuit includes two cylindrical conductors mounted side by side and two power vacuum tubes attached to respective ends of a cylindrical conductor. A conductive yoke is located at the other end of the cylindrical conductors to short circuit the two cylindrical conductors. The coupling transition includes two relatively flat rectangular conductors extending perpendicular to the longitudinal axes of a respective cylindrical conductor to which the flat conductor is attached intermediate the ends thereof. Conductive side covers and end covers are also provided for forming pockets in the waveguide into which the flat conductors extend when the waveguide is attached to a shielding enclosure surrounding the resonant circuit.

  10. Ripple gate drive circuit for fast operation of series connected IGBTs

    DOE Patents [OSTI]

    Rockot, Joseph H.; Murray, Thomas W.; Bass, Kevin C.

    2005-09-20

    A ripple gate drive circuit includes a plurality of transistors having their power terminals connected in series across an electrical potential. A plurality of control circuits, each associated with one of the transistors, is provided. Each control circuit is responsive to a control signal and an optical signal received from at least one other control circuit for controlling the conduction of electrical current through the power terminals of the associated transistor. The control circuits are responsive to a first state of the control circuit for causing each transistor in series to turn on sequentially and responsive to a second state of the control signal for causing each transistor in series to turn off sequentially.

  11. Buffered coscheduling for parallel programming and enhanced fault tolerance

    DOE Patents [OSTI]

    Petrini, Fabrizio; Feng, Wu-chun

    2006-01-31

    A computer implemented method schedules processor jobs on a network of parallel machine processors or distributed system processors. Control information communications generated by each process performed by each processor during a defined time interval is accumulated in buffers, where adjacent time intervals are separated by strobe intervals for a global exchange of control information. A global exchange of the control information communications at the end of each defined time interval is performed during an intervening strobe interval so that each processor is informed by all of the other processors of the number of incoming jobs to be received by each processor in a subsequent time interval. The buffered coscheduling method of this invention also enhances the fault tolerance of a network of parallel machine processors or distributed system processors

  12. EC Publications

    Broader source: All U.S. Department of Energy (DOE) Office Webpages (Extended Search)

    Quantifying Photovoltaic Fire Danger Reduction with Arc-Fault Circuit Interrupters admin 2016-04-18T20:58:24+00:00 Popular Downloads Solar Energy Grid Integration Systems: Final Report of the Florida Solar Energy Center Team (11369 downloads) Modeling System Losses in PVsyst (9347 downloads) Numerical Manufacturing And Design Tool (NuMAD v2.0) for Wind Turbine Blades: User's Guide (7615 downloads) Solar Energy Grid Integration Systems (SEGIS) Proactive Intelligent Advances for Photovoltaic

  13. Circuit for echo and noise suppression of acoustic signals transmitted through a drill string

    DOE Patents [OSTI]

    Drumheller, D.S.; Scott, D.D.

    1993-12-28

    An electronic circuit for digitally processing analog electrical signals produced by at least one acoustic transducer is presented. In a preferred embodiment of the present invention, a novel digital time delay circuit is utilized which employs an array of First-in-First-out (FiFo) microchips. Also, a bandpass filter is used at the input to this circuit for isolating drill string noise and eliminating high frequency output. 20 figures.

  14. Circuit for echo and noise suppression of accoustic signals transmitted through a drill string

    DOE Patents [OSTI]

    Drumheller, Douglas S.; Scott, Douglas D.

    1993-01-01

    An electronic circuit for digitally processing analog electrical signals produced by at least one acoustic transducer is presented. In a preferred embodiment of the present invention, a novel digital time delay circuit is utilized which employs an array of First-in-First-out (FiFo) microchips. Also, a bandpass filter is used at the input to this circuit for isolating drill string noise and eliminating high frequency output.

  15. Test results of a 90 MHZ integrated circuit sixteen channel analog pipeline for SSC detector calorimetry

    SciTech Connect (OSTI)

    Kleinfelder, S.A.; Levi, M.; Milgrome, O.

    1990-10-01

    A sixteen channel analog transient recorder with 128 cells per channel has been fabricated as an integrated circuit and tested at speeds of up to 90 MHz. The circuit uses a switched capacitor array technology to achieve a simultaneous read and write capability and twelve bit dynamic range. The high performance of this part should satisfy the demanding electronics requirements of calorimeter detectors at the SSC. The circuit parameters and test results are presented. 2 refs., 3 figs., 1 tab.

  16. Resonant circuit which provides dual-frequency excitation for rapid cycling of an electromagnet

    DOE Patents [OSTI]

    Praeg, W.F.

    1982-03-09

    Disclosed is a novel ring-magnet control circuit that permits synchrotron repetition rates much higher than the frequency of the sinusoidal guide field of the ring magnet during particle acceleration. The control circuit generates sinusoidal excitation currents of different frequencies in the half waves. During radio-frequency acceleration of the synchrotron, the control circuit operates with a lower frequency sine wave and, thereafter, the electromagnets are reset with a higher-frequency half sine wave.

  17. Characterization and application of microearthquake clusters to problems of scaling, fault zone dynamics, and seismic monitoring at Parkfield, California

    SciTech Connect (OSTI)

    Nadeau, R.M.

    1995-10-01

    This document contains information about the characterization and application of microearthquake clusters and fault zone dynamics. Topics discussed include: Seismological studies; fault-zone dynamics; periodic recurrence; scaling of microearthquakes to large earthquakes; implications of fault mechanics and seismic hazards; and wave propagation and temporal changes.

  18. Further Notice of 230kV Circuit Planned Outages | Department of Energy

    Office of Energy Efficiency and Renewable Energy (EERE) Indexed Site

    Further Notice of 230kV Circuit Planned Outages Further Notice of 230kV Circuit Planned Outages Docket No. EO-05-01. Order No. 202-05-03: Pursuant 10 the United States Department of Energy "DOE") Order No. 102-05-3, issued December 20, 2005 ("DOE Potomac River Order''), Pepco hereby files this Further Notice Of 230kV Circuit Planned Outages serving the Potomac River Substation, and through thaI station, the District of Columbia. Further Notice of 230kV Circuit Planned Outages

  19. Apparatus And Method Of Using Flexible Printed Circuit Board In Optical Transceiver Device

    DOE Patents [OSTI]

    Anderson, Gene R.; Armendariz, Marcelino G.; Bryan, Robert P.; Carson, Richard F.; Duckett, III, Edwin B.; McCormick, Frederick B.; Peterson, David W.; Peterson, Gary D.; Reysen, Bill H.

    2005-03-15

    This invention relates to a flexible printed circuit board that is used in connection with an optical transmitter, receiver or transceiver module. In one embodiment, the flexible printed circuit board has flexible metal layers in between flexible insulating layers, and the circuit board comprises: (1) a main body region orientated in a first direction having at least one electrical or optoelectronic device; (2) a plurality of electrical contact pads integrated into the main body region, where the electrical contact pads function to connect the flexible printed circuit board to an external environment; (3) a buckle region extending from one end of the main body region; and (4) a head region extending from one end of the buckle region, and where the head region is orientated so that it is at an angle relative to the direction of the main body region. The electrical contact pads may be ball grid arrays, solder balls or land-grid arrays, and they function to connect the circuit board to an external environment. A driver or amplifier chip may be adapted to the head region of the flexible printed circuit board. In another embodiment, a heat spreader passes along a surface of the head region of the flexible printed circuit board, and a window is formed in the head region of the flexible printed circuit board. Optoelectronic devices are adapted to the head spreader in such a manner that they are accessible through the window in the flexible printed circuit board.

  20. Methods and systems for rapid prototyping of high density circuits

    DOE Patents [OSTI]

    Palmer, Jeremy A.; Davis, Donald W.; Chavez, Bart D.; Gallegos, Phillip L.; Wicker, Ryan B.; Medina, Francisco R.

    2008-09-02

    A preferred embodiment provides, for example, a system and method of integrating fluid media dispensing technology such as direct-write (DW) technologies with rapid prototyping (RP) technologies such as stereolithography (SL) to provide increased micro-fabrication and micro-stereolithography. A preferred embodiment of the present invention also provides, for example, a system and method for Rapid Prototyping High Density Circuit (RPHDC) manufacturing of solderless connectors and pilot devices with terminal geometries that are compatible with DW mechanisms and reduce contact resistance where the electrical system is encapsulated within structural members and manual electrical connections are eliminated in favor of automated DW traces. A preferred embodiment further provides, for example, a method of rapid prototyping comprising: fabricating a part layer using stereolithography and depositing thermally curable media onto the part layer using a fluid dispensing apparatus.

  1. Apparatus and method for defect testing of integrated circuits

    DOE Patents [OSTI]

    Cole, Jr., Edward I.; Soden, Jerry M.

    2000-01-01

    An apparatus and method for defect and failure-mechanism testing of integrated circuits (ICs) is disclosed. The apparatus provides an operating voltage, V.sub.DD, to an IC under test and measures a transient voltage component, V.sub.DDT, signal that is produced in response to switching transients that occur as test vectors are provided as inputs to the IC. The amplitude or time delay of the V.sub.DDT signal can be used to distinguish between defective and defect-free (i.e. known good) ICs. The V.sub.DDT signal is measured with a transient digitizer, a digital oscilloscope, or with an IC tester that is also used to input the test vectors to the IC. The present invention has applications for IC process development, for the testing of ICs during manufacture, and for qualifying ICs for reliability.

  2. Series-counterpulse repetitive-pulse inductive storage circuit

    DOE Patents [OSTI]

    Honig, E.M.

    1984-06-05

    A high-power series-counterpulse repetitive-pulse inductive energy storage and transfer circuit includes an opening switch, a main energy storage coil, and a counterpulse capacitor. The local pulse is initiated simultaneously with the initiation of the counterpulse used to turn the opening switch off. There is no delay from command to output pulse. During the load pulse, the counterpulse capacitor is automatically charged with sufficient energy to accomplish the load counterpulse which terminates the load pulse and turns the load switch off. When the main opening switch is reclosed to terminate the load pulse, the counterpulse capacitor discharges through the load, causing a rapid, sharp cutoff of the load pulse as well as recovering any energy remaining in the load inductance. The counterpulse capacitor is recharged to its original condition by the main energy storage coil after the load pulse is over, not before it begins.

  3. Programmable Differential Delay Circuit With Fine Delay Adjustment

    DOE Patents [OSTI]

    DeRyckere, John F.; Jenkins, Philip Nord; Cornett, Frank Nolan

    2002-07-09

    Circuitry that provides additional delay to early arriving signals such that all data signals arrive at a receiving latch with same path delay. The delay of a forwarded clock reference is also controlled such that the capturing clock edge will be optimally positioned near quadrature (depending on latch setup/hold requirements). The circuitry continuously adapts to data and clock path delay changes and digital filtering of phase measurements reduce errors brought on by jittering data edges. The circuitry utilizes only the minimum amount of delay necessary to achieve objective thereby limiting any unintended jitter. Particularly, this programmable differential delay circuit with fine delay adjustment is designed to allow the skew between ASICS to be minimized. This includes skew between data bits, between data bits and clocks as well as minimizing the overall skew in a channel between ASICS.

  4. Cooling circuit for a gas turbine bucket and tip shroud

    DOE Patents [OSTI]

    Willett, Fred Thomas

    2004-07-13

    An open cooling circuit for a gas turbine airfoil and associated tip shroud includes a first group of cooling holes internal to the airfoil and extending in a radially outward direction generally along a leading edge of the airfoil; a second group of cooling holes internal to the airfoil and extending in a radially outward direction generally along a trailing edge of the airfoil. A common plenum is formed in the tip shroud in direct communication with the first and second group of cooling holes, but a second plenum may be provided for the second group of radial holes. A plurality of exhaust holes extends from the plenum(s), through the tip shroud and opening along a peripheral edge of the tip shroud.

  5. Investigation of Ground-Fault Protection Devices for Photovoltaic Power Systems Applications

    SciTech Connect (OSTI)

    BOWER,WARD I.; WILES,JOHN

    2000-10-03

    Photovoltaic (PV) power systems, like other electrical systems, may be subject to unexpected ground faults. Installed PV systems always have invisible elements other than those indicated by their electrical schematics. Stray inductance, capacitance and resistance are distributed throughout the system. Leakage currents associated with the PV modules, the interconnected array, wires, surge protection devices and conduit add up and can become large enough to look like a ground-fault. PV systems are frequently connected to other sources of power or energy storage such as batteries, standby generators, and the utility grid. This complex arrangement of distributed power and energy sources, distributed impedance and proximity to other sources of power requires sensing of ground faults and proper reaction by the ground-fault protection devices. The different dc grounding requirements (country to country) often add more confusion to the situation. This paper discusses the ground-fault issues associated with both the dc and ac side of PV systems and presents test results and operational impacts of backfeeding commercially available ac ground-fault protection devices under various modes of operation. Further, the measured effects of backfeeding the tripped ground-fault devices for periods of time comparable to anti-islanding allowances for utility interconnection of PV inverters in the United States are reported.

  6. Pattern of extensional faulting in pelagic carbonates of the Unbria-Marche Apennines of central Italy

    SciTech Connect (OSTI)

    Alvarez, W. )

    1990-05-01

    The Umbria-Marche Apennines provide a new region in which the nature passive-margin extensional faulting can be studied in outcrop. In these dominantly pelagic carbonate rocks of Jurassic and Cretaceous age, horsts acted as shallow, nonvolcani seamounts, while tilted half grabens formed deeper basins. One well-exposed seamount-basin transition agrees in general with the model of listric normal faulting and tilted half grabens, but shows interesting and significant divergences when studied in detail. A small sedimentary wedge at the faulted margin of a horst-block seamount thickens unexpectedly toward the adjacent basin. This wedge developed because of local convex-upward curvature of the shallowest part of a fault which at depth must have concave-up, listric geometry. The local sedimentary wedge resulted from deposition on the hanging wall as it tilted, followed by differential compaction of younger limestones that lapped onto the gentle slope leading from the horst-block seamount toward the basin. The map pattern of listric normal faulting in the Umbria-Marche Apennines suggests that both principal strain axes were extensional, in contrast to the usual pattern of listric faults crossed by transfer faults.

  7. Recurrent motion on Precambrian-age basement faults, Palo Duro basin, Texas Panhandle

    SciTech Connect (OSTI)

    Budnik, R.T.

    1983-03-01

    The distribution of Late Precambrian through Quaternary strata in the Palo Duro basin and surrounding uplifts documents recurrent motion on Precambrian-age basement faults. Basement blocks have been uplifted with little tilting or folding of overlying strata along a system of northwest-southeast oriented faults, part of a regional trend extending from central Colorado to southwestern Oklahoma. The orientation of basement terranes in Colorado and that of a 50-mi (80-km) long mylonite zone in east-central New Mexico suggest a Precambrian age for the faults. An Arkosic sandstone overlies basement and underlies a Cambrian(.) quartzose sandstone in a few Palo Duro basin wells. It may represent debris shed from active fault blocks during the opening of the southern Oklahoma aulocogen in the Late Precambrian or Early Cambrian. Ordovician carbonates thin or are missing beneath Mississippian carbonates on some fault blocks, indicating a post-Ordovician-pre-Mississippian period of faulting. The greatest amount of deformation occurred during the Pennsylvanian. Thickness, distribution, and facies of sediments were controlled by the location of active faults. Lower Pennsylvanian strata thin by up to 50% across some structures. Fault blocks provided sources of arkosic debris and loci for carbonate buildups throughout the Pennsylvanian and Early Permian. Around the periphery of the basin, Late Pennsylvanian or Early Permian faulting caused a wedging out of older units beneath the Wolfcamp. Permian, Triassic, and Neogene units, along with present topography, all have been subtly affected by basement structures. The entire section thins over basement highs. Middle and Upper Permian evaporites are thicker in structural lows. The overlying Dockum Group (Triassic) and Ogallala Formation (Neogene), both nonmarine clastic units, become finer grained over basement highs. Present topographic highs coincide with some basement highs.

  8. A practical approach to accurate fault location on extra high voltage teed feeders

    SciTech Connect (OSTI)

    Aggarwal, R.K.; Coury, D.V.; Johns, A.T. . School of Electronic and Electrical Engineering); Kalam, A. )

    1993-07-01

    This paper describes the basis of an alternative approach for accurately locating faults on teed feeders and the technique developed utilizes fault voltages and currents at all three ends. The method is virtually independent of fault resistance and largely insensitive to variations in source impedance, teed and line configurations, including line untransposition. The paper presents the basic theory of the technique which is then extensively tested using simulated primary system voltage and current waveforms which in turn include the transducer/hardware errors encountered in practice. The performance clearly shows a high degree of accuracy attained.

  9. Method and system for controlling a permanent magnet machine during fault conditions

    DOE Patents [OSTI]

    Krefta, Ronald John; Walters, James E.; Gunawan, Fani S.

    2004-05-25

    Method and system for controlling a permanent magnet machine driven by an inverter is provided. The method allows for monitoring a signal indicative of a fault condition. The method further allows for generating during the fault condition a respective signal configured to maintain a field weakening current even though electrical power from an energy source is absent during said fault condition. The level of the maintained field-weakening current enables the machine to operate in a safe mode so that the inverter is protected from excess voltage.

  10. Engine with hydraulic fuel injection and ABS circuit using a single high pressure pump

    DOE Patents [OSTI]

    Bartley, Bradley E.; Blass, James R.; Gibson, Dennis H.

    2001-01-01

    An engine system comprises a hydraulically actuated fuel injection system and an ABS circuit connected via a fluid flow passage that provides hydraulic fluid to both the fuel injection system and to the ABS circuit. The hydraulically actuated system includes a high pressure pump. The fluid control passage is in fluid communication with an outlet from the high pressure pump.

  11. A Fault-Oblivious Extreme-Scale Execution Environment (FOX)

    SciTech Connect (OSTI)

    Van Hensbergen, Eric; Speight, William; Xenidis, Jimi

    2013-03-15

    IBM Research’s contribution to the Fault Oblivious Extreme-scale Execution Environment (FOX) revolved around three core research deliverables: ● collaboration with Boston University around the Kittyhawk cloud infrastructure which both enabled a development and deployment platform for the project team and provided a fault-injection testbed to evaluate prototypes ● operating systems research focused on exploring role-based operating system technologies through collaboration with Sandia National Labs on the NIX research operating system and collaboration with the broader IBM Research community around a hybrid operating system model which became known as FusedOS ● IBM Research also participated in an advisory capacity with the Boston University SESA project, the core of which was derived from the K42 operating system research project funded in part by DARPA’s HPCS program. Both of these contributions were built on a foundation of previous operating systems research funding by the Department of Energy’s FastOS Program. Through the course of the X-stack funding we were able to develop prototypes, deploy them on production clusters at scale, and make them available to other researchers. As newer hardware, in the form of BlueGene/Q, came online, we were able to port the prototypes to the new hardware and release the source code for the resulting prototypes as open source to the community. In addition to the open source coded for the Kittyhawk and NIX prototypes, we were able to bring the BlueGene/Q Linux patches up to a more recent kernel and contribute them for inclusion by the broader Linux community. The lasting impact of the IBM Research work on FOX can be seen in its effect on the shift of IBM’s approach to HPC operating systems from Linux and Compute Node Kernels to role-based approaches as prototyped by the NIX and FusedOS work. This impact can be seen beyond IBM in follow-on ideas being incorporated into the proposals for the Exasacale Operating

  12. Design structure for in-system redundant array repair in integrated circuits

    DOE Patents [OSTI]

    Bright, Arthur A.; Crumley, Paul G.; Dombrowa, Marc; Douskey, Steven M.; Haring, Rudolf A.; Oakland, Steven F.; Quellette, Michael R.; Strissel, Scott A.

    2008-11-25

    A design structure for repairing an integrated circuit during operation of the integrated circuit. The integrated circuit comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The design structure provides the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The design structure further passes the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

  13. Logarithmic current measurement circuit with improved accuracy and temperature stability and associated method

    DOE Patents [OSTI]

    Ericson, M. Nance; Rochelle, James M.

    1994-01-01

    A logarithmic current measurement circuit for operating upon an input electric signal utilizes a quad, dielectrically isolated, well-matched, monolithic bipolar transistor array. One group of circuit components within the circuit cooperate with two transistors of the array to convert the input signal logarithmically to provide a first output signal which is temperature-dependant, and another group of circuit components cooperate with the other two transistors of the array to provide a second output signal which is temperature-dependant. A divider ratios the first and second output signals to provide a resultant output signal which is independent of temperature. The method of the invention includes the operating steps performed by the measurement circuit.

  14. Research of 100 MHz ultra-low-jitter clock generating circuit

    SciTech Connect (OSTI)

    Qiu, Duyu; Tan, Feng; Tian, Shulin; Zeng, Hao; Ye, Peng

    2015-04-15

    Jitter which quantifies the quality of a clock is an important specification. It is of great significance for an electronic system. To obtain a good signal-to-noise ratio for sampling systems, there must be clocks with low jitter performances. By using the relationship between jitter and phase noise, the 100 MHz clock generating circuit with ultra-low jitter and phase noise characteristics are studied in this paper. Bipolar junction transistor with low noise figure and low corner frequency should be selected. Inductance and capacitance in the feedback circuit are obviously the main contributions to the jitter. Impacts of the loaded quality factor (Q{sub L}) of the circuit on the jitter are analyzed, and the explicit expression for the jitter based on circuit components is derived as well. The simulation and experiment results are proved to show that the jitter and phase noise characteristics can be improved by increasing Q{sub L} of the circuit.

  15. Offset-free rail-to-rail derandomizing peak detect-and-hold circuit

    DOE Patents [OSTI]

    DeGeronimo, Gianluigi; O'Connor, Paul; Kandasamy, Anand

    2003-01-01

    A peak detect-and-hold circuit eliminates errors introduced by conventional amplifiers, such as common-mode rejection and input voltage offset. The circuit includes an amplifier, three switches, a transistor, and a capacitor. During a detect-and-hold phase, a hold voltage at a non-inverting in put terminal of the amplifier tracks an input voltage signal and when a peak is reached, the transistor is switched off, thereby storing a peak voltage in the capacitor. During a readout phase, the circuit functions as a unity gain buffer, in which the voltage stored in the capacitor is provided as an output voltage. The circuit is able to sense signals rail-to-rail and can readily be modified to sense positive, negative, or peak-to-peak voltages. Derandomization may be achieved by using a plurality of peak detect-and-hold circuits electrically connected in parallel.

  16. An artificial neutral network fault-diagnostic adviser for a nuclear power plant with error prediction

    SciTech Connect (OSTI)

    Kim, Keehoon

    1992-12-31

    This thesis is part of an ongoing project at Iowa State University to develop ANN bases fault diagnostic systems to detect and classify operational transients at nuclear power plants.

  17. An artificial neutral network fault-diagnostic adviser for a nuclear power plant with error prediction

    SciTech Connect (OSTI)

    Kim, Keehoon.

    1992-01-01

    This thesis is part of an ongoing project at Iowa State University to develop ANN bases fault diagnostic systems to detect and classify operational transients at nuclear power plants.

  18. Effect of stacking fault energy on mechanism of plastic deformation in nanotwinned FCC metals

    DOE Public Access Gateway for Energy & Science Beta (PAGES Beta)

    Borovikov, Valery; Mendelev, Mikhail I.; King, Alexander H.; LeSar, Richard

    2015-05-15

    Starting from a semi-empirical potential designed for Cu, we have developed a series of potentials that provide essentially constant values of all significant (calculated) materials properties except for the intrinsic stacking fault energy, which varies over a range that encompasses the lowest and highest values observed in nature. In addition, these potentials were employed in molecular dynamics (MD) simulations to investigate how stacking fault energy affects the mechanical behavior of nanotwinned face-centered cubic (FCC) materials. The results indicate that properties such as yield strength and microstructural stability do not vary systematically with stacking fault energy, but rather fall into twomore » distinct regimes corresponding to 'low' and 'high' stacking fault energies.« less

  19. On-line early fault detection and diagnosis of municipal solid waste incinerators

    SciTech Connect (OSTI)

    Zhao Jinsong [College of Information Science and Technology, Beijing University of Chemical Technology, Beijing 100029 (China)], E-mail: jinsongzhao@mail.tsinghua.edu.cn; Huang Jianchao [College of Information Science and Technology, Beijing Institute of Technology, Beijing 10086 (China); Sun Wei [College of Chemical Engineering, Beijing University of Chemical Technology, Beijing 100029 (China)

    2008-11-15

    A fault detection and diagnosis framework is proposed in this paper for early fault detection and diagnosis (FDD) of municipal solid waste incinerators (MSWIs) in order to improve the safety and continuity of production. In this framework, principal component analysis (PCA), one of the multivariate statistical technologies, is used for detecting abnormal events, while rule-based reasoning performs the fault diagnosis and consequence prediction, and also generates recommendations for fault mitigation once an abnormal event is detected. A software package, SWIFT, is developed based on the proposed framework, and has been applied in an actual industrial MSWI. The application shows that automated real-time abnormal situation management (ASM) of the MSWI can be achieved by using SWIFT, resulting in an industrially acceptable low rate of wrong diagnosis, which has resulted in improved process continuity and environmental performance of the MSWI.

  20. Method and system for early detection of incipient faults in electric motors

    DOE Patents [OSTI]

    Parlos, Alexander G; Kim, Kyusung

    2003-07-08

    A method and system for early detection of incipient faults in an electric motor are disclosed. First, current and voltage values for one or more phases of the electric motor are measured during motor operations. A set of current predictions is then determined via a neural network-based current predictor based on the measured voltage values and an estimate of motor speed values of the electric motor. Next, a set of residuals is generated by combining the set of current predictions with the measured current values. A set of fault indicators is subsequently computed from the set of residuals and the measured current values. Finally, a determination is made as to whether or not there is an incipient electrical, mechanical, and/or electromechanical fault occurring based on the comparison result of the set of fault indicators and a set of predetermined baseline values.