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Grot, Boris - Department of Electrical and Computer Engineering, Carnegie Mellon University
Ocin tsim -DVFS Aware Simulator for NoCs Subodh Prabhu, Boris Grot, Paul V. Gratz and Jiang Hu
Preemptive Virtual Clock: A Flexible, Efficient, and Cost-effective QOS Scheme for Networks-on-Chip
Appears in CMP-MSI 2008: 2nd Workshop on Chip Multiprocessor Memory Systems and Interconnects Scalable On-Chip Interconnect Topologies
Appears in the Proceedings of the 15th International Symposium on High-Performance Computer Architecture
Appears in the Proceedings of the 6th Annual Workshop on the Interaction between Operating Systems and Computer Architecture Topology-aware Quality-of-Service Support
Appears in the Proceedings of the 14th International Symposium on High-Performance Computer Architecture
Segment Gating for Static Energy Reduction in Networks-On-Chip
Appears in the Proceedings of the 38th International Symposium on Computer Architecture
Good Memories: Enhancing Memory Performance for Precise Flow Tracking Boris Grot, William Mangione-Smith
Reducing Network-on-Chip Energy Consumption Through Spatial Locality Speculation
Ocin tsim -DVFS Aware Simulator for NoCs Subodh Prabhu, Boris Grot, Paul V. Gratz and Jiang Hu
Appears in CMP-MSI 2008: 2nd Workshop on Chip Multiprocessor Memory Systems and Interconnects Scalable On-Chip Interconnect Topologies
Appears in the Proceedings of the 6th Annual Workshop on the Interaction between Operating Systems and Computer Architecture Topology-aware Quality-of-Service Support
Appears in the Proceedings of the 38th International Symposium on Computer Architecture
Preemptive Virtual Clock: A Flexible, Efficient, and Cost-effective QOS Scheme for Networks-on-Chip
Appears in the Proceedings of the 15th International Symposium on High-Performance Computer Architecture
Appears in the Proceedings of the 14th International Symposium on High-Performance Computer Architecture
Segment Gating for Static Energy Reduction in Networks-On-Chip