- Dynamic TDM Virtual Circuit Implementation for NoC , Kai Zhou1
- Assistant Professor, Department of Electronic Engineering Room 803, Weiqing Building, Tsinghua University, 100084,
- Three-Dimensional Integrated Circuits (3D IC) Floorplan and Power/Ground Network Co-synthesis
- Gemma in April: A Matrix-like Parallel Programming Architecture on OpenCL
- A New Thermal-Conscious System-Level Methodology for Energy-Efficient Processor Voltage Selection
- This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1
- L. Jiao et al. (Eds.): ICNC 2006, Part I, LNCS 4221, pp. 716 725, 2006. Springer-Verlag Berlin Heidelberg 2006
- Making Human Connectome Faster: GPU Acceleration of Brain Network Analysis
- PS-FPG: Pattern Selection based co-design of Floorplan and Power/Ground Network with Wiring Resource Optimization
- Variation-Aware Supply Voltage Assignment for Minimizing Circuit Degradation and Leakage
- IR-drop Reduction Through Combinational Circuit Partitioning
- FPMR: MapReduce Framework on FPGA A Case Study of RankBoost Acceleration
- SIGNAL-PATH LEVEL ASSIGNMENT FOR DUAL-Vt TECHNIQUE
- Minimizing Leakage Power in Aging-Bounded High-level Synthesis with Design Time Multi-Vth Assignment
- A Capacitive Boosted Buffer Technique for High-Speed Process-Variation-Tolerant Interconnect in UDVS application
- Output Remapping Technique for Soft-Error Rate Reduction in Critical Paths Qian Ding, Yu Wang, Hui Wang, Rong Luo, Huazhong Yang
- Temperature-Aware NBTI Modeling and the Impact of Standby Leakage Reduction Techniques on
- Two-phase Fine-grain Sleep Transistor Insertion Technique in Leakage Critical Circuits
- 1-4244-0387-1/06/$20.00 2006 IEEE APCCAS 2006 Fine-grain Sleep Transistor Placement Considering
- Gate Replacement Techniques for Simultaneous Leakage and Aging Optimization
- A Framework for Estimating NBTI Degradation of Microarchitectural Components Michael DeBole, K. Ramakrishnan, Varsha Balakrishnan1
- Published in IET Computers & Digital Techniques Received on 29th March 2009
- A Fast-Locking All-Digital Phase-Locked Loop with a Novel Counter-Based Mode Switching Controller
- Modern floorplanning with boundary clustering constraint* , Yuchun Ma2
- Simultaneous Fine-grain Sleep Transistor Placement and Sizing for Leakage Optimization
- DCCB and SCC Based Fast Circuit Partition Algorithm For Parallel SPICE Simulation
- RankBoost Acceleration on both NVIDIA CUDA and ATI Stream platforms Bo WANG, Tianji WU, Feng YAN, Ruirui LI, Ningyi XU and Yu WANG
- Simultaneous Slack Budgeting and Retiming for Synchronous Circuits Optimization Shenghua Liu1
- Simulation and Analysis of PIG Noise in TSV based 3D MPSoC *, Jiang Xu
- The NBTI Impact on RF Front End in Wireless Sensor Bo Zhao, Yu Wang, Huazhong Yang, Hui Wang
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1101 Two-Phase Fine-Grain Sleep Transistor Insertion
- Leakage power reduction through dual Vth assignment considering threshold voltage variation
- On the Efficacy of Input Vector Control to Mitigate NBTI Effects and Leakage Power
- Performance Evaluation of On-Chip Sensor Network (SENoC) in MPSoC Yao Wangl, Yu Wangl*, JiangXu2, HuazhongYangl
- A Novel Gate-level NBTI Delay Degradation Model with Stacking Effect
- This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1
- Hardware Computing for Brain Network Analysis Yu WANG, Yong HE, Yi SHAN, Tianji WU, Di WU and Huazhong YANG
- 978-1-4244-2953-0/09/$25.00 2009 IEEE 13 10th Int'l Symposium on Quality Electronic Design NBTI-Aware Statistical Circuit Delay Assessment
- Modeling of PMOS NBTI Effect Considering Temperature Variation Hong Luo, Yu Wang, Ku He, Rong Luo, Huazhong Yang
- Journal of Circuits, Systems, and Computers Vol. 15, No. 2 (2006) 197216
- A Case Study of On-Chip Sensor Network in Multiprocessor System-on-Chip
- A Power Gating Scheme for Ground Bounce Reduction during Mode Dept. of Electronic Engineering,
- An Efficient Technique for Analysis of Minimal Buffer Requirements of Synchronous Dataflow Graphs with
- Cost-Aware Lifetime Yield Analysis of Heterogeneous 3D On-Chip Cache Balaji Vaidyanathan
- Parametric Yield Driven Resource Binding in Behavioral Synthesis with Multi-Vth/Vdd Library
- Efficient PageRank and SpMV Computation on AMD GPUs Tianji WU, Bo WANG, Yi SHAN, Feng YAN, Yu WANG and Ningyi XU
- FPGA and GPU Implementation of Large Scale , Tianji WU1
- Temperature-aware NBTI modeling and the impact of input vector control on performance degradation
- Published in IET Circuits, Devices & Systems Received on 30th June 2009
