
- 174 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 27, NO. 1, JANUARY 2008 Reduction of Parametric Failures in Sub-100-nm
- Clock Gating and Negative Edge Triggering for Energy Recovery Clock Vishwanadh Tirumalashetty and Hamid Mahmoodi
- Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis
- 2005 IEEE International SOI Conference Independent Gate Skewed Logic in Double-Gate SOI Technology
- Strain Silicon Optimization for Memory and Logic in Nano-Scale CMOS Rajani Kuchipudi and Hamid Mahmoodi
- 1370 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 6, JUNE 2007 Design of a Process Variation Tolerant Self-Repairing
- Paper 44.2 INTERNATIONAL TEST CONFERENCE 0-7803-9039-3/$20.00 2005 IEEE
- Reliability Analysis of Power Gated SRAM under Combined Effects of NBTI and PBTI in Nano-Scale CMOS
- IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 9, SEPTEMBER 2005 1787 Estimation of Delay Variations due to Random-Dopant
- VLSI Lab Tutorial 1 Cadence Virtuoso Schematic Composer Introduction
- San Francisco State University Nano-Electronics & Computing Research Lab 1 ASIC Design Flow Tutorial
- Embedded Electrical and Computer Engineering MASTER ORAL DEFENSE
- 446 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 2, FEBRUARY 2008 A Low-Power SRAM Using Bit-Line
- 1034 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 14, NO. 9, SEPTEMBER 2006 Transactions Briefs
- LOW POWER DESIGN OF DIGITAL SYSTEMS USING ENERGY RECOVERY CLOCKING AND CLOCK GATING
- NC-Verilog Tutorial Setting the Verilog environment in UNIX
- Incorporating Effects of Process, Voltage, and Temperature Variation in BTI Model for Circuit
- IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 24, NO. 12, DECEMBER 2005 1859 Modeling of Failure Probability and Statistical
- A Low-Power SRAM Using Bit-Line Charge-Recycling Keejong Kim
- San Francisco State University Nanoelectronics and Computing Research Lab 1 Full Custom IC Design Flow Tutorial
- HSPICE and WaveView Tutorial Hspice is used for circuit simulation and WaveView is used to view output waveforms.
- Remote Login to hafez.sfsu.edu You need to have an account on hafez.sfsu.edu to be able to login to it. With the given
- Full-Custom Design Project for Digital VLSI and IC Design Courses using Synopsys Generic 90nm CMOS Library
- Virtual Age: Enabling Technologies and Trends Hamid Mahmoodi 1
- New SRAM Design Using Body Bias Technique for Ultra Low Power Applications Farshad Moradi1,3
- Improved Write Margin 6T-SRAM for Low Supply Voltage Applications Farshad Moradi1
- Ultra Low Power Full Adder Topologies Farshad Moradi1
- 65NM SUB-THRESHOLD 11T-SRAM FOR ULTRA LOW VOLTAGE APPLICATIONS
- A Leakage-Tolerant CMOS Comparator in Ultra Deep Submicron CMOS Technology
- Low-Overhead Design Technique for Calibration of Maximum Frequency at Multiple Operating Points
- A NOVEL LEAKAGE-TOLERANT DOMINO LOGIC CIRCUIT WITH FEEDBACK FROM FOOTER TRANSISTOR IN ULTRA
- Self-Repairing SRAM for Reducing Parametric Failures in Nanoscaled Memory Saibal Mukhopadhyay1
- Low Power Synthesis of Dynamic Logic Circuits Using Fine-Grained Clock Gating Nilanjan Banerjee and Kaushik Roy Hamid Mahmoodi Swarup Bhunia
- Double-Gate SOI Devices for Low-Power and High-Performance Applications Kaushik Roy*, Hamid Mahmoodi**, Saibal Mukhopadhyay*, Hari Ananthan*,
- Low-Overhead Design of Soft-Error-Tolerant Scan Flip-Flops with Enhanced-Scan Capability*
- Double-Gate SOI Devices for Low-Power and High-Performance Applications Kaushik Roy*, Hamid Mahmoodi**, Saibal Mukhopadhyay*, Hari Ananthan*,
- Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM
- Paper 37.4 INTERNATIONAL TEST CONFERENCE 1 A Leakage Control System for Thermal Stability During Burn-In Test
- ACMB230A-19 ACM-TRANSACTION February 3, 2010 20:39 Low-Overhead Fmax Calibration
- IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 11, NOVEMBER 2007 1957 Modeling and Circuit Synthesis for Independently
- 1286 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 13, NO. 11, NOVEMBER 2005 Efficient Testing of SRAM With Optimized March
- Using CentOS in Public Lab for Remote Login to hafez.sfsu.edu The computers in the public computer lab are able to boot either Microsoft Windows or CentOS. To
- San Francisco State University Nano Electronics & Computing Research Center Remote Connection to Hafez through VM Ware
- VLSI Lab Tutorial 3 Virtuoso Layout Editing Introduction
- Embedded Electrical and Computer Engineering MASTER ORAL DEFENSE
- Embedded Electrical and Computer Engineering MASTER ORAL DEFENSE
- Embedded Electrical and Computer Engineering MASTER ORAL DEFENSE
- Synopsys Charles Babbage Grant and Research Lab Opening Ceremony
- Embedded Electrical and Computer Engineering MASTER ORAL DEFENSE
- Energy-efficient Hardware Architecture and VLSI Implementation of a Polyphase Channelizer
- 1-Bit Sub Threshold Full Adders in 65nm CMOS Technology Farshad Moradi, Dag T. Wisland,
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 14, NO. 2, FEBRUARY 2006 183 A Novel High-Performance and Robust Sense
- VLSI Lab Tutorial 2 Simulation Using Spectre
- New Subthreshold Concepts in 65nm CMOS Technology Farshad Moradi1
- Robust Sense Amplifier Design under Random Dopant Fluctuations in Nano-Scale CMOS Technologies
- ANALYSIS OF SRAM RELIABILITY UNDER COMBINED EFFECT OF TRANSISTOR AGING,
- High Speed and Leakage-Tolerant Domino Circuits for High Fan-in Applications in 70nm CMOS Technology
- J Electron Test DOI 10.1007/s10836-008-5072-4
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 17, NO. 1, JANUARY 2009 33 Ultra Low-Power Clocking Scheme Using
- Analysis of SRAM Reliability under Combined Effect of NBTI, Process and Temperature Variations
- Virtual Age: Next Wave of Change in Society Ali A. Jalali a
- THERMAL ESTIMATION FOR ACCURATE ESTIMATION OF IMPACT OF BTl AGING EFFECTS ON NANO-SCALE SRAM CIRCUITS
- AC 2011-592: ENHANCING THE INTEREST, PARTICIPATION, AND RE-TENTION OF UNDERREPRESENTED STUDENTS IN ENGINEERING
- COMPARISON OF PERFORMANCE PARAMETERS OF SRAM DESIGNS IN 160m CMOS AND CNTFET TECHNOLOGIES
- Postsilicon Adaptation for Low-Power SRAM under
- Embedded Electrical and Computer Engineering MASTER ORAL DEFENSE
- Data-Dependant Sense-Amplifier Flip-Flop for Low Power Applications In this paper, we present a new sense amplifier based flip-flop that
- Embedded Electrical and Computer Engineering MASTER ORAL DEFENSE
- Embedded Electrical and Computer Engineering MASTER ORAL DEFENSE
- Abstract--Clock distribution network is an important part of digital integrated circuits. The clock signal carried by the
- In this paper, a multi-level wordline driver scheme is presented to improve SRAM read and write stability while lowering power
- Analysis of Reliability of Flip-Flops under Transistor Aging Effects in Nano-scale CMOS Technology
- IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 12, DECEMBER 2011 4241 Asymmetrically Doped FinFETs for
- Optimal Body Biasing for Maximizing Circuit Performance in 65nm CMOS Farshad Moradi1,3, Tuan Vu Caol, Dag T. WislandI, Snorre Aunee, Hamid Mahmoodi2,
- Impact of NBTI on performance of domino logic circuits in nano-scale CMOS M. Houshmand Kaffashian a,n