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Detrey, Jérémie - Laboratoire Lorrain de Recherche en Informatique et ses Applications (LORIA), Université Henri Poincaré -Nancy-Université
A Constructive Proof of the Turing Completeness of Circal
Hardware Accelerator for the Tate Pairing in Characteristic Three Based on
A VHDL Library of LNS Operators Jeremie Detrey Florent de Dinechin
Outils pour une comparaison sans a priori entre arithmtique logarithmique
When FPGAs are better at floating-point than microprocessors
FAST ARCHITECTURES FOR THE T PAIRING OVER SMALL-CHARACTERISTIC SUPERSINGULAR ELLIPTIC CURVES 1 Fast Architectures for the T Pairing over
Laboratoire de l'Informatique du Paralllisme cole Normale Suprieure de Lyon
Arithmetic Operators for Pairing-Based Cryptography
Laboratoire de l'Informatique du Paralllisme cole Normale Suprieure de Lyon
Accelerating Lattice Reduction with FPGAs Jeremie Detrey1
A parameterized floating-point exponential function for FPGAs Jeremie Detrey Florent de Dinechin
Jeremie DETREY TutoRISC : un RISC dans mon FPGA Ecole Normale
FLOATING-POINT TRIGONOMETRIC FUNCTIONS FOR FPGAS Jeremie Detrey, Florent de Dinechin
SCCircal: a Static Compiler Mapping XCircal to Virtex FPGAs
RENPAR'15 / CFSE'3 / SympAAA'2003 La Colle sur Loup, France, 15 au 17 octobre 2003
ALGORITHMS AND ARITHMETIC OPERATORS FOR COMPUTING THE T PAIRING IN CHARACTERISTIC THREE 1 Algorithms and Arithmetic Operators for
Hardware Accelerator for the Tate Pairing in Characteristic Three Based on
A Low-Area yet Performant FPGA Implementation of Shabal
A parameterizable floating-point logarithm operator Jeremie Detrey and Florent de Dinechin
Laboratoire de l'Informatique du Parallelisme Ecole Normale Superieure de Lyon
Fonctions lmentaires en virgule flottante pour les acclrateurs reconfigurables
Arithmetic Operators for Pairing-Based Cryptography
A tool for unbiased comparison between logarithmic and floating-point arithmetic
TutoRISC : un RISC dans mon FPGA Jrmie Detrey
ALGORITHMS AND ARITHMETIC OPERATORS FOR COMPUTING THE T PAIRING IN CHARACTERISTIC THREE 1 Algorithms and Arithmetic Operators for
Parameterized floating-point logarithm and exponential functions for FPGAs
A Low-Area Yet Performant FPGA Implementation of Shabal
Floating point or LNS: Choosing the right arithmetic on an application basis
Second Order Function Approximation Using a Single Multiplication on FPGAs
Laboratoire de l'Informatique du
RenPar'17 / SympA'2006 / CFSE'5 / JC'2006 Canet en Roussillon, 4 au 6 octobre 2006
d'ordre : 396 attribu par la bibliothque : 06ENSL0 396
Laboratoire de l'Informatique du Paralllisme cole Normale Suprieure de Lyon
Laboratoire de l'Informatique du Paralllisme cole Normale Suprieure de Lyon
A Comparison between Hardware Accelerators for the Modified Tate Pairing over F2m and F3m
Multipartite Tables in JBits for the Evaluation of Functions on FPGAs
Table-based polynomials for fast hardware function evaluation