- Our reference: MICPRO 1849 P-authorquery-v8 AUTHOR QUERY FORM
- Optimization of Digital BiCMOS Circuits, An Overview M.S. Elrabaa Sludenr Member, IEEE, a d M.I . Elmasry,i;Ellow, IEEE.
- A NEW STATICDIFFERENTIALCMOS LOGIC WITH SUPERIOR LOW POWER PERFORMANCE
- 192 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 27, NO. 5, MAY 1992 Design and Optimization of Buffer Chains and Logic
- 454 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 27. NO. 3. MARCH 1992 Multiemitter BiCMOS CML Circuits
- An All-Digital Clock Frequency Caputring Circuitry For NRZ Data Communications
- An Efficient Network-on-Chip Architecture Based on the Fat-Tree (FT) Topology
- A Two-Phase Return-to-Zero (RZ) Asynchronous Transceiver Circuit for Pipe-Lined SoC Interconnects
- A New Client Interface Architecture for the Modified Fat Tree (MFT) Network-on-Chip
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1 Robust Two-Phase RZ Asynchronous SoC Interconnects
- Analog Integrated Circuits and Signal Processing, 43, 183190, 2005 c 2005 Springer Science + Business Media, Inc. Manufactured in The Netherlands.
- 604 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 4, APRIL 1997 Low-Power BiCMOS Circuits for High-Speed Interchip Communication
- 86 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 29, NO. 2, FEBRUARY 1994 Novel Low-Voltage Low-Power
- Abstract--The architecture of the class of routers to implement the modified Fat Tree topology is shown. The router architecture
- A Digital Clock Re-Timing Circuit for On-Chip Source-Synchronous Serial Links
- The 6th Saudi Engineering Conference, KFUPM, Dhahran, December 2002 Vol. 4. 167 REVIEW OF HIGH-SPEED DIGITAL CMOS CIRCUITS
- Split-Gate Logic Circuits for Multi-Threshold Technologies Muhammad E. S. Elrabaa, and Mohamed I. Elmasry*
- ISCAS 2000 -IEEE InternationalSymposium on Circuits and Systems, May 28-31, 2000, Geneva, Switzerland A CONTENTION-FREE DOMINO LOGIC FOR SCALED-DOWN CMOS
- Muhammad E. S. Elrabaa December 2007 The Arabian Journal for Science and Engineering, Volume 32, Number 2C 109
- A High-Throughput Network-on-Chip Architecture for Systems-on-Chip Interconnect
- A Portable Clock Recovery Circuit (CRC) For Systems-On-Chip Serial Data Communication
- Abdelhafid Bouhraoua and Muhammad E. S. Elrabaa December 2007 The Arabian Journal for Science and Engineering, Volume 32, Number 2C 13
- A Universal 3.3V 1 GHz BiCMOS Transceiver (Driver/Receiver) M. S. Elrabaa, Student Member, IEEE. M. I. Elmasry, Fellow, IEEE
- Abstract--A novel approach for satisfying heterogeneous bandwidth requirements of clients connected using a modified
