- Interconnect-Efficient LDPC Code Design Aiman El-Maleh, Basil Arkasosy, M. Adnan Al-Andalusi
- A Hybrid Test Compression Technique for Efficient Testing of Systems-on-a-Chip
- A STATIC TEST COMPACTION TECHNIQUE FOR COMBINATIONAL CIRCUITS BASED ON INDEPENDENT FAULT CLUSTERING
- An Efficient Test Vector Compression Technique Based on Block Merging
- Defect Tolerant N2 -Transistor Structure for Reliable Nanoelectronic Designs
- Hindawi Publishing Corporation EURASIP Journal on Wireless Communications and Networking
- An Efficient Test Compression Technique Based on Block Merging
- Test Data Compression for System-on-a-Chip using Extended Frequency-Directed Run-Length
- Test Vector Decomposition Based Static Compaction Algorithms for Combinational Circuits
- USING INPUT/OUTPUT QUEUES TO INCREASE LDPC DECODER PERFORMANCE
- IMPROVING BER PERFORMANCE OF LDPC CODES BASED ON INTERMEDIATE DECODING RESULTS
- Finite State Machine State Assignment for Area and Power Minimization
- SIMULATED EVOLUTION ALGORITHM FOR MULTIOBJECTIVE VLSI NETLIST BI-PARTITIONING
- GENERAL ITERATIVE HEURISTICS FOR VLSI MULTIOBJECTIVE PARTITIONING Sadiq M. Sait, Aiman H. El-Maleh, Raslan H. Al-Abaji
- An Efficient Test Relaxation Technique for Combinational Circuits Based on Critical Path Tracing
- Extended Frequency-Directed Run-Length Code with Improved Application to System-on-a-Chip Test Data Compression
- A Retiming-Based Test Pattern Generator Design for Built-In Self Test of Data Path Architectures
- FUZZY SIMULATED EVOLUTION FOR POWER AND PERFORMANCE OPTIMIZATION OF VLSI PLACEMENT
- The Pitfalls of Necessary Assignments Wu-Tung Cheng, Rob Thompson, Aiman El-Maleh, Don Ross and Janusz Rajski
- A New Collaborative Scheme of Test Vector Compression Based on Equal-Run-Length Coding (ERLC)
- Efficient Test Compaction for Combinational Circuits Based on Fault Detection Count-Directed Clustering
- ON EFFICIENT EXTRACTION OF PARTIALLY SPECIFIED TEST SETS FOR SYNCHRONOUS SEQUENTIAL CIRCUITS
- Generate information to be transmitted, Compare transmitted and received information and
- Efficient Static Compaction Techniques for Sequential Circuits Based on Reverse Order Restoration and Test Relaxation
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- Robust Computing with Nano-scale Devices Lecture Notes in Electrical Engineering
- ENHANCING PERFORMANCE OF ITERATIVE HEURISTICS FOR VLSI NETLIST PARTITIONING
- An Efficient Test Relaxation Technique for Synchronous Sequential Circuits Aiman El-Maleh and Khaled Al-Utaibi
- A Geometric-Primitives-Based Compression Scheme for Testing Systems-on-a-Chip
- 1. ABSTRACT This paper presents an efficient and novel method for
- An Efficient Test Vector Compression Technique Based on Geometric Shapes Saif al Zahir1
- Evolutionary Algorithms for VLSI Multiobjective Netlist Partitioning 1 Evolutionary Algorithms for VLSI Multiobjective Netlist
- Esa Alghonaim Aiman El-Maleh, M. Adnan Landolsi and Sadiq M. Sait October 2010 The Arabian Journal for Science and Engineering, Volume 35, Number 2B 135
- Efficient Test Compaction for Combinational Circuits Based on Fault Detection Count-Directed Clustering
- An Efficient Test Relaxation Technique for Synchronous Sequential Circuits
- Efficient Static Compaction Techniques for Sequential Circuits Based on Reverse Order Restoration and Test Relaxation
- An Efficient Test Relaxation Technique for Combinational & Full-Scan Sequential Circuits
- Transistor-Level Based Defect-Tolerance for Reliable Nanoelectronics Aiman H. El-Maleh1
