- Multiplier Architectures for Media Processing Shankar Krithivasan and Michael J. Schulte
- A Low-Power Multithreaded Processor for Baseband Communication Systems
- Integer Multiplication with Overflow Detection or Saturation
- High-Speed Multioperand Decimal Adders Robert D. Kenney and Michael J. Schulte, Senior Member, IEEE
- Combined Multiplication and Sum-of-Squares Units Michael J. Schulte, Louis Marquette, Shankar Krithivasan,
- Decimal Floating-Point Square Root Using Newton-Raphson Iteration Liang-Kai Wang and Michael J. Schulte
- Decimal Floating-Point Adder and Multifunction Unit with Injection-Based Liang-Kai Wang and Michael J. Schulte
- A Binary Integer Decimal-based Multiplier for Decimal Floating-Point Arithmetic
- Journal of VLSI Signal Processing, 11, 112 (1999) c 1999 Kluwer Academic Publishers, Boston. Manufactured in The Netherlands.
- A Hardware Algorithm for Variable-Precision Logarithm Ja vierHormigo and Julio Villalba
- Reduced Power Dissipation Through Truncated Multiplication
- Architecture Support for Reconfigurable Multithreaded Processors in Programmable Communication Systems
- Proceedings of the 33rd Hawaii International Conference on System Sciences -2000 0-7695-0493-0/00 $10.00 (c) 2000 IEEE 1
- Low-Power Multiple-Precision Iterative Floating-Point Multiplier with SIMD Support
- A Parallel IEEE P754 Decimal Floating-Point Multiplier Brian Hickmann, Andrew Krioukov, and Michael Schulte
- Symmetric Table Addition Methods for Neural Network Approximations
- Implementing Communications Systems on an SDR SoC John Glossner1
- Design tradeoffs using truncated multipliers in FIR filter implementations
- Hindawi Publishing Corporation EURASIP Journal on Embedded Systems
- Rapid Vascular Rendering using 4D Cluster Visualization
- Hardware Design of a Binary Integer Decimal-based Floating-point Adder
- Decimal Multiplication Via Carry-Save Addition Mark A. Erle
- Automated Generation of Configurable Media Processors
- Future Wireless Convergence Platforms John Glossner, Ph.D., EVP & CTO
- Hardware Designs for Decimal Floating-Point Addition and Related Operations
- Instruction Set Extensions for Software Defined Radio on a Multithreaded Processor
- Abstract--PLX FP is a floating-point instruction set architecture (ISA) extension to PLX that is designed for fast and
- AHARDWARE ACCELERATOR FOR ELLIPTIC CURVE CRYPTOGRAPHY OVER GF(2M
- A Quadruple Precision and Dual Double Precision Floating-Point Multiplier Ahmet Akkas
- A High-Frequency Decimal Multiplier Robert D. Kenney and Michael J. Schulte
- A Combined Interval and Floating Point Multiplier James E. Stine and Michael J. Schulte
- A Low-Power Carry Skip Adder with Fast Saturation Michael J. Schulte1,3
- A 64-bit Decimal Floating-Point Adder John Thompson, Nandini Karra, and Michael J. Schulte
- A Family of Variable-Precision Interval Arithmetic Processors
- A Combined Two's Complement and Floating-Point James E. Stine
- IEEE TRANSACTIONS ON COMPUTERS, VOL. X, NO. Y, MONTH 2008 1 Decimal Floating-Point Multiplication
- Using truncated multipliers in DCT and IDCT hardware accelerators
- Performance Evaluation of Decimal Floating-Point Arithmetic Michael J. Schulte, Nick Lindberg, and Anitha Laxminarain
- Hardware Design of a Binary Integer Decimal-based IEEE P754 Rounding Unit
- Improved Combined Binary/Decimal Fixed-Point Multipliers Brian Hickmann and Michael Schulte
- Low Latency Interventional MRI Visualization using a GPU Cluster , M. Schulte1
- Benchmarks and Performance Analysis of Decimal Floating-Point Applications Liang-Kai Wang, Charles Tsen, Michael J. Schulte, and Divya Jhalani
- Floating-Point Division Algorithms for an x86 Microprocessor with a Rectangular Multiplier
- Software Solutions for Converting a MIMO-OFDM Channel into Multiple SISO-OFDM Channels
- THE SANDBLASTER SBX 2.0 ARCHITECTURE John Glossner1
- Instruction Set Extensions for ABS Processing on a Multithreaded Software Defined Radio Platform
- Hindawi Publishing Corporation EURASIP Journal on Embedded Systems
- Arithmetic Units for Software Defined Radio Suman Mamidi, Michael
- Abstract--We describe the generation of the simulation environment for the Sandbridge Sandblaster multithreaded
- Instruction Set Extensions for Reed-Solomon Encoding and Decoding Suman Mamidi and Michael J. Schulte
- Decimal Floating-Point Division Using Newton-Raphson Liang-Kai Wang and Michael J. Schulte
- A Subword-Parallel Multiplication and Sum-of-Squares Unit Shankar Krithivasan, Michael J. Schulte, and John Glossner
- Multioperand Decimal Addition Robert D. Kenney and Michael J. Schulte
- A Static Low-Power, High-Performance 32-bit Carry Skip Adder Kai Chirca1,2
- Truncated Squarers with Constant and Variable Correction E. George Walters IIIa, Michael J. Schulteb, and Mark G. Arnolda
- Sandblaster Low-Power Multithreaded SDR Baseband John Glossner
- A Hardware Algorithm for Variable-Precision Division Javier Hormigo Julio Villalba
- Parallel Saturating Multioperand Adders Michael Schulte, Pablo Balzola, Jie Ruan
- Reliable Computing, 5, 311?? (1999) c 1999 Kluwer Academic Publishers, Boston. Manufactured in The Netherlands.
- A Low-Power Multithreaded Processor for Software Defined Radio Michael Schulte2
- 0018-9162/07/$25.00 2007 IEEE September 2007 23Published by the IEEE Computer Society P E R S P E C T I V E S
- Sandblaster Low Power DSP John Glossner1,2
