- DART: A Programmable Architecture for NoC Simulation Danyao Wang, Natalie Enright Jerger, J. Gregory Steffan
- Low-Latency Virtual-Channel Routers for On-Chip Networks Robert Mullins, Andrew West and Simon Moore
- DART: Fast and Flexible NoC Simulation using FPGAs Danyao Wang, Natalie Enright Jerger, and J. Gregory Steffan
- Elastic-Buffer Flow Control for On-Chip Networks George Michelogiannakis, James Balfour and William J. Dally
- An Evaluation of Server Consolidation Workloads for Multi-Core Designs
- Low-Cost Router Microarchitecture for On-Chip Networks Department of Computer Science
- Region-Based Routing: An Efficient Routing Mechanism to Tackle Unreliable Hardware in Network on Chips
- Microarchitecture of a High-Radix Router John Kim, William J. Dally, Brian Towles1
- A Low-Radix and Low-Diameter 3D Interconnection Network Design , Xiuyi Zhou
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- Argia: Exploiting Packet Latency Slack in On-Chip Networks
- ECE 1749H: Interconnec1on Networks for
- DBAR: An Efficient Routing Algorithm to Support Multiple Concurrent Applications in Networks-on-Chip
- SigNet: Network-on-Chip Filtering for Coarse Vector Directories Natalie Enright Jerger
- IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 28, NO. 1, JANUARY 2009 3 Keynote Paper
- Virtual Circuit Tree Multicasting: A Case for On-Chip Hardware Multicast Natalie Enright Jerger, Li-Shiuan Peh, and Mikko Lipasti
- An Evaluation of Server Consolidation Workloads for Multi-Core Designs
- ECE 1749H: Interconnec3on Networks for
- ECE 1749H: Interconnec1on Networks for
- ECE 1749H: Interconnec3on Networks for
- IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 1, JANUARY 2011 173 A 48-Core IA-32 Processor in 45 nm CMOS
- ECE 1749H: Interconnec1on Networks for
- ECE 1749H: Interconnec1on Networks for Parallel Computer
- ECE 1749H: Interconnec1on Networks for
- ECE 1749H: Interconnec1on Networks for
- ECE 1749H: Interconnec1on Networks for
- COST-EFFICIENT DRAGONFLY TOPOLOGY FOR LARGE-SCALE
- Performance and Power Optimization through Data Compression in Network-on-Chip Architectures
- BulletProof: A Defect>Tolerant CMP Switch Architecture Kypros Constantinides
- Advances in semiconductor tech-nology have let microprocessors integrate
- Circuit-Switched Coherence Natalie Enright Jerger, Mikko Lipasti, and Li-Shiuan Peh
- Corona: System Implications of Emerging Nanophotonic Technology Dana Vantrease
- SCARAB: A Single Cycle Adaptive Routing and Bufferless Mitchell Hayenga
- ON-CHIP INTERCONNECTION ARCHITECTURE OF THE
- In-Network Coherence Filtering: Snoopy Coherence without Niket Agarwal, Li-Shiuan Peh, and Niraj K. Jha
- Circuit-Switched Coherence Natalie Enright Jerger, Li-Shiuan Peh, and Mikko Lipasti
- Virtual Tree Coherence: Leveraging Regions and In-Network Multicast Trees for Scalable Cache Coherence
- CHARACTERIZING THE CELL EIB ON-CHIP NETWORK
- Flattened Butterfly Topology for On-Chip Networks John Kim, James Balfour, and William J. Dally
- GOAL: A Load-Balanced Adaptive Routing Algorithm for Torus Networks Arjun Singh , William J Dally , Amit K Gupta , Brian Towles
- Achieving Predictable Performance through Better Memory Controller Placement in Many-Core CMPs
- CHIP MULTIPROCESSOR COHERENCE AND INTERCONNECT SYSTEM DESIGN
- A 5-GHZ MESH INTERCONNECT FOR A TERAFLOPS PROCESSOR
- A Case for Dynamic Frequency Tuning in On-Chip Asit K. Mishra
- Power-driven Design of Router Microarchitectures in On-chip Networks Hangsheng Wang Li-Shiuan Peh Sharad Malik
- Near-Optimal Worst-case Throughput Routing for Two-Dimensional Mesh Networks
- ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers* Chrysostomos A. Nicopoulos, Dongkook Park, Jongman Kim,
- Friendly Fire: Understanding the Effects of Multiprocessor Prefetches Natalie D. Enright Jerger, Eric L. Hill, and Mikko H. Lipasti
- Rotary Router: An Efficient Architecture for CMP Interconnection Networks
- Express Virtual Channels: Towards the Ideal Interconnection Fabric
- Design Tradeoffs for Tiled CMP On-Chip Networks James Balfour
- Recursive Partitioning Multicast: A Bandwidth-Efficient Routing for Networks-On-Chip
- A New Theory of Deadlock-Free Adaptive Routing in Wormhole Networks
- CMP Network-on-Chip Overlaid With Multi-Band RF-Interconnect M. Frank Chang
- Design and Evaluation of a Hierarchical On-Chip Interconnect for Next-Generation CMPs
- ECE 1749H: Interconnec1on Networks for
- Whole Packet Forwarding: Efficient Design of Fully Adaptive Routing Algorithms for Networks-on-Chip
- Natalie Enright Jerger Information
- Exploration of Temperature Constraints for Thermal Aware Mapping of 3D Networks on Chip
