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Su, Bogong - Department of Computer Science, William Paterson University of New Jersey
A New Source-Level Benchmarking for DSP Processors Bogong Su, Erh-Wen Hu, Joseph Manzano, Steve Regula
SOFTWARE PIPELINING OF NESTED LOOPS FOR REAL-TIME DSP APPLICATIONS
ASSEMBLY CODE CONVERSION THROUGH PATTERN MAPPING BETWEEN TWO VLIW DSP PROCESSORS: A CASE STUDY
Assembly Code Conversion of Software-Pipelined Loop between two VLIW DSP Processors
Impact of Source-Level Loop Optimization on DSP Architecture Design Dept. of Computer Science
DE-PIPELINE A SOFTWARE-PIPELINED LOOP Bogong Su 1
GURPR--A Method for Global Software Pipelinina: BoRonn Su: Shiyuan Dins. Jian Wang and Jinshi Xia
A Study of Performance Measurement of DSP Processors Bogong Su, Erh-Wen Hu,
Performance Analysis of Digital Signal Processors Using SMV Benchmark
DSP Performance Comparison by using SMV Benchmark E. Hu*, C. Ku*, A. Russo**, B. Su* and J. Wang***
New DSP Benchmark based on Selectable Mode Vocoder (SMV)
Software De-Pipelining Technique Bogong Su 1
LOOP OPTIMIZATION WITH TRADEOFF BETWEEN CYCLE COUNT AND CODE SIZE FOR DSP APPLICATIONS
Code Migration from Conventional DSPs to VLIW DSPs Dept. of Computer Science
A SCALABLE LOOP OPTIMIZATION APPROACH FOR SCALABLE DSP PROCESSORS
Analysis of Loop Behavior of Selectable Mode Vocoder (SMV) and Its Impact of Instruction Level Parallelism
