Palermo, Sam - Department of Electrical and Computer Engineering, Texas A&M University

• Jitter Analysis: The dual-Dirac Model, RJ/DJ, and Q-Scale
• IEEE JOURNAL OF SOLID-STATECIRCUITS, VOL. 31, NO. 12, DECEMBER 1996 l iMultl-phaseClock Generator(VCO)
• 876 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 6, JUNE 2000 Improved Sense-Amplifier-Based Flip-Flop
• Electronics Bipolar Junction Transistors
• 6 2007 IEEE International Solid-State Circuits Conference ISSCC 2007 / SESSION 2 / OPTICAL COMMUNICATIONS / 2.2
• ELEN 689 High-Speed Links Circuits and Systems
• Electronics Dr. Aydin Ilker Karsilayan
• 2120 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 9, SEPTEMBER 2008 Design and Comparison of Three 20-Gb/s Backplane
• Burst Mode Packet Receiver using a Second Order DLL Haechang Lee, Chi Ho Yue, Samuel Palermo, Kenneth W. Mai, and Mark Horowitz
• ECEN 689 High-Speed Links Circuits and Systems Lab4 Receiver Circuits
• ELEN-325. Introduction to Electronic Circuits: Design Approach Jose Silva-Martinez ELEN-325. Part IV.
• Agilent AN 154 S-Parameter Design
• ELEN-325. Introduction to Electronic Circuits Jose Silva-Martinez Confidential 3/25/2009
• I. Introduction ata bandwidth for state of the art wire-linked
• 1012 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 4, APRIL 2005 Autonomous Dual-Mode (PAM2/4) Serial Link
• Bandpass filtering of high-speed forwarded clocks Timothy M. Hollis David J. Comer
• 1550nm Optical Interconnect Transceiver with Low Voltage Electroabsorption Modulators Flip-Chip Bonded to 90nm
• IEEE Communications Magazine August 200294 Challenges in the Design of
• A number of students have had trouble getting their DC bias conditions working in the lab. This is because the Beta of our lab transistors may not match the PSpice model. I would compare the
• IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS--I: REGULAR PAPERS, VOL. 56, NO. 1, JANUARY 2009 17 Clocking Analysis, Implementation and Measurement
• IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 9, SEPTEMBER 2007 1999 Equalization and Clock and Data Recovery
• ELEN 689 High-Speed Links Circuits and Systems
• IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 5, MAY 2008 1235 A 90 nm CMOS 16 Gb/s Transceiver
• Power Efficiency Modeling and Optimization of High-Speed Equalized-Electrical I/O Architectures
• An Accurate and Efficient Analysis Method for Multi-Gbls Chip-to-chip Signaling Bryan K. Casper, Matthew Haycock, Randy Mooney
• ISSCC 2007 / SESSION 17 / ANALOG TECHNIQUES AND PLLs /173 17.7 A Double-Tail Latch-Type Voltage Sense Amplifier input and output pads (for probe station measurement) was
• Laboratory Manual ELEN 474: VLSI Circuit Design
• MOSFET DEVICES If the MOSFET is operating in saturation, then the following conditions are satisfied
• IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 12, DECEMBER 2007 2745 A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS
• Pages 3-9 outline the noise analysis simulation set-up. At the part where it talks about adding flicker noise, switch back to the following below (pages 1-2).
• ELEN 474 Midterm # 1 Instructor: Dr. Jose Silva-Martinez
• Electronics Operational Amplifiers
• 436 2007 IEEE International Solid-State Circuits Conference ISSCC 2007 / SESSION 24 / MULTI-GB/s TRANSCEIVERS / 24.1
• 230 2007 IEEE International Solid-State Circuits Conference ISSCC 2007 / SESSION 12 / GIGABIT CDRs AND EQUALIZERS / 12.5
• November 10, 2009 Final Project
• Copyright by Samuel Palermo 2010, All Rights Reserved High-Speed Serial I/O Design for Channel-
• Laboratory Manual ELEN-325 Electronics
• IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 4, APRIL 2010 899 A 0.6 mW/Gb/s, 6.47.2 Gb/s Serial Link Receiver
• IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS--II: EXPRESS BRIEFS, VOL. 57, NO. 5, MAY 2010 343 Power Efficiency Comparisons of Interchip Optical
• 1314 IEEE JOURNAL OF SOLID-STATECIRCUITS, VOL. 31, NO. 9, SEPTEMBER 1996 ased Methodology for the Design of CMOS Analog Circuits and
• Electronics MOS Field-Effect Transistors
• 3526 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 12, DECEMBER 2009 A 10-Gb/s Compact Low-Power Serial I/O With
• INTRODUCTION The microprocessor architecture transition from
• 468 2009 IEEE International Solid-State Circuits Conference ISSCC 2009 / SESSION 28 / TD: DIRECTIONS IN COMPUTING AND SIGNALING / 28.1
• High-Speed Transmitters in 90nm CMOS for High-Density Optical Interconnects
• Supply Regulation Techniques for Phase-Locked Loops
• A Multi-Band Single-LoopPLL Frequency Synthesizer with Dynamically-ControlledSwitched Tuning VCO
• IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS--I: REGULAR PAPERS, VOL. 58, NO. 2, FEBRUARY 2011 253 Clock-Jitter-Tolerant Wideband Receivers: An
• DESIGN OF HIGH-SPEED OPTICAL INTERCONNECT TRANSCEIVERS
• A MULTI-BAND PHASE-LOCKED LOOP FREQUENCY SYNTHESIZER SAMUEL MICHAEL PALERMO
• ECEN 325: Electronics TR 2:20-3:35, ZACH 223C
• ELEN-325. Introduction to Electronic Circuits: A Design Approach Jose Silva-Martinez Chapter IIIa
• ELEN-325. Introduction to Electronic Circuits Jose Silva-Martinez Confidential 3/10/2009
• Electronics Introduction
• PSpice Hints for Project PSpice Transient and Fourier Analysis Settings
• October 27, 2010 ELEN-474: Analog VLSI
• ECEN 689-603: Special Topics in High-Speed Links Circuits & Systems Spring 2011
• Advances in IC fabrication technolo-gy, coupled with aggressive circuit
• IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 12, DECEMBER 2006 2885 A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in
• 1010 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 4, APRIL 2008 A Scalable 515 Gbps, 1475 mW Low-Power I/O
• http://www.hp.com/go/tmappnotes HTest & Measurement
• 70 2005 IEEE International Solid-State Circuits Conference 0-7803-8904-2/05/$20.00 2005 IEEE. ISSCC 2005 / SESSION 3 / BACKPLANE TRANSCEIVERS / 3.6
• 152 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 53, NO. 1, JANUARY 2005 High-Speed Electrical Backplane Transmission
• IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 12, DECEMBER 2008 2905 A T-Coil-Enhanced 8.5 Gb/s High-Swing SST
• Characterizing Sampling Aperture of Clocked Comparators M. Jeeradit1
• The Designer's Guide Community downloaded from www.designers-guide.org Copyright 2006, William Evans All Rights Reserved 1 of 6
• 954 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 4, APRIL 2006 A 22-Gb/s PAM-4 Receiver in 90-nm
• IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 2, FEBRUARY 1998 237 Time Resolution of NMOS Sampling
• IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 3, MARCH 2010 629 An 80 mW 40 Gb/s 7-Tap T/2-Spaced Feed-Forward
• IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 11, NOVEMBER 2002 1375 Jitter Optimization Based on Phase-Locked Loop
• AN ESTIMATION APPROACH TO CLOCK AND DATA RECOVERY
• IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 8, AUGUST 2006 1867 A Digital Clock and Data Recovery Architecture for
• 1818 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS--I: REGULAR PAPERS, VOL. 56, NO. 8, AUGUST 2009 Strong Injection Locking in Low-Q LC Oscillators
• 2138 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 8, AUGUST 2009 CMOS Oscillators for Clock Distribution and
• Figure 1. Structures for clock distribution (a) Inverter chain (b) CML chain (c) Transmition line (d) Inductive load and (e) CDW
• High-Speed Links Circuits and Systems Yung-Chung Lo
• ELEN 689 High-Speed Links Circuits and Systems
• ECEN 689 High-Speed Links Circuits and Systems Lab3 Transmitter Circuits
• ELEN 689 High-Speed Links Circuits and Systems
• ECEN 689 High-Speed Links Circuits and Systems Lab6 Stateye Link Modeling
• March 30, 2011 ECEN 689: High-Speed Links
• Channel Transient Simulation Test Figure 1 Channel Transient Test Circuit with 9-bit differential PRBS
• 448 2011 IEEE International Solid-State Circuits Conference ISSCC 2011 / SESSION 25 / CDRs & EQUALIZATION TECHNIQUES / 25.7
• 356 2011 IEEE International Solid-State Circuits Conference ISSCC 2011 / SESSION 20 / HIGH-SPEED TRANSCEIVERS & BUILDING BLOCKS / 20.6
• 446 2011 IEEE International Solid-State Circuits Conference ISSCC 2011 / SESSION 25 / CDRs & EQUALIZATION TECHNIQUES / 25.6
• Preliminary Exam: Dr Samuel Palermo Younghoon Song
• This chapter describes the basic principles of high-speed electrical and optical link design. It begins with an overview of the electrical circuits required to achieve high-
• PRBS generation and Return Loss simulation
• High Speed Link Simulator Stateye and Matlab
• EE689 Dr.Palermo Parallel PRBS generator and detector Parallel PRBS generation and detection circuit could be used in the project to detect the data
• 3.6 BACKPLANE TRANSCEIVERS 12Gb/s Duobinary Signaling
• Lab 2: Introduction to NI Elvis Environment. Objectives
• ECEN 689 High-Speed Links Circuits and Systems Lab2-Channel Models
• 2646 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 12, DECEMBER 2005 A 6.25-Gb/s Binary Transceiver in 0.13-m CMOS
• UNIVERSITY OF CALIFORNIA Los Angeles
• April 8, 2010 ECEN 689: High-Speed Links
• Electronics MOS Field-Effect Transistors
• DesignCon 2004 Channel Compliance Testing Utilizing
• ECEN 474: (Analog) VLSI Circuit Design MWF 9:10-10:00, ZACH 223B
• Using Clock Jitter Analysis to Reduce BER in
• Curriculum Vitae -Samuel Palermo 1 Samuel Palermo
• 1844 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS--I: REGULAR PAPERS, VOL. 56, NO. 8, AUGUST 2009 Simulation and Analysis of Random Decision Errors
• IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 31, NO. 4, NOVEMBER 2008 731 Controlled Intersymbol Interference Design
• A 10Gb/s Compact Low-Power Serial I/O with DFE-IIR Equalization
• ELEN-325. Introduction to Electronic Circuits: A design approach Jose Silva-Martinez Part II. Fundamentals of Circuit Analysis.
• Time Domain Reflectometry Theory
• BUILT-IN SELF TEST FOR PIPELINE ADC'S B. Provost, S. Palermo, E. Snchez-Sinencio, S.H.K. Embabi
• ECEN 689 High-Speed Links Circuits and Systems Lab1 -Transmission Lines
• ECEN689 Lab6 Prelab 1. Supply Noise
• IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 1, JANUARY 2010 235 Optical I/O Technology for Tera-Scale Computing
• IBM90nm FO4 Delay ECEN689 High Speed I/O
• 602 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 4, APRIL 2004 A 27-mW 3.6-Gb/s I/O Transceiver
• Laboratory Manual ELEN 474: VLSI Circuit Design
• 810 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS--II: EXPRESS BRIEFS, VOL. 56, NO. 11, NOVEMBER 2009 A Comparator With Reduced Delay Time in 65-nm
• 98 2008 IEEE International Solid-State Circuits Conference ISSCC 2008 / SESSION 5 / HIGH-SPEED TRANSCEIVERS / 5.1
• ECEN 689 High-Speed Links Circuits and Systems Lab5 Equalization Circuits
• HSPICE MOSFET Models Manual Version X-2005.09, September 2005
• ECEN 325: Electronics TR 8:00-9:15, ZACH 223B (Lecture)
• Texas A&M University. All rights reserved. 1 Laboratory Manual
• Sam Palermo Analog & Mixed-Signal Center
• Sam Palermo Analog & Mixed-Signal Center
• If you would like to cite any of this material, please use the following: S. Palermo, "CMOS Nanoelectronics Analog and RF VLSI Circuits. Chapter 9: High-Speed
• ECEN 689-605: Special Topics in High-Speed Links Circuits & Systems Spring 2012