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Olukotun, Kunle - Department of Computer Science, Stanford University
710272-1732/00/$10.00 2000 IEEE The Hydra chip multiprocessor
Rationale, Design and Performance of the Hydra Multiprocessor
0018-9162/96/$10.00 1997 IEEE September 1997 79 A Single-Chip
The Software Stack for Transactional Memory Challenges and Opportunities
Exposing Speculative Thread Parallelism in SPEC2000 Manohar K. Prabhu
The quest to automatically paral-lelize general-purpose programs is a long-
The Jrpm System for Dynamically Parallelizing Java Programs Michael K. Chen
TEST: A Tracer for Extracting Speculative Threads Michael K. Chen
Hydra is a chip multiprocessor (CMP) with integrated support for thread-level speculation. Thread-level speculation provides a way
Method speculation of object-oriented programs attempts to exploit method-level parallelism (MLP) by executing sequen-
Thread-level speculation is a technique that enables parallel execu-tion of sequential applications on a multiprocessor. This paper
Software and Hardware for Exploiting Speculative Parallelism with a Multiprocessor
In the future, advanced integrated circuit processing and packaging technology will allow for several design options for multiprocessor
Using Thread-Level Speculation to Simplify Manual Parallelization
56 IEEE Spectrum | January 2005 | NA ROBERTHOUSER
A Single Chip Multiprocessor Integrated with DRAM Tadaaki Yamauchi1
26 September 2005 QUEUE rants: feedback@acmqueue.com The Future of
CONSIDERATIONS IN THE DESIGN OF HYDRA
