Pedram, Massoud - Department of Electrical Engineering, University of Southern California

• Module Assignment for Low Power Jui-Ming Chang and Massoud Pedram
• Abstract--This paper presents an intra-process dynamic voltage and frequency scaling (DVFS) technique targeted toward
• To appear in IEEE Transactions on VLSI Systems, 2011 Abstract--A tri-modal Multi-Threshold CMOS (MTCMOS) switch
• 1-xxxx-xxxx-4/10/$25.00 2010 IEEE 10th Int'l Symposium on Quality Electronic Design Minimizing the Power Consumption of a Chip Multiprocessor under
• Technology Mapping and Packing for Coarse-Grained, Anti-Fuse Based FPGAs* Chang Woo Kang, Ali Iranli, and Massoud Pedram
• Hybrid Electrical Energy Storage Systems Massoud Pedram, Naehyuck Chang, Younghyun Kim, and Yanzhi Wang
• Statistical Timing Analysis of Flip-flops Considering Codependent Setup and Hold Times
• Design and Application of Multimodal Power Gating Structures Ehsan Pakbaznia and Massoud Pedram
• Dynamic Thermal Management for MPEG-2 Decoding Department of Electrical Engineering
• 1 | P a g e Abstract -A compact canonical form and a computational
• BEAM: Bus Encoding Based on Instruction-Set-Aware Memories
• High-Level Power Modeling, Estimation, and Optimization Enrico Macii Massoud Pedram Fabio Somenzi
• Accurate power estimation is essential for low power digital CMOS circuit design. Power dissipation is input pattern depend-
• Flow-Through-Queue based Power Management for Gigabit Ethernet Controller1
• Alphabetic Trees: Theory and Applications in Layout-Driven Logic Synthesis
• Optimal Selection of Voltage Regulator Modules in a Power Delivery Network
• Closing the Gap between Carry Select Adder and Ripple Carry Adder: A New Class of Low-power High-performance Adders
• Model Order Reduction of Large Circuits Using Balanced Truncation Payam Rabiei and Massoud Pedram
• University of Southern California 1 M. Pedram Nov 1997
• Apollo: Adaptive power optimization and Control for the land Warrior
• Maximum Power Estimation Using the Limiting Distributions of Extreme Order Statistics
• Balanced Truncation with Spectral Shaping for RLC Interconnects
• Power Minimization in IC Design: Principles and Applications
• Abstract In this paper we study tradeoffs between energy dissipation and delay in battery-powered digital CMOS designs. In
• Power Optimal MTCMOS Repeater Insertion for Global Buses
• To appear in IEEE Trans. on VLSI Systems, 2008 1 Abstract -This paper tackles the problem of dynamic power
• Clustering Techniques for Coarse-grained, Antifuse-based FPGAs Chang-woo Kang and Massoud Pedram
• Dynamic Power ... Abbasian et. al.1 Wavelet-Based Dynamic Power Management for
• Low Power Design Low Power Design
• A Robust Power Gating Structure and Power Mode Transition Strategy for MTCMOS Design
• ALBORZ: Address Level Bus Power Optimization Yazdan Aghaghiri
• IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATTION (VLSI) SYSTEMS, VOL. 5, NO. 4, DECEMBER 1997 1 Energy Minimization Using Multiple Supply
• We present an algorithm for solving a general min-cut, two-way partitioning problem subject to timing constraints. The
• Energy-Aware Networked Multimedia Systems: Modeling, Analysis and
• PROPAGATION ALGORITHM OF BEHAVIOR PROBABILITY IN POWER ESTIMATION BASED ON MULTIPLE-VALUED LOGIC
• OBDD-Based Function Decomposition: Algorithms and Implementation 1
• Gate Sizing with Controlled Displacement* Wei Chen, Cheng-Ta Hsieh, Massoud Pedram
• An Integrated Logical and Physical Design Flow for Deep Submicron Circuits
• An Energy-Aware Simulation Model and Transaction Protocol for Dynamic Workload Distribution in Mobile Ad Hoc Networks1
• Forecasting-based Dynamic Virtual Channels Allocation for Power Optimization of Network-on-Chips
• Analysis and Optimization of Static Power Considering Transition Dependency of Leakage Current in VLSI Circuits
• Gate Delay Calculation Considering the Crosstalk Capacitances Soroush Abbaspour and Massoud Pedram
• Low Power Techniques for Address Encoding and Memory Allocation Wei-Chung Cheng and Massoud Pedram
• Stochastic Sequential Machines Synthesis with Application to Constrained Sequence Generation
• Reducing the Sub-threshold and Gate-tunneling Leakage of SRAM Cells using Dual-Vt and Dual-Tox Assignment
• Interconnect Design Methods for Memory Design* Abstract -This paper presents a solution to the problem of
• Battery-Aware Power Management Based on Markovian Decision
• Power Minimization in a Backlit TFT-LCD Display by Concurrent Brightness and Contrast Scaling
• Model-Order Reduction Using Variational Balanced Truncation with
• Low Power Design Low PowerLow Power
• Abstract-This paper is concerned with the analysis and opti-mization of the ground bounce in digital CMOS circuits.
• Factored Edge-Valued Binary Decision Diagrams 1 Paul Tafertshofer and Massoud Pedram
• Analysis of Power-Clocked CMOS with Application to the Design of Energy-Recovery Circuits*
• To appear in IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems 1 Abstract--Design of a suitable power gating (e.g., multi-
• Analysis and Optimization of Sequential Circuit Elements to Combat Single-Event Timing Upsets
• Revision of Manuscript 42: Gate-level Power Estimation Using Tagged Probabilistic
• System-Level Power Management: An Overview Ali Iranli and Massoud Pedram
• Constructing Minimal Spanning/Steiner Trees with Bounded Path Length
• Post Sign-off Leakage Power Optimization Hamed Abrishami
• Dynamic Voltage and Frequency Scaling Under a Precise Energy Model Considering Variable and Fixed
• Gate Delay Calculation Considering the Crosstalk Capacitances
• To appear in IEEE Transactions on VLSI Systems 1 Design and Analysis of Two Low Power SRAM
• Durability of Wireless Networks of Battery-Powered Devices Maryam Soltan and Massoud Pedram
• Energy-Aware MPEG-4 FGS Streaming Kihwan Choi, Member IEEE, Kwanho Kim, Member IEEE, and Massoud Pedram, Fellow IEEE
• Memory Bus Encoding for Low Power: A Tutorial1 Wei-Chung Cheng and Massoud Pedram
• Calculating the Effective Capacitance for the RC Interconnect in VDSM Technologies
• Chromatic Encoding: a Low Power Encoding Technique for Digital Visual Interface
• Adaptive Models for Input Data Compaction for Power Simulators* Radu Marculescu, Diana Marculescu, Massoud Pedram
• `TVLSI-00029-2003.R1 An Analytical Model for Predicting the Remaining Battery
• Continuous Frequency Adjustment Technique Based on Dynamic Workload Prediction1
• Low Power Address Bus Encoding Massoud Pedram
• Submitted to IEEE Design and Test of Computers, Special Issue on Embedded Systems for Real-Time Multimedia 1 A Backlight Power Management Framework for
• DTM: Dynamic Tone Mapping for Backlight Scaling University of Southern California
• An Analytical Model for Predicting the Remaining Battery Capacity of Lithium-Ion Batteries
• Composite Sequence Compaction for Finite-State Machines Using Block Entropy and High-Order Markov Models*
• Determining the Optimal Timeout Values for a Power-Managed System based on the Theory of Markovian Processes: Offline and Online
• Low Power State Assignment Targeting Two-and Multi-level Logic Implementations
• CGTA: Current Gain-based Timing Analysis for Logic Cells Shahin Nazarian Massoud Pedram Emre Tuncer Tao Lin
• Irredundant Address Bus Encoding for Low Yazdan Aghaghiri
• ASP-DAC 2003 1 LowLow--power Synthesis ofpower Synthesis of FSMsFSMs withwith
• Statistical Logic Cell Delay Analysis Using a Current-based Model
• Battery-Supercapacitor Hybrid System for High-Rate Pulsed Load Applications
• Dynamic Voltage and Frequency Scaling based on Workload Decomposition*
• BEAR-FP: A Robust Framework for Floorplanning Massoud Pedram Ernest S. Kuh
• A CLASS OF IRREDUNDANT ENCODING TECHNIQUES FOR REDUCING BUS YAZDAN AGHAGHIRI
• 1-xxxx-xxxx-4/10/$25.00 2010 IEEE 11th Int'l Symposium on Quality Electronic Design Multi-Objective Optimization Techniques for VLSI Circuits
• Power Estimation and Optimization at the Logic Massoud Pedram
• Accurate Modeling and Calculation of Delay and Energy Overheads of Dynamic Voltage Scaling in Modern
• Stochastic Modeling of a Power-Managed System: Construction and Optimization
• Dynamic Voltage Scaling of OLED Displays Donghwa Shin, Younghyun Kim,
• An Energy-Aware Simulation Model and Transaction Protocol
• Fine-Grained Dynamic Voltage and Frequency Scaling for Precise Energy and Performance Trade-off based on the Ratio of Off-chip Access to On-chip Computation
• Frame-Based Dynamic Voltage and Frequency Scaling
• 1-xxxx-xxxx-4/10/$25.00 2010 IEEE 11th Int'l Symposium on Quality Electronic Design Multi-Corner, Energy-Delay Optimized, NBTI-Aware Flip-Flop Design
• A Unified Framework for System-level Design: Modeling and Performance Optimization of Scalable Networking Systems
• Abstract--This paper presents an irredundant encoding technique to minimize the switching activity on a multiplexed
• Effective Capacitance for the RC Interconnect in VDSM Technologies
• Information Theoretic Measures for Power Analysis1 Diana Marculescu, Radu Marculescu, Massoud Pedram
• EZ Encoding: A Class of Irredundant Low Power Codes for Data Address and Multiplexed Address Buses
• OS-Directed Power Management for Mobile Electronic Systems Qinru Qiu, Qing Wu and Massoud Pedram
• Energy-Aware MPEG-4 FGS EnergyEnergy--Aware MPEGAware MPEG--4 FGS4 FGS
• Layout Driven Logic Restructuring/Decomposition Massoud Pedram and Narasimha Bhat
• An Empirical Study of Crosstalk in VDSM Technologies Shahin Nazarian, Massoud Pedram Emre Tuncer
• Fanout Optimization under a Submicron Transistor-Level Delay Model
• Power Minimization Techniques at the RT-Level and Afshin Abdollahi and Massoud Pedram
• Advanced Power Estimation Techniques MASSOUD PEDRAM
• EDGE VALUED BINARY DECISION K. Vrudhula and Massoud Pedram and Yung-Te
• To appear in IEEE Transactions on VLSI Systems 1 Dynamic Voltage and Frequency Scheduling
• Abstract -This paper presents a supervised learning based power management framework for a multi-processor system, where a
• Journal of Low Power Electronics, Vol. 6, N 2, August 2010 A Markovian Decision-based Approach for Extending
• A High-Efficiency, Auto Mode-Hop, Variable-Voltage, Ripple Control Buck Converter
• Forecasting-Based Dynamic Virtual Channel Management for Power Reduction in Network-on-Chips
• To appear in Int'l Journal of Low Power Electronics, American Scientific Publishers, 2009 NED: A Novel Synthetic Traffic Pattern for
• To appear in IEEE Trans. on VLSI Systems, 2008 1 Abstract -This paper presents an energy-efficient packet
• To appear in Canadian Journal of Electrical and Computer Engineering Two High Performance and Low Power Serial
• To appear in IEEE Trans. on VLSI Systems, 2008 1 BZ-FAD: A Low-Power Low-Area Multiplier
• Chang Woo Kang, Ali Iranli, and Massoud Pedram University of Southern California
• Fast Interconnect and Gate Timing Analysis for Performance Optimization Soroush Abbaspour, Massoud Pedram, Amir Ajami, Chandramouli Kashyap
• Cycle-based Decomposition of Markov Chains with Applications to Low Power Synthesis and Sequence
• A Leakage-aware Low Power Technology Mapping Algorithm Considering the Hot-Carrier Effect1
• Low Power RT-Level Synthesis Techniques: A Tutorial Massoud Pedram and Afshin Abdollahi
• Modeling and Analysis of Non-Uniform Substrate Temperature Effects in High Performance VLSI
• Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits
• Capacitive Coupling Noise in High-Speed VLSI Circuits
• Abstract -In this paper, new formulations for the energy dissipation of lossy transmission lines driven by CMOS inverters are provided, and a new performance metric for the energy optimization under the delay
• Transition Reduction in Memory Buses Using Sector-based Encoding Techniques
• Leakage Current Reduction in CMOS VLSI Circuits by Input Vector Afshin Abdollahi
• Multi. Val. Logic., 2000, Vol. 00, pp. 1 17 # 2000 OPA (Overseas Publishers Association) N.V. Reprints available directly from the publisher Published by license under
• Revised Manuscript Estimation of Peak Power Dissipation in VLSI Circuits
• Department of Electronic Engineering, Zhejiang University, Hangzhou, China. Department of Electrical Engineering-Systems, University of Southern California, Los Angeles, USA.
• GatedClockRoutingforLowPower MicroprocessorDesign
• Improving the E ciency of Monte Carlo Power Estimation Chih-Shun Ding Cheng-Ta Hsieh Massoud Pedram
• Prof. Wu is with the Institute of Circuits and Systems, Ningbo University, Ningbo 315211, China Prof. Pedram is with the Department of Electrical Engineering Systems, University of Southern California, Los
• S1NBS/BR(e) /* point c becomes
• Submitted to TVLSI -Special Issue on Low-Power Design Theoretical Bounds for Switching Activity Analysis in Finite-State Machines
• Simultaneous Gate Sizing and Placement Wei Chen, Cheng-Ta Hsieh, Massoud Pedram
• Project supported by NNSF(No.69573008) of China and NSF Grant (No.53-4503-2694) of USA. Bounded Algebra and Current-Mode Digital Circuits
• *Supported by NNSF of China (No.69573008) and DARPA under contract # F33615-95-C-1627. A SYNTHESIS METHODOLOGY FOR ECL CIRCUITS
• *Supported by the NSF of China (#69773034) and DARPA under contract #F33615-95-C-1627. SYNCHRONOUS DERIVED CLOCK AND
• Micro-Processor Power Estimation Using Profile-Driven Program Synthesis AUTHOR LIST
• Submited to Trans. on CAD Revised Version Probabilistic Modeling of Dependencies During Switching Activity Analysis
• State Assignment based on Two-dimensional Placement and Hypercube Mapping
• Vector Compaction Using Dynamic Markov Models* Radu Marculescu, Diana Marculescu, Massoud Pedram
• A New Description of MOS Circuits at Switch-Level With Applications
• Combining Technology Mapping with Layout Massoud Pedram
• Power Optimization in VLSI Layout: A Massoud Pedram
• Information Theoretic Measures for Power Analysis1 Diana Marculescu, Radu Marculescu, Massoud Pedram
• Edge-Valued Binary-Decision Diagrams Yung-Te Lai, Massoud Pedram Sarma B.K. Vrudhula
• Computing the Area versus Delay Trade-off Curves in Technology Mapping 1
• Power Estimation Methods for Sequential Logic Chi-Ying Tsui Jose Monteiro Massoud Pedram Srinivas Devadas
• Power Conscious CAD Tools and Methodologies: A Perspective
• EVBDD-based Algorithms for Integer Linear Programming, Spectral Transformation, and
• Multi-dimensional SLA-based Resource Allocation for Multi-tier Cloud Computing Systems
• 978-3-9810801-7-9/DATE11/2011 EDAA Timing Variation-Aware Custom Instruction
• 978-3-9810801-7-9/DATE11/2011 EDAA Variation Aware Dynamic Power Management for
• Power and Performance Modeling in a Virtualized Server System Massoud Pedram and Inkwon Hwang
• Deterministic Clock Gating to Eliminate Wasteful Activity due to Wrong-path Instructions in Out-of-Order Superscalar Processors1
• Minimizing Data Center Cooling and Server Power Costs Ehsan Pakbaznia and Massoud Pedram
• Minimizing the Energy Cost of Throughput in a Linear Pipeline by Opportunistic Time Borrowing
• Abstract -A gate level probabilistic error propagation model is presented which takes as input the Boolean function of the gate,
• A Mathematical Solution to Power Optimal Pipeline Design by Utilizing Soft Edge Flip-Flops
• In-Order Pulsed Charge Recycling in Off-Chip Data Buses Kimish Patel, Wonbok Lee, Massoud Pedram
• A Stochastic Local Hot Spot Alerting Technique1 Hwisung Jung Massoud Pedram
• Sizing and Placement of Charge Recycling Transistors in MTCMOS Circuits
• Minimizing Power Dissipation during Write Operation to Register Files
• Active Bank Switching for Temperature Control of the Register File in a Microprocessor
• A Current-based Method for Short Circuit Power Calculation under Noisy Input Waveforms*
• Lifetime-Aware Hierarchical Wireless Sensor Network Architecture with Mobile Overlays
• Stochastic Dynamic Thermal Management: A Markovian Decision-based Approach
• Charge Recycling in MTCMOS Circuits: Concept and Ehsan Pakbaznia
• Backlight Dimming in Power-Aware Mobile Displays University of Southern California
• Low-Power Clustering with Minimum Logic Replication for Coarse-grained, Antifuse based FPGAs
• SACI: Statistical Static Timing Analysis of Coupled Interconnects
• Crosstalk Analysis in Nanometer Technologies Shahin Nazarian Ali Iranli Massoud Pedram
• Low-leakage SRAM Design with Dual Vt Transistors Behnam Amelifard
• Analysis and Synthesis of Quantum Circuits by Using Quantum Decision Diagrams1 Afshin Abdollahi Massoud Pedram
• Non-Gaussian Statistical Interconnect Timing Analysis Soroush Abbaspour, Hanif Fatemi, Massoud Pedram
• Cell Delay Analysis Based on Rate-of-Current Change Shahin Nazarian Massoud Pedram
• Timing-Driven Placement Based on Monotone Cell Ordering Constraints Chanseok Hwang
• Parameterized Block-Based Non-Gaussian Statistical Gate Timing Analysis
• VGTA: Variation_Aware Gate Timing Analysis Soroush Abbaspour, Hanif Fatemi, Massoud Pedram
• Low-Power Fanout Optimization Using Multiple Threshold Voltage Inverters
• Hierarchical Power Management with Application to Scheduling University of Southern California
• An Effective Power Mode Transition Technique in MTCMOS Circuits Afshin Abdollahi
• VITA: Variation-Aware Interconnect Timing Analysis for Symmetric and Skewed Sources of Variation Considering
• Sensitivity-Based Gate Delay Propagation in Static Timing Analysis Shahin Nazarian, Massoud Pedram Emre Tuncer, Tao Lin
• HEBS: Histogram Equalization for Backlight Scaling Ali Iranli, Hanif Fatemi, Massoud Pedram
• PMP: Performance-Driven Multilevel Partitioning by Aggregating the Preferred Signal Directions of I/O Conduits
• Off-chip Latency-Driven Dynamic Voltage and Frequency Scaling for an MPEG Decoding
• LIFETIME-AWARE MULTICAST ROUTING IN WIRELESS AD HOC Morteza Maleki and Massoud Pedram
• Power Minimization in a Backlit TFT-LCD Display by Concurrent Brightness and Contrast Scaling
• A Game Theoretic Approach to Low Energy Wireless Video Ali Iranli, Kihwan Choi, and Massoud Pedram
• A Compressed Frame Buffer to Reduce Display Power Consumption in Mobile Systems School of CSE
• Abstract-This paper presents a detailed empirical study and analyti-cal derivation of voltage wave-form and energy dissipation of global
• This research was supported in part by DARPA PAC/C program under contract DAAB07-02-C-P302 and by NSF under grant no. 9988441.
• BEAM: Bus Encoding Based on Instruction-Set-Aware Memories Yazdan Aghaghiri
• Technology Mapping for Low Leakage Power and High Speed with Hot-Carrier Effect Consideration1
• This paper presents a state assignment technique to reduce dynamic power consumption in finite state machines (FSM).
• Battery-Aware Power Management Based on Markovian Decision Processes
• Power-aware Source Routing Protocol for Mobile Ad Hoc Morteza Maleki, Karthik Dantu, and Massoud Pedram
• Abstract -In this paper, new formulations for the energy dissipation of lossy transmission lines driven by CMOS inverters are provided, and a new
• Buffered Routing Tree Construction Under Buffer Placement Interconnect delay has become a critical factor in
• Abstract -This work presents accurate closed-form expressions for the interconnect energy dissipation in high-speed ULSI circuits.
• Software-Only Bus Encoding Techniques for an Embedded System Wei-Chung Cheng, Jian-Lin Liang and Massoud Pedram
• Analysis of Substrate Thermal Gradient Effects on Optimal Buffer Insertion Amir H. Ajami, Kaustav Banerjee*
• Abstract -This paper presents a spectrally-weighted balanced trun-cation technique for RLC interconnects, when the interconnect circuit
• Non-Uniform Chip-Temperature Dependent Signal Integrity Amir H. Ajami, Kaustav Banerjee*
• Dynamic Power Management in a Mobile Multimedia System with Guaranteed Quality-of-Service
• Analysis of Non-Uniform Temperature-Dependent Interconnect Performance in High Performance ICs
• Abstract In many applications, it is important to know how power is consumed while software is being executed on the target
• Power Optimization and Management in Embedded Systems1 Massoud Pedram
• Abstract-This paper presents a numerically stable and efficient algorithm for model reduction of large RLC net-
• Abstract--This paper is concerned with the analysis and optimization of the ground bounce in digital CMOS circuits. First, an analytical
• Power-optimal Encoding for DRAM Address Bus Wei-Chung Cheng and Massoud Pedram
• Low Power Sequential Circuit Design by Using Priority Encoding and Clock Gating*
• This paper presents a partitioning-based, timing-driven placement algorithm. The partitioning step itself is timing-driven and based on
• Dynamic Power Management of Complex Systems Using Generalized Stochastic Petri Nets*
• Massoud Pedram Qing Wu Department of Electrical Engineering-Systems
• Qinru Qiu and Massoud Pedram Department of Electrical Engineering-Systems
• Massoud Pedram1 , Chi-Ying Tsui2
• ABSTRACT -This paper presents an optimal algorithm for solving the problem of simultaneous fanout optimiza-
• ABSTRACT -This paper presents an integrated design flow which combines floorplanning, technology mapping, and
• Calculation of Ramp Response of Lossy Transmission Lines Using Two-port Network Functions
• Gated Clock Routing Minimizing the Switched Capacitance* Jaewon Oh and Massoud Pedram
• ABSTRACT -This paper presents a new design flow, FPD-SiMPA, and a set of techniques for synthesizing high-perfor-
• An Exact Solution to Simultaneous Technology Mapping and Linear Placement Problem*
• Sequence Compaction for Probabilistic Analysis of Finite-State Machines* Diana Marculescu, Radu Marculescu, Massoud Pedram
• High-Level Power Modeling, Estimation, and Optimization Enrico Macii Massoud Pedram Fabio Somenzi
• Hierarchical Sequence Compaction for Power Estimation* Radu Marculescu, Diana Marculescu, Massoud Pedram
• Stochastic Sequential Machine Synthesis Targeting Constrained Sequence Generation*
• Efficient Power Estimation for Highly Correlated Input Streams* Radu Marculescu, Diana Marculescu, Massoud Pedram
• Register Allocation and Binding for Low Power Jui-Ming Chang and Massoud Pedram
• times. Although the incremental approach with spatiotemporal correlation provide roughly the same gain in
• 1 / 0 Pad Assignment based on the Circuit Structure* Massoud Pedram, Kamal Chaudhary, Ernest S. Kuh
• Accurate Prediction of Physical Design Characteristics forI Random Logic
• Energy-Aware Distributed Multimedia Massoud Pedram
• Review of the Apollo Testbed Project Massoud Pedram
• PrecomputationPrecomputation--based Guarding forbased Guarding for Dynamic and Leakage Power ReductionDynamic and Leakage Power Reduction
• Afshin Abdollahi University of
• Dynamic Power Management in a Mobile Multimedia System with
• Dynamic Voltage and Frequency Scaling Under a Precise Energy Model Considering
• Fine-Grained Dynamic Voltage and Frequency Scaling for Precise Energy and Performance
• Extending the Lifetime of a Network ofExtending the Lifetime of a Network of BatteryBattery--Powered Mobile Devices byPowered Mobile Devices by
• Concurrent Contrast and Brightness Scaling for a Backlit TFT-LCD Display
• Interconnect Design MethodsInterconnect Design Methods for Memoryfor Memory
• Technology Mapping and PackingTechnology Mapping and Packing for Coarsefor Coarse--grained, Antigrained, Anti--fuse Basedfuse Based
• Optimizing the Energy-Delay-Ringing Product in On-Chip CMOS Line Drivers
• Concurrent Extraction of Partial Kernels with Timing Consideration
• Analysis of Jitter due to Power-Supply Noise in
• Analysis and Optimization of Power/Ground Bounce in Digital CMOS Circuits
• Memory Bus Encoding For Low Power 1 Memory Bus Encoding for
• Analysis of Substrate Thermal Gradient Effects on Optimal Buffer
• Analysis of Non-Uniform Temperature-Dependent Interconnect
• Microprocessor Power AnalysisMicroprocessor Power Analysis by Labeled Simulationby Labeled Simulation
• Architectural Power Optimization by Bus Splitting
• Post-Layout Timing-Driven Cell Placement Using an Accurate Net Length Model with
• Performance-Driven Concurrent Placement and Gate Sizing for
• Battery-Powered Digital CMOS Massoud Pedram
• Gate Sizing and Replication to Minimize the Effects of Virtual Ground Parasitic Resistances in MTCMOS Designs
• Energy-Aware Task Scheduling and Dynamic Voltage Scaling in a Real-Time System
• Trace-Driven Steady-State Probability Estimation in FSMs with Application to Power Estimation*
• STAX: Statistical Crosstalk Target Set Compaction Shahin Nazarian, Massoud Pedram, Sandeep K. Gupta, Melvin A. Breuer
• Abstract -This paper introduces techniques for power efficient design of power delivery network in multiple voltage-island
• Floorplanning with Pin Assignment* Massoud Pedram Malgorzata Marek-Sadowska Emest S. Kuh
• Maximum Power Transfer Tracking for a Photovoltaic-Supercapacitor Energy System
• PROBABILISTIC ERROR PROPAGATION IN A LOGIC CIRCUIT USING THE BOOLEAN
• Effects of Non-uniform Substrate Temperature on the Clock Signal Integrity in High Performance Designs*
• Runtime Mechanisms for Leakage Current Reduction in CMOS VLSI Circuits1, 2
• NBTI-Aware Flip-Flop Characterization and Design Hamed Abrishami, Safar Hatami, Behnam Amelifard, Massoud Pedram
• This paper presents LEOPARD, a Logical Effort-based fanout OPtimizer for ARea and Delay, which relies on the availability of a (near) continuous size buffer library. Based on the concept of
• A Fast INC-XOR Codec for Low Power Address Buses H. Parandeh-Afshar1,*
• Simultaneous Gate Sizing and Fanout Optimization
• To appear in Encyclopedia of Computer Science and Technology, 1995 Design Technologies for Low Power VLSI
• BSTRACT -This ergy consumption
• Cycle-Accurate Macro-Models for RT-Level Power Analysis* Qinru Qiu, Qing Wu, Massoud Pedram
• Precomputation-based Guarding for Dynamic and Leakage Power Reduction
• Lifetime Prediction Routing in Mobile Ad Hoc Networks Morteza Maleki, Karthik Dantu, and Massoud Pedram
• Energy Minimization Using Multiple Supply Voltages Jui-Ming Chang and Massoud Pedram
• Resilient Dynamic Power Management under Uncertainty Hwisung Jung and Massoud Pedram
• Sleep Transistor Distribution in Row-Based MTCMOS Designs Chanseok Hwang1
• Power-Aware Scheduling and Dynamic Voltage Setting for Tasks Running on a Hard Real-Time System1
• Parameterized Block-Based Non-Gaussian Variational Gate Timing Analysis
• A Game Theoretic Approach to Dynamic Energy Minimization in Wireless Transceivers
• Frame-Based Dynamic Voltage and Frequency Scaling for an MPEG Player
• StochasticStochasticStochasticStochasticStochasticStochasticStochasticStochastic Modeling of a PowerModeling of a PowerModeling of a PowerModeling of a PowerModeling of a PowerModeling of a PowerModeling of a PowerModeling of a Power--------Managed System
• Dynamic Voltage and Frequency Scaling based on Workload Decomposition
• Accurate and Efficient Power Simulation Strategy by Compacting the Input Vector Set
• Improving Sampling E ciency for System Level Power Estimation Chih-Shun Ding Cheng-Ta Hsieh Massoud Pedram
• Concurrent Logic Restructuring and Placement for Timing Closure Jinan Lou, Wei Chen, Massoud Pedram
• Characterization and Design of Sequential Circuit Elements to Combat Soft Error1
• Efficient Compression and Handling of Current Source Model Library Waveforms
• IEICE Electronics Express, Vol.* No.*,*-* IEICE 2008
• Post-Layout Timing-Driven Cell Placement Using an Accurate Net Length Model with Movable Steiner Points*
• TRANSMITTANCE SCALING FOR REDUCING POWER DISSIPATION OF A BACKLIT TFT-LCD
• Deriving a Near-optimal Power Management Policy Using Model-Free Reinforcement Learning and Bayesian Classification
• Logical-Physical Co-design for Deep Submicron Circuits: Challenges and Solutions
• Strati ed Random Sampling for Power Estimation Chih-Shun Ding Qing Wu Cheng-Ta Hsieh Massoud Pedram
• Frame-Based Dynamic Voltage and Frequency Scaling for a MPEG Decoder
• Reducing Transitions on Memory Buses Using Sector-based Encoding Technique
• Model Order Reduction of Large Circuits Using Balanced Truncation
• TFA: A Threshold-Based Filtering Algorithm for Propagation Delay and Output Slew Calculation of High-Speed VLSI Interconnects
• Power Simulation and Estimation in VLSI Circuits Massoud Pedram
• 50. F. Najm, R. Burch, P. Yang, I. Hajj. "Probabilistic simulation for reliability analysis of CMOS VLSI circuits." IEEE Transactions on CAD, 1990, volume 9, pages 439-450.
• Temperature-Aware Dynamic Resource Provisioning in a Power-Optimized Datacenter
• Abstract-Phase-locked loops (PLL) in RF and mixed signal VLSI circuits experience supply noise which translates to a timing jitter.
• ISPD 2001ISPD 2001 Analysis and Optimization of
• Lifetime-Aware Intrusion Detection under Safeguarding Constraints
• Effects of NonEffects of Non--Uniform SubstrateUniform Substrate Temperature on the Clock SignalTemperature on the Clock Signal
• Modulation-Aware Energy Balancing in Hierarchical Wireless Sensor Networks1
• A New Design for Double Edge Triggered Flip-flops* Massoud Pedram, Qing Wu
• Architectural Energy Optimization by Bus Splitting Cheng-Ta Hsieh and Massoud Pedram
• An Empirical Investigation of Mesh and Torus NoC Topologies Under Different Routing Algorithms and Traffic Models
• Scaling Analysis of On-Chip Power Grid Voltage Variations in Nanometer Scale ULSI
• Energy-Aware MPEG-4 FGS Streaming Kihwan Choi1
• ENERGY EFFICIENT STRATEGIES FOR DEPLOYMENT OF A TWO-LEVEL WIRELESS SENSOR NETWORK
• Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are
• Buffered Routing Tree Construction under Buffer
• Massoud Pedram and Qing Wu Department of Electrical Engineering-Systems
• Maximizing Profit in Cloud Computing System via Resource Allocation Hadi Goudarzi and Massoud Pedram
• Clock-Gating and Its Application to Low Power Design of Sequential Circuits Department of Electrical Engineering-Systems, University of Southern California
• Interconnection Analysis for Standard Cell Layouts Massoud Pedram Bryan T. Preas
• Chromatic Encoding: a Low Power Encoding Technique for Digital Visual
• Thermal Modeling, Analysis and Management in VLSI Circuits: Principles and Methods
• Qing Wu, Member, IEEE, Qinru Qiu, Massoud Pedram, Member, IEEE, and Chih-Shun Ding, Member, IEEE Abstract In this paper we present a methodology and
• Off-chip Latency-Driven Dynamic Voltage and Frequency Scaling for
• Abstract--This paper presents a solution to the problem of per-formance-driven buffered routing tree generation for VLSI cir-
• Afshin Abdollahi University of
• Multi-pad Power/Ground Network Design for Uniform Distribution of Ground Bounce*
• Abstract--Scaling the minimum feature size of VLSI circuits to sub-quar-ter micron and the clock frequency to 2GHz has caused the crosstalk noise
• Codex-dp: Co-design of Communicating Systems Using Dynamic Programming
• Abstract-CMOS Phase-locked loops (PLL) are ubiquitous in RF and mixed-signal integrated circuits. A general comprehensive stochastic
• Simultaneous Gate Sizing and Fanout Optimization , Cheng-Ta Hsieh+
• IEEE PROC. OF INFORMATION PROCESSING IN SENSOR NETWORKS, APRIL 2005 QoM and Lifetime-constrained Random
• ABSTRACT -This paper presents a solution to the problem of performance-driven buffered routing tree generation in elec-
• ASP-DAC 2003 1 Technology Mapping for Low Leakage Power and HighTechnology Mapping for Low Leakage Power and High
• Leakage Power Modelling andLeakage Power Modelling and MinimizationMinimization
• To appear in IEEE Transactions on VLSI Systems Accurate Timing and Noise Analysis of
• An Interleaved Dual-Battery Power Supply for Battery-Operated Electronics
• HVS-Aware Dynamic Backlight Scaling in TFT LCD's Ali Iranli, Wonbok Lee, and Massoud Pedram
• CAD for Low Power: Status and Promising Directions Massoud Pedram
• Architectural Power Optimization by Bus Splitting Cheng-Ta Hsieh and Massoud Pedram
• To appear in IEEE Transactions on VLSI Systems Statistical Design Optimization of FinFET
• Abstract--This paper addresses the problem of low-power fanout optimization for near-continuous size inverter libraries.
• Sim: A Fast Micro-Architecture Simulator Based on Basic Block Characterization
• Abstract --Aggressive CMOS scaling results in low threshold voltage and thin oxide thickness for transistors manufactured in
• Abstract--In this paper, we present a dynamic thermal management (DTM) algorithm based on (i) accurate estimation of
• To appear in IEEE Trans. on Computer Aided Design of VLSI Circuits and Systems 1 Abstract--in this paper we present and solve the problem of
• We present LEOPARD, a fanout optimization algorithm based on the effort delay model for near-continuous size buffer
• Design of an Efficient Power Delivery Network in an SoC to Enable Dynamic Power Management
• Before Mapping After Mapping Area Power Area Delay Power
• Low Power CAD: Trends and Challenges Massoud Pedram
• A Current Source Model for CMOS Logic Cells Considering Multiple Input Switching and Stack Effect
• Minimizing the Electricity Bill of Cooperative Users under a Quasi-Dynamic Pricing Model
• Stochastic Modeling of a Thermally-Managed Multi-Core System
• High-Level Modeling Approach for Analyzing the Effects of Traffic Models on Power and Throughput in Mesh-based NoCs
• Battery-Aware Power Management Based on Markovian Decision Processes
• To appear in Int'l Journal of Electronics, 2010 Analysis of Crosstalk-Affected Propagation Delay of VLSI
• Extending the Lifetime of a Network of Battery-Powered Mobile Devices by Remote Processing: A Markovian Decision-based Approach
• Optimizing the Power Delivery Network in Dynamically Voltage Scaled Systems with Uncertain Power Mode Transition Times
• Efficient Representation, Stratification, and Compression of Variational CSM Library Waveforms Using Robust Principle Component Analysis
• Low-Power Design of Sequential Circuits Using a Quasi-Synchronous Derived Clock*
• Low-power Fanout Optimization Using MTCMOS and Multi-Vt Techniques
• Buffer Sizing for Minimum Energy-Delay Product by Using an Approximating Polynomial
• An efficient logic extraction algorithm, which is known as Fast Extract, was proposed by J. Rajski et al [1]. This
• Power-Aware Bus Encoding Techniques for I/O and Data Busses in an Embedded System
• Integrated Logical and Physical Design February 1998 Massoud Pedram 1
• A New Canonical Form for Fast Boolean Matching in Logic Synthesis and Verification
• To appear in Journal of the Society for Information Display, 2009 White LED Backlight Control for Motion Blur Reduction and
• Fanout Optimization under a Submicron Transistor-Level Delay Model
• *This project was sponsored in part by NNSF of China (Grant No.69973039) and NSF of USA (Grant No. Low Power DCVSL Circuits Employing AC Power Supply
• Theoretical Bounds for Switching Activity Analysis in Finite-State Machines* Diana Marculescu, Radu Marculescu, Massoud Pedram
• Interconnection Length Estimation for Optimized Standard Cell Layouts
• Layout Driven Technology Mapping Massoud Pedram and Narasimha Bhat
• Heterogeneous Modulation for Trading-off Energy Balancing with Bandwidth Efficiency in Hierarchical Sensor Networks
• Demand-Side Load Scheduling Incentivized by Dynamic Energy Hadi Goudarzi, Safar Hatami, and Massoud Pedram
• To appear in J Zhejiang Univ-Sci C (Comput & Electron) 1 An accurate analytical I-V model for sub-90-nm MOSFETs and its
• Charge Allocation for Hybrid Electrical Energy Storage Systems
• Charge Migration Efficiency Optimization in Hybrid Electrical Energy Storage (HEES) Systems
• Versatile High-Fidelity Photovoltaic Module Emulation Woojoo Lee, Younghyun Kim, Yanzhi Wang, Naehyuck Chang, Massoud Pedram,
• Concurrent Optimization of Consumer's Electrical Energy Bill and Producer's Power Generation Cost under a Dynamic Pricing
• Charge Replacement in Hybrid Electrical Energy Storage Systems Qing Xie, Yanzhi Wang, and Massoud Pedram Younghyun Kim, Donghwa Shin, and Naehyuck Chang
• Multiple-Source and Multiple-Destination Charge Migration in Hybrid Electrical Energy Storage Systems*
• 978-3-9810801-8-6/DATE12/2012 EDAA Minimizing the Latency of Quantum Circuits during
• This research is sponsored in part by a grant from the National Science Foundation, and by the Brain Korea 21 Project, IC Design