- String Matching on Multicontext FPGAs using Self-Reconfiguration
- A Methodology for Energy Efficient FPGA Designs Using Malleable Algorithms
- A Modeling and Exploration Framework for Mapping of Linear ArrayA Modeling and Exploration Framework for Mapping of Linear Array of Tasks onto Adaptive Computing Systemsof Tasks onto Adaptive Computing Systems Egor Andreev, Sumit Mohanty, Viktor K. Prasan
- Appears inthe Proceedings ofthe 11 InternationalConference on Paralleland DistributedComputingSystems (PDCS 1998)1
- Performance Optimization of a De-centralized Task Allocation Protocol via Bandwidth and Buffer Management
- Parallel Exact Inference on a CPU-GPGPU Heterogenous System Hyeran Jeon1
- High Performance Dictionary-Based String Matching for Deep Packet Inspection
- Memory-Efficient Pipelined Architecture for Large-Scale String Matching
- MIP Formulation for Robust Resource Allocation in Dynamic Real-Time Systems
- ArchitectureArchitecture--Independent Programming andIndependent Programming and SynthesisSynthesis of Networked Sensing Applicationsof Networked Sensing Applications Amol Bakshi, Viktor K. Prasanna
- Maximum Data Gathering in Networked Sensor Systems Bo Hong and Viktor K. Prasanna
- Constructing Topographic Maps in Networked Sensor Systems
- Scalable Packet Classification: Cutting or Merging? Weirong Jiang and Viktor K. Prasanna
- A Memory-Efficient and Modular Approach for String Matching on FPGAs Hoang Le and Viktor K. Prasanna
- A Methodology for Synthesis of Efficient Intrusion Detection Systems on FPGAs1 Zachary K. Baker and Viktor K. Prasanna
- Adaptive Sector Grouping to Reduce False Sharing in Distributed RAID
- A Memory-Balanced Linear Pipeline Architecture for Trie-based IP Lookup Weirong Jiang and Viktor K. Prasanna
- An Algorithm Designer's Workbench for Platform FPGAs
- Automated Incremental Design of Flexible Intrusion Detection Systems on Zachary K. Baker and Viktor K. Prasanna
- Bandwidth-Aware Resource Allocation for Heterogeneous Computing Systems to Maximize Throughput
- Fast and Accurate Traffic Matrix Measurement Using Adaptive Cardinality Counting
- DRIVE: An Interpretive Simulation and Visualization Environment for Dynamically Recon gurable Systems?
- A High-Performance and Energy-efficient Architecture for Floating-point based LU Decomposition on FPGAs
- UTILIZATION-BASED TECHNIQUES FOR STATICALLY MAPPING HETEROGENEOUS APPLICATIONS ONTO THE HIPER-D
- Scalable Parallel Implementation of Bayesian Network to Junction Tree Conversion for Exact Inference1
- Network Intrusion Detection and Alert Correlation Xiaosong Lou and Ying Chen, {xlou, chen2}@usc.edu
- Software Toolchain for Large-Scale RE-NFA Construction on FPGA
- Trust Overlay Networks for Global Reputation Aggregation in P2P Grid Computing*
- IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, VOL. 8, NO. 5, MAY 1997 521 An Optimal Multiplication Algorithm on
- Matrix Computations on Heterogeneous Reconfigurable Systems Ling Zhuo, Qingbo Wang, Viktor K. Prasanna
- Towards Practical Architectures for SRAM-based Pipelined Lookup Engines
- On-chip storage model Off-chip storage model
- Towards a Model-based Application Integration Framework for Smart Oilfields Cong Zhang, Amol Bakshi, Viktor Prasanna
- Towards Automatic Synthesis of a Class of Application-Specific Sensor Networks
- A Semantic Framework for Integrated Asset Management in Smart Oilfields Ramakrishna Soma
- Page 1 of 15 Trust Overlay Networks for Global Reputation
- Scalable Multi-Pipeline Architecture for High Performance Multi-Pattern String Matching
- COMA: A COoperative MAnagement Scheme for Energy Efficient Implementation of Real-Time Operating Systems on FPGA Based Soft Processors
- Parallel Exact Inference on the Cell Broadband Engine Processor$,$$
- Enabling Scope-Based Interactions in Sensor Network Macroprogramming
- A Methodology for Synthesis of Efficient Intrusion Detection Systems on FPGAs1 Zachary K. Baker and Viktor K. Prasanna
- Run-time Performance Optimization of an FPGA-based Deduction Engine for SAT Solvers?
- 2120 IEEE TRANSACTIONS ON SIGNAL PROCESSING, VOL. 52, NO. 7, JULY 2004 Dynamic Data Layouts for Cache-Conscious
- Parallel Exact Inference Yinglong Xia1
- Parallel Evidence Propagation on Multicore Yinglong Xia1
- Towards Green Routers: Depth-Bounded Multi-Pipeline Architecture for Power-Efficient IP Lookup
- High-Performance and Area-Efficient Reduction Circuits on FPGAs Ling Zhuo and Viktor K. Prasanna
- Beyond TCAMs: An SRAM-based Parallel Multi-Pipeline Architecture for Terabit IP Lookup
- Scalable and Modular Algorithms for Floating-Point Matrix Multiplication on Ling Zhuo and Viktor K. Prasanna
- Collusive Piracy Prevention in P2P Content Delivery Networks
- Selfish Grids: Game-Theoretic Modeling and NAS/PSA Benchmark Evaluation
- Hybrid Intrusion Detection with Weighted Signature Generation over Anomalous
- Automatic Synthesis of Efficient Intrusion Detection Systems on FPGAs1
- Journal of Grid Computing (2005) Springer 2005 DOI: 10.1007/s10723-005-5465-x
- Orthogonal Striping and Mirroring in Distributed RAID for I/O-Centric Cluster Computing
- Gossip-based Reputation Aggregation for Unstructured Peer-to-Peer Networks*
- Selfish Grid Computing: Game-Theoretic Modeling and NAS Performance Results
- Efficient Hardware Data Mining with the Apriori Algorithm on FPGAs1
- Fuzzy Trust Integration for Security Enforcement in Grid Computing*
- Trusted Grid Computing with Security Assurance and Resource Optimization
- Integrated Access Control and Intrusion Detection (IACID) Framework for Secure Grid Computing
- Automatic Synthesis of Efficient Intrusion Detection Systems on FPGAs
- Automatic Synthesis of Efficient Intrusion Detection Systems on FPGAs1
- Page 1 of 30 Trust-Preserving Overlays for Fast Reputation
- Adaptive Trust Negotiation and Access Control Tatyana Ryutov, Li Zhou, and Clifford Neuman Travis Leithead, Kent E. Seamons
- Non-Cooperative Grids: Game-Theoretic Modeling and Strategy Optimization
- A Scalable Set-Union Counting Approach to Pushing Back DDoS Attacks
- Head-Body Partitioned String Matching for Deep Packet Inspection
- Transitive Closure on the Cell Broadband Engine: A study on Self-Scheduling in a Multicore Processor
- A SRAM-based Architecture for Trie-based IP Lookup Using FPGA Hoang Le, Weirong Jiang, Viktor K. Prasanna
- A Hybrid Approach for Mapping Conjugate Gradient onto an FPGA-Augmented Reconfigurable Supercomputer
- A Hardware/Software Approach to Molecular Dynamics on Reconfigurable Ronald Scrofano
- Hindawi Publishing Corporation EURASIP Journal on Embedded Systems
- Cache-Friendly Implementations of Transitive Closure* Michael Penner and Viktor K Prasanna
- Genetic Programming using Self-Reconfigurable FPGAs
- A Unified Resource Scheduling Framework for Heterogeneous Computing Environments
- A FPGA-based Parallel Architecture for Scalable High-Speed Packet Classification Weirong Jiang
- Energy-Efficient Discrete Cosine Transform on Ronald Scrofano
- Cluster Comput (2006) 9:281296 DOI 10.1007/s10586-006-9741-8
- Worm Containment and DDoS Attack Defense Min Cai and Yu Chen, {mincai, cheny}@usc.edu
- PDPTA `02 International Conference 519 Greedy Heuristics for Resource Allocation in Dynamic Distributed
- Node Level Primitives for Parallel Exact Inference Yinglong Xia
- Optimizing System Life time for Data Gathering in Networked Sensor Systems Bo Hong and Viktor K. Prasanna
- Field-Split Parallel Architecture for High Performance Multi-Match Packet Classification Using FPGAs
- Parallel IP Lookup using Multiple SRAM-based Pipelines Weirong Jiang and Viktor K. Prasanna
- Automatic Synthesis of Efficient Intrusion Detection Systems on FPGAs
- Design Space Exploration Using Arithmetic-Level HardwareSoftware
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- Junction Tree Decomposition for Parallel Exact Inference Yinglong Xia1
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 16, NO. 2, FEBRUARY 2008 167 Area-Efficient Arithmetic Expression Evaluation
- Optimizing Graph Algorithms for Improved Cache Performance*+ Joon-Sang Park
- EXACT INFERENCE ON MANYCORE PROCESSORS USING POINTER JUMPING
- Distributed Evidence Propagation in Junction Trees Yinglong Xia
- Automation Framework for Large-Scale Regular Expression Matching on FPGA*
- IEEE TRANSACTIONS ON COMPUTERS 1 Energy-Efficient Task Mapping for Data-driven
- Architecture-Aware Data Structure Optimization for Green IP Lookup
- A Memory Efficient and Modular Approach for String Matching Hoang Le, Edward Yang, Viktor Prasanna
- Semantic Web Technologies for Event Modeling and Analysis: A Well Surveillance Use Case
- Provenance Collection in Reservoir Management Workflow Environments Fan Sun, Jing Zhao
- TOPOLOGICALLY ADAPTIVE PARALLEL BREADTH-FIRST SEARCH ON MULTICORE PROCESSORS
- A SCALABLE PIPELINE ARCHITECTURE FOR LINE RATE PACKET CLASSIFICATION ON FPGAS
- Hierarchical Dependency Graphs: Abstraction and Methodology for Mapping Systolic Array
- Automatic Construction of Large-Scale Regular Expression Matching Engines on FPGA
- Detecting Dirty Queries during Iterative Development of OWL based Applications
- Parallel Exact Inference on the Cell Broadband Engine Processor
- Compact Architecture for High-Throughput Regular Expression Matching on FPGA
- SCALABLE HIGH-THROUGHPUT SRAM-BASED ARCHITECTURE FOR IP-LOOKUP Hoang Le, Weirong Jiang, Viktor K. Prasanna
- Energy-Efficient Task Mapping for Data-Driven Sensor Network Macroprogramming
- Multi-Terabit IP Lookup Using Parallel Bidirectional Pipelines
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- Preliminary Investigation of Advanced Electrostatics in Molecular Dynamics on Reconfigurable Computers
- J. Parallel Distrib. Comput. 66 (2006) 566577 www.elsevier.com/locate/jpdc
- Copyright 2006, Society of Petroleum Engineers This paper was prepared for presentation at the 2006 SPE Intelligent Energy Conference and
- Copyright 2006, Society of Petroleum Engineers This paper was prepared for presentation at the 2006 SPE Intelligent Energy Conference and
- System-level Support for Macroprogramming of Networked Sensing Applications
- A Computationally-efficient Engine for Flexible Intrusion Detection1
- MATLAB/Simulink Based Hardware/Software Co-Simulation for Designing Using FPGA Configured Soft Processors
- An FPGA-Based Floating-Point Jacobi Iterative Solver Gerald R. Morris and Viktor K. Prasanna
- High Performance Linear Algebra Operations on Reconfigurable Systems
- Design Tradeoffs for BLAS Operations on Reconfigurable Hardware Ling Zhuo and Viktor K. Prasanna
- Designing Scalable FPGA-Based Reduction Circuits Using Pipelined Floating-Point Cores
- Supporting Topographic Queries in a Class of Networked Sensor Systems Mitali Singh and Viktor K. Prasanna
- Optimizing a Class of In-network Processing Applications in Networked Sensor Systems
- Rapid Energy Estimation of Computations on FPGA based Soft Processors
- Automatic Synthesis of Efficient Intrusion Detection Systems on FPGAs
- Energy-Efficient Communication in Multi-Channel Single-Hop Sensor Networks Amol Bakshi and Viktor K. Prasanna
- INTERNATIONAL JOURNAL OF EMBEDDED SYSTEMS, VOL. X, NO. XX, JUNE 2004 1 Energy-Efficient Hardware/Software Co-Synthesis
- If I am owner of current RP remove next packet from transmit queue
- Time and Area Efficient Pattern Matching on FPGAs Zachary K. Baker
- Bandwidth-Aware Resource Allocation for Computing Independent Tasks in Heterogeneous Computing Systems
- A Hierarchical Approach for Energy Efficient Application Design Using Heterogeneous Embedded Systems
- Collaborative and Distributed Computation in Mesh-like Wireless Sensor Arrays
- Tiling, Block Data Layout, and Memory Hierarchy Performance
- An Estimation and Simulation Framework for Energy Efficient Design using Platform FPGAs
- ENERGY-EFFICIENT AND PARAMETERIZED DESIGNS FOR FAST FOURIER TRANSFORM ON FPGAS
- Energy Efficiency of FPGAs and Programmable Processors for Matrix Multiplication
- Area and Time Efficient Implementations of Matrix Multiplication on FPGAs
- A Modular and Extensible Simulator for Performance Evaluation of Adaptive Applications in Heterogeneous Computing Environments
- Efficient Metacomputation using Self-Reconfiguration Reetinder Sidhu and Viktor K. Prasanna
- Analysis of Memory Hierarchy Performance of Block Data Layout Neungsoo Park, Bo Hong, and Viktor K. Prasanna
- A Model-based Methodology for Application Specific Energy Efficient Data Path Design using FPGAs
- Rapid Design Space Exploration of Heterogeneous Embedded Systems using Symbolic Search and
- CACHE CONSCIOUS WALSH-HADAMARD TRANSFORM Neungsoo Park and Viktor K. Prasanna
- FPGA-based Cryptography for Internet Security
- A Self-Reconfigurable Gate Array Architecture Reetinder Sidhu
- Dynamic Data Layouts for Cache-conscious Factorization of DFT Neungsoo Park, Dongsoo Kang, Kiran Bondalapati and Viktor K. Prasanna
- An Adaptive Cryptographic Engine for IPSec Architectures Andreas Dandalis and Viktor K. Prasanna
- E cient Matrix Multiplication Using Cache Conscious Data Neungsoo Park, Wenheng Liuy
- Efficient Collective Communication in Distributed Heterogeneous Systems Prashanth B. Bhat
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- Mapping Loops onto Recon gurable Architectures ? Kiran Bondalapati and Viktor K. Prasanna
- Appears in the Proceedings of the 7 IEEE Intnl. Symposium on High Performance Distributed Computing (HPDC 1998)1
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- Reconfigurable Architectures Workshop, International Parallel Processing Symposium, Reconfigurable Meshes: Theory and Practice 1
- Energy Efficient Adaptation of Multicast Protocols in Power Controlled Wireless Ad Hoc Networks
- A Hierarchical Model for Distributed Collaborative Computation in Wireless Sensor Networks
- Issues in Designing Middleware for Wireless Sensor Yang Yu, Bhaskar Krishnamachari, and Viktor K. Prasanna
- Energy-Balanced Task Allocation for Collaborative Processing in Wireless Sensor
- TIME AND ENERGY EFFICIENT VITERBI DECODING USING FPGAS Jingzhao Ou, Viktor K. Prasanna
- Data Gathering with Tunable Compression in Sensor Networks
- Run-Time Adaptation for Grid Environments Ammar H. Alhusaini
- Time and Energy Efficient Matrix Factorization using FPGAs
- SYSTEM-LEVEL ENERGY TRADEOFFS FOR COLLABORATIVE COMPUTATION IN
- IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, VOL. 8, NO. 1, JANUARY 1997 1 Constant Time Algorithms for Computational
- Performance Modeling of Reconfigurable SoC Architectures and Energy-Efficient Mapping of a Class of Applications
- Adaptive Parallel Rendering on Multiprocessors and Workstation Clusters
- Computing Lennard-Jones Potentials and Forces with Reconfigurable Hardware
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- HIGH-PERFORMANCE AND PARAMETERIZED MATRIX FACTORIZATION ON FPGAS Ling Zhuo and Viktor K. Prasanna
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- PARAMETERIZED AND ENERGY EFFICIENT ADAPTIVE BEAMFORMING ON FPGAS USING MATLAB/SIMULINK
- Constrained Flow Optimization with Applications to Data Gathering in Sensor Networks
- Adaptive Matrix Multiplication in Heterogeneous Environments Bo Hong and Viktor K. Prasanna
- Trust Management in P2P and Grid Computing Shanshan Song and Runfang Zhou, {shanshan.song, rzhou}@usc.edu
- MILAN: A Model Based Integrated Simulation Framework for Design of Embedded Systems
- Applying Semantic Web Techniques to Reservoir Engineering: Challenges and Experiences from Event Modeling
- High-Performance FPGA-Based General Reduction Methods Gerald R. Morris, Ling Zhuo, and Viktor K. Prasanna
- An architecture of a workflow system for Integrated Asset Management in the smart oil field domain
- Decision Forest: A Scalable Architecture for Flexible Flow Matching on FPGA Weirong Jiang, Viktor K. Prasanna
- Domain-Specific Modeling for Rapid System-Wide Energy Estimation of Reconfigurable Architectures
- Parallel Inferencing for OWL Knowledge Bases Ramakrishna Soma
- Large-Scale Wire-Speed Packet Classification on FPGAs Weirong Jiang
- Scalable and Modular Algorithms for Floating-Point Matrix Multiplication on FPGAs
- Dynamic Precision Management for Loop Computations on Recon gurable Architectures
- Energy-efficient and Fault-tolerant Resolution of Topographic Queries in Networked Sensor Systems
- Scalable Hybrid Designs for Linear Algebra on Reconfigurable Computing Systems
- A HIERARCHICAL SIMULATION FRAMEWORK FOR APPLICATION DEVELOPMENT ON SYSTEM-ON-CHIP ARCHITECTURES
- Efficient Parallel Data Mining with the Apriori Algorithm on FPGAs1
- Algorithm Design and Synthesis for Wireless Sensor Networks Amol Bakshi and Viktor K. Prasanna
- Energy-Latency Tradeoffs for Data Gathering in Wireless Sensor Networks
- Analysis of High-performance Floating-point Arithmetic on FPGAs Gokul Govindu, Ling Zhuo, Seonil Choi and Viktor Prasanna
- Energy-Efficient Signal Processing Using FPGAs Seonil Choi, Ronald Scrofano, and
- High-Performance Reduction Circuits Using Deeply Pipelined Operators on FPGAs
- A Hierarchical Model for Distributed Collaborative Computation in Wireless Sensor Networks
- A Model-Based Framework for Developing and Deploying Data Aggregation Services
- Utilization-Based Heuristics for Statically Mapping Real-Time Applications onto the HiPer-D Heterogeneous Computing System
- A Semantic Framework for Integrated Modeling and Simulation of Transportation Systems
- Risk-Resilient Heuristics and Genetic Algorithms for
- Communication Models for Algorithm Design in Wireless Sensor Networks
- A Methodology for Energy Efficient Application Synthesis Using Platform FPGAs
- WormShield: Fast Worm Signature Generation with Distributed Fingerprint Aggregation
- Scalable Hybrid Designs for Linear Algebra on Reconfigurable Computing Ling Zhuo and Viktor K. Prasanna
- A Model-Based Extensible Framework for Efficient Application Design Using FPGA
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- IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, TPDS-0228-0806 1 Collaborative Detection of DDoS Attacks
- Security-Driven Heuristics and A Fast Genetic Algorithm for Trusted Grid Job Scheduling
- An Integer Programming Approach for Static Mapping of Paths onto Heterogeneous Real-Time Systems
- Energy-Optimal and Energy-Balanced Sorting in a Single-Hop Wireless Sensor Network
- Shanshan Song, Kai Hwang, and Runfang Zhou
- Portable and Scalable Algorithms for Irregular All-to-All Communication Wenheng Liu, Cho-Li Wang and Viktor K. Prasanna
- Energy-Efficient Design of Kernel Applications for FPGAs Through Domain-Specific , R. Scrofano2
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- PyGen: A MATLAB/Simulink Based Tool for Synthesizing Parameterized and Energy Efficient Designs Using FPGAs
- High Throughput and Large Capacity Pipelined Dynamic Search Tree on FPGA
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- This submission addresses: Recent research advances in MoDES Design of High-Performance Embedded System
- Optimizing Matrix Multiplication on Heterogeneous Reconfigurable Systems
- Pipelined Datapath for an IEEE-754 64-Bit Floating-Point Jacobi Solver Gerald R. Morris1
- Optimal Energy-Balanced Algorithm for Selection in a Single Hop Sensor Network
- Recon gurable Computing Systems Kiran Bondalapati and Viktor K. Prasanna
- The Abstract Task Graph: A Methodology for Architecture-Independent Programming of Networked Sensor Systems
- Rapid System-Level Performance Evaluation and Optimization for Application Mapping
- REGULAR EXPRESSION SOFTWARE DECELERATION FOR INTRUSION DETECTION SYSTEMS1
- Distributed Aggregation Schemes for Scalable Peer-to-Peer and Grid Computing*
- Energy-Efficient Multi-Hop Packet Transmission using Modulation Scaling in Wireless Sensor
- SIMULATION OF ADAPTIVE APPLICATIONS IN HETEROGENEOUS COMPUTING ENVIRONMENTS
- ModelML: a Markup Language for Automatic Model Synthesis Cong Zhang Amol Bakshi Viktor K. Prasanna
- Adaptive Trust Negotiation and Access Control Tatyana Ryutov, Li Zhou, and Clifford Neuman
- 0018-9162/07/$25.00 2007 IEEE58 Computer Published by the IEEE Computer Society circuit on an FPGA. In practice, area, clock rate, and
- Scalable High Throughput and Power Efficient IP-Lookup on FPGA Hoang Le and Viktor K. Prasanna
- Federated Access Control and Intrusion Detection for Grid Computing Li Zhou Clifford Neuman
- Filtering Shrew DDoS Attacks Using A New Frequency-Domain Approach
- Area-Efficient Evaluation of Arithmetic Expressions Using Deeply Pipelined Floating-Point Cores1
- A Framework for Energy Efficient Design of Multi-Rate Applications using Hybrid
- Proceedings of the International Parallel and Distributed Processing Symposium (IPDPS'02) 1530-2075/02 $17.00 2002 IEEE
- Optimizing Graph Algorithms for Improved Cache Performance* Joon-Sang Park, Michael Penner, and Viktor K Prasanna
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 13, NO. 11, NOVEMBER 2005 1305 Energy-and Time-Efficient Matrix
- Collaborative Defense against Periodic Shrew DDoS Attacks in Frequency Domain
- Efficient Floating-point based Block LU Decomposition on FPGAs Vikash Daga2
- Creating Parameterized and Energy-Efficient System Generator Designs
- Negotiation of Multilateral Security Decisions for Grid Computing Li Zhou Clifford Neuman
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 16, NO. 1, JANUARY 2008 45 A Cooperative Management Scheme for Power
- Area, and Power Performance Analysis of a Floating-point based Application on FPGAs Gokul Govindu, Ling Zhuo, Seonil Choi, Padma Gundala, Viktor K Prasanna
- This CiSoft Seminar will also be webcast. Please register at: http://usccisoft.omnovia.com/
- Integrating Provenance Information in Reservoir Engineering Jing Zhao, Na Chen
- * Author currently at Chevron Corp., Houston, TX, USA Intelligent model management and Visualization for smart oilfields
