- Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques
- Computational Model of Edge Effects in Graphene Nanoribbon Transistors
- Single-ended Coding Techniques for Off-chip Interconnects to Commodity Memory
- Graphene Tunneling FET and its Applications in Low-power Circuit Design
- Eliminating NonDeterminism During Test of HighSpeed Source Synchronous Differential Buses
- Analytical model for TDDB-based performance degradation in combinational logic
- IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 25, NO. 1, JANUARY 2006 155 Gate Sizing to Radiation Harden
- Input Ordering in Concurrent Checkers to Reduce Power Consumption
- Context-Independent Codes for Off-Chip Interconnects Kartik Mohanram and Scott Rixner
- Graphene nanoribbon FETs: Technology exploration and CAD
- Tunable transient filters for soft error rate reduction in combinational circuits
- 1234 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 12, NO. 11, NOVEMBER 2004 Lowering Power Consumption in Concurrent
- Power Consumption of Logic Circuits in Ambipolar Carbon Nanotube Technology
- Parallel domain decomposition for simulation of large-scale power grids
- Masking timing errors on speed-paths in logic circuits Mihir R. Choudhury and Kartik Mohanram
- Synthesis of Low-Cost Parity-Based Partially Self-Checking Circuits Kartik Mohanram
- Analysis of delay caused by bridging faults in RLC interconnects
- Closed-form simulation and robustness models for SEU-tolerant design
- Technology exploration for graphene nanoribbon FETs Mihir Choudhury
- TIMBER: Time borrowing and error relaying for online timing error resilience
- Bi-decomposition of large Boolean functions using blocking edge graphs
- Transistor Sizing for Radiation Hardening Quming Zhou and Kartik Mohanram
- Dominant Critical Gate Identification for Power and Yield Optimization in Logic Circuits
- Novel dual-Vth independent-gate FinFET circuits Masoud Rostami and Kartik Mohanram
- Timing-driven optimization using lookahead logic circuits Mihir Choudhury and Kartik Mohanram
- Novel Library of Logic Gates with Ambipolar CNTFETs: Opportunities for Multi-Level Logic Synthesis
- 392 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 28, NO. 3, MARCH 2009 Reliability Analysis of Logic Circuits
- Analytical model-based technique for efficient evaluation of noise robustness considering parameter variations
- Approximate logic circuits for low overhead, non-intrusive concurrent error detection
- Power Signal Processing: A New Perspective for Power Analysis and Optimization
- Parameter-Variation-Aware Analysis for Noise Robustness Mosin Mondal Kartik Mohanram Yehia Massoud
- Dependable = Unaffordable Alan L. Cox, Kartik Mohanram, and Scott Rixner
- Design optimization for robustness to single-event upsets
- Large power grid analysis using domain decomposition
- Simulation of transients caused by single-event upsets in combinational logic
- Semi-analytical Model for Schottky-barrier Carbon Nanotube and Graphene Nanoribbon Transistors
- Analytical Theory of Graphene Nanoribbon Transistors Mihir Choudhury
- Cost-Effective Radiation Hardening Technique for Combinational Logic
- 7141-4244-1176-9/07/$25.00 2007 IEEE. A Model-Based Technique for Efficient Evaluation
- Partial Error Masking to Reduce Soft Error Failure Rate in Logic Kartik Mohanram*
- Cost-Effective Approach for Reducing Soft Error Failure Rate in Logic Circuits Kartik Mohanram
- Structure Preserving Reduction of Frequency-dependent Interconnect
- Elmore Model for Energy Estimation in RC Trees Quming Zhou and Kartik Mohanram
- Accurate and scalable reliability analysis of logic circuits Mihir R. Choudhury and Kartik Mohanram
- J Electron Test DOI 10.1007/s10836-009-5103-9
