
- 1118 IEEE TRANSACTIONS ON MAGNETICS, VOL. 43, NO. 3, MARCH 2007 Quasi-Cyclic LDPC Codes for the Magnetic
- 3D DRAM Design and Application to
- High-Rate Quasi-Cyclic LDPC Codes for Magnetic Recording Channel with Low Error Floor
- 830 IEEE TRANSACTIONS ON MAGNETICS, VOL. 46, NO. 3, MARCH 2010 New Phase-Locked Loop Design: Understanding the Impact of a
- Two Fault Tolerance Design Approaches for Hybrid CMOS/Nanodevice Digital Fei Sun and Tong Zhang
- IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 6, NO. 3, MAY 2007 341 Defect and Transient Fault-Tolerant System Design
- VLSI Implementation-Oriented )-Regular Low-Density
- Relaxed Tree Search MIMO Signal Detection Algorithm Design and VLSI Implementation
- A 54 MBPS (3; 6)REGULAR FPGA LDPC DECODER Tong Zhang and Keshab K. Parhi
- Systematic Design Approach of Mastrovito Multipliers over GF (2
- Systematic Design of Original and Modified Mastrovito Multipliers for General Irreducible Polynomials
- UNIVERSITY OF MINNESOTA This is to certify that I have examined this copy of a doctoral thesis by
- IEEE TRANSACTIONS ON MAGNETICS, VOL. 46, NO. 3, MARCH 2010 933 Improving Burst Error Tolerance of LDPC-Centric
- Leveraging Access Locality for the Efficient Use of Multibit Error-Correcting Codes in L2 Cache
- Run-Time Data-Dependent Defect Tolerance for Hybrid CMOS/Nanodevice Digital Memories
- 1060 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS--I: REGULAR PAPERS, VOL. 54, NO. 5, MAY 2007 Low-Power State-Parallel Relaxed
- 328 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 15, NO. 3, MARCH 2007 Relaxed K-Best MIMO Signal Detector Design and
- Block-LDPC: A Practical LDPC Coding System Design Approach
- )-Regular LDPC Code and Decoder/Encoder Design Tong Zhang* and Keshab K. Parhi
- Systematic Design of Original and Modified Mastrovito Multipliers for
- Hybrid Resistor/FET-Logic Demultiplexer Architecture Design for Hybrid CMOS/Nanodevice Circuits
- On the Selection of Arithmetic Unit Structure in Voltage Overscaled Soft Digital Signal Processing
- On the Use of Strong BCH Codes for Improving Multilevel NAND Flash Memory Storage Capacity
- Low Power Trellis Decoder with Overscaled Supply Yang Liu, Tong Zhang, and Jiang Hu
- Nonlinear Soft-Output Signal Detector Design and Implementation for MIMO Communication Systems with
- MULTILEVEL FLASH MEMORY ON-CHIP ERROR CORRECTION BASED ON TRELLIS CODED MODULATION
- A HIGH THROUGHPUT LIMITED SEARCH TRELLIS DECODER FOR CONVOLUTIONAL CODE DECODING
- JOINT CODE-ENCODER-DECODER DESIGN FOR LDPC CODING SYSTEM VLSI IMPLEMENTATION
- JOINT CODE AND DECODER DESIGN FOR IMPLEMENTATION-ORIENTED )-REGULAR LDPC CODES
- PROC. OF GLOBECOM'01, SAN ANTONIO, TX, NOV. 2001 1 High-Performance, Low-Complexity Decoding of Generalized Low-Density
- A CLASS OF EFFICIENT-ENCODING GENERALIZED LOW-DENSITY PARITY-CHECK CODES
- ELECTRICAL, COMPUTER, AND SYSTEMS ENGINEERING DEPARTMENT ABET COURSE SYLLABUS
- PARALLELISM/REGULARITY-DRIVEN MIMO DETECTION ALGORITHM DESIGN Tong Zhang, Yan Xin, and Sizhong Chen
- 2718 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS--I: REGULAR PAPERS, VOL. 57, NO. 10, OCTOBER 2010 Using Data Postcompensation and Predistortion to
- 1412 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 18, NO. 10, OCTOBER 2010 Improving Multi-Level NAND Flash Memory
- IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS--II: EXPRESS BRIEFS, VOL. 57, NO. 9, SEPTEMBER 2010 701 A 1.1-Gb/s 115-pJ/bit Configurable MIMO Detector
- Design of VLSI Implementation-Oriented LDPC Codes Hao Zhong and Tong Zhang
- 3-D Data Storage, Power Delivery, and RF/Optical
- 66 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 18, NO. 1, JANUARY 2010 Design of Spin-Torque Transfer Magnetoresistive
- ELECTRICAL, COMPUTER, AND SYSTEMS ENGINEERING DEPARTMENT ABET COURSE SYLLABUS
- IEEE TRANSACTIONS ON MAGNETICS, VOL. 46, NO. 1, JANUARY 2010 87 Using Embedded Dynamic Random Access Memory to Reduce Energy
- On the HighSpeed VLSI Implementation of ErrorsandErasures Correcting ReedSolomon Decoders
- ON FINITE PRECISION IMPLEMENTATION OF LOW DENSITY PARITY CHECK CODES DECODER
- JOINT CODE AND DECODER DESIGN FOR IMPLEMENTATIONORIENTED (3; K)REGULAR LDPC CODES
- Spin-Transfer Torque Magnetoresistive Content Addressable Memory (CAM) Cell Structure Design
- A 54 MBPS (3, 6)-REGULAR FPGA LDPC DECODER Tong Zhang and Keshab K. Parhi
- Design of on-chip error correction systems for multilevel NOR and NAND flash memories
- Joint (3; k)Regular LDPC Code and Decoder/Encoder Design Tong Zhang* and Keshab K. Parhi
- An FPGA Implementation of ( )-Regular Low-Density
- Use of Parity Checks Inherent in LDPC Codes for Dominant Error Events Detection and k-Constraint Enforcement
- An FPGA Implementation of (3; 6)Regular LowDensity ParityCheck Code Decoder
- A CLASS OF EFFICIENTENCODING GENERALIZED LOWDENSITY PARITYCHECK CODES
- 4784 IEEE TRANSACTIONS ON MAGNETICS, VOL. 44, NO. 12, DECEMBER 2008 Concatenated Low-Density Parity-Check and BCH Coding System for
- IEEE TRANSACTIONS ON VEHICULAR TECHNOLOGY, VOL. 57, NO. 4, JULY 2008 2319 Bypass Decoding: A Reduced-Complexity Decoding
- Breadth-First Tree Search MIMO Signal Detector Design and VLSI Implementation Sizhong Chen, Tong Zhang and Yan Xin
- TCAS-I 1399 1 Self-Timed Dynamically Pipelined Adaptive Signal
- Exploiting Three-Dimensional (3D) Memory Stacking to Improve Image Data Access Efficiency for Motion Estimation Accelerators
- ON FINITE PRECISION IMPLEMENTATION OF LOW DENSITY PARITY CHECK CODES DECODER
- Energy-Efficient Soft-Output Trellis Decoder Design Using Trellis Quasi-Reduction and Importance-Aware Clock Skew
- EFFICIENT COHERENT DETECTOR VLSI DESIGN FOR CONTINUOUS PHASE Tong Zhang, Jie Wu and Gary J. Saulnier
- Low Power State-Parallel Relaxed Adaptive Viterbi Decoder Design and Implementation
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 13, NO. 9, SEPTEMBER 2005 1013 Parallel High-Throughput Limited Search Trellis
- Low Power Soft-Output Signal Detector Design for Wireless MIMO Communication Systems
- PROC. OF GLOBECOM'01, SAN ANTONIO, TX, NOV. 2001 1 HighPerformance, LowComplexity Decoding of Generalized LowDensity
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 17, NO. 3, MARCH 2009 439 Transactions Briefs
- ELECTRICAL, COMPUTER, AND SYSTEMS ENGINEERING DEPARTMENT ABET COURSE SYLLABUS
- Systematic Design Approach of Mastrovito Multipliers over
- Area-Efficient Min-Sum Decoder Design for High-Rate QC-LDPC Codes in Magnetic Recording
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 18, NO. 4, APRIL 2010 517 Computation Error Analysis in Digital Signal
- VLSI ImplementationOriented (3; k)Regular LowDensity