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Ghosh, Shalini - Computer Science Laboratory, SRI International
Joint Minimization of Power and Area in Scan Testing by Scan Cell Reordering Shalini Ghosh1
Submitted to the Journal of Low Power Electronics Selecting Error Correcting Codes to Minimize Power in
Shalini Ghosh The Dissertation Committee for Shalini Ghosh certifies that this is
Estimating Detection Probability of Interconnect Opens using Stuck-at Tests
Dynamic Low-Density Parity Check Codes for Fault-tolerant Nanoscale Memory
Low-Density Parity Check Codes for Error Correction in Nanoscale Memory
Synthesis of Low Power CED Circuits Based on Parity Codes Shalini Ghosh1
Detection Probabilities of Interconnect Breaks: An Analysis
Reducing Power Consumption in Memory ECC Checkers Shalini Ghosh1
Low-Power Weighted Pseudo-Random BIST Using Special Shalini Ghosh
Biographical Sketch of Dr. Shalini Ghosh Computer Science Laboratory,
Joint Minimization of Power and Area in Scan Testing by Scan Cell Reordering Technical Report: UT-CERC-TR-NAT02-1
Markov Logic Networks in Health Informatics Shalini Ghosh, Natarajan Shankar, Sam Owre, Sean David
Dynamic LDPC Codes for Nanoscale Memory with Varying Fault Arrival Rates
Machine Reading Using Markov Logic Networks for Collective Probabilistic Inference
