- Macro Data Load: An Efficient Mechanism for Enhancing Loaded Data Reuse
- Cache Equalizer: A Placement Mechanism for Chip Multiprocessor Distributed Shared Caches
- J. Parallel Distrib. Comput. 71 (2011) 115 Contents lists available at ScienceDirect
- Progressive Hashing for Packet Processing Using Set Associative Memory.
- An Analytical Model to Study Optimal Area Breakdown between Cores and Caches in a Chip Multiprocessor
- CHAP: Enabling Efficient Hardware-Based Multiple Hash Schemes for IP Lookup
- An Efficient Hardware-based Multi-hash Scheme for High Speed IP Lookup Socrates Demetriades, Michel Hanna, Sangyeun Cho and Rami Melhem
- Achieving Predictable Performance with On-Chip Shared L2 Caches for Manycore-Based Real-Time Systems
- Figure 1. Definition of four ranges of process variation A Data-Driven Statistical Approach to Analyzing Process Variation
- I-Cache Multi-Banking and Vertical Interleaving Sangyeun Cho
- Better than the Two: Exceeding Private and Shared Caches via Two-Dimensional Page Coloring
- A Flexible Data to L2 Cache Mapping Approach for Future Multicore Processors
- Reducing Cache Traffic and Energy with Macro Data Load
- A Characterization Study on Memory Value Reuse Lei Jin and Sangyeun Cho
- A Dynamic Pressure-Aware Associative Placement Strategy for Large Scale Chip Multiprocessors
- A Novel Scalable IPv6 Lookup Scheme Using Compressed Pipelined Tries
- Journal of Circuits, Systems, and Computers Vol. 18, No. 6 (2009) 10811092
- SOFTWARE PRACTICE AND EXPERIENCE Softw. Pract. Exper. 2010; 40:239258
- Dynamic Co-Management of Persistent RAM Main Memory and Storage Resources
- Dynamic Cache Clustering for Chip Multiprocessors Mohammad Hammoud Sangyeun Cho Rami Melhem
- ACM: An Efficient Approach for Managing Shared Caches in Chip Multiprocessors
- CA-RAM: A High-Performance Memory Substrate for Search-Intensive Applications
- Managing Distributed, Shared L2 Caches through OS-Level Page Allocation Sangyeun Cho Lei Jin
- StealthWorks: Emulating Memory Errors Musfiq Rahman, Bruce R. Childers and Sangyeun Cho
- Early Prediction of Product Performance and Yield Via Technology Benchmark
- Taming Single-Thread Program Performance on Many Distributed On-Chip L2 Caches
- Flip-N-Write: A Simple Deterministic Technique to Improve PRAM Write Performance, Energy and Endurance
- Accurately Approximating Superscalar Processor Performance from Traces Kiyeon Lee, Shayne Evans, and Sangyeun Cho
- Guest Editors' Introduction....................................................................................................................................................................................................................................
- TPTS: A Novel Framework for Very Fast Manycore Processor Architecture Simulation
- Journal of Parallel and Distributed Computing 57, 14 32 (1999) Coherence and Replacement Protocol of DICE
- On the Interplay of Parallelization, Program Performance, and Energy Consumption
- Preliminary Studies to Develop a Ubiquitous Computing and Health-monitoring System for Wheelchair Users
- SOS: A Software-Oriented Distributed Shared Cache Management Approach for Chip Multiprocessors
- An Intra-Tile Cache Set Balancing Scheme Mohammad Hammoud, Sangyeun Cho, and Rami G. Melhem
- PRISM: Zooming in Persistent RAM Storage Behavior Ju-Young Jung and Sangyeun Cho
- A Content-Aware Block Placement Algorithm for Reducing PRAM Storage Bit Writes
- IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 21, NO. 1, FEBRUARY 2008 55 Decomposition and Analysis of Process Variability
- Corollaries to Amdahl's Law for Energy Sangyeun Cho, Member, IEEE Rami G. Melhem, Fellow, IEEE
- Fast, Energy Efficient Scan inside Flash Memory SSDs Sungchan Kim
- MAESTRO: Orchestrating Predictive Resource Management in Future Multicore Systems
- J. Parallel Distrib. Comput. 71 (2011) 889896 Contents lists available at ScienceDirect
- BarrierWatch: Characterizing Multithreaded Workloads across and within Program-Defined Epochs
- Scalable Multi-Cache Simulation Using GPUs Michael Moeng, Sangyeun Cho, and Rami Melhem
- In-N-Out: Reproducing Out-of-Order Superscalar Processor Behavior from Reduced In-Order Traces
- An Analytical Performance Model for Co-Management of Last-Level Cache
- CS/COE 0447 Spring 2012 Lab 2: Immediate Values, Memory, and System Calls
- Sustainable Computing at PittCS Panos K. Chrysanthis and Kirk Pruhs
- CS/COE 0447 Spring 2012 Lab #6: 1-bit Adders and Number Representation
- J. Parallel Distrib. Comput. 71 (2011) 115 Contents lists available at ScienceDirect
- A Novel Scalable IPv6 Lookup Scheme Using Compressed Pipelined Tries
- NSF-supported Research on Sustainable Computing at PittCS Panos K. Chrysanthis Kirk Pruhs
- ADVANCED HASHING SCHEMES FOR PACKET FORWARDING USING SET ASSOCIATIVE
- Proceedings The 11th Workshop on
- University of Pittsburgh Computer Science Day
- The WorldFIP Protocol Standard and Specifications In the previous chapter we have seen the definition of the fieldbus and its
- SOCRATES DEMETRIADES CV CONTACT INFORMATION
- Introduction to Fieldbus Systems In this chapter we will present an introduction to the Distributed Computer
- CS/COE 0447 Spring 2012 Exam 1 Extra Practice
- Worst Case Response Time of WorldFIP Aperiodic Traffic
- Real-Time Analysis of FIP-based Systems
- 1-[Almeida 2002], L. Almeida, et. al, "Schedulability Analysis of Real-Time Traffic in WorldFIP Networks: An Integrated Approach", Submitted to IEEE at September
- An Efficient Hardware-based Multi-hash Scheme for High Speed IP Lookup Socrates Demetriades, Michel Hanna, Sangyeun Cho and Rami Melhem
- A Modified Scheduling Algorithm for The FIP Fieldbus System
- Technical Program 1:00pm-1:15pm Welcome and introduction to workshop
- CS0447/COE 147 Spring 2012 Lab 3: Endianness, Bit Manipulation, Strings, Loops
- CS131 -Software for Personal Computing Course Syllabus, Summer 2008 term
- Conclusions and Future Work In this chapter we will review the entire research thesis objectives and results.
- CS 0447/COE 0147 Spring 2012 Lab #7: Multiplication and Division
- Progressive Hashing for Packet Processing Using Set Associative Memory.
- Call for Papers IEEE Micro Special Issue
- Real-Time Communications in WorldFIP 3.1. Introduction to FIP Real-Time Analyses.
- CS/COE 0447 Spring 2012 Lab #6: 1-bit Adders and Number Representation
- the problem by speeding up a workload with parallel pro-cessing at a lower clock frequency (and lower voltage). But
- CHAP: Enabling Efficient Hardware-based Multiple Hash Schemes for IP Lookup
