- PROCESSOR DESIGN IN 3D DIE-STACKING TECHNOLOGIES
- FD-HGAC: A Hybrid HeuristidGeneticAlgorithm Hardware/Software Co-synthesisFramework with Fault Detection
- Design Space Exploration for 3D Architectures
- 118 Computer E M B E D D E D C O M P U T I N G
- Code Compression for VLlW Processors Using Variable-to-fixed Coding
- An Instruction-Level Analytical Power Model for De-signing the Low Power Systems on a Chip
- On-chip Bus Thermal Analysis and Optimization Feng Wang, Yuan Xie, N. Vijaykrishnan, and M. J. Irwin
- Thermal-Aware IP Virtualization and Placement for Networks-on-Chip Architecture W. Hung, C. Addo-Quaye, T. Theocharides, Y. Xie, N. Vijaykrishnan, and M. J. Irwin
- Reliability-Aware Co-synthesis for Embedded Systems Y. Xie, L. Li, M. Kandemir, N. Vijaykrishnan, and M. J. Irwin
- Co-synthesiswith custom ASICs Yuan Xie, Wayne Wolf
- FLAW: FPGA Lifetime AWareness Suresh Srinivasan, Karthik Sarpatwari
- LZW-Based Code Compression for VLIW Embedded Systems Chang Hong Lin
- Architecting Microprocessor Components in 3D Design Space Balaji Vaidyanathan , Wei-Lun Hung, Feng Wang, Yuan Xie, Vijaykrishnan Narayanan, Mary Jane Irwin
- Accurate Stacking Effect Macro-modeling of Leakage Power in Sub-100nm Circuits
- Variation-aware Task Allocation and Scheduling for MPSoC Feng Wang, C. Nicopoulos, Xiaoxia Wu, Yuan Xie and N. Vijaykrishnan
- Temperature-aware NBTI modeling and the impact of input vector control on performance degradation
- A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks
- The effect of threshold voltages on the soft error rate V. Degalahal, R. Ramanarayanan, N. Vijaykrishnan, Y. Xie and M. J. Irwin
- Three-Dimensional Cache Design Exploration Using 3DCacti Yuh-Fang Tsai, Yuan Xie, N. Vijaykrishnan, and Mary Jane Irwin
- Soft Error Analysis and Optimizations of C-elements in Asynchronous Circuits
- Interconnect and Thermal-aware Floorplanning for 3D Microprocessors W.-L. Hung, G.M. Link, Yuan Xie, N. Vijaykrishnan, and M. J. Irwin
- Journal of VLSI Signal Processing 2007 * 2007 Springer Science + Business Media, LLC. Manufactured in The United States.
- Journal of VLSI Signal Processing 45, 177189, 2006 * 2006 Springer Science + Business Media, LLC. Manufactured in The Netherlands.
- A Novel Criticality Computation Method in Statistical Timing Analysis
- Variation Analysis of CAM Cells Amol Mupid1
- Leakage Optimized DECAP Design for FPGAs Balaji Vaidyanathan, Suresh Srinivasan, Yuan Xie, Narayanan Vijaykrishnan
- Guaranteeing Performance Yield in High-Level Synthesis W.-L. Hung, Xiaoxia Wu, and Yuan Xie
- Modeling the Impact of Process Variation on Critical Charge Distribution , Rong LUO1
- Crosstalk-Aware Energy Efficient Encoding for Instruction Bus through Code Compression
- ANALYSIS OF SUBTHRESHOLD FINFET CIRCUITS FOR ULTRA-LOW POWER DESIGN
- Design and Management of 3D Chip Multiprocessors Using Network-in-Memory Feihui Li, Chrysostomos Nicopoulos, Thomas Richardson, Yuan Xie,
- Dependability Analysis of Nano-scale FinFET circuits Feng Wang*, Yuan Xie*, Kerry Bernstein
- Delay and Energy Efficient Data Transmission for On-Chip Buses Madhu Mutyam Melvin Eze N. Vijaykrishnan Yuan Xie
- Reliability-Aware SOC Voltage Islands Partition and Floorplan
- Optimal Topology Exploration for Application-Specific 3D Architectures Ozcan Ozturk, Feng Wang, Mahmut Kandemir, and Yuan Xie
- SEAT-LA: A Soft Error Analysis tool for Combinational Logic R. Rajaraman, J. S. Kim, N. Vijaykrishnan, Y. Xie, M. J. Irwin
- Temperature-Sensitive Loop Parallelization for Chip Multiprocessors Sri Hari Krishna Narayanan, Guilin Chen, Mahmut Kandemir, Yuan Xie
- An ILP Formulation for Reliability-Oriented High-Level Synthesis , O. Ozturk**
- Reliability-Centric High-Level Synthesis , N. Mansouri
- Improving Soft-error Tolerance of FPGA Configuration Bits
- Total Power Optimization through Simultaneously Multiple-VDD
- Analysis of Two Code Compression Algorithms for Embedded Systems YuanXie ' ' .
- Code Compression Using Variable-to-fixed Coding Based on Arithmetic Coding*
- Profile-driven Selective Code Compression Yuan Xie and Wayne Wolf
- Allocation and scheduling of conditional task graph in hardwarelsoftware co-synthesis
- Thermal-Aware Floorplanning Using Genetic Algorithms W-L. Hung, Y. Xie, N. Vijaykrishnan, C. Addo-Quaye, T. Theocharides, and M. J. Irwin
- Modeling of PMOS NBTI Effect Considering Temperature Variation Hong Luo, Yu Wang, Ku He, Rong Luo, Huazhong Yang
- Collaborative VLSI-CAD Instruction in the Digital Sandbox Alex K. Jones1
- Influence of Leakage Reduction Techniques on Delay/Leakage Uncertainty Yuh-Fang Tsai, N. Vijaykrishnan, Yuan Xie, and Mary Jane Irwin
- Variation Impact on SER of Combinational Circuits K. Ramakrishnan, R. Rajaraman, S. Suresh, N. Vijaykrishnan, Y. Xie, M. J. Irwin
- Soft Error Rate Analysis for Combinational Logic Using An Accurate Electrical Masking Model
- An Accurate and Efficient Model of Electrical Masking Effect for Soft Errors in Combinational Logic
- Temperature-Aware Voltage Islands Architecting in System-on-Chip Design W.-L. Hung, G. M. Link, Yuan Xie, N. Vijaykrishnan, N. Dhanwada, and J. Conner
- Abstract--Radiation induced soft errors in combinational logic is expected to become as important as directly induced
- A Novel Dimensionally-Decomposed Router for On-Chip Communication in 3D Architectures
- Low-leakage Robust SRAM cell design for Sub-1OOnm Technologies
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 14, NO. 5, MAY 2006 525 Code Compression for Embedded VLIW Processors
- Adaptive Power Management in Software Radios using Resolution Adaptive Analog to Digital Converters
- Reliability-Centric Hardware/Software Co-design , N. Mansouri*
