Katevenis, Manolis G.H. - Institute of Computer Science, Foundation of Research and Technology, Hellas

• Tracing a largescale Peer to Peer System: an hour in the life of Gnutella
• Variable Packet Size Buffered Crossbar (CICQ) Switches
• Design of an Application Programming Interface for IP Network Monitoring #
• Pipelined Heap (Priority Queue) Management for Advanced Scheduling in HighSpeed Networks
• An Efficient ProcessorNetwork Interface for Local Area Multiprocessors
• FORTHICS / TR171 July 1996 CreditFlowControlled ATM
• FORTHICS /TR328 November 2003 Performance Evaluation of
• Multiple Priorities in a TwoLane Buffered Crossbar Nikos Chrysos and Manolis Katevenis #
• Variable Packet Size Buffered Crossbar (CICQ) Switches
• Variable-Size Multipacket Segments in Buffered Crossbar (CICQ) Architectures
• The Network RamDisk : Using Remote Memory on Heterogeneous NOWs \Lambda
• FORTHICS / TR 258 June 1999 Hardware Implementation of a Routing
• E 2 XB: A DOMAINSPECIFIC STRING MATCHINGALGORITHM FOR INTRUSION
• Pipelined Heap (Priority Queue) Management for Advanced Scheduling in High-Speed Networks
• Performance Analysis of Content Matching Intrusion Detection Systems S. Antonatos # , K. G. Anagnostakis + , E. P. Markatos # , M. Polychronakis ##
• FORTH-ICS/TR-339 July 2004 Design of a 32x32
• FORTHICS / TR 222 July 1998 Heap Management in Hardware
• Multiple Priorities in a Two-Lane Buffered Crossbar Nikos Chrysos and Manolis Katevenis
• Lightweight Transactions on Networks of Workstations Athanasios E. Papathanasiou Evangelos P. Markatos \Lambda
• Exclusionbased Signature Matching for Intrusion Detection Evangelos P. Markatos, Spyros Antonatos, Michalis Polychronakis, Kostas G. Anagnostakis
• Wormhole ### ###### ######### ### ## ##### ###### ########, ##### 1996
• Buffer Requirements of CreditBased Flow Control when a Minimum Draining Rate is Guaranteed
• Issues in Reliable Network Memory Paging Evangelos P. Markatos \Lambda
• Benes Switching Fabrics with O(N )Complexity Internal Backpressure
• Using Processor Affinity in Loop Scheduling on SharedMemory Multiprocessors
• Tracing a large-scale Peer to Peer System: an hour in the life of Gnutella
• Speeding up TCP/IP: Faster Processors are not Enough Evangelos P. Markatos \Lambda
• Variable Packet Size Buffered Crossbar (CICQ) Switches
• Fast and Transparent Recovery for Continuous Availability of Clusterbased Servers
• Efficient Per-Flow Queueing in DRAM at OC-192 Line Rate using Out-of-Order Execution Techniques
• Benes Switching Fabrics with O(N )Complexity Internal Backpressure
• VariableSize Multipacket Segments in Buffered Crossbar (CICQ) Architectures
• FORTHICS / TR124 July 1994 A Memory Controller for Access Interleaving
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• VClevel Flow Control and Shared Buffering in the Telegraphos Switch
• Palantir: AVisualization Tool for the World Wide Web Nektarios Papadakakis Evangelos P. Markatos Athanasios E. Papathanasiou 1
• Experimental ATM Network Interface Performance Apostolos Dollas \Lambda Kyprianos Papadimitriou Constantinos Mathioudakis
• VariableSize Multipacket Segments in Buffered Crossbar (CICQ) Architectures
• Secondary Storage Management for Web Proxies Evangelos P. Markatos Manolis G.H. Katevenis
• On Caching Search Engine Query Results Evangelos P. Markatos
• Submitted July 2003 --Current copy is an `on-going' version Few buffers suffice: Explaining why and how
• Multiple Priorities in a TwoLane Buffered Crossbar Nikos Chrysos and Manolis Katevenis
• WebConscious Storage Management for Web Proxies Evangelos P. Markatos, Dionisios N. Pnevmatikatos,
• FORTHICS /TR325 October 2003 Design Issues of VariablePacketSize,
• A Top10 Approach to Prefetching on the Web Evangelos P. Markatos and Catherine E. Chronaki
• PANEPISTHMIO KRHTHS TMHMA EPISTHMHS UPOLOGISTWN
• Efficient PerFlow Queueing in DRAM at OC192 Line Rate using OutofOrder Execution Techniques
• Design of an Application Programming Interface for IP Network Monitoring
• Code Generation for Packet Header Intrusion Analysis on the IXP1200 Network Processor
• Exclusion-based Signature Matching for Intrusion Detection Evangelos P. Markatos, Spyros Antonatos, Michalis Polychronakis, Kostas G. Anagnostakis
• FORTH-ICS /TR-328 November 2003 Performance Evaluation of
• Benes Switching Fabrics with O(N)-Complexity Internal Backpressure
• FORTH-ICS / TR-316 December 2002 Benes Switching Fabrics with
• Benes Switching Fabrics with O(N)-Complexity Internal Backpressure
• Switching Fabrics with Internal Backpressure using the ATLAS I SingleChip ATM Switch
• Implementation of a Reliable Remote Memory Pager Evangelos P. Markatos and George Dramitinos \Lambda
• FORTHICS / TR 257 June 1999 IP Routing Table Organization and Management
• On Using Network Memory to Improve the Performance of TransactionBased Systems \Lambda
• Implementation and Evaluation of a Remote Memory Pager \Lambda Evangelos P. Markatos George Dramitinos
• On using Reliable Network RAM for Database Systems Athanasios E. Papathanasiou and Evangelos P. Markatos \Lambda
• DIRECTMAPPED ASYNCHRONOUS FINITESTATE MACHINES IN CMOS TECHNOLOGY
• Telegraphos: HighPerformance Networking for Parallel Processing on Workstation Clusters
• The Memory Structures of ATLAS I, a High Performance, 16x16 ATM Switch Supporting Backpressure.
• Pipelined Memory Shared Buffer for VLSI Switches Manolis Katevenis, Panagiota Vatsolaki, and Aristides Efthymiou
• Benes Switching Fabrics with O(N )Complexity Internal Backpressure
• MemSpyer User's guide Antonis Danalis
• FORTHICS / TR 221 July 1998 Design and Implementation of a
• Issues in the Design and Implementation of UserLevel DMA Evangelos P. Markatos Manolis G.H. Katevenis
• ATLAS I: A GeneralPurpose, SingleChip ATM Switch with CreditBased Flow Control
• VIAttached Database Storage Yuanyuan Zhou, Member, IEEE, Angelos Bilas, Member, IEEE, Suresh Jagannathan, Member, IEEE,
• Pipelined Heap (Priority Queue) Management for Advanced Scheduling in HighSpeed Networks
• ATLAS II: Optimizing a 10Gbps SingleChip ATM Switch Dionisios Pnevmatikatos and George Kornaros
• Lightweight Transactions on Networks of Workstations \Lambda Athanasios E. Papathanasiou Evangelos P. Markatos y
• ACTUAL-DELAY CIRCUITS ON FPGA: TRADING-OFF LUTS FOR SPEED Evangelia Kassapaki, Pavlos M. Mattheakis and Christos P. Sotiriou
• Performance Analysis of Content Matching Intrusion Detection Systems S. Antonatos , K. G. Anagnostakis
• An Active Traffic Splitter Architecture for Intrusion Detection I. Charitakis , K. Anagnostakis
• Variable Packet Size Buffered Crossbar (CICQ) Switches
• FORTH-ICS /TR-325 October 2003 Design Issues of Variable-Packet-Size,
• Weighted Fairness in Buffered Crossbar Scheduling Nikos Chrysos
• Copyright: IEEE Communications Society, International Conference on Communications, Paris, 2004.
• Submitted 24-06-2003. Current copy is an `on-going' version. Nash Equilibria
• Transient Behavior of a Buffered Crossbar Converging to Weighted Max-Min Fairness
• Efficient Per-Flow Queueing in DRAM at OC-192 Line Rate using Out-of-Order Execution Techniques
• CreditFlowControlled ATM over HIC Links in the ASICCOM ``ATLAS I'' SingleChip Switch
• FORTHICS / TR172 July 1996 The Architecture, Operation and Design of the Queue
• Wormhole IP over (Connectionless) ATM Manolis Katevenis, Iakovos Mavroidis, Ioannis Mavroidis, and Georgios Glykopoulos
• Adding Flexibility to a Remote Memory Pager Evangelos P. Markatos George Dramitinos
• UserLevel DMA without Operating System Kernel Modification
• Tracing a largescale Peer to Peer System: an hour in the life of Gnutella
• Multiple Priorities in a Two-Lane Buffered Crossbar Nikos Chrysos and Manolis Katevenisy
• Variable Packet Size Buffered Crossbar (CICQ) Switches
• Multiple Priorities in a Two-Lane Buffered Crossbar Nikos Chrysos and Manolis Katevenis
• Pipelined MultiQueue Management in a VLSI ATM Switch Chip with CreditBased FlowControl \Lambda
• FORTHICS / TR303 March 2002 Benes Fabrics with Internal Backpressure
• Implementation of ATLAS I: a SingleChip ATM Switch with Backpressure
• On using Network Memory to Improve the Performance of TransactionBased Systems
• Wormhole IP over (Connectionless) ATM Manolis Katevenis, Iakovos Mavroidis, Georgios Sapountzis,
• Exclusionbased Signature Matching for Intrusion Detection Evangelos P. Markatos, Spyros Antonatos, Michalis Polychronakis, Kostas G. Anagnostakis \Lambda
• An Active Traffic Splitter Architecture for Intrusion Detection I. Charitakis , K. Anagnostakis
• Variable-Size Multipacket Segments in Buffered Crossbar (CICQ) Architectures
• Generating Realistic Workloads for Network Intrusion Detection Systems
• Using Remote Memory to avoid Disk Thrashing: A Simulation Study
• On Using Network RAM as a nonvolatile Buffer Dionisios Pnevmatikatos Evangelos P. Markatos
• Speeding up TCP/IP: Faster Processors are not Enough Evangelos P. Markatos
• MultiQueue Management and Scheduling for Improved QoS in Communication Networks
• Transient Behavior of a Buffered Crossbar Converging to Weighted MaxMin Fairness
• Fast, Large-Scale String Match for a 10Gbps FPGA-based Network Intrusion Detection
• Pipelined Multi-Queue Management in a VLSI ATM Switch Chip with Credit-Based Flow-Control
• FORTHICS / TR143 November 1995 Design, Implementation, and Testing of
• Multiple Priorities in a TwoLane Buffered Crossbar Nikos Chrysos and Manolis Katevenis y
• FORTHICS / TR 278 November 2000 An ASIC Core for Pipelined
• Visualizing Working Sets Evangelos P. Markatos \Lambda
• Appears in Proceedings of the 4th International Workshop on Software and Performance (ACM WOSP 2004) Generating Realistic Workloads for Network Intrusion
• ATLAS I: A SingleChip ATM Switch with HIC Links and MultiLane BackPressure
• INSTITUTE OF COMPUTER SCIENCE, FORTH COMPUTER ARCHITECTURE -VLSI DESIGN -PARALLEL & DISTRIBUTED SYSTEMS
• ATLAS I: A Singlechip ATM switch for NOWs Manolis G.H. Katevenis Panagiota Vatsolaki
• Weighted Fairness in Buffered Crossbar Scheduling Nikos Chrysos y , Manolis Katevenis y
• The Remote Enqueue Operation on Networks of Workstations
• FORTH-ICS / TR-172 July 1996 The Architecture, Operation and Design of the Queue
• Benes Switching Fabrics with O(N)-Complexity Internal Backpressure
• !#"%$'&()012( "%3546 73)()86 @9A6B4@3'8B 0C4 354ED"%F
• CreditFlowControlled ATM for MP Interconnection: the ATLAS I SingleChip ATM Switch
• Copyright 1998. Association for the Advancement of Computing in Education (AACE). Distributed via the Web by permission of AACE. The paper appears in Proceedings of the Webnet 98 World Conference.
• FORTHICS / TR309 April 2002 Weighted MaxMin Fairness
• http://archvlsi.ics.forth.gr/wormholeIP/ http://archvlsi.ics.forth.gr/wormholeIP/
• Implementing Asynchronous Circuits using a Conventional EDA Tool-Flow
• DIRECT-MAPPED ASYNCHRONOUS FINITE-STATE MACHINES IN CMOS TECHNOLOGY
• TransForm: Theoretical Foundations of Transactional Memory TransForm is an EU-funded research project targeted at building the theoretical underpinning for the