Torresen, Jim - Department of Informatics, Universitetet i Oslo

• Implementing Backpropagation Training on a Reconfigurable Computer Using Pipelining of the Training Patterns
• An FPGA Implemented Processor Architecture with Adaptive Resolution Jim Torresen and Jonas Jakobsen
• EXPLOITING MULTIPLE DEGREES OF BP PARALLELISM ON THE HIGHLY PARALLEL COMPUTER AP1000
• A Dynamic Fitness Function Applied to Improve the Generalisation when Evolving a Signal
• Two-Step Incremental Evolution of a Prosthetic Hand Controller Based on Digital Logic Gates
• Scalable Evolvable Hardware Applied to Road Image Recognition Jim Torresen
• Evolvable Hardware as a New Computer Architecture
• Introduction N. Sundararajan
• Parallel back propagation training algorithm for MIMD computer with 2Dtorus network
• Implementing Evolution of FIR-Filters Efficiently in an FPGA Knut Arne Vinger and Jim Torresen
• INCREASED COMPLEXITY EVOLUTION APPLIED TO EVOLVABLE HARDWARE
• Implementation of Backpropagation Neural
• Scalable Evolvable Hardware Applied to Road Image Recognition Jim Torresen
• Efficient Image Filtering and Information Reduction in
• An Evolvable Hardware Tutorial Jim Torresen
• TwoStep Incremental Evolution of a Prosthetic Hand Controller Based on Digital Logic Gates
• HIGH PERFORMANCE COMPUTING BY CONTEXT SWITCHING RECONFIGURABLE LOGIC
• General Mapping of FeedForward Neural Networks onto an MIMD Computer
• Improving a Network Security System by Reconfigurable Hardware Shaomeng Li, Jim Torresen, Oddvar Srasen
• EVOLVING BOTH HARDWARE SUBSYSTEMS AND THE SELECTION OF VARIANTS OF SUCH INTO AN ASSEMBLED SYSTEM
• A CAMERA BASED SPEED LIMIT SIGN RECOGNITION SYSTEM
• A Review of Parallel Implementations of
• Reconfigurable Logic Applied for Designing Adaptive Hardware Systems
• The relation of Weight Update Frequency to Convergence of BP Jim Torresen 1=2 , Shinji Tomita 1 , Olav Landsverk 2
• A DivideandConquer Approach to Evolvable Hardware Jim Torresen
• International Journal of Knowledge-based and Intelligent Engineering Systems 12 (2008) 187199 187 Incremental evolution of a signal
• Recognizing Speed Limit Sign Numbers by Evolvable Jim Torresen1, Jorgen W. Bakke1 and Lukas Sekanina2
• Exploring Knowledge Schemes for Efficient Evolution of Hardware Jim Torresen
• Evolving Multiplier Circuits by Training Set and Training Vector Partitioning
• A Dynamic Fitness Function Applied to Improve the Generalisation when Evolving a Signal
• Evolvable Hardware as a New Computer Architecture
• A Variable Word-Width Content Addressable Memory for Fast String Matching
• Exploiting Stateful Inspection of Network Security in Reconfigurable Hardware
• A SIGNAL PROCESSING ARCHITECTURE BASED ON RAM TECHNOLOGY Jim Torresen
• Reconfigurable Logic Applied for Designing Adaptive Hardware Systems
• Efficient Recognition of Speed Limit Signs Jim Torresen, Jorgen W. Bakke and Lukas Sekanina
• DETECTION OF NORWEGIAN SPEED LIMIT SIGNS Lukas Sekanina Jim Torresen
• Exploiting Reconfigurable Hardware for Network Security Shaomeng Li, Jim Torresen, Oddvar Soraasen
• Possibilities and Limitations of Applying Evolvable Hardware to RealWorld Applications
• On-Chip Evolution Using a Soft Processor Core Applied to Image Recognition Kyrre Glette and Jim Torresen
• A Signal Processing Architecture based on Evolving Digital Logic Gates