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Aragón Alcaraz, Juan Luis - Departamento de Ingenieria y Tecnologia de Computadores, Universidad de Murcia
Selective Branch Prediction Reversal by Correlating with Data Values and Control Flow
Power-Aware Control Speculation through Selective Throttling Juan L. Aragn1
Extending SRT for Parallel Applications in Tiled-CMP Architectures Daniel Sanchez, Juan L. Aragon and Jose M. Garcia
MLP-aware Instruction Queue Resizing: The Key to Power-
FATSEA An Architectural Simulator for General Purpose Computing on GPUs
Efficient Microarchitecture Policies for Accurately Adapting to Power Constraints
Sim-PowerCMP: A Detailed Simulator for Energy Consumption Analysis in Future Embedded CMP Architectures
Leakage Energy Reduction in Value Predictors through Static Decay Juan M. Cebrin, Juan L. Aragn and Jos M. Garca
EnergyEfficient Design for Highly Associative Instruction Caches in NextGeneration Embedded Processors
Confidence Estimation for Branch Prediction Reversal Juan L. Aragn1
Thesis Overview: Reducing Branch Misprediction Penalty through Confidence Estimation
Adaptive VP Decay: Making Value Predictors Leakage-efficient Designs for High Performance Processors
Efficient Message Management in Tiled CMP Architectures Using a Heterogeneous
Page 1 of 8 Curriculum Vitae of Juan L. Aragn
REPAS: Reliable Execution for Parallel ApplicationS in Tiled-CMPs
T. Srikanthan et al. (Eds.): ACSAC 2005, LNCS 3740, pp. 15 27, 2005. Springer-Verlag Berlin Heidelberg 2005
Dual Path Instruction Processing Juan L. Aragn1
Power Token Balancing: Adapting CMPs to Power Constraints for Parallel Multithreaded Workloads
Evaluating Dynamic Core Coupling in a Scalable Tiled-CMP Architecture Daniel Sanchez, Juan L. Aragon and Jose M. Garcia
A Log-Based Redundant Architecture for Reliable Parallel Computation Daniel Sanchez, Juan L. Aragon and Jose M. Garcia
An Analytical Model for the Calculation of the Expected Miss Ratio in Faulty Caches
Control Speculation for Energy-Efficient Next-Generation Superscalar Processors
Token3D: Reducing Temperature in 3D die-stacked CMPs through Cycle-level Power Control Mechanisms
Optimizing CAM-based instruction cache designs for low-power embedded systems
J Supercomput DOI 10.1007/s11227-011-0670-9
J Supercomput (2011) 55: 2850 DOI 10.1007/s11227-010-0396-0
