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- J Supercomput (2010) 53: 247268 DOI 10.1007/s11227-009-0292-7
- Reducing the Latency of L2 Misses in Shared-Memory Multiprocessors through On-Chip Directory Integration
- Directory-Based Conflict Detection in Hardware Transactional Memory
- J Supercomput (2008) 45: 341364 DOI 10.1007/s11227-008-0178-0
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- Dealing with Traffic-Area Trade-Off in Direct Coherence Protocols for Many-Core CMPs
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- Dealing with Transient Faults in the Interconnection Network of CMPs
- A Low Overhead Fault Tolerant Coherence Protocol for CMP Architectures
- Optimizing a 3D-FWT Video Encoder for SMPs and HyperThreading Architectures
- Evaluating IA-32 web servers through simics: a practical experience
- Efficient and Scalable Barrier Synchronization for Many-Core CMPs
- A G-line-based Network for Fast and Efficient Barrier Synchronization in Many-Core CMPs
- ARTICLE IN PRESS J. Parallel Distrib. Comput. ( )
- Validating a token coherence protocol for scientific Fernandez-Pascual
- Characterizing Energy Consumption in Hardware Transactional Memory Systems Epifanio Gaona-Ramirez, Ruben Titos-Gil, Juan Fernandez, Manuel E. Acacio
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- Cache Coherence Protocols for Many-Core CMPs 93 Cache Coherence Protocols for Many-Core CMPs
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- Fast and Efficient Synchronization and Communication Collective Primitives
- Address Compression and Heterogeneous Interconnects for Energy-Efficient High-Performance in Tiled CMPs
- A fault-tolerant directory-based cache coherence protocol for CMP architectures
- DiCo-CMP: Efficient Cache Coherency in Tiled CMP Architectures Alberto Ros, Manuel E. Acacio, Jose M. Garcia
- CellStats: a Tool to Evaluate the Basic Synchronization and Communication Operations of the Cell BE
- Direct Coherence: Bringing Together Performance and Scalability in Shared-Memory
- Sim-PowerCMP: A Detailed Simulator for Energy Consumption Analysis in Future Embedded CMP Architectures
- An Efficient Cache Design for Scalable Glueless Shared-Memory Multiprocessors
- Memory Subsystem Characterization in a 16-Core Snoop-Based Chip-Multiprocessor Architecture
- A Two-Level Directory Architecture for Highly Scalable cc-NUMA Multiprocessors
- On the Evaluation of x86 Web Servers Using Simics: Limitations and Trade-Offs
- The Use of Prediction for Accelerating Upgrade Misses in cc-NUMA Multiprocessors
- A Novel Approach to Reduce L2 Miss Latency in Shared-Memory Multiprocessors
- Future Generation Computer Systems 18 (2002) 317333 MPIDelphi: an MPI implementation for
- Characterization of Conflicts in Log-Based Transactional Memory (LogTM) J. Ruben Titos, Manuel E. Acacio, Jose M. Garcia
- Owner Prediction for Accelerating Cache-to-Cache Transfer Misses in a cc-NUMA Architecture
- An efficient implementation of a 3D wavelet transform based encoder on hyper-threading technology
- GLocks: Efficient Support for Highly-Contended Locks in Many-Core CMPs Jose L. Abellan, Juan Fernandez and Manuel E. Acacio
- UNIVERSIDAD DE MURCIA Departamento de Ingeniera y Tecnologa de Computadores
- Extending the TOKENCMP Cache Coherence Protocol for Low Overhead Fault Tolerance
- Page 1 of 6 Manuel E. Acacio
- The Impact of Non-coherent Buffers on Lazy Hardware Transactional Memory Systems
- Characterizing the Basic Synchronization and Communication Operations in Dual Cell-Based
- Evaluation of Low-Overhead Organizations for the Directory in Future Many-Core CMPs
- A scalable organization for distributed directories Alberto Ros *, Manuel E. Acacio, Jos M. Garca
- Speculation-Based Conflict Resolution in Hardware Transactional Memory
- Heterogeneous Interconnects for Energy-Efficient Message
- A Direct Coherence Protocol for Many-Core Chip Multiprocessors
- Exploiting address compression and heterogeneous interconnects for efficient message management in tiled CMPs
- : Extending Magny-Cours Coherence for Large-Scale Servers Alberto Ros
- Fault-tolerant cache coherence protocols for CMPs: evaluation and trade-offs
- Efficient Message Management in Tiled CMP Architectures Using a Heterogeneous
- Multicore Platforms for Scientific Computing: Cell BE and NVIDIA Tesla
- On the Evaluation of Dense Chip-Multiprocessor Architectures
- ZEBRA : A Data-Centric, Hybrid-Policy Hardware Transactional Memory Design
- Eager meets Lazy: the Impact of Write-Buffering on Hardware Transactional Memory
