Yoo, Hoi-Jun - Department of Electrical Engineering and Computer Science, Korea Advanced Institute of Science and Technology

• Bitwise Competition Logic for Compact Digital Comparator
• A Low-Power Graphics LSI integrating 29Mb Embedded DRAM for Mobile Multimedia Applications
• Ramchan Woo 1 Design and Implementation of Low-Power
• A Low-Power Vector Processor Using Logarithmic Arithmetic for Handheld 3D Graphics Systems
• ISSCC 2004 / SESSION 8 / CIRCUITS FOR DIGITAL SYSTEMS / 8.2 8.2 A 51mW 1.6GHz On-Chip Network for Low-Power
• A 10Gbps/port 8x8 Shared Bus Switch with embedded DRAM Hierarchical Output Buffer
• A Distributed Crossbar Switch Scheduler for On-Chip Networks Kangmin Lee, Se-Joong Lee, and Hoi-Jun Yoo
• 150 2008 IEEE International Solid-State Circuits Conference ISSCC 2008 / SESSION 7 / TD: ELECTRONICS FOR LIFE SCIENCES / 7.8
• Cost-efficient Network-on-Chip Design Using Traffic Monitoring System Kwanho Kim, Donghyun Kim, Kangmin Lee, and Hoi-Jun Yoo
• IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 7, JULY 2004 1101 A Low-Power 3-D Rendering Engine With Two
• Master's Thesis Logarithmic Arithmetic Unit
• A 5.1-W UHF RFID Tag Chip integrated with Sensors for Wireless Environmental Monitoring
• 308 2008 IEEE International Solid-State Circuits Conference ISSCC 2008 / SESSION 16 / LOW-POWER DIGITAL / 16.2
• 308 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS--II: EXPRESS BRIEFS, VOL. 52, NO. 6, JUNE 2005 Packet-Switched On-Chip Interconnection Network
• Master's Thesis Design and Implementation of Ultra-low power,
• An Arbitration Look-Ahead Scheme for Reducing End-to-End Latency in Networks on chip
• Analysis of Body Sensor Network Using Human Body as the Channel
• A Low Power Reconfigurable I/O DRAM Macro with Single Bit line Writing Scheme
• An Embedded 8-bit RISC Controller for Yield Enhancement of the 90-nm PRAM
• Graphics Hardware (2004) T. Akenine-Mller, M. McCool (Editors)
• Traffic Monitoring System for Application-Specific Networks-on-Chip
• 104 4-900784-01-X 2005 Symposium on VLSI Circuits Digest of Technical Papers Adaptive Network-on-Chip with Wave-Front Train Serialization Scheme
• 148 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 14, NO. 2, FEBRUARY 2006 Low-Power Network-on-Chip for High-Performance
• 266 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 1, JANUARY 2008 A Fully Integrated Digital Hearing Aid Chip
• Yoon Chi Won 1998/12/28 Row Cycle
• 2002 IEEE International Solid-State Circuits Conference 0-7803-7335-9 2002 IEEE ISSCC 2002 / SESSION 4 / BACKPLANE INTERCONNECTED ICs / 4.7
• Semiconductor System Lab 1 Design and Implementation of
• Min-wuk Lee 1 A fixedA fixed--point 3D graphics library withpoint 3D graphics library with
• A Fixed-point 3D Graphics Library with Energy-efficient Cache Architecture for Mobile Multimedia Systems
• An 81.6 GOPS Object Recognition Processor Based on NoC and Visual Image Processing Memory
• IEEE Transactions on Consumer Electronics, Vol. 51, No. 3, AUGUST 2005 Contributed Paper
• SSSSSSSS LLLLSemiconductor System LabSemiconductor System LabSemiconductor System LabSemiconductor System Lab MS Thesis 1
• A Low Power 3D Rendering Engine with Two Texture Units and 29Mb Embedded DRAM for 3G Multimedia Terminals
• A 6.3nJ/op Low Energy 160-bit Modulo-Multiplier for Elliptic Curve Cryptography Processor
• Networks-on-chip and Networks-in-Package for High-Performance SoC Platforms
• Cost-Optimization and Chip Implementation of On-Chip Network
• An Energy-Efficient Analog Front-End Circuit for a Sub-1V Digital Hearing Aid Chip
• A Comparative Performance Analysis of a DDR-SDRAM, a D-RDRAM, and a DDR-FCRAM using a POPeye Simulator
• Visual Image Processing RAM for Fast 2-D Data Location Search
• 612 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 5, MAY 2002 A Reconfigurable Multilevel Parallel Texture
• A 1.12pJ/b Resonance Compensated Inductive Transceiver with a Fault-Tolerant Network Controller
• 192 2005 IEEE International Solid-State Circuits Conference 0-7803-8904-2/05/$20.00 2005 IEEE. ISSCC 2005 / SESSION 10 / MICROPROCESSORS AND SIGNAL PROCESSING / 10.6
• 366 2007 IEEE International Solid-State Circuits Conference ISSCC 2007 / SESSION 20 / TD: PROXIMITY DATA AND POWER TRANSMISSION / 20.6
• SSSSSSSS LLLLSemiconductor System LabSemiconductor System LabSemiconductor System LabSemiconductor System Lab Jaeseo Lee, Gigabit Optical Interface IC Design 1
• SS LSemiconductor System Lab Sunyoung Kim 1
• A 231MHz, 2.18mW 32-bit Logarithmic Arithmetic Unit for Fixed-Point 3D Graphics System
• Optimization of Portable System Architecture for Real-Time 3D Graphics Ju-ho Sohn, Ramchan Woo and Hoi-Jun Yoo
• 184 978-4-900784-04-8 2007 Symposium on VLSI Circuits Digest of Technical Papers A PRAM includes 8b embedded RISC to generate the optimized
• 178 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 1, JANUARY 2010 A 5.2 mW Self-Configured Wearable Body Sensor
• Design and Implementation of CMOS LVDS 2.5Gb/s Transmitter and 1.3Gb/s Receiver for Optical Interconnections
• Doctoral Thesis SIMD Vertex Shader
• Semiconductor System Lab 1 Performance Analysis of Gigabit Ethernet
• A 66fps 38mW Nearest Neighbor Matching Processor with Hierarchical VQ Algorithm for Real-Time Object Recognition
• Implementation of Memory-Centric NoC for 81.6 GOPS Object Recognition Processor
• A Low Power Compression Processor for Body Sensor Network System Hyejung Kim, Sungdae Choi, and Hoi-Jun Yoo
• Dynamic Voltage and Frequency Scaling (DVFS) Scheme for Multi-Domains Power Management
• A Real-Time Feedback Controlled Hearing Aid Chip with Reference Ear Model
• A Power Management Unit with Continuous Co-Locking of Clock Frequency and Supply Voltage for
• A 4-Gb/s Clock and Data Recovery Circuit Using Four-Phase 1/8-Rate Clock Seong-Jun Song, Jaeseo Lee, Sung Min Park, and Hoi-Jun Yoo
• A VPM (VIRTUAL PIPELINED MEMORY) ARCHITECTURE FOR A FAST ROW-CYCLE DRAM
• In this paper a high fairness arbitration mechanism is proposed for shared bus architecture in a
• 1352 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 10, OCTOBER 2002 A 120-mW 3-D Rendering Engine With 6-Mb Embedded DRAM
• 1 2003 IEEE International Solid-State Circuits Conference 0-000-000-0/00/$10.00 2003 IEEE ISSCC 2003 / SESSION 26 / EMBEDDED AND DIGITAL SYSTEMS / PAPER 26.6
• A Low Power Digital Signal Processor with Adaptive Band Activation for Digital Hearing Aid Chip
• A 0.9-V 67-W Analog Front-End using Adaptive-SNR Technique for Digital Hearing Aid
• 1758 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 11, NOVEMBER 2001 An 80/20-MHz 160-mW Multimedia Processor
• Abstract--A reference ear modeling method for the real-time feedback controlled digital hearing aid chip is proposed and
• IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 8, AUGUST 2007 1767 A Low-Power Unified Arithmetic Unit for
• SSSSSSSS LLLLSemiconductor System LabSemiconductor System LabSemiconductor System LabSemiconductor System Lab Seong-Jun Song 1
• A Two-Electrode 2.88nJ/Conversion Biopotential Acquisition System for Portable Healthcare Device
• Sensor Node Base Station Transmitter
• A 76.8 GB/s 46 mW Low-latency Network-on-Chip for Real-time Object Recognition Processor
• The Brain Mimicking Visual Attention Engine: An 80x60 Digital Cellular Neural Network for Rapid Global Feature Extraction
• Vision Platform for Mobile Intelligent Robot Based on 81.6 GOPS Object Recognition Processor
• Figure 1. (a) Basic structure of the proposed system (b) Proposed architectural block diagram
• A 0.6pJ/b 3Gb/s/ch Transceiver in 0.18 m CMOS for 10mm On-chip Interconnects
• Figure 1. Transceiver block diagram A 200Mbps 0.02nJ/b dual-mode inductive coupling
• 132 2008 IEEE International Solid-State Circuits Conference ISSCC 2008 / SESSION 6 / UWB POTPOURRI / 6.9
• Abstract--This paper presents an energy-efficient wideband signaling receiver for communication channels using the human
• 104 978-4-900784-04-8 2007 Symposium on VLSI Circuits Digest of Technical Papers SunyoungKim,SeungJinLee,NamjunCho,SeongJunSongandHoiJunYoo
• Solutions for Real Chip Implementation Issues of NoC and Their Application to Memory-Centric NoC
• Low Energy On-Body Communication for BSN Hoi-Jun Yoo, Seong-Jun Song, Namjun Cho and Hye-Jeong Kim
• 154 2007 IEEE International Solid-State Circuits Conference ISSCC 2007 / SESSION 8 / BIOMEDICAL DEVICES / 8.2
• 278 2007 IEEE International Solid-State Circuits Conference ISSCC 2007 / SESSION 15 / MULTIMEDIA AND PARALLEL SIGNAL PROCESSORS / 15.5
• Clearphone : A 0.9 V 96 W Digital Hearing Aid Sunyoung Kim, Namjun Cho, Seong-Jun Song, Donghyun Kim, Kwanho Kim and Hoi-Jun Yoo
• 558 2006 IEEE International Solid-State Circuits Conference ISSCC 2006 / SESSION 30 / SILICON FOR BIOLOGY / 30.4
• A Fixed-point Multimedia Co-processor with 50Mvertices/s Programmable SIMD Vertex Shader for Mobile Applications
• An Autonomous SRAM with On-Chip Sensors in an 80nm Double Stacked Cell Technology
• A Reconfigurable Crossbar Switch with Adaptive Bandwidth Control for Networks-on-Chip
• LOW ENERGY TRANSMISSION CODING FOR ON-CHIP SERIAL COMMUNICATIONS Kangmin Lee, Se-Joong Lee, and Hoi-Jun Yoo
• Arbitration Latency Analysis of the Shared Channel Architecture for High Performance Multi-Master SoC
• 2004 IEEE International Solid-State Circuits Conference 0-7803-8267-6/04 2004 IEEE ISSCC 2004 / SESSION 27 / SRAM / 27.4
• A High-Speed and Lightweight On-Chip Crossbar Switch Scheduler for On-Chip Interconnection Networks
• CMOS Optical Receiver Chipset For Gigabit Ethernet Applications
• 1 2003 IEEE International Solid-State Circuits Conference 0-000-000-0/00/$10.00 2003 IEEE ISSCC 2003 / SESSION 2 / MULTIMEDIA SIGNAL PROCESSING / PAPER 2.4
• A Practical Method to use eDRAM in the Shared Bus Packet Switch Kangmin Lee, Se-Joong Lee, and Hoi-Jun Yoo
• Design and Implementation of Read-Compare-Write Circuits
• Page 1, Hoi-Jun Yoo Gigabit Throughput CMOS ICs for Optical Interconnection Applications
• Embedded DRAM (eDRAM) Power-Energy Estimation for System-on-a-Chip (SoC) Applications
• A 120mW Embedded 3D Graphics Rendering Engine with 6Mb Logically Local Frame-Buffer and 3.2GByte/s Run-time Reconfigurable Bus for PDA-Chip
• 2001 IEEE International Solid-State Circuits Conference 0-7803-6608-5 2001 IEEE ISSCC 2001 / SESSION 9 / INTEGRATED MULTIMEDIA PROCESSORS / 9.2
• %,, 567&.8.9.) Clock Distribution Line
• A FAST SYNCHRONOUS PIPELINED DRAM (SP-DRAM) ARCHITECTURE WITH SRAM BUFFERS
• 32 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 1, JANUARY 2010 A 201.4 GOPS 496 mW Real-Time Multi-Object
• REAL-TIME OBJECT RECOGNITION WITH NEURO-FUZZY CONTROLLED
• Power and Area-Efficient Unified Computation of Vector and Elementary Functions
• 2432 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 11, NOVEMBER 2007 A 0.9 V 96 W Fully Operational
• IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 9, SEPTEMBER 2007 2021 A 0.2-mW 2-Mb/s Digital Transceiver Based
• IEEE Communications Magazine December 200590 0163-6804/05/$20.00 2005 IEEE TOPICS IN CIRCUITS FOR COMMUNICATIONS
• Networks on Chips 422 0740-7475/05/$20.00 2005 IEEE Copublished by the IEEE CS and the IEEE CASS IEEE Design & Test of Computers
• 254 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 1, JANUARY 2005 A 0.7-fJ/Bit/Search 2.2-ns Search Time Hybrid-Type
• 358 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 2, FEBRUARY 2004 A 210-mW Graphics LSI Implementing Full 3-D
• IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 7, JULY 2003 1213 A 4-Gb/s CMOS Clock and Data Recovery Circuit
• IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 2, FEBRUARY 2002 191 Race Logic Architecture (RALA): A Novel Logic
• 944 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 6, JUNE 2001 A 7.1-GB/s Low-Power Rendering Engine in 2-D
• JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.1, NO. 2, JUNE, 2001116 POPeye : A System Analysis Simulator for DRAM
• IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS--II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 45, NO. 9, SEPTEMBER 1998 1263 Dual-Self-Timed CMOS Logic for
• IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 10, OCTOBER 1997 1597 A Study of Pipeline Architectures for High-Speed Synchronous DRAM's
• A Simulator for a DRAM Performance Evaluation Kangmin Lee, Chi-Weon Yoon, Ramchan Woo, Jeong-Hun Kook,
• Design and implementation of Low-Power Network-on-Chip for Application to
• Doctoral Thesis 3 SoC
• SS LSemiconductor System Lab Design of Low Power Digital
• Design and Implementation of High Performance
• 2 : 2006. 2. 16 By Kim Tae-gyu
• A 8-W, 0.3-mm2 RF-Powered Transponder with